ACM-SIGDA Physical Design Workshop #5 1996: Proceedings

Fifth ACM/ SIGDA Physical Design Workshop Proceedings

April 15-17, 1996 Reston, Virginia, USA

Foreword Welcome to the Fifth ACM SIGDA Physical Design Workshop (PDW-96)! Our workshop is being held in the midst of a watershed era of growth and innovation in the EDA industry, most notably within the "back-end" domains of physical design and physical verification. Timing-, signal integrity- and power-consciousness have rapidly become mainstream design requirements, with reliability and yield just around the corner. Many classic techniques have broken down, from the design of cell libraries to place-and-route to physical verification. That this sea change is partly due to the continued scaling of process technology (weaker drivers driving more resistive interconnects, lower supply voltages reducing noise margins, slew rates affecting signal integrity and timing, neighboring interconnects coupling more noticeably, ...) is well recognized. But the changing nature of the semiconductor business itself - the changing nature of design teams has had an equally and design projects (more design starts, shorter (synthesis-driven) design cycles, ... ) profound impact on our context. We are here because all those problems in physical design which were declared "solved" four years ago (!) are now - without question very much unsolved. Interconnect design, block placement, estimation and cell layout are just a few of the wide-open topics addressed in this workshop. We are also here because few if any of us can claim to know "the real killer issues" in physical design. (What kind of problem will cause the XYZ chip to miss its market window in 1999? Timing? Thermal? Noise? Algorithms or flows?) The two evening panels bring together a number of luminaries in the field to discuss future needs and directions for deep-submicron design, as well as "disconnects" in back-end (data management and physical verification) flows. The Tuesday afternoon panel highlights the emerging need for yield optimization in physical design. Finally, we are here to make new friends and expand our horizons. There will be plenty of opportunities to chat, eat, and imbibe (which we hope will make up for the lack of opportunity to sleep!). The Monday afternoon sessions will highlight what is arguably an extremely rich opportunity in physical design, CAD for micro electromechanical systems (MEMS), and the workshop will close with an open problems session. We are grateful to the U.S. National Science Foundation for its generous support of this workshop (NSF grant MIP-9531666). Additional sponsorship has been provided by ACM SIGDA and Avant! Corporation. On behalf of the technical program and organizing committees, we hope that PDW-96 will be a rewarding and enjoyable experience for you.

Andrew B. Kahng Technical Program Chair

Gabriel Robins General Chair

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Workshop Organization

Steering Committee:

General Chair:

M. Lorenzetti (Mentor Graphics)

G. Robins (U. of Virginia)

B. T. Preas (Xerox PARC)

Technical Program Committee:

Keynote Address:

C. K. Cheng (UC San Diego)

C. L. Liu (U. Illinois Urbana-Champaign)

J. P. Cohoon (U. of Virginia)

Benchmarks Co-Chairs:

J. Cong (UC Los Angeles) A. Domic (Cadence)

F. Brglez (NOCSU)

J. Frankle (Xilinx)

W. Swartz (TimberWolf Systems)

E. G. Friedman (Rochester)

Local Arrangements Chair:

D. D. Hill (Synopsys)

M. J. Alexander (U. of Virginia)

L. G. Jones (Motorola)

Treasurer:

A. B. Kahng (UC Los Angeles, Chair)

S. B. Souvannavong

Y.-L. Lin (Tsing Hua)

Publicity Chair:

K. S. J. Pister (UC Los Angeles)

J. L. Ganley (Cadence)

M. Marek-Sadowska (UC Santa Barbara)

Sponsors:

C. Sechen (Washington)

ACM / SIGDA

R.-S. Tsay (Avant! Corporation)

U.S. National Science Foundation

G. Zimmermann (Kaiserslautern)

Avant! Corporation

http: //www. cs. Virginia. edu/- pdw96/

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Contact Information Gabriel Robins Department of Computer Science Thornton Hall University of Virginia Charlottesville, VA 22903-2442 (804) 982-2207 (804) 982-2214 (fax) robins c-cs.virginia.edu

Jason Cong UCLA Computer Science Department 4711 Boelter Hall Los Angeles CA 90095-1596 (310) 206-2775 (310) 825-2273 (fax) cong~cs.ucla.edu Antun Domic Cadence Design Systems, Inc. 2655 Seely Road, Building 6, MS 6B1 San Jose, CA 95134 (408) 428-5837 (408) 428-5828 (fax) domic cadence.com

C. L. Liu University of Illinois, Urbana-Champaign 1304 West Springfield Avenue Urbana, IL 61801 (217) 333-6769 (217) 333-3501 (fax) liucl cs.uiuc.edu

Jon Frankle Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 (408) 879-5348 (408) 559-7114 (fax) jon.frankle Axilinx.com

Michael Lorenzetti Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070-7777 (503) 685-1258 (503) 685-4790 (fax) [email protected] Bryan T. Preas Xerox PARC 3333 Coyote Hill Road Palo Alto, CA 94304 (415) 812-4845 (415) 812-4471 (fax) preas(4parc.xerox.com

Eby G. Friedman Department of Electrical Engineering Computer Studies Building 420 University of Rochester Rochester, New York 14627 (716) 275-1022 (716) 275-2073 (fax) friedman Oee.rochester.edu

Chung-Kuan Cheng CSE Department University of California, San Diego La Jolla, CA 92093-0114 (619) 534-6184 (619) 534-7029 (fax) kuan~cs.ucsd.edu

Dwight D. Hill Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 (415) 694-4421 (415) 965-8637 (fax) hill synopsys.com

James P. Cohoon Department of Computer Science Thornton Hall University of Virginia Charlottesville, VA 22903-2442 (804) 982-2210 (804) 982-2214 (fax) cohoon~virginia.edu

Larry G. Jones Motorola, Inc. MD OE321 6501 William Cannon Drive West Austin. TX 78735-8598 (512) 891-8867 (512) 891-3161 (fax) jones~ssdt-oakhill.sps.mot.com iv

Andrew B. Kahng UCLA Computer Science Department 3713 Boelter Hall Los Angeles CA 90095-1596 (310) 206-7073 (310) 825-7578 (fax) abk~cs.ucla.edu

Gerhard Zimmermann Department of Computer Science University of Kaiserslautern Erwin-Schroedinger-Strasse P.O. Box 3049 D-67653 Kaiserslautern, Germany +49 631 205-2628 +49 631 205-3558 (fax) zimmermaAinformatik.uni-kl.de

Youn-Long Lin Department of Computer Science Tsing Hua University Hsin-Chu, Taiwan 30043 Republic of China 886-35-731070 886-35-723694 (fax) ylin cs.nthu.edu.tw

Franc Brglez Dept. of Electrical and Computer Engineering North Carolina State University, Box 7911 Raleigh, NC 27695-7911, USA (919) 248-1925 (919) 248-9245 brglez~cbl.ncsu.edu

Kristofer S. J. Pister UCLA Department of Electrical Engineering Los Angeles, CA 90095-1594 (310) 206-4420 (310) 206-8495 (fax) pister ee.ucla.edu

William P. Swartz TimberWolf Systems, Inc. 10880 Cassandra Way Dallas, TX 75228-2493 (214) 613-6772 (214) 682-1478 (fax) bills twolf.com

Malgorzata Marek-Sadowska Room 4157, Engineering I Dept. of Electrical and Computer Engineering University of California Santa Barbara, CA 93106-9560 (805) 893-2721 (805) 893-3262 (fax) mms Kece.ucsb.edu

Michael J. Alexander Department of Computer Science Thornton Hall University of Virginia Charlottesville, VA 22903-2442 (804) 982-2291 (804) 804-982-2214 (fax) alexander tvirginia.edu

Carl Sechen Department of Electrical Engineering Box 352500 University of Washington Seattle. WA 98195-2500 (206) 685-8756 (206) 543-3842 (fax) sechen(ee.washington.edu

Sally B. Souvannavong Department of Computer Science Thornton Hall University of Virginia Charlottesville, VA 22903-2442 (804) 982-2291 (804) 804-982-2214 (fax) sallys~cs.virginia.edu

Ren-Song Tsay Avant! Corporation 1208 East Arques Avenue Sunnyvale, CA 94086 (408) 738-8814 (408) 738-8508 (fax) tsayLavanticorp .com

Joseph L. Ganley Cadence Design Systems, Inc. 555 River Oaks Parkway, MS 2A2 San Jose, CA 95134-1937 (408) 944-7232 (408) 894-2700 (fax) ganleyvcadence.com

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Program

Sunday, April 14 6:00pm-8:30pm: Registration (the registration desk will also be open 8:00am-5:00pm on Monday and 8:00am-12:00pm on Tuesday)

7:OOpm-8:30pm: Reception (refreshments provided)

Monday, April 15 8:30am-8:40am: Welcome 8:40am-10:OOam: Session 1: Timing-Driven Interconnect Resynthesis Session Chair: E. S. Kuh (UC Berkeley) * Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion T. Okamoto and J. Cong, UIC Los Angeles * Simultaneous Routing and Buffer Insertion for High Performance Interconnect J. Lillis, C.-K. Cheng and T.-T. Y. Lin, UC San Diego * Timing Optimization by Redundancy Addition and Removal L. A. Entrena, E. Olias and J. Uceda, U. Carlos III of Madrid and U. Politecnica of Madrid

I 7 13

* Open Commentary - Moderators: D. D. Hill (Synopsys) and P. Suaris (Interconnectix) 10:00am-10:20am: Break (refreshments provided) 10:20am-12:00pm: Session 2: Interconnect Optimization Session Chair: C. L. Liu (U. Illinois Urbana-Champaign) * Optimal Wire-Sizing Formula Under the Elmore Delay Model C.-P. Chen, Y.-P. Chen and D. F. Wong, U. Texas Austin

21

* Reducing Coupled Noise During Routing A. Vittal and M. Marek-Sadowska, UC Santa Barbara

27

* Simultaneous Transistor and Interconnect Sizing Using General Dominance Property J. Cong and L. He, UC Los Angeles

34

* HierarchicalClock-Network Optimization D. Lehther, S. Pullela, D. Blaauw and S. Ganguly, Somerset Design Center, Motorola * Open Commentary - Moderators: D. D. Hill (Synopsys) and M. Lorenzetti (Mentor)

40

12:00pm-2:00pm: Lunch

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Workshop Keynote Address: Prof. C. L. Liu, U. Illinois Urbana-Champaign Algorithmic Aspects of Physical Design of VLSI Circuits

2:00pm-2:45pm: Session 3: Tutorial: Making MEMS Speaker: K. J. Gabriel (ARPA)

45

2:45pm-3:00pm: Break (refreshments provided)

3:00pm-4:15pm: Session 4: Physical Design for MEMS Session Chair: K. J. Gabriel (ARPA) * Physical Design for Surface-Micromachined MEMS

53

G. K. Fedder and T. Mukherjee, Carnegie-Mellon U. * Consolidated Micromechanical Element Library

61

R. Mahadevan and A. Cowen, MCNC * Synthesis and Simulation for MEMS Design E. C. Berg, N. R. Lo, J. N. Simon, H. J. Lee and K. S. J. Pister, UC Los Angeles

67

4:15pm-4:30pm: Break (refreshments provided) 4:30-6:00pm: Session 5: Panel: Physical Design Needs for MEMS Moderator: K. S. J. Pister (UC Los Angeles) Panelists include: * S. F. Bart (Analog Devices)

71

* G. K. Fedder (Carnegie-Mellon U.)

76

* K. J. Gabriel (ARPA) * I. Getreu (Analogy) * R. Grafton (NSF) * R. Harr (ARPA)

81

* R. Mahadevan (MCNC)

83

* J. E. Tanner (Tanner Research)

86

6:00pm-8:00pm: Dinner 8:OOpm-9:30pm: Session 6: Panel: Deep-Submicron Physical Design:

Future Needs and Directions Moderator: N. Mokhoff (Managing Editor, EE Times) Panelists include: * T. C. Lee (President/CEO, Neo Paradigm Labs) * L. Scheffer (Architect, Cadence)

89

* W. Vercruysse (UltraSPARC III CAD Manager, Sun) * M. Wiesel (Design Manager, Intel) * T. Yin (VP R&D, Avant! Corporation)

Vii

Tuesday, April 16

8:30am-9:50am: Session 7: Partitioning Session Chair: D. F. Wong (U. Texas Austin) * VLSI Circuit Partitioningby Cluster-Removal Using Iterative Improvement Techniques S. Dutt and W. Deng, U. Minnesota and LSI Logic * A Hybrid Multilevel/Genetic Approach for Circuit Partitioning C. J. Alpert, L. Hagen and A. B. Kahng, UC Los Angeles and Cadence * Min-Cut Replication for Delay Reduction J. Hwang and A. El Gamal, Xilinx and Stanford U.

92 100 106

* Open Commentary - Moderators: J. Frankle (Xilinx) and G. Zimmermann (U. Kaiserslautern) 9:50am-10:1Oam: Break (refreshments provided) 10:lOam-11:50am: Session 8: Topics in Hierarchical Design Session Chair: M. Sarrafzadeh (Northwestern U.) * Two-Dimensional Datapath Regularity Extraction R. X. T. Nijssen and J. A. G. Jess. TU Eindhoven * HierarchicalNetlength Estimation for Timing Prediction W. Hebgen and G. Zimmermann, U. Kaiserslautern * Exploring the Design Space for Building-Block Placements Considering Area, Aspect Ratio. Path Delay and Routing Congestion H. Esbensen and E. S. Kuh, UC Berkeley * Genetic Simulated Annealing and Application to Non-Slicing Floorplan Design S. Koakutsu, M. Kang and W. W.-M. Dai, Chiba U. and UC Santa Cruz * Open Commentary - Moderators: L. Scheffer (Cadence) and T. Yin (Avant! Corporation)

111 118

126 134

11:50pm-1:30pm: Lunch

1:30pm-3:00pm: Session 9: Poster Session * Physical Layout for Three-DimensionalFPGAs M. J. Alexander, J. P. Cohoon, J. L. Colfiesh, J. Karro, E. L. Peters and G. Robins, U. Virginia

142

* Efficient Area Minimization for Dynamic CMOS Circuits B. Basaran and R. A. Rutenbar, Carnegie-Mellon U.

150

* A Fast Technique for Timing-Driven Placement Re-engineering M. Hossain, B. Thumma and S. Ashtaputre, Compass Design Automation * Over-the-Cell Routing with Vertical Floating Pins I. Peters, P. Molitor and M. XVeber, U. Halle and Deuretzbacher Research GmbH

154

* Congestion-Balanced Placement for FPGAs Y. Sun, R. Gupta and C. L. Liu, Altera and U. Illinois Urbana-Champaign

163

* Fanout Problems in FPGA K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu, UC Santa Barbara and Actel

169

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158

* Performance-Driven Layout Synthesis: Optimal Pairing & Chaining A. J. Velasco, X. Marin, J. Riera, R. Peset and J. Carrabina, U. Autonoma de Barcelona and Philips Research Labs Eindhoven

176

* Clock-Delayed Domino for Adder and CombinatorialLogic Design G. Yee and C. Sechen, U. Washington

183

3:00pm-4:00pm: Session 10: Manufacturing/Yield Issues I Session Chair: Eby G. Friedman (U. Rochester) * Layout Design for Yield and Reliability K. P. Wang, M. Marek-Sadowska and W. Maly, UC Santa Barbara and Carnegie-Mellon U.

190

* Yield Optimization in Physical Design (invited survey paper) V. K. R. Chiluvuri, Motorola

198

4:00pm-4:15pm: Break (refreshments provided) 4:15pm-5:45pm: Session 11: Panel: Manufacturing/Yield Issues II Moderator: L. G. Jones (Motorola) Panelists include: * V. K. R. Chiluvuri (Motorola) * I. Koren (U. Massachusetts Amherst)

207

* J. Burns (IBM Watson Research Center) * W. Maly (Carnegie-Mellon U.)

5:45pm-7:30pm: Dinner 7:30pm-8:00pm: Session 12a: Design Views in Routing Session Chair: B. T. Preas (Xerox PARC) * A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph and Tile Expansion Approach H.-P. Tseng and C. Sechen, U. Washington

210 218

* A Multi-Layer Chip-Level Global Router L.-C. E. Liu and C. Sechen, U. Washington

8:00pm-9:30pm: Session 12b: Design Views, Data Modeling and Flows:

Critical Disconnects Moderator: A. B. Kahng (UC Los Angeles) Panelists include: * W. W.-M. Dai (UC Santa Cruz and Ultima Interconnect Technology, Inc.)

226

* L. G. Jones (Motorola) * D. Lapotin (IBM Austin Research Center) * E. Nequist (VP R&D, Cooper & Chyan) * R. Rohrer (Fellow, Avant! Corporation) * C. Palesko (VP. Savantage)

228

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Wednesday, April 17 8:30am-9:50am: Session 13: Performance-Driven Design Session Chair: M. Marek-Sadowska (UC Santa Barbara) * A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven Placement Problems G. E. Tellez, D. A. Knol and M. Sarrafzadeh, Northwestern U.

234

* Reduced Sensitivity of Clock Skew Scheduling to Technology Variations J. L. Neves and E. G. Friedman, U. Rochester

241

* Multi-Layer Pin Assignment for Macro Cell Circuits L.-C. E. Liu and C. Sechen, U. Washington

249

* Open Commentary- Moderator: J. Cong (UC Los Angeles) 9:50pm-10:10pm: Break (refreshments provided) 10:10am- 11:30am: Session 14: Topics in Layout Session Chair: D. D. Hill (Synopsys) * Constraint Relaxation in Graph-Based Compaction S.-K. Dong, P. Pan, C. Y. Lo and C. L. Liu, Silicon Graphics. Clarkson ]U., Lucent Technologies and U. Illinois 'Urbana-Champaign

256

* An 0(n) Algorithm for Transistor Stacking with Performance Constraints B. Basaran and R. A. Rutenbar, Carnegie-Mellon U. * Efficient Standard Cell Generation When Diffusion Strapping is Required B. Guan and C. Sechen, U. Washington

262

* Open Commentary - Moderators: D. D. Hill (Synopsys) and E. G. Friedman (U. Rochester) 11:30am-12:00pm: Session 15: Open Problems Moderators: A. B. Kahng (UC Los Angeles) and B. T. Preas (Xerox PARC) 12:00pm-2:00pm: Lunch (and benchmark competition results) 2:00pm: Workshop adjourns

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Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion * Takumi Okamoto 1,2 okamoto~cs .ucla. edu

Jason Cong I conglcs .ucla. edu

Dept. of Computer Science, University of California, Los Angeles, CA 90095 2 C&C Research Laboratories, NEC Corp., Miyamae, Kawasaki 216, Japan

Abstract This paper presents an algorithm for interconnect layout optimization with buffer insertion. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a buffered Steiner tree so that the required arrival time (or timing slack) at the source is maximized. In the algorithm, Steiner routing tree construction and buffer insertion are achieved simultaneously by combining A-tree construction and dynamic programming based buffer insertion algorithms, while these two steps were carried out independently in the past. Extensive experimental results indicate that our approach outperforms conventional two-step approaches. Our buffered Steiner trees increase the timing slack at the source by up to 75% compared with those by the conventional approaches. 1.

given tree topology. [7, 8] has integrated wire sizing and power minimization with the algorithm in [6] under a more accurate delay model taking signal slew into account. On interconnect topology optimization problem, the analysis in [9] and [10] showed that as we reduce the device dimension, resistance ratio, which is defined as the ratio of the driver resistance versus the unit wire resistance, decreases. As a result the distributed nature of the interconnect structure must be considered, and conventional algorithm for total wire capacitance minimization does not necessarily lead to the minimum interconnect delay. For interconnect optimization in deep submicron VLSI design, recently a number of interconnect topology optimization algorithms have been proposed, including bounded-radius bounded-cost trees[ri], AHHK trees[12], maximum performance trees[13], A-trees[10], low-delay trees[14, 15], and IDW/CFD trees[16]. Although steady progress has been made in buffer insertion and Steiner tree construction for delay minimization, and encouraging experimental results were reported, we believe that these two steps need to be carried out simultaneously in order to construct even higher performance buffered Steiner trees directly. The independent two-step approach often leads to sub-optimal designs due to the following reasons: in the case of buffer insertion followed by Steiner tree construction, there is a problem that wiring delay and routability can not be estimated accurately in buffer insertion as mentioned above: in the case of Steiner tree construction followed by buffer insertion, there is a problem that Steiner tree optimized for delay does not necessarily result in a minimum-delay buffered Steiner tree. Figure 1 shows an example, where sink si is the most critical among all the sinks. In certain cases, which depends on the technology and criticality of sinks, the buffered Steiner tree in Figure l(a) is desired, while Figure l(b) shows a minimumdelay Steiner tree followed by buffer insertion.

Introduction

For timing optimization of VLSI circuits, buffer insertion (or fanout optimization) and interconnect topology optimization take important roles and a number of algorithms were proposed for these problems over the past a few years. On fanout optimization problem, most of previous work focused on construction of buffered trees in logic synthesis with consideration of user-defined timing and area constraints[1, 2, 3]. The timing measures used during this stage mainly consist of gate delays and a rough approximation for interconnect delay, which is assumed to be piecewise linear with the number of fanouts. When the wiring effect is dominant, traditional synthesis tools that use such a fanout-based model may be optimizing a timing value which is significantly different from the actual post layout value. Another problem with traditional synthesis is in area estimation. Typically, the tools try to optimize only the total gate area, and the interconnect area and the routabilitv of the chip are not taken into account. As a result, although the total gate area of the synthesized netlist is quite small, it may not fit into the target die area after layout. In recent years, [4, 6, 5, 7, 8] attack the fanout optimization problem after layout information is available. In [4], a fanout optimization algorithm based on alphabetic trees is presented that generates fanout trees free of internal edge crossings thus improving routing area. In [5], buffer insertion based on a minimum spanning tree is proposed. In [6]. a polynomial time algorithm using dynamic programming is proposed for delay-optimal buffer insertion problem on a

t S I (Critical)

S l(Critical) h

Source (a) Minimum-Delay Buffered Tree

*This work is partially supported by National Science Foundation Young Investigator Award MIP9357582 and a matching grant from Intel Corporation.

S2

Source 4

(b) Minimum-Delay Tree Followed by Buffer Insertion

Figure 1. Example of Buffered Steiner Tree

1

S4

In this paper, we presents an algorithm for interconnect layout optimization with buffer insertion. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a buffered Steiner tree so that the required arrival time (or timing slack) at the source is maximized. In the algorithm. Steiner tree construction and buffer insertion are achieved simultaneously by combining A-tree algorithm[10] and dynamic programming based buffer insertion algorithm[6]. Extensive experimental results indicate that our approach outperforms conventional two-step approaches. Our buffered Steiner trees increase the timing slack at the source by up to 75% compared with those by the conventional approaches. 2.

Hereafter, it is assumed that only one type of buffer is considered for the buffer insertion, and signal polarity is neglected. Our algorithm, however, is easily extended to general case, where more than one types of buffer can be used and signal polarity must be considered, by using the methods similar to those in [7, 8]. 3. Related Work We briefly review the A-tree algorithm in [10] and the buffer insertion algorithm in [6], which are basis of our proposed algorithm. 3.1. A-tree Algorithm In [10], it was shown that a routing tree which minimizes the Elmore delay upper bound in [20] can be achieved by minimizing a weighted combination of the objectives of the minimum Steiner tree, the shortest path tree, and the "quadratic minimum Steiner tree" (a tree that minimizes the summation of source-node path lengths, taken over all possible node locations). Therefore, a minimum-cost rectilinear arborescence(A-tree) formulated in [21] is of interest since it heuristically addresses all of these terms in the decomposed upper bound at once.

Delay Models and Problem Formulation

2.1. Delay Models As in most previous works on interconnect layout optimization, we adopt the Elmore delay model[17] for interconnects and standard RC models for buffers. For wire e, let l, c, and r, be its length, capacitance and resistance, respectively. Further, let e, denote the wire entering node v from its parent. We use the following basic models for interconnects delay Dwire and buffer delay DbSff: ce = cole

Definition 1: A rectilinear Steiner tree T is called an A-tree if every path connecting the source so and any node p on the tree is a shortest path.

re = rOle

Dwire(ev) = r.,j(

In [10], an efficient algorithm based on bottom-up tree construction from the sinks was proposed for minimum-cost A-tree, which extends the algorithm in [21]. The algorithm starts with a set of subtrees, each consisting of a sink, and iteratively performs two subtrees "merging" or a subtree "growing" until all subtrees are merged into one tree. Two type of move is used for the bottom-up construction: safe move which cannot worsen the sub-optimality of an existing set of subtrees and heuristic move that may not lead to an optimal solution. According to their experimental results, A-trees constructed by the algorithm are at most 4% within the optimal, and achieve interconnect delay reduction by as much as 66% when compared to the best-known Steiner routing topology. In our approach here, we use only heuristic move in the A-tree algorithm for simplicity(essentially the algorithm in [21]). Despite using only heuristic moves, [21] has similar performance as the A-tree algorithm in [10]. The algorithm in [21] works as follows: A set called ROOT consisting of the roots of current subtrees which will eventually be merged to form the solution is maintained; Initially, ROOT contains the roots of n trivial trees, each consisting of a single sink. The algorithm then iteratively merges a pair of roots such that the "merged" root is as far from the source as possible, and terminates when

- + c(Tv))

2

Dbuff(b, ci) = db + rbCi,

where co and ro are capacitance and resistance for unit length wire, respectively, c(T,) is the lumped capacitance of subtree T, rooted at v, db and rb are buffer b's intrinsic delay and output resistance, respectively, and cl is the load on buffer b. When wire e is very long, we can divide e into a sequence of wires connected by degree-2 nodes to capture the distributed nature of the interconnect delay. Note that we assume wires are of a uniform width. Wiresize optimization can be carried out in a separate step after the buffered tree construction using the algorithm in [18, 19] or during the buffered tree construction as mentioned in Section 6. 2.2. Problem Formulation We use required arrival time as our optimization objective. The required arrival time at the root of tree T., denoted q(Tv), is defined as follows: q(Ti,) =

E

(qn

uE'zks(TO,

-

delay(v, u)),

where qu is the required arrival time of sink u, sinks(Tv) is a set of sinks of tree T, and delay(u, v) is delay from v to u defined by our delay models. This measure is useful since it is a typical objective when optimizing the performance of combinational networks. If we assume the signal arrives at the root of T at t = 0, the timing requirements are met when q(T) is non-negative. The buffered Steiner tree problem for delay minimization is stated as follows:

ROOT1 = 1.

More formal description of the algorithm is shown in Figure 2, where all sinks are assumed lie in the first quadrant with so at the origin for simplicity. But it is easy to extend the algorithm to the general case. 3.2. Buffer Insertion For given required arrival times at the sinks of a given Steiner tree, the buffer insertion algorithm in [6] chooses the buffering position on the tree such that the required arrival time at the source is as late as possible, where the delay is calculated based on the definition in Section 2. The algorithm assumes that the the topology of the routing tree (or Steiner tree) is given, as well as the possible (legal) positions of the buffers.

Given: A source so and sinks S1, S2 .s.. ,S, of a signal S. with given positions and a required arrival time associated with si (1 < i < n). Find: Steiner tree T, that spans S and has buffers inserted. Objective: Maximize q(Ts 0 ).

2

Procedure HeuristicAtree() ROOT - {sj I 0 < i < n}; while IROOTI > 1 do Find v, w E ROOT such that the sum min(vx, wt) + min(vy, wy) is maximum; ROOT - ROOT + {r} - {v} - {w}, where r is a node with coordinates (min(v,, w~),rmin(v,, wy)); Merge T, and Tut to T, adding edges from r to v and w, respectively; end while; end procedure

Procedure bottom.up(T) foreach v G T in topological order from sinks to source do if v is a sink then Z-

(qv - Dire(ev), c, + cej;

else ZI

a set of options for v's left child;

Zr a set of options for v's right child; Zv - ; for (z E Z2 , j E Z,) do /* redundant Merge of Z1 and Z,2/ if qj < qj then Zv Zv U (q,, ci + min{cj I gi < qI); end if; end for;

Figure 2. A-tree Algorithm Using Heuristic Move

Zv -

Zv U (maxZEz.(qz - Dbsff(bcZ)), Cb);

for z G Z, do

qz - qz -Dwjre(ev);

In the algorithm, which is based on dynamic programming technique, a set of (qj, ci) pairs is maintained for possible buffers assignment at each legal positions of the buffers, where qj and ci are the required arrival time and the capacitance of dc-connected subtreel rooted at i corresponding to q, respectively(Figure 3). Note that ci is not the total capacitance of entire subtree rooted at i. Each pair is called an option. The algorithm consists of two phases as follows. During the first phase the function "bottom-up(" in Figure 4 computes the irredundant set of all possible options 2, Zv for each node v(or legal positions of the buffers) in the tree in bottom up manner(Figure 5(a)) 3 . For the options at the root of the entire tree, the actual delay is calculated, using the output resistance Rgyte of the gate which produces the signal: q= go-Rguteco, qrco and then the option which gives the maximum q,,,... is chosen. The second phase traces back the computations of the first phase that led to this option, and determines the computed buffer positions on the way (Figure 5(b)).

CZ E CZ + cc; end for; end if; end for; end Procedure; Figure 4. Algorithm Finding a Set of Options

Tv

TO

eler ZIl -A

M~ix(qORgaticO)

eer At

AtRtb Zr

top down r

(a) Option Calculation in Bottom-up Phase

TIT (b) Buffer Insertion in Top-Down Phase

Figure 5. Illustration of buffer insertion

ce

4.

Sink

Simultaneous Steiner Tree Construction and Buffer Insertion

4.1. Basic Idea of the Proposed Approach We develop an algorithm for simultaneous Steiner tree construction and buffer insertion, called buffered A-tree (BAtree) algorithm, by combining the A-tree and buffer insertion algorithms in Section 3. In such combination, the concept of critical path isolation(Figure 7(a)) and balanced load decomposition(Figure 7(b)) are also applied, which are techniques used for fanout optimization(or buffer insertion) in logic synthesist, 2, 3]. In logic synthesis, when one or several sinks are timing-critical, the critical path isolation tech-

Figure 3. An Option at the Root of Subtree T, In the algorithm in [6], candidate points for the buffer insertion are right after the Steiner points in the tree, which makes it possible to unload the critical path as much as possible(Figure 6(a)). In our implementation, we also make each Steiner point itself be a candidate(Figure 6(b)), in addition to the points right after the Steiner points, in order to reduce the number of buffers inserted. Moreover, an edge whose length is longer than certain threshold given by user is divided in order to make it possible to insert buffer in the middle of the wire(Figure 6(b)).

I' hi

7 i, ii'h'

l "dc-connected" means "directly connected by wires'. 2 Irredundant set has no two options (q, c) and (q', c') such that q > q' and c < c' [6]. 3 For simplicity, a binary tree is assumed here, but the algorithm is easily applied to general trees by addition of dummy nodes and 0 length wires[8]. Node which has only one child, where Z, or Zr are NULL in Figure 4, can be also treated by a simple extension.

AT

(a) Candidates for Buffer Insenion Points in 161

AT,rt

(b) Candidates for Buffer Insertion Points in Our Implementation

Figure 6. Candidate Points for Buffer Insertion

3

nique generates a fanout tree so that the root gate drives the critical sinks and a smaller additional load due to buffered non-critical paths. On the other hand, if required times at sinks are within a small range, balanced load decomposition is applied in order to decrease the load at output of root gate. These transformations are applied recursively in a bottom-up process from the sinks in the same manner as the A-tree and buffer insertion algorithms. Therefore, it is natural for us to apply these techniques in combination with the A-tree and buffer insertion algorithms.

Tv V.

ZV ev . y

ew

Source

-- -

Zw

Tw

(xu, yw)

Trv y) --

01

Figure 8. Evaluation of a Merged Subtree Definition 2: The maximum possible required time at the root r of subtree Tr generated by merging of T, and T., denoted R.., is defined as follows: (a) Cntical Signal Isolation

R-

(b) Balanced Load Decomposition

Figure 7. Fanout Optimization in Logic Synthesis

The maximum R'. among all possible Definition 3: merging pairs v and w in the set of roots ROOT of the current subtrees, denoted Rmz(ROOT), is defined as follows:

Rmai(ROOT) =

R_

Definition 4: The distance between the source and the merging point for v and w, denoted D_, is defined as follows: Dw = min(v,, w,) + min(v,, w,). This definition is for the case that v and w are in the first quadrant with so at the origin. Other cases can be defined in a similar way. Definition 5: The maximum D_ among all possible merging pairs v and w in the set of roots ROOT of the current subtrees, denoted Dmax(ROOT), is defined as follows:

2. Merge T, and T. to Tr, and compute a set of options at r by bottom.up(Tr). 4.2. Selection of Roots to be Merged in BA-tree In our algorithm, the computation of options and tree construction are performed simultaneously. Suppose that subtrees T, and T. are merged into Tr as shown in Figure 8. Let Zv and Z. be the sets of options at v and w, respectively computed in the previous steps. Based on Z,, Zw, dist(r, v), dist(r,w), and buffer b's characteristics, a set of options Zr at r are temporarily computed for evaluation of the best merge. Since the parent nodes of the current subtree's roots, v and w, are not determined yet at this stage, 1,, and 1,. were assumed to be 0 in the computation of Z, and Z., respectively. In the temporary computation of Zr, we update Z, and Z. using lev = dist(r, v) and le = dist(r, w) when computing the arrival time at r with the assumption that 1,r = dist(so, r). Note that dist(so,r)

Dmax(ROOT) =

Dvw.

max v,wEROOT

Now, we can define the merging cost for v and w. Definition 6: The merging cost for v and w, denoted mcost(v, w, ROOT), is defined as follows: mcost(v, w, ROOT) = Rvw Rmax(ROOT)

Dvw Dmoz (ROOT)'

where a is a fixed constant with 0.0 < a < 1.0. Note that instead of using a * R_ + f * D_, for the cost, we use the scaled objective above. The use of the scaled objective avoids the problem of choosing a different pairs of a and Qfor each instance. For the subtrees merging in BA-tree algorithm, we select T, and T. whose mcost(v, w, ROOT) is maximum among

,r.

We introduce the following definitions before describing how to select two subtrees to be merged in BA-tree construction. 4

max v,wEROOT

1. Select v and w with taking critical path isolation and balanced load decomposition into account.

1

ZCZr

where r is the merging point of T, and T., and Zr is a set of options at r.

In our approach, the concepts of critical path isolation and balanced load decomposition are used when choosing two subtrees (T, and T.) to be merged in the A-tree algorithm. Every pair of subtree roots v and w are evaluated by computing the required time at the root of subtree Tr, which results from merging of Tv and T.. Then, the best pair for merging is chosen so that critical path isolation and balanced load decomposition are achieved(See Section 4.2). The required times at the root of Tr is calculated based on 4 the options at v and w, dist(r, v) and dist(r, W) for the interconnect delay, and the effect of buffer insertion at r. For the evaluation, we keep a set of options at each of subtree's roots by using bottom-up() during the construction of A-tree. Basically the following two steps are iterated in BA-tree algorithm.

is an upper bound of

= max qz,

dist(v, w) denotes Manhattan distance between v and w

4

all possible pairs of subtrees. Clearly, if we set a = 0.0, our root selection criteria for merging is the same as that in the A-tree algorithm presented in Section 3.1. By using mcost in the A-tree construction, required time maximization with buffer insertion(critical path isolation and balanced load decomposition) and wire length minimization can be achieved simultaneously. The second term in mcost contributes to the wire length minimization as the original A-tree algorithm. The first term contributes to the critical path isolation and balanced load decomposition as the fanout optimization in logic synthesis. When one or several sinks are timing-critical, those sinks are isolated since the merging for those sinks, whose R are smaller than the others, will be applied in the later stage. Figure 9(a) shows an example for this case, where sink SI is the most critical among all the sinks. Sink Si will be isolated since the merging for si, whose R is smaller than the others, will be applied after S 4 , s 3 , and 52 are merged. On the other hand, if required times at sinks are within a small range, the merging will be performed so that the load is balanced, since R of the merging for those sinks are also within a small range. Figure 9(b) shows an example for this case, where required times at sinks SI, S2, S3, ands 4 are within a small range. The load will be balanced, since R of the merging for the sinks are within a small range.

Procedure BA-tree-bottomup() ROOT E {si I 0 < i < nj; foreach v E ROOT do bottom-up(v); /* Zv is computed for each sink '/ end for; while IROOTI > 1 do Find v, w E ROOT with max, c-EROOT mcost(v, w, ROOT); /* Z, is temporarily computed for its evaluation*/ ROOT - ROOT + {r} - {v} - {w}, where r is a node with coordinates (rnin(vr, w,), min(vy, wy)); Merge T, and T, to T, adding edges from r to v and w, respectively; bottom-up(Tr); /* Z,,Z,,Zw are re-computed here with pruning */ end while; end procedure

Figure 10. Algorithm for Simultaneous A-Tree Construction and Option Computation region, and we evaluated the average results. The loading capacitances and required times at the sinks are also

randomly chosen from the intervals [0.05pF, 0.15pF] and [5.0ns, 10.0nus], respectively. The parameters used in the experiments are summarized in Table 1.

Psi

Table 1. Parameters for Experiments Output Resistance of Gate Output Resistance of Buffer Intrinsic delay of Buffer Wire Resistance Wire Capacitance Loading Capacitance of Sink Loading Capacitance of Buffer Required Time at Sink

Source (a) Tree with Cntical Sink Isolation

(b) Tree with Balance Load Decomposition

Figure 9. Example of BA-tree 4.3.

Cb

q,

1000Q 800Q 0.lns 0.12Q/ttm 0.15fF/jlm 0.05pF - 0.15pF 0.05pF 5.Ons - 10.0ns

We compared results obtained by the following two methods:

Overall Algorithm

The algorithm consists of two phases in the same way with the buffer insertion[6]: bottom up tree construction with option computation and top down buffer insertion. Formal description for the first phase, bottom up tree construction with option computation, is shown in Figure 10. Option computation at each subtree's root by bottom up() and mcost(v, w, ROOT) evaluation at the merging are integrated into A-tree algorithm. The second phase, top down buffer insertion, is the same with the one in the buffer insertion[6]. The option which gives the maximum required time at root is chosen, then traces back the computations of the first phase that led to this option. During the backtrace, the buffer positions are determined.

Ml: A-tree[21] followed by buffer insertion[6]. M2: BA-tree construction(s in mcost: 0.2, 0.4) Table 2 shows average required times at the sources of the buffered Steiner trees generated by the two methods. The difference of the required time is increased as the number of sinks is increased. Although the difference is not so large for nets with 10 sinks, the required time at source of BAtree is larger than that by Ml by 49% with a = 0.2 and 75% with a = 0.4 for nets with 100 sinks.

Table 2. Required Time at Source(ns) #sinks

5.

Rgate rb db ro c0 cg

Experimental Results

We implemented BA-tree on a Sun SPARC 5 workstation under the C/UNIX environment, and tested it on signal nets with 10, 25, 50, and 100 sinks5 . For each net size, 100 nets were randomly generated on a 10mm x 10mm routing

M2(a : 0.2)

M2(a : 0.4)

10

3.051.00

Ml

3.07 (1.01)

3.10 (1.027

25 50 100

2.22(l.00) 1.65(1.00 0.88(1.00-

2.29 (1.03) 1.80 1.09) 1.31 1.49)

2.37 (1.07) 1.94 1.18 1.54 (1.75)

Table 3 shows average runtimes, which is increased due to the merging pair evaluation by 1.5 times (10 sinks) to 40 times (100 sinks) in BA-tree.

'The number of sinks in signal nets before buffer insertion is usually up to 100 and most of them are less than 25.

5

-

#sinks 10 L 25 50 100

"A [3] K. J. Singh and A. Sangiovanni-Vincentelli, Heuristic Algorithm for the Fanout Problem," Proc. ACM/IEEE Design Automation Conf., 1990, pp. 3 5 7 360. [4] H. Vaishnav and M. Pedram, "Routability-Driven Fanout Optimization," Proc. ACM/IEEE Design Automation Conf., 1993, pp.2 3 0 - 23 5 . [5] L. N. Kannan, P. R. Suaris, and H. G. Fang, "A Methodology and Algorithms for Post-Placement Delay Optimization," Proc. ACM/IEEE Design Automation Conf., 1994, pp.3 27 -33 2 . [6] L.P.P.P. van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay," Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 86 5 -868. [7] J. Lillis, C. K. Cheng, and T. T. Lin, "Optimal and Efficient Buffer Insertion and Wire Sizing," Proc. IEEE Custom Integrated Circuits Conf., 1995, pp. 25 9 -26 2 . [8] J. Lillis, C. K. Cheng, and T. T. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," Proc. IEEE Int. Conf. ComputerAided Design, 1995, pp. 1 38 -1 43 . [9] D. Zhou, F. P. Preparata, and S. M. Kang, "Interconnection Delay in Very High-Speed VLSI," IEEE Trans. Circuits Syst., 38(7), pp. 77 9 -7 90 , July 1991. [10] J. Cong, K. S. Leung, and D. Zhou, "PerformanceDriven Interconnect Design Based on Distributed RC Delay Mode," Proc. ACM/IEEE Design Automation Conf., 1993, pp.6 0 6 -611. [11] J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, "Provably Good Performance-Driven Global Routing," IEEE Trans. Computer-Aided Design, 11(6), pp. 73 9 -752, June 1992. [12] C. J. Alpert, T. C. Hu, H. Huang, and A. B. Kahng, "A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Routing," Proc. IEEE Int. Symp. Circuits Syst., 1993, pp. 186 9 -1 8 72 . [13] J. P. Cohoon and L. J. Randall, "Critical Net Routing," Proc. IEEE Int. Conf. Computer Design, 1991, pp.l 7 4-177. [14] K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, "Rectilinear Steiner Trees with Minimum Elmore Delay" Proc. ACM/IEEE Design Automation Conf., 1994, pp.3 81 -3 86 . [15] K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, "Near-Optimal Critical Sink Routing Tree Constructions," IEEE Trans. Computer-Aided Design, 14(12), pp.1417-1436, Dec. 1995. [16] X. Hong, T. Xue, E. S. Kuh, C. K. Cheng, and J. Huang, "Performance-Driven Steiner Tree Algorithms for Global Routing," Proc. ACM/IEEE Design Automation Conf., 1993, pp. 177-181. [17] W. C. Elmore, "The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifier," J. Applied Physics, 19, pp. 55-63, 1948. [18] J.Cong and C.-K.Koh, "Simultaneous Driver and Wire Sizing for Performance and Power Optimization," IEEE Trans. VLSI, 2(4), pp.408-423, Dec. 1994. [19] J.Cong and K.S.Leung, "Optimal Wiresizing Under the Distributed Elmore Delay Model," IEEE Trans. Computer-Aided Design, 14(3), pp.3 2 1 -336, Mar. 1995. [20] J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks," IEEE Trans. ComputerAided Design, 2(3), pp.202-211, 1983. [21] S.K. Rao, P. Sadayappan, F.K. Hwang, and P.W. Shor, "The Rectilinear Steiner Arborescence Problem," Algorithmica 7, pp.27 7 -288, 1992.

Table 3. Run Time(s) M1 M2(a: 0.2) 1 M2(o : 0.4) 0.03 1.5) 0.03 (1.5) 0.02(1.00) 0.03(1.00) I 0.16(5.3) - 0.15(5.0) 0.06(1.00) 1 1.02(17.0) 1 1.01(16.8) 0.18(1.00) 1 7.18(42.2) - 6.95(38.6)

Table 4 shows wire length, which is increased by 0% (10 sinks) to 7% (100 sinks) with a = 0.2 and 5% (10 sinks) to 28% (100 sinks) with a = 0.4.

#sinks 10 25 50 100

Table 4. Wire Length(mm) 0.4) M2 ( Ml M2 a: 0.2) 2.5821.00 .69(1.05) .57-(1.00) 4.32(1.02) 4.70(1.11) 4.25(l.00) 6.08(1.00) 6.29(1.03) 7.17(1.18 8.64(1.00) 9.23(1.07) 11.0o(1.28)

Table 5 shows the number of buffers inserted, which is also increased by 0% (10 sinks) to 8% (100 sinks) with a = 0.2 and 0% (10 sinks) to 15% (100 sinks) with a = 0.4. Note that minimization for the number of buffers as in [6] is not considered here. Therefore, redundant buffers might be included in the results.

#sinks 10

Table 5. #Buffers Inserted M1 M2(a: 0.2) M2(a: 0.4) 8(1.00) 8 1.00) 8(1.00)

25

18(1.00)

18(1.00)

18(1.00)

50 100

31(1.00) 53(1.00)

32(1.03) 57(1.08)

33(1.06) 61(1.15)

Through Table 2 to 5, tradeoff between the required time, wire length and number of buffers can be seen with the different parameter a. 6. Conclusions In this paper. we have presented an algorithm, BA-tree, which derives buffered Steiner tree so that the required arrival time at the source is maximized. The algorithm achieves Steiner tree construction and buffer insertion simultaneously, while these two steps were carried out independently in the past. We have shown its efficiency and effectiveness experimentally. Future work will include the total capacitance minimization and their trade-off with the required time at the source. We also plan to incorporate optimal wiresizing for further delay optimization. Our preliminary study shows that all these optimization techniques can be combined in the bottom-up dynamic programming paradigm employed in this paper. Interested readers may contact the authors for the follow-up work. References [1] C. L. Berman, J. L. Carter, and K. F. Day, "The fanout problem: From theory to practice," Advanced Research in VLSI: Proc. 1989 Decennial Caltech Conf., pp.69-99, 1989. [2] H. J. Touati, C. W. Moon, R. K. Brayton, and A. Wang, "Performance Oriented Technology Mapping," Proc. sixth MIT VLSI Conf., pp.79-97, 1990.

6

Simultaneous Routing and Buffer Insertion for High Performance Interconnect John Lillis, Chung-Kuan Cheng Dept. of Computer Sci. & Engr.

Ting-Ting Y. Lin Dept. of Elect. & Computer Engr.

University of California. San Diego La Jolla. CA 92093-0114

Abstract We present an algorithm for simultaneously finding a Rectilinear Steiner Tree T and buffer insertion points into T. The objective of the algorithm is to minimize a cost function (e.g., total area or power) subject to given timing constraints on the sinks of the net. An interesting side-effect of our approach is that we are able to derive an entire cost/delay tradeoff curve for added flexibility. The solutions produced by the algorithm are optimal subject to the constraint that the routing topology be induced by a permutation on the sinks of the net. We show that high quality sink permutations can be derived from a given routing structure such as the Minimum Spanning Tree. This derivation provides an error bound on the minimum area solution induced by the permutation. The effectiveness of our algorithm is demonstrated experimentally.

the generalization of area minimization subject to timing constraints. Also of interest is the approach in [12] where the authors derive fanout trees from a sink permutation. However, [12] did not consider area overhead or optimize the topology embedding. Recently, [7] gave an efficient implementation of this generalization (and minimization of power) and also incorporated a generalized buffer delay model taking signal slew into account. Like the P-Tree algorithm, this work also computes a cost/delay tradeoff curve. Since both the P-Tree algorithm and typical buffer insertion algorithms adopt -a bottom-up dynamic programming approach, it is natural to attempt simultaneous optimization by both techniques. This is the topic of this paper. The remainder of the paper is organized as follows. Section 2 introduces necessary concepts and definitions; Section 3 gives details of our algorithm: Section 4 discusses experimental results and we conclude in Section 5.

1

Introduction In recent years, interconnect delay has become an increasingly critical factor in VLSI systems, in some cases accounting for over 50% of overall delay. This trend is a result of the increased resistance of interconnect when feature sizes enter the sub-micron range and will become more dramatic in the future. Two promising techniques for improving interconnect performance are the topic of this paper: performance driven routing and buffer insertion. Previous work in performance driven routing includes [1], [3], [4] and [2]. Recently, in [9], the P-Tree performance driven routing algorithm was proposed. The key idea behind the P-Tree algorithm is restricting the solution space by a permutation constraint on the sinks of the given net; in other words, given such a sink permutation, only routing topologies which can be induced by that permutation are considered. As a result, the problem is sufficiently constrained to allow a pseudo-polynomial dynamic programming algorithm solving the problem of minimizing area subject to timing constraints on the sinks of the net under the Elmore delay model [10]. The algorithm also computed an entire cost/delay treadeoff curve. This approach has yielded impressive results in both area overhead and delay versus previously proposed methods. In the area of buffer insertion, van Ginneken [13] presented an efficient algorithm for inserting buffers into a given static routing topology so as to maximize the required arrival time at the root of the tree and sketched

2

Preliminaries

2.1 Delay Models Throughout this paper we use the Elmore delay model to model interconnect delay and a simple RC delay model for buffers and drivers. In the Elmore model, the delay of a wire segment e = (u, v) transmitting a signal from node u to node v is defined as follows. Let r, and ce be the resistance and capacitance of e respectively. Further, let c(Tv) be the capacitive load at node v. The delay of the segment is expressed as ret 2 + c(Tv)). Similarly, the delay of a buffer b at node v is determined by c(Tv). the capacitive load at v, and b's intrinsic (load independent) delay db and output resistance rb. The delay through the buffer with load cl on its output is db + rbCl

We note that a more accurate buffer delay model taking signal slew into account can be incorporated by the techniques presented in [7] and [8]. For simplicity, we do not present those techniques here.

7

2.2 Definitions and Problem Formulations Central to the algorithm we present are the concepts of the Grid Graph of a terminal set and the notion of a topology being induced by a pin permutation.

Algorithm: MST-tohierarchv Let Tm be a rectilinear Minimum Spanning Tree Vv E Tm, let h(v) be a single node tree labeled v Repeat n - 1 times 1. select a leaf node v and its parent u in Tm 2. delete edge (u, v) from Tm 3. replace h(u) with a new tree t where t.left= h(u) and t.right= h(v) return last tree formed

Definition 2.1 Grid Graph [5]: given a set of terminals N, N 's Grid Graph GG(N) = (V, E) is defined by the following process: Construct vertical and horizontal lines through each terminal. Let V be identified with the set of intersection points of these lines.

Figure 1: Constructing Hierarchy Consistent with MST

There is an edge in E between two vertices iff the corresponding intersection points are connected by a single horizontal or vertical segment.

3.1 Finding High Quality Permutations We adopt the technique proposed in [9] to construct a sink permutation which we summarize here (the reader is referred to [9] for further details). The method is broken into three phases: (1) construction of a hierarchical decomposition of the terminals consistent with the Minimum Spanning Tree, (2) reorienting the hierarchical structure such that the driver is attached to the root while maintaining consistency and (3) application of a dynamic programming algorithm to optimize the tour length of-the induced permutation. The first phase is illustrated in pseudo-code in Figure 1. It was shown in [9] that the hierarchy produced by this algorithm (and and any reorientation of it) is consistent with the MST. By consistency, we mean that any permutation derived by a depth first traversal of the hierarchy can induce the MST itself. This is a useful property since it ensures that the minimum area routing topology induced by the permutation is no worse than 50% larger than the optimal rectilinear steiner tree spanning the points [6]. Among the possible permutations produced by a depth first traversal, we select the one with minimal tour length. Finding this permutation can be done in 0(n4 ) time by dynamic programming [9]. The intuition is that tour length minimization should lead to good clustering characteristics in the permutation. We illustrate this process in Figure 2. In Fig. 2(a) we see an MST for the point set with node e designated at the driver: in 2(b), we see a hierarchical decomposition consistent with the MST; in 2(c), we see the reoriented hierarchy and the possible permutations derived from the hierarchy along with their tour lengths. The minimum tour-length permutation in Figure 2 is "d c b a". To give some insight into the next phase of the algorithm and Formulation 2.1, we show in Figure 3(a) an abstract topology induced by the permutation and in Fig. 3(b) an embedding of that topology into the routing graph (which gives the minimum area Rectilinear Steiner Tree for this case).

Definition 2.2 Permutation Induced Abstract Topology: Consider a terminal set N and a permutation wron the sinks of N. A binary tree T is an abstract topology induced by 7r if its leaves are identified with the terminals in N and it obeys the ordering imposed by wr when T is interpreted as a binary search tree (the driver being implicitly attached to the root). Definition 2.3 Abstract Topology Embedding: Given a abstract topology T (as a binary tree), leaves identified with the terminal set N and a target graph G = (V, E) (e.g., G = GG(N)), an embedding of T into G is a mapping of the internal nodes of T to V. We use the term "abstract topology" to emphasize that such a topology is not a true routing topology in that its internal nodes are not mapped. Only when such a topology is embedded in the plane or a routing graph such as GG(N), does a physical routing topology result. Given this framework, we solve the following problem: Problem 2.1 Given terminal set N, required arrival times for each sink, driver parameters, buffer parameters and sink permutation -r, find the minimum cost routing topology induced by 7r and embedded in GG(N) possibly with buffers inserted at prescribed points where all timing requirements are satisfied. Cost may be a combination of the contribution of inserted buffers and consumed routing resources. For instance, one may wish to minimize the dynamic power dissipation of the net, in which case cost is the total capacitance associated with the solution.

3

Algorithm

In describing our algorithm for simultaneous routing and buffer insertion, we first describe the somewhat independent phase of finding a good sink permutation. Next we describe the algorithm solving Formulation 2.1 by (1) describing the nature and properties of the solutions sets we compute by dynamic programming, (2) giving some important primitives for manipulating those solution sets and (3) sketching the entire algorithm in terms of the primitives.

3.2 Nature of Solution Sets In the following we refer to the i'th sink in the given permutation 7w as sink i. Further, we will assume that our cost metric is total capacitance which corresponds to dynamic power dissipation [11]. The algorithm can be adapted for area minimization by ap-

8

c(14,6) C

(p, c, q) E S(v, i, j)

-

(p, C,q) E Sb(v, i, j)

-

3 routing tree rooted at vertex v, spanning sinks i..j, with cost p. load c and required time q. 3 routing tree rooted at vertex v, spanning sinks i..j, with cost p, load c and required time q and v is a branching point.

, Id(1.4)

.,(O.3)

, M5.i1)

c di2.O)

W~

(b)

1

.,

PERM

TOUR LEN

c4db dc-b cdb. dcb.

24 26 2(0 19

In [13] and [7], the following pruning property was used to keep solution sets as small as possible. Property 3.1 Solution (p, c, q) in solution set S is sub-optimal if 3 solution (p', c', q') E S where p' < p, c' < c and q' > q (in the case where all parameters are equal, either may be discarded). An interesting special case of this property is when all p's are equal (or we are optimizing performance independent of cost). In such a case, we have the property that a solution set with all sub-optimal solutions discarded can be arranged in strictly increasing order of both c and q. We refer to such sets as cq-sets. In [7] it was proposed that solution sets be organized first by p; i.e., one would partition the sets into cq-sets with identical p values. For such sets we maintain the invariant that they are arranged in increasing order of c and q. For a solution set S. it will be useful to refer to the cq-set associated with p; we do so by S[p]. As will be discussed in the next section, organizing the solutions in such a manner allows efficient detection of Property 3.1. 3.3 Primitives We now describe three useful primitives for manipulating cq-sets and solution sets: join-cq-sets(, augment.soln-set() and join-soln-sets(. The routine join-cq-sets(Cj, C,) takes left and right cq-sets of a vertex and produces the optimal cq-set at that vertex. This is done in a linear time process by similar to merging sorted lists by starting with the minimum load pairs and advancing the critical (this technique was used extensively in [13] and [7]). Pseudocode appears in Figure 4.

(C)

Figure 2: Finding a sink permutation

0 .

o.

....-.

.

0 0

d

C

b

(a)

(b)

Figure 3: Abstract Topology and an Embedding propriately weighting the cost of routing and logic resources. For simplicity, we present the algorithm two assumptions: (1) the buffer library does not contain inverters and (2) buffer insertion points are only at branching points. The algorithm can be easily adapted to eliminate these assumptions. Consider a routing tree rooted at a vertex v of GG(N and spanning sinks i..j (possibly containing buffers). Such a tree is characterized by three parameters:

While (i < ICl] and j < IC11) Let (cl,q1) = Ci[i]

p: the total capacitance of the tree.

Let (c2,q2) = C [j] C - C U {(cl + c2, min(ql, q2))}

c: the capacitive load of the tree at v.

If (qi
q. Such a problem is a special case of a two-dimensional orthogonal range query [14] and can be solved in logarithmic time (see [7], [8] for details). This approach is summarized in Figure 5.

3.4

= {(cb, q')}

Prune S' versus solutions in S S - S uS'

q = min(qi, q,).

c = cb

B'}

1= q - rbc - db is maximized S

P = Pl + PrX

c = cl + cr

E

Overall Algorithm

The overall structure of the algorithm appears in Figure 6. The keys are in steps 5 and 6 where we compute Sb and S. The base case of computing S(v, i, i) is simply a matter of computing the distance between vertex v and sink i and the associated Elmore delay and subtracting this from qj, the given required arrival

in a final phase. Each of these sets is computed by making a linear pass through the grid graph and using the

10

previously computed intermediate solution set to bootstrap. To compute LS(v)Vv, we make a left-to-right traversal of each row inductively computing the solutions from that of our neighbor. Similarly, we compute RS(v) by right to left passes and using LS(v), US(v) is computed by traversing each column top-to-bottom and finally we compute S(v, i, j) with a bottom-to-top sweep. We illustrate the process with pseudo-code for computing US(v) in Figure 7. In the figure we use v{rc} to indicate the vertex in the r'th row and c'th column so that we may easily identify a vertex's neighbors. We also use d(u, v) to denote the physical distance between vertices u and v. US(v {j,}) - RS(v { 1 ,}) Vc E {I..n} for c = 1 to n for r = 2 to n A - augment.oln.set(LS(v{r....c}), d(v{_... US(V{rc}) - RS(v{r c}) U A Prune sub-optimal solutions from USvf,,,c

c,,

Wire Resistance Wire Capacitance Sink Capacitance Driver Resistance Buffer Resistance Buffer Intrinsic Delay Buffer Input Capacitance

v{1 , ,,))

2 Use the P-Tree algorithm to derive the routing topology T induced by the sink permutation which minimizes the cost metric. Apply a static buffer insertion algorithm to this topology. 3 The proposed simultaneous routing buffer insertion algorithm.

S

In each case, the result is a tradeoff curve from which we select the solution minimizing the metric. For each net size we ran the algorithms on 25 randomly generated point sets. Results were normalized to the result of Alg 3. As can be seen from the table, the proposed approach does in fact improve over the two phase approaches. With respect to running time, the two phase approaches have an advantage in that solutions in the basic P-Tree algorithm without buffering are characterized by load and required-time only - since there is no buffering, load also captures the notion of cost. Thus, the added complexity of the simultaneous approach must be weighed against the solution improvement yielded. Nevertheless, when high quality solutions are required, the simultaneous method appears quite practical for most typical net sizes. For instance, our relatively unoptimized implementation is able to route 12 pin nets in about 30 cpu seconds on a SUN Sparc 20. A topic of our current research is development of more powerful bounding techniques and, more generally, methods for improving performance by search space limitation. A very simple technique of this sort

Figure 8: Computation of Sb(v, i, j)

Complexity

Evaluating the algorithm in terms of the number of primitives it executes, we have an 0(n 5 ) algorithm. This can be seen in the computation of Sb: there are 0(n 4 ) sets Sb(v, i, j) (note that there are n2 vertices in GG(N)) and for each such set we execute 0(n) primitives. Of course, the the primitives are not constant time operations. However, it can be argued that the size of these sets is polynomially bounded in the parameters of the problem instance (e.g., grid size) and thus the algorithm is pseudo-polynomial overall. Additionally, this leads to a natural way of trading precision for running time by "coarsening" the problem instance (e.g., by using a coarser grid and taking advantage of the resultant discretization).

4

O.Ins 0.03pF

1 Use the P-Tree algorithm to derive the minimum area routing topology T induced by the sink permutation. Apply a static buffer insertion algorithm T.

S 0 for k = i..j - 1 S - S U join(S(v, i, k), S(v, k + 1, j)) Prune suboptimal solutions from S

3.5

270Q 500Q

approach. Since the quality of a routing solution depends on both its timing and its cost, we adopt the Cost*Delayproduct as our metric of comparison (where Delay is the maximum source to sink delay - i.e., for simplicity, we assume identical required arrival times). In our experiments we use the 0.5pm technology parameters used in [9] and [4]. We also introduced a single non-inverting buffer. These parameters are given in Table 1. We compared two different two-phases approaches to the proposed simultaneous approach under the Cost*Delay metric and the results are reported in Table 2. The three approaches are as follows.

To compute Sb(v, ij), we consider the partition points k E {i..j- 1}. Because of the bottom up nature of the algorithm, the optimal solution sets S(v, i, k) and S(v, k + 1, j) have been previously computed. Pseudocode for computation of S(v, i, j) appears in Figure 8.

-

1.0fF

Table 1: Technology Parameters

Figure 7: Computation of US(v) Vv e V

Sb(v, i, j)

.112Q/pm .039fF/pim

Experiments

The main focus of our experiments was to determine the benefit afforded by taking the proposed approach of simultaneous routing and buffering versus a two phase

11

n=6 n=9 n=12

Alg I 1.03 1.07 1.11

Alg 2 1.04 1.06 1.12

[8] J. Lillis, C. K. Cheng, T. T. Lin, "Optimal Wire Sizing for Low Power and a Generalized Delay Model," Technical Report #CS96-468, CSE Dept., UCSD.

Alg 3 1.0 1.0 1.0

[9] J. Lillis, C. K. Cheng, T. T. Lin, C.-Y. Ho, "New Techniques for Performance Driven Routing with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," Technical Report #CS96-469, CSE Dept., UCSD.

Table 2: Relative Cost*Delay Results with which we have had some promising initial results is the following. Initially compute the min area solution in 0(n5 ) time and let qrnj be the resulting required time (this is done by the P- TreeA algorithm and is strongly polynomial). When running the timing optimization algorithm, consider a solution (p, c, q) E S(v, i, j). Let d be a lower bound on the delav from the driver to v (e.g., the delay of the driver with minimum possible load plus a lower bound on interconnect delay to vertex v). If q - d < qmin then solution (p, c, q) can be discarded since the min area solution is better. Surprisingly, this has yielded an order of magnitude speed up in some cases. We are exploring generalizations of this concept.

5

[10] W.C. Elmore, "The Transient Response of Damped Linear Network with particular Regard to Wideband Amplifiers," J. Applied Physics 19 (1948), pp 55-63. [11] N.H.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993, pp. 231-237. [12] H. Vaishnav, M. Pedram, "Routability-Driven Fanout Optimization." Proc. ACII/IEEE Design Automation Conf., 1993, pp. 230-235. [13] L.P.P.P van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay," Proc. International Symposium on Circuits and Systems. 1990, pp 865-868. [14] F. F. Yao, "Computational Geometry," Ch. 7 in "Handbook of Theoretical Computer Science. Vol A.," Elsevier Science Publishers, 1990.

Conclusions

We have presented an algorithm for optimization of timing and cost of a net by simultaneous routing and buffer insertion. Preliminary results are promising and show improvement over 2-phase approaches.

References [1] K. D. Boese, A. B. Kahng, G. Robins, "HighPerformance Routing Trees With Identified Critical Sinks," Proc. ACM/IEEE Design Automation Conf., 1993, pp. 182-187.

[2] M. Borah, R.M. Owens, M.J. Irwin, "Fast algorithm for performance-oriented Steiner routing," Proc. Fifth Great Lakes Symposium on VLSI, 1995 pp. 198-203.

[3] J.J. Cong, K.S. Leung, D. Zhou, "Performance-driven interconnect design based on distributed RC delay model," Proc. ACM/IEEE Design Automation Conf., 1993 pp. 606-611.

[4] T. D. Hodes, B. A. McCoy, G. Robins, "DynamicallyWiresized Elmore-Based Routing Constructions," Proc. IEEE Intl. Symp. Circuits and Systems, 1994. [5] F. K. Hwang, D. S. Richards, P. Winter, "The Steiner Tree Problem," Elsevier Science Publishers, (1992), pp. 213-214. [6] F.K. Hwang, "On Steiner Minimal Trees with Rectilinear Distance," SIAM J. Applied Math. 30 (1976), pp. 104- 114. [7] J. Lillis, C. K. Cheng, T. T. Lin, "Optimal Wire Sizing for Low Power and a Generalized Delay Model," Proc. IEEE Intl. Conf. Computer-Aided Design, 1995, pp. 138-143.

12

TIMING OPTIMIZATION BY REDUNDANCY ADDITION AND REMOVAL Luis A. Entrena*, Emilio Olias*, Javier Uceda* *

* Universidad Carlos III of Madrid, Spain {entrena, olias} @ing.uc3m.es ** Universidad Politecnica of Madrid, Spain [email protected]

ABSTRACT Redundancy Addition and Removal is a logic optimization method that has recently been proposed. This method uses Automatic Test Pattern Generation (ATPG) techniques to identify optimization transforms. It has been applied successfully to combinational and sequential logic optimization and to layout driven logic synthesis for Field Programmable Gate Arrays (FPGAs). In this paper we present an improved Redundancy Addition and Removal technique that allows to identify new types of optimization transforms and it is more efficient because it reduces the number of ATPG runs required. Also, we apply the Redundancy Addition and Removal method to timing optimization. The experimental results show that this improved Redundancy Addition and Removal technique produces significant timing optimization with very little area cost.

---

added redundancy created redundancy

Figure 1. Example of redundancy addition and removal The basic idea underlying the previous approaches in [ 1-7] can be summarized as follows. A wire is selected and tested for stuck-at fault. If no test is possible, then the wire is redundant and can be removed. Otherwise, the mandatory assignments (those assignments that are required for a test to exist) obtained during test generation suggest the additions that will force the tested wire to become redundant. However, it is not known whether these additions can be performed without changing the circuit functionality. This must be further verified by performing additional tests. In this paper we propose an efficient technique that allows to identify which connections/gates can be certainly added to the input of an existing gate in the circuit with a single test run. This technique is also extended to multiple wire addition, allowing to identify a bigger set of alternatives than with previous approaches. The Redundancy Addition and Removal technique has been applied in the past to area optimization of combinational and sequential circuits. In this paper, we apply this technique to timing optimization of combinational logic networks. Since this technique can take into account accurate area and delay estimations, it can be applied in a similar manner to technologydependent timing optimization. Logic restructuring techniques for timing optimization have been proposed based on other optimization methods [10], [11]. These techniques are commonly used in combination with other timing synthesis techniques [9]. We show that the improved Redundancy Addition and Removal technique proposed may produce significant timing optimization with very little area cost.

1. INTRODUCTION Redundancy Addition and Removal has been shown to be a powerful logic optimization method by several authors [1-7]. With this method, a logic network is optimized by iteratively adding and removing redundancies that are efficiently identified using Automatic Test Pattern Generation (ATPG) techniques. Due to the nature of redundancy, the addition of a redundant wire/gate may make some wires/gates become redundant elsewhere in the circuit. After the removal of the created redundancies, the resulting circuit may have less area or a smaller delay. The Redundancy Addition and Removal approach is illustrated with the example in Fig. 2 (taken from [1]). This is an irredundant circuit. In this circuit a connection can be added from the output of g5 as a new input to g9 without changing the logic functionality of the network. In other words, the added connection is redundant. By adding this connection, two connections, gl-g4 and g6-g7 become redundant and can be removed. The resulting network contains less gates and a shorter critical path. The added wire, g5-g9, is called an alternative wire of gl-g4 and g6g7 [3] The Redundancy Addition and Removal technique can be successfully applied to some physical design related problems, such as routing [3]. If routing cannot be completed, the unroutable wires may be substituted by alternative wires in order to complete the routing. Also, this technique is particularly well suited for resynthesis, because it allows to identify optimal functional alternatives to a wire/gate based on accurate area and delay estimations.

13

alternative wire candidate. In this section, we will describe how the connections that can be certainly added to a destination node can be identified with a single redundancy test. The optimization transforms are obtained by comparing the results of this redundancy test with the set of mandatory assigments

(SMA) of the removal candidate. We call this technique "two-way" transform identification.

In the sequel, we note a connection as a triple (S, D, P), where S is the source node, D is the destination node and P is the polarity (1 for inverted and 0 for non-inverted). Also, an input to a gate G has a controlling value Cont(G) if this

value determines the output of the gate G regardless of the other inputs. The controlling value of an AND(OR) gate is 0(1). The inverse of the controlling value is called the sensitizing value Sens(G). The sensitizing value of an AND(OR) gate is 1(0). Note that all candidate connection faults that have the same destination node have exactly the same static observability conditions. They only differ in the controllability condition. Therefore, connection faults that have the same destination node have the same mandatory observation assignments and only differ in the mandatory control assignment. Let D be a node and c be the controlling value of D. Suppose that we perform the implication of the mandatory observation assignments that are common to all connection faults that have the same destination node D. A mandatory assignment v obtained this way in a node N, such that v = c, indicates that the connection C = (N, D, 0) is redundant and therefore it can be added without changing the circuit's functionality. The demonstration of this statement is simple: the fault associated to the added connection is C stuck-at c and the necessary control assignment for this fault is N = c, which is incompatible with the previous assignment N = v = c. Analogously, if a mandatory assignment v is obtained in a node N, such that v = c, then the connection C = (N, D, 1) is redundant and therefore it can be added without changing the circuit's functionality.

Figure 2. An irredundant circuit This paper is organized as follows. Section 2 describes the improved transform identification technique, that we call "two-way" transform identification. Section 3 describes

how this technique is extended with the addition of redundant gates. Section 4 describes the timing optimization algorithm based on this approach. Section 5 presents the experimental results. Finally, section 6 presents the conclusions of this work. 2. TWO-WAY TRANSFORM IDENTIFICATION The techniques developed so far to identify logic optimization transforms by redundancy addition and removal [1-7] can be called "one-way", because the redundancy test of a fault allows to identify candidate connections for addition, but it is not known whether they can be certainly added without changing the circuit functionality. Consider for example the circuit shown in Fig. 2 and the target fault g6 stuck-at 1. When this fault is tested, a mandatory assignment g5 = 0 is obtained; in other words, all input vectors that are able to test this fault put a logic value 0 at the output of g5. The implications performed to obtain this result are shown below: (1) Mandatory control assignment: g6 = 0 (2) Mandatory observation assignments:

Example. Consider again the example in Fig. 2. The mandatory observation assignments for all connection faults whose destination node is g9 are: g8 = 1, f = 1. By implication, using recursive learning [8], we get the mandatory assignments shown below. The recursivity level is indicated by the indentation. g8 = I => Recurviviav level = I

g3 = 1, g4 = Of= I

(3) Implications: g6 = 0 => d = 0, g2 = 0 g3 = I => a = 1, b = I

Justification of g4 = i g4= I => c =1, g =1 gi =I => b =1, d = I gi = I => g5 = 1 c = 1 => g2 = 0 d = 1 => g6 = 1 Justificationof g7 =1 g7 = I => g6 = 1, g3 = 1 g3 = I => a = I, b = 1 g6 = I => Recursiviify level = 2 Justification of g2 = I g2 = I => e = 1, c = 0

d = 0=> gi = 0 gl = 0, g2 = 0 => g5 = 0 This result suggests the addition of a new connection from g5 as a new input of g9 (dotted line in Fig. 2), because when this wire is added, it blocks the propagation of the fault g6 stuck-at 1, which thus becomes redundant. The same result is obtained by the addition of wires from g6, g4, d, g2, gi, and, through an inverter, g3, a and b. However, we do not know which of these new connections can be added without changing the circuit functionality, i.e., if they are redundant connections. In order to check this, an additional redundancy test is required for each

14

g2 =I =>g5 =1 c = O=>g4 = 0 Justification of d = I d = 1, b = I => g] = I gI = I => g5 =I

g5 =1 g8 = If = I g8 = I => Recursivitv level = I

The optimization transformations are easily identified by comparing the mandatory assignments that are obtained in each node of the network by the redundancy test of the destination node and the redundancy test for each fault dominated by the destination node. If a node N has mandatory assignments of different value for each of these tests, then it is possible to add one connection from N to the destination node to eliminate at least one connection. Thus, for the previous example, we have the following mandatory assignments: (i) g5 = I obtained from the

Justification of g4 = I

15

g4 = I => c = 1, gI = I gi = 1 => b = 1, d = l c= 1=> g2 = 0 d= 1=>g6 =I Justificationof g7 =1 g7 = 1 => g6 = 1, g3 = 1 g3 =I => a = 1, b = I g6 = I => Recursivity level = 2 Justificationof g2 = I g2 = 1 => e = 1, c =0 c = 0=> g4 = 0 Jusnficationof d = I d = 1, b= = > g =1

d a

b

=I 0 and b > 0 are constants that can be computed in 0(1) time. In the case where lower bound (L > 0) and upper bound (U > 0) on the wire widths are given, we show that the optimal wire-sizing function f (x) is a truncated version of ae- b that can also be determined in 0(1) time. Our wire-sizing formula can be iteratively applied to optimally size the wire segments in a routing tree.

1

Introduction

As VLSI technology continues to scale down, interconnect delay has become the dominant factor in deep submicron designs. As a result, wire-sizing plays an important role in achieving desirable circuit performance. Recently, many wire-sizing algorithms have been reported in the literature [1, 2, 4, 5, 7]. All these algorithms size each wire segment uniformly, i.e., identical width at every position on the wire. In order to achieve non-uniform wire-sizing, existing algorithms have to chop wire segments into large number of small segments. Consequently, the number of variables in the optimization problem is increased substantially and thus results in long runtime and large storage. In this paper, we consider non-uniform wire-sizing. Given a wire segment W of length L, a source with driver resistance Rd, and a sink with load capacitance CL. For each x e [0, L], let f (x) be the wire width of W at position x. Figure 1 shows an example. Let ro and co be the respective wire resistance and wire capacitance per unit square. Let D be the Elmore delay from the source to the sink of W. We show that the optimal wire-sizing function f that minimizes D satisfies a differential equation which can be analytically solved. We have f(x) = ae-b., where a > 0 and b > 0 are constants that can be computed in O(1) time. These constants depend on Rd, CL, L, ro, and co. In the case where lower bound (L > 0) and upper bound (U > 0) on the wire widths are given, i.e. L < f (x) < U, 0 < x < L, we show that the optimal wire-sizing function f (x) is a truncated version of ae-b. which can also be determined in O(1) time. Our wiresizing formula can be iteratively applied to optimally size the wire segments in a routing tree. The remainder of this paper is organized as follows. In

wire

load

-

Figure 1: Non-uniform wire-sizing. Section 2, we show how to compute the Elmore delay for non-uniformly sized wire segments. In Section 3.1, we derive the optimal wire-sizing function when the wire widths are not constrained to be within any bounds. In Section 3.2, we consider the case where lower and upper bounds for the wire widths are given. We discuss in Section 4 the importance of our wire-sizing formula in sizing the wire segments in a routing tree. Finally, we present some experimental results and concluding remarks in Section 5.

2

Elmore Delay Model

We use the Elmore delay model [3]. Suppose W is partitioned into n equal-length wire segments, each of length Ax = A. Let xi be iAx, 1 < i < n. The capacitance and resistance of wire segment i can be approximated by coAxf(xi) and roAx/f(xi), respectively. Thus the Elmore delay through W can be approximated by

Dn=

Rd (CL

+±Zco n f jxi) A x) + i=,

f(ZcfxiA Cof0 (X,)AX + C) ,o E L)( CL).

The first term is the delay of the driver, which is given by the driver resistance Rd multiplied by the total capacitance of W and CL. The second term is the sum of the delay in each wire segment i, which is given by its own resistance ro Ax/f(xi) multiplied by its downstream capacitance E>i cof(xj)Ax+ CL. (See Figure 2.) As n - co, D,, - D where D

=

Rd(CL +

Jo

j

cof (x)dx) +

(j

cof(t) dt+ CL) dx

*This work was partially supported by the Texas Advanced

is the Elmore delay through the driver and W.

Research Program under Grant No. 003658459.

21

CL

I4

fix)

wire

Proof: Let xr E [0, ]. Assume f is continuous at ax. We consider f which is a local modification of f in a small region [x - Jx + 26]. The function i is defined as follows:

a

driver

L

- -

0

LXx

r0

fixj)

T0 ,

x

fix 3 )

fix 2 )

fix 4 )

CL

ATt

cOf(x 1 ) _X

Cofx

C of(x2 )

3)

D

=

Cofx.

rj) o

cof (s) ds + cody + C3 + CL) dt

x

+-(CONY + C3 + CL) +

Figure 2: Elmore Delay Model.

IC co f (s) ds + CL) dt.

rL

f

o(I

Optimal Wire-Sizing Function

In this section, we derive closed-form formula for the optimal wire-sizing function. It is reasonable to assume that wire-sizing functions are bounded and piecewise smooth with at most finite number of discontinuity points. We consider two cases: unconstrained and constrained wire-sizing. In unconstrained wire-sizing, there is no bound on the value of f (x); i.e. we determine f : [0, L] -s (0. cc) that minimizes D. In constrained wire-sizing, we are given L > 0 and U < cc, and require that L < f () < U, 0 < x < L; i.e., we determine f : [0, L] -+ [L, U] that minimizes D.

3.1

< x + 2

Rd(CL+Cl1+Coy+C3+CL)+

j

x

x

< t otherwise x -I

The wire W could be divide into three regions Q 1 , Q2 , and Q3 as shown in Figure 3. We denote the signal delay through Qi by Di. Hence the total signal delay D = ,3=, Di. We represent the wire resistance (capacitance) of Q, by Ri (Ci). We have R2 = r and C2 = cody. The signal delay through the wire can be calculated as follows:

roAx

-T

3

f)f(t)

f

rx, lx

X

R d

f( {

Thus

dD

=

coJ(Rd + ro

f(t)dt)

y2 By setting dD = 0, we get

2

We now consider unconstrained wire-sizing. We show that the optimal wire-sizing function satisfies a second order ordinary differential equation which can be analytically solved.

Therefore, f using y Let J5- 0, we get 2

02

r

.- dt)-

rO 5(CL + Co :+

Unconstrained Wire-Sizing

ire

J-21

10

ro(CL + co

fag

f(t)dt)

co(Rd + rO

jo+

7

dt)

ym-n gives minimum delay.

f f (t)dt) co(Rd + rO 1X f(tdt)

ro(CL + CO -

Since f is an optimal wire-sizing function, we have Ymi. f(x) and hence

03

RJ

f 2 (X)

Figure 3: Local modification of an optimal wire-sizing function.

Theorem 1 Let f be an optimal wire-sizing function. We have f 2 (X)

=

ro(CL + co Jf: f(t)dt) co(Rd + ro fj, (tdt)

ro(CL + co fJ f(t)dt) co(Rd + ro

CL

fo

I(t)dt)

For the case where f is not continuous at x, we have f is either left-continuous or right-continuous at x. All we need to do is to start with using the interval [x - 3, x] or [x, x + 6]

U

respectively.

Note that CL +CO Jf f (t)dt is equal to the downstream capacitance at point . (denoted by F(x)) and Rd + ro f(()dt is equal to the upstream resistance at point x (denoted by ,(x)). Hence we can rewrite Equation (1) as follows:

(1)

f r) =

r)o(X) CoA(x),

22

(2)

Since F is strictly decreasing and ct is strictly increasing, therefore f is strictly decreasing. By rearranging the terms in Equation (1) and differentiating it with respect to x twice, we get the following theorem.

Separating the variables and integrating both sides, we get Clr

where

C2

is a constant. It follows that

Theorem 2 Let f(x) be an optimal wire-sizing function. We have fU(X)f(_)

=

(3)

fi(X)2

Proof: We first multiply Equation (1) by the denominator of its right hand side and then differentiating both side with respect to x. We get 2f(x)f'(r)(Rd +

fr 1dt)

T

y

=

eCIC2 = ae

where a > 0 and b > 0. (Note that b > 0 follows from the fact that f is decreasing. ) In order to determine a and b, we substitute f (r) = ae- bx into Equation (4) and check the two boundary points x - 0 and x = L. We obtain the following two equations:

-2rof(x).

=

fJ0 f (t)

Iny,

+ C2 =

cobRda + roco(e

cobRda + roco(e

Since f(x) 0 0, we can divide both side by f(x) and get

)a - rebCL

-

1)a

-

-

robCLe

=

0,

=

0.

We can simplify these two equations and get f

'(x)(Rd + ro

I

J.0 f (t)

dt)

=

-ro.

ab

rO

=

Rd'

Since f is strictly decreasing, f'(x) < 0. Dividing the above equation by f'(x) and then differentiate both sides with respect to x, we obtain

2

b b [Rd 2/1eCL

-

r 0 co

~

2

-

=

00.

f"(_)f(r) = f(X) 2 . Note that the function g(z)

We can analytically solve the differential equation in (3) and obtain a closed-form solution. We have the following theorem.

Theorem 3 Let f(x) 6

b,

= aebr,

where a

-

bR

and

R~dCL(4 roco

-e

9

0.

= z

Ve0C

e-2

is a

strictly increasing function in z, g(0) < 0, and limzc> g(z) > 0. Thus g(z) has a unique root b > 0. We can use NewtonRaphson method [9] to determine b and, in practice, five to seven iterations are sufficient. Since a = j and b > 0, we have a > 0. Figure 4 shows the exponentially decreasing nature of the optimal wire-sizing function.

(4) wire width

We have that f is an optimal wire-sizing function.

f(X)

Proof: Let y = f (x) and P = y'. We have y" = differential equation (3) can be rewritten as p( dP

P)

p dP. The dy

-bx

=0.

.f(x)=ae

Since P = f'(x) < 0. we have 1....Z.. @. ., pC^AzzUrz t- .. wzre

YddP dy

- P = 0. Figure 4: Optimal unconstrained wire-sizing.

Separating P and y, we get dP -

-

dy

3.2

Constrained Wire-Sizing

.

We now consider constrained wire-sizing. It is clear that if the wire-sizing function f obtained for the unconstrained case lies within bounds L and U, then f is also optimal for constrained wire sizing. On the other hand, if for some x, f(x) is not in [LU], a simple approach is to round f(r) to either L or U; i.e. the new function is obtained by a direct truncation of f by y = L and y = U. (See Figure 5.) Unfortunately, the resulting function is not optimal. The

Integrating both sides, we get P = Cly,

where c1 is a constant. Since P = y', we have dy dx =cy.

23

wire width

wire width

flx)

ftx) U'fll)=U \-ha \flal-tie

U

U

bx

L

B

A

C

x)=ae (a)

L

,p-ABC

wire width

x wire position

wire width fla)

fla)

V U-hb

U

l -ha ffll)at

Figure 5: Direct truncation is not optimal.

L A I- 1I

reason is as follows: Suppose the curves f(x) = ae- bx and y = U intersect at x = v, from Equation (2) v must satisfy

-

(h)

I12

--

fia)

flat

F (V)

flat)=,e

(5)

fl(-L

LA A

for v to be on the optimal curve. However, from Figure 5, it is clear that v does not satisfy Equation (5), because both of its upstream resistance and downstream capacitance should be recalculated according to the new function, in which the two values associated with v are reduced because of the truncation. Thus this simple approach is not optimal. Recall that the optimal unconstrained wire-sizing function is a decreasing function. We can show that the optimal constrained wire-sizing function must also be decreasing. Theorem 4 Let f

U

ab,

U -

-

17L

wire width

wire widei

fla)=U

f(v)

C

1,-12 (a) Tire-BC

L

hpi-AB

wire width

lX=

B

B

B

-

I]

(d)

rpe-A

--

13

L (e}

(J)

,pe-B

L

hvpe-C

Figure 6: Six types of optimal wire-sizing functions.

We now define six wire-sizing functions fBC, fABC

ae-b

L

be an optimal constrained wire-sizing

function. We have, f is decreasing on [0,C]. According to Theorem 4, the optimal wire-sizing function

f, similar to the one shown in Figure 5, consists of (at most) three parts. The first part is f(r) = U, the middle part is a decreasing function, and the last part is f(r) = L. The three parts of f(x) partition W into three wire segments, A, B, and C, where A has width U, C has width L, and B is defined by the middle part of f(r). It is easy to see that the middle part of f(x) must be of the form f(x) = ae-ba for some a > 0 and b > 0. To see this, we can consider the wire segment A to be a part of the driver and its resistance to be a part of Rd. Similarly, the wire segment C can be considered as a part of the load and its capacitance as a part of CL. According to Equation (4), we can re-calculate a and b using the new values of Rd and CL, as long as we know the length of the wire segments A and B. As mentioned before, not all three parts of f(r) needed to be present. In fact, an optimal constrained wire-sizing function f(r) can be of any one of the six types of functions (type-A, type-B, type-C, type-AB, type-BC, and type-ABC) as shown in Figure 6. Note that the six function types clearly are named after the wire-segment types which are presented in W. For example, in a type-AB function, W consists only of wire segments A and B. As shown in Figure 6, 11, 12, and 13 are the length of wire segments A, B, and C, respectively.

f},

fc,

fAB,

0 < r < 11,

U f(r)w={

fA,

as follows: All six functions are of the form

,

max IRdln ~jRd L2< (1 + In L) C'L -I L> mar{L - C ma'C{(1 +

(I + InLL

=

L2

According to Theorem 6, we only need to check the six feasibility conditions. Only the functions in H needed to be computed. In general, IHI < 6 and we have never encountered any case where IHI : 1.

L< minA

3

~TOC+oI-)-1

ABC

Theorem 6 Let H = {fzIz E r and L satisfies fo}. Let f e H be a function which has minimum delay. We have, f is an optimal constrained wire-sizing function.

(sP

R 5

I____

C, + c 0 Li,

Lemma 1 The six feasibility conditions 0 {.(PA, 4PB, (PC, S AB, VPBC, (PABC} cover all possible L > 0. Moreover, if L satisfies cp, where z E F, then f is legal and is of type-z.

VA

+

) cnL

L )n

-O

Cn

nn

C-

,

I

Rd&}

InL COd rpL

I

is of moderate size, optimal wire-sizing function will change speakfrom type-AB to type-BC as we increase Rd CL Roughly ghysek ing, the larger the ratio R., the smaller the wire sizes. When the wire length L is very large, optimal wire-sizing function is most likely to be of type-ABC.

C

}

and and

CL

e

4

p

Application to Routing Trees

}d.

Table 2: Feasibility Conditions.

We also have the following interesting observations. In Figure 7, we show the relationships among the six types of optimal wire-sizing functions with respect to the three parameters: wire length L, driver resistance Rd, and load capacitance CL. The horizontal axis represents the ratio of the driver resistance to the load capacitance. The vertical axis represents the wire length L. Suppose we keep Rfixed CL and varies L. When L is small, optimal wire-sizing functions tend to be of type-A, type-B, or type-C. As we increase L, wire-sizing function types will change to type-AB or type-BC when is of moderate size and will be of type-ABC when L

L

is large. Suppose we keep C fixed and varies Rd. When CL

L

is small, as we increase Rd optimal wire-sizing function will change from type-A to type-B and then to type-C. When L

Our wire-sizing formula can be applied to size a general routing tree. Recently, [2] presents a wire-sizing algorithm GWSA-C for sizing the wire segments in routing trees to minimize weighted delay. Each segment in the tree is sized uniformly, i.e. uniform wire width per segment. Basically, GWSA-C is an iterative algorithm with guaranteed convergence to a global optimal solution. In each iteration of GWSA-C, the wire segments are examined one at a time; each time a wire segment is uniformly re-sized optimally while keeping the widths of the other segments fixed. We can incorporate our wire-sizing formula into GWSA-C to size each wire segment non-uniformly. When we apply our wiresizing formula to size a wire segment in a tree, Rd should be set to be the total (weighted) upstream resistance including the driving resistance, and the CL should be set to be the total (weighted) downstream capacitance, including the load capacitances of the sinks in the subtree. (See Figure 8.) It can be shown that this modified algorithm is extremely fast and always converges to a global optimal solution.

25

CL. while processing wire segment .3

Precision Requirement (pm) 0.1 0.01 0.001 0.0001 0.00001 0.000001 I-

the downstream capacitance of W3

Rd. the upstream resistance of w 3 2 . 'I ';

4

7

WI

Wn

I

Table 4: The number of Newton-Raphson iterations.

35

Experimental Results and Concluding Remarks

a

E V I

We implemented and tested our algorithm in C on a Sun Sparc 5 workstation with 16 MB memory. The parameters used are shown in Table 3. The results are given in Table 4. The first column labeled "Precision Requirement" specifies the required accuracy of the wire width values. The second column shows the number of Newton-Raphson iterations. Our results show that even under very strict precision requirement the number of iterations is at most 7. Thus, in practice, the optimal wire-sizing functions can be computed in 0(1) time and hence our method is extremely fast. We also performed experiments to compare the nonuniform wire-sizing solutions with the uniform ones in which wires are chopped into different number of segments. The results are drawn in Figure 9. Wire widths are plotted as the functions of positions on the wire segments. It shows that the more segments a wire is chopped into, the closer the solution is to our formula. When the wire is chopped into 1000 segments, it can be shown that the corresponding curve and the non-uniform wire-size curve are almost identical. Finally, we note that the authors in [8] independently solved the unconstrained wiring-sizing problem using a different approach.

Unit Resistance: Unit Capacitance: Minimum Wire Width: Maximum Wire Width: Driver Resistance: Load Capacitance:

|

W

Figure 8: Sizing a segment of a routing tree.

5

# of iterations 5 5 5 6 6 D

25

15

Figure 9: Approximating non-uniform wire-sizing by uniform wire-sizing.

0.008 Q£/pm 6.0 * o0-,' F/pm I 1.0 pm 3.5 pm 25 Q 1.0 * 10-2 F

Table 3: RC Parameters

References [1] J. Cong and K. Leung, "Optimal wiresizing under Elmore

delay model," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 14(3), pp. 321-336, 1995.

[2] Chung-Ping Chen, D. F. Wong. "A fast algorithm for optimal wire-sizing under Elmore delay model" Proc. IEEE ISCAS, 1996. [3] W. C. Elmore, "The transient response of damped linear networks with particular regard to wide band amplifiers", J. Applied Physics, 19(1), 1948. [4] N. Menezes, S. Pullela, F. Dartu, and L. T. Pillage, "RC interconnect syntheses-a moment fitting approach", Proc. ACM/IEEE Intl, Conf. Computer-Aided Design, November 1994. [5] N. Menezes, R. Baldick, and L. T. Pillage, "A sequential quadratic programming approach to concurrent gate and wire sizing", Proc. ACM/IEEE Intl, Conf. ComputerAided Design, 1995. [6] R. S. Tasy, "Exact zero skew," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Feb. 1993. [7] Q. Zhu, W. M. Dai, and J. G. Xi, "Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models," Proc. IEEE Intl. Conf. on Computer-Aided Design, pp. 628-633, 1993. [8] J.P. Fishburn and C.A. Schevon, "Shaping a distributedRC line to minimize Elmore delay", IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 42, No. 12, pp. 1020-1022, December 1995. [9] A. Ralston and P. Rabinowitz, A First Course in Numerical Analysis, McGraw-Hill, 1978.

26

Reducing Coupled Noise During Routing Ashok Vittal and Malgorzata Marek-Sadowska Department of Electrical and Computer Engineering, University of California Santa Barbara, CA 93106 Abstract - The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of tolerable coupled noise on drive strength, the possibility of using overlaps to reduce susceptibility to noise and the use of jogs. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which is more accurate than the charge sharing model used in previous work. These results lead to a new problem formulation for interconnect synthesis constrained by coupled noise. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to make better informed decisions. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances.

smaller set of situations where simulation needs to be performed. This verification issue is addressed in Section II. As coupled noise pulse widths are typically much smaller than the clock period, the dynamic noise margin [2], [3], [6] rather than the static noise margin, applies. The noise susceptibility of digital logic gates is usually specified by a noise amplitude - pulse width plot, defining the allowed region of operation. Larger noise pulse amplitudes can be tolerated as the pulse width gets smaller. Therefore, given a layout, we need to be able to calculate the pulse width and amplitude on a victim net. We derive a new expression for the noise pulse integral and a simple bound on the noise pulse amplitude in Section II. Our expression does not involve the solution of the differential equations characterizing the system as in [7] and is simple enough to be used during design and verification. Our noise amplitude bound could be considered to be analogous to the signal delay bounds in [8] which have been the foundation for many interconnect design algorithms. We have developed a router guided by our new measure and use our analysis results to show that the charge sharing model used in previous work on coupled noise-driven layout ([9], [10], [11]) is extremely pessimistic. Coupled noise control during layout is critical as the noise pulse amplitude and width induced on a quiet (nonswitching) line by an adjacent switching line is primarily a function of the layout. Other researchers have also identified coupled noise as a major problem during layout synthesis. As parasitic control in analog circuits is critical to correct operation, there has been work on the layout of analog systems considering coupled noise. In [12], a maze router with limited analysis capability is proposed to avoid bad routes. Maze routing does not scale well to digital complexities, so that these methods cannot be used. Besides, the use of a simulator in an optimization loop is computationally too expensive. The post-route spacing algorithm proposed in [13] considers crosstalk while compacting a given layout. We address the issue of routing considering coupled noise in this paper. Our channel routes could use this post-processing for further improvement. Other approaches include track permutation of a given channel route [9] to maximize the minimum coupled noise slack among all nets using integer linear programming, the switchbox version [10] of the ILP formulation and the modification of a graph-based approach (Glitter [14]), to include coupled noise costs[1l]. These two approaches are reviewed next. The elegant integer linear programming formulation [9] finds an optimal track permutation, given an initial channel

I. Introduction* Coupled noise between signal lines is a potential cause of failure in high speed electronic systems [1], [2], [3], [4]. Aggressive scaling in lateral dimensions with relatively unchanged vertical dimensions in sub-micron CMOS VLSI causes the coupling capacitance between adjacent lines to become a significant fraction of the capacitance to the substrate [5]. This leads to increased coupled noise.Further, increasing system speeds cause signal spectra to exhibit significant energy at higher frequencies leading to increased coupled noise. When high-speed ECL circuits and lowpower CMOS circuits are integrated on a chip, the small noise margins of ECL, the large logic swings of CMOS circuits and the high current drive of ECL drivers create coupled noise problems. Besides, increasing system complexities lead to increased coupled energy, again increasing the need for techniques aimed at reducing the deleterious effects of coupled noise. It is important to be able to quickly check if a given routing solution will not lead to logic failures caused by coupled noise. A layout can be certified correct either using a simple capacitive charge sharing model to compute noise or using exhaustive simulation. The simulation method is timeconsuming and the charge sharing model is very pessimistic, so there is a need for simple methods which provide better accuracy. Such a method could at least identify a much *. This work was supported in part by the Defence Advanced Research Projects Agency under contract DABT63-93-C-0039, the National Science Foundation under Grant MIP 9419119 and in part by LSI Logic & Silicon Valley Research through the California MICRO program.

27

be assumed. The total coupled noise voltage can then be computed as the sum of the individual coupled noise contributions of each of the aggressors, rather than having to look at all possible switching combinations (there are exponentially many such scenarios which would otherwise need to be analyzed). As lines immediately adjacent to the victim net act as shields, we need to consider only the immediately adjacent lines. In Figure 1, therefore, our analysis omits the coupled noise contribution from net Z. We now analyze the coupled noise contribution from one aggressor net, with all other aggressor nets grounded. The total peak noise voltage and pulse width will later be obtained using superposition. The equivalent circuit is as shown in Figure 2. The attenuation along the interconnect is neglected (line lengths of a few mm or less). The resistance RI is the driver resistance of the aggressor (typically a few tens of kiloohms for CMOS and a few hundreds of ohms in ECL) and Cl is the total line capacitance of the aggressor net. X is the coupling capacitance and is proportional to the overlap length. R2 is the output resistance (typically several tens of kiloohms in CMOS and a few hundreds of ohms in ECL) of the victim net and C2 is the capacitance to ground of the victim net. RI and R2 are obtained from the transistor characteristics and the capacitances per unit length are obtained either from tabulated experimental results or from a commercial field solver. While RI is the familiar driver resistance (of the aggressor net), R2 is the output resistance (of the victim net). The ratio RI/R 2 can vary over a wide range (especially when transistor sizing optimizations are resorted to) as these are resistances corresponding to two different logic gates. We are interested in computing the peak voltage and the noise pulse width at node 0 for a unit step input.

route. The track permutation maximizes the minimum crosstalk slack among all nets. However, this is sub-optimal as finer grain permutations - track segment permutation rather than track permutation may lead to better results. Section III will show an example for which no track permutations are possible, while track segment permutations lead to optimal results. In [10], track segment permutations in a switchbox are considered. In Section III, we show that even this method is sub-optimal because the initial route is not driven by coupled noise considerations. Besides, drive strengths are not considered and Section II will show that the coupled noise model is simplistic. The channel routing heuristic presented in [11] modifies a well-known channel router [14], [15] to reflect coupled noise issues. The important notion of digital sensitivity is also introduced - logic and temporal information may make coupling between certain pairs of nets tolerable, i.e., noise coupled to a net may not lead to system malfunction if, for instance, the signal isn't being latched at that time. A capacitive charge sharing model is used to find the amplitude of the noise pulse: we show that this model is very pessimistic. The expression which we derive cannot be broken down into pairwise potential coupled noise contributions as required by their formulation. This is intuitive because the coupled noise contribution of a net adjacent to a victim net depends on other adjacent nets as well. This makes pairwise decomposition of noise required by the graph-based approach impossible. Coupled noise is considered only between adjacent horizontal segments. As the worst case has to be considered for coupled noise, the router may end up with poor routes as shown in Section HI. Besides, shields are assumed to be available wherever necessary and the issue of hooking up the shields to some reference supply voltage is not considered. We derive new results for the analysis of coupled noise pulse height and width in Section II, enabling the verification of dynamic noise margins. Section III uses these expressions to show that routing driven by the new model could be significantly better than routing driven by the charge sharing model. A new algorithm is also proposed and experimental results are presented. Section IV concludes with a discussion on the likely impact of this paper.

to

C2

Figure 2. Equivalent circuit for calculating coupled noise The following two theorems lead to expressions for the coupled noise pulse amplitude and width. Both the expressions are derived from the differential equations characterizing the system and no explicit time-domain solution is necessary. Theorem 1 The integral of the coupled noise over time is given by

II. Coupled noise calculation 2.1 Coupled noise bounds Consider a quiet victim net coupled to several other "aggressor" switching nets, as shown in Figure 1. Net V is

= R,

fvodt

V

A,

A

m

|

Proof: The nodal equation for the output node 0 is dv

Figure 1. A victim net V coupled to aggressors

(1)

X

(X + C2)

Al-A4

-

v + --

dv (X

-

)

=

0

Integrating this over positive time, using the initial conditions (all voltages at 0) and the final values (VO at 0 and Vm at I)and simplifying, we get the result

coupled to nets Al through A4 . Let the rise times of the signals be much larger than the propagation delays, so that a lumped RC model is adequate[3]. As the noise pulse is essentially a small signal, linearity and time-invariance can

Clearly, the proof holds even if the input has non-zero

rise time.

28

The possibility of using overlaps with nets switching slowly to decrease the overall crosstalk on a victim net. Note that overlap is never used to advantage by any of the previous routing methods. Our expression shows that increasing overlap length increases the crosstalk contribution of that particular aggressor. However, it also increases the line capacitance of the victim net and could make the sum of crosstalk contributions of other nets smaller! Thus, not all overlap is bad. Overlap with slow switching nets reduces the noise susceptibility to coupling from other nets. The limiting case of a slowly switching net is, of course, a ground net which serves to increase the line-toground capacitance of the nets adjacent to it. Nets which switch slowly are therefore a resource which needs to be shared among the nets which are coupled noise-critical. Figure 3 shows SPICE results which verify this. Overlap with S reduces the peak noise coupled to V from 1.22V to 0.93V - a significant reduction.

Theorem 2 The peak noise pulse height is bounded above by P

C2 I

(I

+-+-

X

(2)

C,

R +-)

R2

X

Proof: When the coupled noise pulse is at its maximum, the derivative of VO with respect to time is zero. Using this in the nodal equation at 0, we get VP

dv.

-

= x

R2,

-

dt v0 =VP

From the nodal equation at M, we get I-v

dv

dt vo= VP

RI

'

Vp V

(X + C,)

Using the two equations above, we get R2 V

=

R. R

X

(I

(X + C1 )

VO

0

P

The equation at 0 can also be written as v, +

ox

v.

V, + A = X

Vm.,

I... .L.

L.LA.

A.,

In order to utilize this degree of freedom, jogs or doglegs may be essential. For instance, if a net with a stringent noise margin is being routed through a channel which has only two slowly switching nets, one on the top left and the other on the bottom right of the channel, the net would have to be routed with a jog if its coupled noise constraint is to be satisfied. Note that the graph-based solution does not introduce jogs and would therefore be sub-optimal. The use of a purely capacitive charge sharing model may lead to incorrect conclusions about the coupled noise. For instance, the charge sharing model may predict that adjacency to net a is better than adjacency to net b, but the actual situation might be the opposite due to a larger drive resistance or line capacitance of net b. The noise calculations based on a capacitive charge sharing model may, therefore, show poor fidelity to the actual coupled noise. Figure 4 shows SPICE simulations to support this.

x x+

.

in (a), while in (b) it overlaps with only F. Noise in (a) is smaller.

v=

The term A is the integral of the noise pulse till the time when the maximum is reached and is strictly positive. Neglecting A and substituting for the voltage at M when the noise pulse reaches its maximum and rearranging, we get the required upper bound.E Note that in Theorem 2, when RI/R 2 = 0, the expression for the peak coupled noise voltage reduces to vP =

2

(b) time IOns Figure 3. Increased overlap leading to smaller total coupled noise The victim net, V,overlaps with the slow S net and the fast F net

Using this equation with t equal to the time when the coupled noise pulse reaches its maximum, we get (X + C 2 )

. . . . . . . . . . 2

0X v dt = X

-

.. . . . . ...

v

(a)

t

(X + C 2 )

3

v

=" V

C2

which is similar in form to the capacitive charge sharing expression. However, in this expression, C2 is the sum of the line-to-ground capacitance and all the line-to-line couplings from lines adjacent to line 2 (other than line 1). The pairwise capacitance ratio used in [11] is, therefore, pessimistic even in the limiting case of a coupled node with infinite output resistance. As the expression depends on other line-to-line couplings, the decoupling of total noise into independent pairwise contributions is not possible. The noise contribution depends on the other lines adjacent to the aggressor net and this cannot be handled by any graph-based approach - the formulation would need to be based on hypergraphs With line-to-line couplings becoming a significant fraction of lineto-ground capacitances in sub-micron ICs, the graph-based approach is less applicable. 2.2 Design implications Theorems 1 and 2 lead to several interesting design implications. These include:

v

+ X

Dox

1t 3.6 (a)

Db

II

I

time Figure 4. Pure charge sharing model exhibits poor fidelity when driver sizes vary. (a) shows twice the overlap as (b), but with a weaker driver. The coupled noise is larger for (b).

. The drive strength of ECL gates is equal to their output resistance. In this case, the expression shows that it is use-

29

ful to route nets of equal drive strengths adjacent to each other. In this way the ratio RI/R 2 is not too large when either net is considered as the victim net. Thus the optimal track assignment of a set of equal length nets entering and leaving a channel (with no other connection to be made) is obtained by sorting in order of drive strength. * Coupled noise is less of a problem for strongly driven nets. These nets have small R2, so that the peak coupled noise voltage is smaller and the noise integral is proportionately smaller. * Longer tolerable overlap lengths are obtained than using the charge sharing model. This could lead to more flexible routing. * Coupled noise could be a problem for all net lengths as it depends on the ratio of the line-to-line capacitance to the line-to-ground capacitance. The fidelity of the new expressions are evaluated next using comparisons with exact analytical solutions and SPICE simulations for 0.5 micron CMOS. Figures 5a, 5b and 5c compare the peak noise voltage computed with the capacitive charge sharing model and the new expression for the practical range of parameter ratios. On average, the upper bound is a factor of 2.5 smaller than the pessimistic prediction of the charge sharing model.

25

charge sharing model

\ \

Vu)

output voltage and the noise pulse are shown. The interconnect is modelled by 100 distributed LC sections for the SPICE simulation. The peak noise pulse height is 0.7V and the equivalent pulse width is 4 ns. The peak pulse height is calculated by our formula to be IV. The capacitive charge sharing model predicts 1.65V peak pulse height and pulse width equal to the input pulse width (iOns). Note that the SPICE results are consistent with a finite output resistance the noise voltage discharges before the end of the clock period.

05 I

1

7

Cn

A

2

,d

Normalize coupled noise

15 '.1 05 1

v,

2

charge sharing model

'.2

I

I I

T N. - A.

III

25

entire length. The total line-to-substrate capacitances are 70fF and the line-to-line coupling capacitance is 50fF. The MOSFET models are from MOSIS. The SPICE simulation results for the circuit is shown in Figure 7a and the simulation results for the RC network are shown in Figure 7b. The

Figure 7. Model fidelity. a) RC equivalent circuit. b) Simulated output and noise voltage.

15 '.1

5a. Coupled noise variation with RI/R 2

Figure 6. Coupled noise in 0.5 micron CMOS. a) Circuit configuration. b) Simulated (SPICE) output and noise voltage.

n-

4 4,'f'0*(tn!6

1.3 Normalize( coupled '.2 noise

Consider the case of two minimum size driver-receiver pairs in 0.5 micron CMOS coupled capacitively as shown in Figure 6. The lines are 1mm long and run parallel along the

III. Routing to minimize coupled noise new bound l

CI/C2

4

h

K

Sb. Coupled noise variation with C1/C2

.

..

H

..

.9

10(

30

Equations (1) and (2) in Section II could be used by coupled noise-driven routers. As we are interested in large complexities, coupled noise should be considered when an entire set of nets is being routed. We, therefore, demonstrate the use of the new expressions in a channel router. We must emphasize, however, that other routers could also utilize the formulas. We begin by showing that the two coupled noiseconstrained channel routers proposed so far are incapable of using these new expressions. 3.1 A pathological instancefor the ILPformulation The integer linear formulation for finding track permutations is not amenable to change using the new expressions as the noise coupled to a net is no longer a sum of weighted overlap lengths and an intractable non-linear programming formulation becomes necessary. Even for the ILP case, the

channel routing instance in Figure 8 shows an example where track segment permutation rather than track permutation is necessary. The C nets are critical but have been routed

1i DJ A~

*---

S I. 1 a) Crosstalk bounds violated on C nets

E;

this problem is NP-complete when total coupled noise is to be minimized and provide a travelling salesperson solution. This solution is of independent theoretical interest and can be used even in the absence of coupled noise (with crossing count based costs, for instance). 3.3 Wire ordering to minimize total coupled noise Consider the problem of ordering the nets entering a channel [17], [18]. The ordering determines the aggressor nets for each victim net and we wish to minimize the "total" crosstalk. Formally, the problem is stated as the MCWO (minimum crosstalk wire ordering) problem below. Instance: An NxN crosstalk matrix [C] where C(i,j) specifies the crosstalk on net i due to the adjacent j net and a number TC. Question: Is there an ordering of the nets such that the total crosstalk is less than TC. Theorem 3 [MCWO] is NP-complete. Proof: Reduction from the travelling salesperson problem with distance matrix C(ij) and maximum Hamiltonian path cost of TC. a The proof of Theorem 3 enables the use of the heuristics developed for the travelling salesperson problem to obtain a wire ordering. Note that this NP-completeness result does not use vertical constraints as in [11] and is therefore a stronger result. Vertical constraints make channel routing NPcomplete and our result shows that crosstalk independently makes the problem intractable. 3.4 Greedy channel routing The pivotal idea of greedy channel routing is to route the channel using a column scan and completely routing a column before moving on to the next, introducing jogs when necessary. In order to consider coupled noise, the track assignment during the scan should attempt to satisfy crosstalk constraints on all nets. This is facilitated by the fact that precise adjacency information is available for the columns already routed. Equations (1) and (2) of Section II can now be used to dynamically identify the nets which are crosstalk-critical and appropriate jogs used to diminish the noise coupled onto these nets. The cost function used is based on our bound. Theorem 4 gives a sufficient condition for any routing solution to be free of coupled noise problems. We first define the notation used in the statement of the Theorem. A(i) is the set of aggressor nets for net i and comprises all nets routed adjacent to it. X.- is the coupling capacitance between nets i and j, Cg is the line-to-ground capacitance per unit length, li is the length of net i, Rjo is the output resistance of the driver for net j, Ri is the driver resistance for net i and E i is the maximum amplitude function dependent on the noise integral divided by the output resistance. E i is determined by simulation for each receiver and is typically of the form shown in Figure 10 below. Note that this function is a property of a net. For a multi-pin net, the lumped capacitance model leads to identical coupled noise waveforms on all receivers. Therefore, we find the allowed coupled noise on the net for a given total coupling to be equal to the corresponding smallest allowed noise amplitude. For nets with bidirectional drivers,

metall line metal2 line vvia

Lu Lurs,

b) Better routing satisfies crosstalk bounds Figure 8. Track segment permutation vs. track permutation. In (a), the tracks on the top half cannot be swapped with the tracks on the bottom half due to vertical constraints imposed by the U and D nets. Tack segment permutations are used to get the solution in (b) which satisfies crosstalk bounds. adjacent to each other by a coupled noise-oblivious router. The S nets, had they been interposed between the C nets, could have served to reduce the coupled noise. Track permutations to alleviate coupled noise on the C nets are not possible as there are vertical constraints imposed on every pair of upper and lower tracks by the nets on the right. If track segment permutations had been allowed, the routing shown in Figure 8b becomes possible. Note that coupled noise is particularly a problem when the layout is dense, as in the Deutsch difficult example. On such benchmarks, the ILP formulation performs poorly as its solution space is limited by the stringent vertical constraints imposed, much like the instance shown in Figure 8a. 3.2 Pathologicalinstancefor the graph-basedapproach Graph-based approaches cannot handle interactions over sets of nets when the set size is larger than 2, so that the work presented in [14], [15], [11] is less powerful. A pathological instance for the algorithm is shown in Figure 9. YZ

YZ

11

1

Z

Z

*

(a) (b) Figure 9. The importance of using jogs or doglegs when routing is constrained by coupled noise. a) No jogs or doglegs are used leading to large coupled noise. b) A dogleg in net Z reduces coupled noise. The primary reason for the sub-optimality shown in Figure 9 is that the algorithm constrains the entire net to run on a single track, which makes the combination of coupling constraints and routing constraints difficult to handle. We therefore propose the use of a new channel router which maintains exact adjacency information at each stage and can introduce jogs when necessary, either motivated by coupled noise issues or for routing purposes. It is based on the "greedy" channel router described in [ 16]. We briefly review the work presented in [16] and outline a new technique to find the optimal "greedy move". We begin with the problem of wire ordering at the ends of the channel - we show that

31

the maximum amplitude can be similarly defined as the worst case scenario - the smallest allowed amplitude for that particular coupled capacitance for every possible driverreceiver combination. In short, the function Ei serves to formalize the dynamic noise margin concept and is defined over coupling capacitance space as this is easily derivable from the layout.

This is the standard greedy routing algorithm with two novel features. . The initial wire ordering is not simply clustering in the middle and uses the heuristic motivated by Theorem 3. . The jog insertion phases uses the dynamically updated coupled noise information to find an optimal jog, if necessary. to reduce coupled noise. Upper and lower bounds on the coupled noise expression are determined along with upper and lower bounds for the right hand side of the inequality in Theorem 4. This allows quick and accurate identification of coupled noisecritical nets. In order to keep the number of vias required from becoming excessive, only two jogs per column for coupled noise reduction are allowed. Tradeoff exploration of jogs for coupled noise reduction is possible by modifying the jog insertion heuristic. Almost every stage of the greedy channel router can be modified to reflect coupled noise concerns. Our implementation changes only two of the phases.

Maximum noise

amplitude Noise pulse width

X

Figure 9. Transforming the A-W plot to a Ei vs. X plot Theorem 4 A routing solution will not fail due to coupled noise if, for all nets i, Rj s

je~)

(

where

R

Cj .Xi

C' -I <Ej( + -+ij )

E jle A (i)

X'

Ci = CX 1i +

A

3.5. Channel routing results

In this sub-section we describe the experimental results obtained using our channel router. We compare the greedy channel router oblivious to coupled noise with the algorithm outlined in the previous sub-section, both implemented in C. The implementation in [11] was not available[19] and therefore could not be compared. The average normalized (to the supply voltage) coupled noise results are presented in Table 1. On average, the algorithm leads to about 22% lower cou-

X jj)

xj

j e A (i)

Proof: The sum of the left hand side of the inequality is just the sum of the upper bounds on noise contributions from all aggressor nets, from Theorem 1. This amplitude must be smaller than the maximum allowed amplitude for this amplitude-pulse width product. The expression for the amplitudepulse width product is substituted from Theorem 2 to obtain the result.C Theorem 4 directly suggests a linear time verification procedure which scans the layout and updates the corresponding maximum peak noise (the right hand side of the inequality in Theorem 4) and noise sums (the left hand side of the inequality) for each net. This verification procedure is optimal in time complexity as any verification procedure has to scan the entire layout before pronouncing it correct. The layout determines the sets A(i), the Cis and the Xijs. Note that during any stage of a greedy routing process, we can determine upper and lower bound on all relevant capacitances to find all nets which are potentially coupled-noise critical. An optimal jog is inserted to improve the coupled noise situation. The algorithm template is defined below. Algorithm Xtinguish

TABLE 1. Channel routing results Normalized average crosstalk CMOS ECL Bench- # #Colmark nets umns Xtinguish Greedy Xtinguish Greedy

Input: Channel routing instance, technology parameters Cg, Ri, Xo, X functions. Output: Channel routing solution satisfying crosstalk bounds. begin{ initial wire ordering using a travelling salesperson heuristic route channel from left to right( make top and bottom connections collapse split nets add jogs to reduce coupled noise I/ this is new add jogs to reduce split net range add jogs to raise rising nets and lower falling nets widen channel if necessary proceed to next column 1 update coupled noise information H/this is also new I

3a

30

45

.136

.166

.072

.097

3b

47

62

.148

.155

.085

.087

3c 3cr

54 54

103 103

.154 .146

.239 .227

.088 .091

.138 .131

ddr

72

169

.217

.242

.131

.137

exI

235

417

.083

.091

.051

.052

ex2

282

421

.063

.066

.033

.037

ex3

291

421

.043

.067

.028

.039

ex4

270

421

.060

.072

.036

.042

nI

77

139

.185

.262

.099

.150

n2

77

117

.115

.155

.071

.090

n3

78

123

.169

.157

.096

.091

n4

74

150

.197

.257

.119

.147

rl

77

139

.187

.252

.109

.143

r2

77

117

.124

.152

.070

.090

r3

78

123

.153

.158

.091

.092

r4

74

150

.218

.244

.121

.140

r5

112

150

.131

.141

.076

.082

157

.229

.232

.131

.132

Deutsch 52

32

References

pled noise for CMOS and ECL. Drive strengths are assumed to vary from lx to lOx. The number of tracks is typically the same for both solutions, i.e., there is no area penalty. The time required for each of these is at most a few seconds on a DEC 3100 workstation. The parameters used are representative of 0.5 micron CMOS and ECL.

[1] 1. Catt, "Crosstalk (noise) in digital systems", IEEE Transactions on Electronic Computers, Vol. 16, No. 6, pp.743-763, 1967. [2] P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits", IEEE Journal of Solid-State Circuits, June 1994, pp. 655-662. [3] S.I. Long and S.E. Butner, Gallium Arsenide Digital IC Design, McGraw-Hill, 1990, Ch. 5. [4] R.R. Tummala and E.J. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, 1989. [5] L. Gal, "On-chip crosstalk - the new signal integrity challenge", Proceedings of the Custom Integrated Circuits Conference, 1995, pp. 12.1.1 - 12.1.4. [6] G.A. Katopis, "Delta-I noise specification for a high-performance computing machine", Proceedings of the IEEE, September 1985, pp. 1405-1415. [71 T. Sakurai, "Closed form expressions for interconnection delay, coupling and crosstalk in VLSIs", IEEE Transactions on Electron Devices, Vol. 40, No. 1, 1993, pp. 118-123. [8] J. Rubinstein, P. Penfield and M.A. Horowitz, "Signal delay in RC tree networks", IEEE Transactions on Computer-Aided Design of ICs and Systems, Vol. 2. No.3, 1983, pp. 202-210. [9] T. Gao and C.L. Liu, "Minimum crosstalk channel routing", Digest of Technical Papers of the International Conference on Computer-Aided Design, 1993, pp. 692-696. [10] T. Gao and C.L. Liu, "Minimum crosstalk switchbox routing", Digest of Technical Papers of the International Conference on Computer-Aided Design. 1994, pp. 610-615. [11] D. Kirkpatrick and A. Sangiovanni-Vincentelli, "Techniques for crosstalk avoidance in the design of high-performance digital systems", Digest of Technical Papers of the International Conference on Computer-Aided Design. 1994, pp. 616-619. [12] S. Mitra, S.K. Nag, R.A. Rutenbar and L.R. Carley, "Systemlevel routing of mixed-signal ASICs in WREN", Digest of Technical Papers of the International Conference on Computer-Aided Design, 1992, pp. 394-399. [13] A. Onozawa, K. Chaudhary and E.S. Kuh, "Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSIs", IEEE Transactions on CAD of ICs and Systems, Vol. 14, No. 6, 1995, pp. 707-719. [141 H.H. Chen and E.S. Kuh, "Glitter: a gridless variable width channel router", IEEE Transactions on Computer-Aided Design of ICs and Systems, Vol. 5, No. 4, 1986, pp. 459-465. [15] U. Choudhury and A. Sangiovanni-Vincentelli, "Constraintbased channel routing for analog and mixed analog/digital circuits", IEEE Transactions on Computer-Aided Design of ICs and Systems, Vol. 12, No. 4, 1990, pp. 497-5 10. [16] R. L. Rivest and C.M. Fiduccia, "A greedy channel router", Proceedings of the DAC, 1982, pp. 418-424. [17] P. Groenveld, "Wire ordering for detailed routing", IEEE Design and Test of Computers, December 1989, pp. 6-17. [18] M. Marek-Sadowska and M. Sarrafzadeh, "The crossing distribution problem", IEEE Transactions on Computer-Aided Design of ICs and Systems, Vol. 14, No. 4, 1995, pp. 423-433. [19] D. Kirkpatrick, private communication, May 1995. [20] D. Theune, R. Thiele, W. John and T. Lengauer, "Robust methods for EMC-driven routing", IEEE Transactions on Computer-Aided Design of ICs and Systems, Vol. 13, No. 11, 1994, pp. 1366-1378. [21] G.L. Matthaei, J.C.-H. Shu and S.I. Long, "Simplified calculation of wave coupling between lines in high-speed integrated circuits", IEEE Transactions on Circuits and Systems, Vol. 37, No. 10, 1990, pp. 1201-1208.

IV. Discussion and conclusions The analysis results of Section II enable quick computation of bounds for coupled noise which are intuitive and enable better design. We believe that these bounds will spawn a new class of coupled noise-constrained layout systems. Section III has shown that routing algorithms could utilize these bounds to improve layouts. While the focus has been on channel routing, this is by no means the only routing formulation which could be modified to include coupled noise. Area routers, switchbox routers, etc. could also use our work. We believe that our channel routing results of Section IV will lead to a paradigm shift away from graph-based approaches to algorithms which maintain exact adjacency information, especially with coupled noise becoming a major issue. We have considered only channels where a lumped capacitance model is appropriate and the question of long channels remains open. We are currently addressing the issue of bounds on crosstalk for layout where transmission line analysis is necessary. This is particularly essential for PCBs and MCMs. It is usually handled by grouping nets into net classes and conducting simulations to determine allowable overlap lengths [20]. It appears to be difficult to obtain simple, elegant bounds for these cases which capture relevant parameters and are accurate. The RC model is considerably in error for these cases[21] and could be optimistic. The wide variety of termination possibilities of these lines also make good abstractions difficult. For sub-micron VLSI, however, our methods appear to be adequate. Timing analysis can be used by routers [5], [11] to identify pairs of nets between which interaction is allowed. Our algorithm can be extended easily to handle this information too. Post-layout optimization for crosstalk such as the work in [9] and [13] could be used to further improve our results. Note that jog insertion is not attempted by these techniques. Our algorithm addresses this issue and therefore complements these methods well. Besides, our models (after suitable linearization) should improve the results [9] and [13] obtain. In conclusion, we have presented new results for coupled noise computation in VLSI circuits. We have used these to show several novel design implications and have presented innovative routing techniques for coupled noise reduction.

Acknowledgments We would like to thank D. Kirkpatrick of UC, Berkeley for providing the benchmarks and for many discussions. We would also like to thank C.-C. Lin of UCSB for providing us his greedy channel router implementation.

33

SIMULTANEOUS TRANSISTOR AND INTERCONNECT SIZING USING GENERAL DOMINANCE PROPERTY Jason Cong and Lei He Department of Computer Science University of California, Los Angeles, CA 90095 *

given cell library for performance optimization. Recent gate sizing works can be found in [1, 2, 3]. However, all these works ignored the sizing of interconnects. The interconnect sizing problem, often called the wiresizing problem, was first introduced in [6, 7] where the authors developed the first polynomial-time optimal wiresizing algorithm to minimize the weighted Elmore delay between the unique source and a set of critical sinks. Later on, the wiresizing problem to minimize the maximum delay along a RC tree was formulated as a posynomial programming problem and solved in [12] by the sensitivity-based algorithm similar to that in [9]. In addition, the optimal wiresizing problem for interconnects with multiple sources was formulated and solved optimally in [4]. All these works, however, did not consider the need to size the driving transistors again after interconnects have been changed. Several recent studies consider both gate and interconnect sizing. The work in [5] formulated the simultaneous driver and wire sizing problem to size a single routing tree driven by a chain of cascaded drivers and developed an efficient optimal algorithm for both delay and power optimization. The authors of [11] studied the simultaneous wire sizing and buffer insertion problem for a single RC tree and solved it by a dynamic programming approach. Finally, the concurrent gate and wire sizing problem was studied in [15] using a sequential quadratic programming technique with the assumption that all transistor sizes in a gate are scaled isotropically. However, if we assume that all transistor in a gate are sized isotropically, it often leads to suboptimal designs, especially in the full-custom layout. In this paper, we shall study the simultaneous transistor and interconnect sizing (STIS) problem, where the optimal size for each transistor (instead of a gate or cell) and the optimal wire width for each wire segment are computed independently in order to achieve more optimized designs. We show that the STIS problem under a number of transistor and interconnect models has the objective functions of the following form:

ABSTRACT We study the simultaneous transistor and interconnect sizing (STIS) problem in this paper. We define a class of optimization problems named CH-posynomial programs and show a general dominance property for all CH-posynomial programs (Theorem 1). Based on this property, a set of lower and upper bounds for the optimal solution of a CH-posynomial program can be computed through local refinement operations very efficiently (in polynomial time). We show that the STIS problem under a number of transistor and interconnect models is CH-posynomial programs, for example, when we use the RC tree model for interconnects and the step or the slope model for transistors. Preliminary experimental results show that in nearly all cases, the optimal solution is achieved because the recursive application of local refinement operations using the dominance property leads to the identical lower and upper bounds. Moreover, the STIS algorithm produces the more optimized solution when compared with optimal transistor sizing only. 1. INTRODUCTION It is well recognized that interconnect delay has become the dominating factor in determining the circuit performance in deep submicron designs. We believe that the most effective way for performance optimization in deep submicron design is to consider both logic and interconnect designs throughout the entire design process. As part of our effort to develop a unified methodology and platform for simultaneous logic and interconnect design and optimization, we study the simultaneous transistor and interconnect sizing problem (STIS) for delay minimization in this paper. Most previous works consider the device sizing and the interconnect sizing problems separately. The device sizing problem includes both gate sizing and transistorsizing problems. In [9], the transistor sizing problem was formulated as a posynomial programming problem under the Elmore delay formulation for the RC tree model and solved by a sensitivity-based heuristics. Later, the authors of [13] applied the delay model developed in [10] for their transistor sizing formulation and solved it by a convex programming technique. The gate sizing problem usually assumes that all transistor sizes within each gate scale isotropically [14] (i.e., all transistor sizes increase or decrease by an uniform factor), or each gate has a discrete set of implementations (cells) with different driving capabilities pre-designed as a

f(X)

=

±. 5bhi .

E

p4i

pqji'

where

zi, z,

E X =

X,

YZP +

,z'i pti

,n)

p,q E (1,2,-,m),

apq,ij, bp,i and cp,i > °

(1)

and its coefficients have the following symmetry:

* This work is partially supported by ARPA/CSTO under contract J-FBI-93-112, the NSF Young Investigator Award MIP9357582 and a grant from Intel Corporation under the NYI matching award program.

1. apq,i > 0 if and only if a,,ji > 0; 2. b,i > 0 only if cp,, > 0 or a,,i, > O for any q and j;

34

3. cpi > 0 only if bpi > 0 or apq,i, > 0 for any q and j; Following the notations in [8], we call the class of functions as CH-posynomials.

Gate2

Definition 1 Eqn. (1) is a simple CH-posynomial if all coefficients are constants independent of X. Definition 2 Eqn. (1) is a general CH-posynomial if coefjicients are functions of xi and x, satisfying the following conditions: ap,,ij monotonically increases with respect to zx while monotonically decreases with respect to x,, and br,, monotonically increases with respect to xi while cp,, monotonically decreases with respect to xi.

M9

Gatel Gate3

M10

(a)

(b)

Figure 1. (a) the gate-level circuit diagram where (b) the gate2 and gate3 are fanout of gatel. transistor-level circuit diagram where gatel and the routing tree linked to its output comprise a DCConnected-Component DCC,. The output of gatel, denoted as N., is the root of the routing tree. The inputs of gate2 and gate3 are sinks of the routing tree.

Furthermore, we call an optimization problem to minimize a simple CH-posynomial as a simple CH-posynomialprogram, and to minimize a general CH-posynomial a general CHposynomial program. We study the following dominance property for CH-posynomial programs. Definition 3 (Dominance Relation) For two vectors X and X', we say that X dominates X' (denoted as X > X') if x, > z$ for all i.

2. FORMULATIONS We consider the CMOS static logic in this paper. Since the transistor channel length is usually fixed to the minimum feature size, we only allow the channel width to change during transistor sizing and shall use width to refer both the channel width of a transistor and the wire width of an interconnect. We will first formulate the delay as a function of the transistor/wire widths, then show the STIS problem for delay minimization is a CH-posynomial program.

Definition 4 (Local Refinement Operation) The local refinement operation of a solution vector X, with respect to any particularvariable zi and function f (X), is to minimize f (X) subject to only evaluating xi while keeping the value of any xj(j - i). We say that the result solution vector is the local refinement of X (with respect to zi). For simplicity of presentation. we shall use solution instead of solution vector.

2.1. Delay Formulation Because an MOS transistor is a voltage-controlled device, an MOS circuit can be partitioned into a number of DCConnected Components (DCCs) [18]. A DCC is a set of transistors and wires that are connected by DC-current paths containing only transistor channels or wires. The DC current can not cross the boundary of a DCC. In most cases, a DCC consists of a gate G and a routing tree connecting the output (denoted as N.) of G to the inputs of all gates driven by G (see Figure 1). Our delay computation is similar to that in the switch level timing analysis tool Crystal [16]. The delay will be computed based on a stage, which is a DC-current path from a signal source (either the Vdd or the ground) to the gate of a transistor, including both transistors and wires (see Figure 2). The delay of a stage is the summary of delays through all transistors and wires in the stage.

Definition 5 (Dominance Property) Let X* be the optimal solution to minimize f (X). If X dominates X*, a local refinement of X still dominates X*; If X is dominated by X*, a local refinement of X is still dominated by X* We proved the following important Theorem 1 that will lead to our STIS algorithm later on. Theorem 1 The dominance property holds for both simple and general CH-posynomial programs. The authors of [7] first proposed the dominance property for their single-source optimal wiresizing formulation. Our results greatly generalize the concept of the dominance property and reveal that the dominance property holds for a large class of optimization problems instead of the single optimization problem in [7], which is an instance of the simple CH-posynomial program. The dominance property leads to an efficient algorithm to compute a set of lower and upper bounds of the optimal solution to a CH-posynomial program by local refinement operations very efficiently (in polynomial time). The algorithm has guaranteed convergence and optimality and can be applied to many optimization problems in VLSI CAD and other domains. We will show that the STIS problem is CH-posynomial programs when we use the RC tree model for interconnects and the step or the slope model for transistors. Preliminary experimental results show that in nearly all cases, the optimal solution is achieved because the recursive application of local refinement operations using the dominance property leads to the identical lower and upper bounds. So the algorithm is optimal in the practical sense. Besides, the STIS algorithm produces the more optimized solution when compared with optimal transistor sizing only.

A. Delay through transistors A transistor can be modeled by the source-drain effective resistance r and the gate, source and drain capacitances cg, c, and Cd. Let 2 be the transistor width, r, c5 , c, and Cd can be written as the following: r

=

ro/x

C9

=

Cg5

X

CS

=

c'o

X

Cd

=

CdO

X

Where c,0, co and Cdo are the gate, source and drain capacitances for a unit-width transistor and can be viewed as constants without loss much accuracy. In addition, ro is called unit effective resistance that is defined in the following: Let

35

width x and length I are No M2

M6 M,9 (-)

N.

No

M3

H

M4

H (')

5

TO I/x

=

co

I

I + ci

I

Tk. Let Tk be the resistance of the uni-segment Ek with downstream node at Nk, the delay t(P'(No, N,)) along the

unique path PI(N0 , Nt) between node No and sink Nt is t(P'(N, N,)) =

:

Tk

(3)

.Ck

Nk EP'(NoTVt )

C. Delay through a stage (3), the delay (2) and Eqn. With respect to Eqn. t(P(NsNt), X) of stage P(Ns, Nt) can be written as according to [19]:

a rising input drive an inverter with total capacitance loading CL. If the 50% delay is 7, we say that r = r/CL is the effective resistance of the n-type transistor and the unit effective resistance ro is given by r x with x being the size of the n-type transistor. The unit effective resistance of the p-type transistor can be defined similarly by the delay under the falling input waveform. If X = {x1 ..-. ,xn} is the sizing solution for all transistors and wires, in general, ro shall be a function of X. For simplicity of presentation, we use rO instead of ro(X). However, it is worthwhile to mention that the unit effective resistance can consider the nonlinear characteristic of the transistor and the waveform slope effect. High accuracy can be achieved when using a table based method and more discussions will be given in Section 2.3. Under this transistor model, the gate part of a DCC becomes an RC network. Let PM(N,, N0) denote the path corresponding to all transistors in a stage. When computing the delay through these transistors, we only consider the effective resistances in path PM(N',, N) and the capacitances connected to nodes in path PM(N,, No). Let cl denote the total capacitance at node Nk due to source/drain capacitances of all transistors linked to Nk and C, the total capacitance due to the routing tree and its sinks. If R(PM (Ns, Nk)) is the total resistance of the partial path from the source N, to node Nk in path PM(N , Nk), the Elmore delay through path PM(Ns, Nk), denoted as t(PM(N,, No)) is =

=

C

We treat node N. as the root of the routing tree. Consider node Nk in the routing tree and let Tk denote the subtree rooted at node Nk (including node Nk). We denote the total capacitance within Tk as Ck, including the total wire capacitances and the total sink capacitances within

Figure 2. For DCCI in Figure 1, (a) a stage from the Vdd to the gate of transistor Mg; (b) a stage from the Vdd to the gate of transistor Mg; (c) a stage from the ground to the gate of transistor M 6 . Clearly, a transistor and a wire may belong to multiple stages.

t(PM(N,, No))

r

(4)

t(P(N,, NO)I X) t(PM(N,, No)) + t(P'(N,,.N,))

-

)+(1, X,

t,

Zfl t 0ia

1,

stS

hi

i

.

5i

I +

ixi

1i*l,*lJ ± h(

Ii

where xi is the width for a transistor Mi or a wire unisegment Ei, and 1i is the length for a wire uni-segment Ei or 1I= 1 for a transistor Mi. The coefficients f~st, f st gt /h't and hl t can be determined for stage P(N7 , Nt) with respect to the given rO, CgO, cA 1cdO co and cj for either transistors

or wires. 2.2.

STIS Formulation to Minimize Delay for Multiple Critical Paths In order to simultaneously minimize delay along multiple critical paths in a circuit, we propose to minimize the weighted delay t(X) of all stages in these critical paths:

t(X)

At t(P(N, Nt), X)(5)

= P(Ns,Nt)Ecr~itic. poth,

R(PY (N,, N,)) *c

where the penalty weight A"t indicates the criticality of stage P(Ns, Nt). A simplified weight assignment scheme is used in this paper. The weight of a stage is 1 if the stage is in a critical path, otherwise, it is 0. Let

N;,EPM(N-,N,)

R(PM(N,, No)) - Co

(2)

B. Delay through wires A routing tree is modeled as a distribute RC tree, similarly to [7, 4]. Each sink has an extra capacitance due to the gate capacitance of a transistor in a gate driven by the routing tree. Each wire segment is divided into a sequence of sub-segments. Each sub-segment is treated as a 7r-type RC circuit. Since we assume that the wire width is uniform within a sub-segment, a sub-segment is called a uni-segment. Note that the segment division controls how aggressively we perform wiresizing optimization. Clearly, if the unit-width unit-length wire has wire resistance ro, wire area capacitance co and wire fringing capacitance cl, the resistance r and the capacitance c for a uni-segment with

Fo(i, j)

=

E P(N

Fi (i, j)

=

G(i)

=

A' t . fV(i,j)

N,)ECriti-CI poths

I:

As' -fl t(i, j)

E

Ast , gst (i)

P(N, Ni)Ecr-iti-l poths

Hi (i)

=

5 P(N-Nt)EcriticaI poth,

36

A

t

t

.

hi (i).

Theorem 3 The STIS problem under a DP-slope model is a general CH-posynomial program with the dominance property.

and eliminate those terms independent of X, Eqn. (5) becomes

t(X) =

(6)

Foi, j) -

, I., +

+ aG(i)- I' +EHxl(i)

F (i, j) -

1

An example of DP-slope model is the model developed in [10]. For an inverter, let 7o be the delay under the step input and T, be the delay under the input with the transition time of s, [10] derived the following relation

I,

I'

7

= -

a

s

+

7Th

(7)

where ce is a constant determined by the technology. According to Eqn. (7), the unit effective resistance of a transistor is an increasing function of its input transition time. Because increasing the size of a transistor always increases the gate capacitance of the transistor, the input waveform will become slower due to a larger capacitance loading. Thus, the unit effective resistance of a transistor is an increasing function of its size. Since Eqn. (7) is an accurate solution for the inverter delay, we believe that at least most models to consider the waveform slope effect are DP-slope models. It is worthwhile to mention that if Eqn. (7) is used to compute a gate delay by assuming that the input switch time is twice the Elmore delay in the previous stage, like the transistor sizing formulation in [13], the path delay is a simple CHposynomial and the STIS problem to minimize the weighted delay of all stages in multiple critical paths is also a simple CH-posynomial program with the dominance property. However, Theorem 3 is much more general in the sense that it is applicable to a DP-slope model of any form and even without a closed form, as long as the effective unit resistance is an increasing function of the transistor size. A slope model without using a closed form will be discussed in Section 3.2. We would like to emphasize that the STIS algorithm will be developed for any DP-slope model which satisfies Theorem 3.

With respect to Eqn. (6), we define the following STIS problem to minimize delay through multiple critical paths: Formulation 1 Given a circuit and the lower and upper bounds for the width of every transistor/wire, the STIS problem is to determine the width for every transistor/wire (or equivalently, a sizing solution X) such that the weighted delay through multiple critical paths given by Eqn. (6) is minimized. In practice, it is often the case that we want to size the transistors and wires without increase in the layout area (using the free space in the current layout) or with bounded increase in the layout area. Therefore, there is an upper bound associated with each transistor and wire during the optimization. On the other hand, there is a lower bound associated with each transistor and wire due to the technology feature sizes and reliability concerns (like electromigration). Thus, the lower and upper bounds are used to handle these constraints. It will be seen later on that the lower and upper bounds are also the starting point for our STIS algorithm. 2.3. Dominance Property for STIS Problems Coefficient functions Fo, F1 , G and HI in Eqn. (6) are determined by parameters rT, c 9 Og,co,cdo, co and cl. Since we assume that the unit resistance ro for wires and all capacitance parameters are constants independent of X, the property of these coefficients will be determined by the unit effective resistance ro for the transistor. The unit effective resistance ro for the transistor defined in Section 2.1.A is a function of the input waveform slope. The step model assumes that the input waveform is always a step so that ro is a constant independent of the sizing solution X. As a result, all coefficients of Eqn. (6) are positive constants independent of X. Thus, we have the following theorem.

3. ALGORITHMS Generic Algorithms to Exploit Dominance Property For a CH-posynomial f(X), let X be the lower bound of its definition domain and X the upper bound. Since its optimal solution X* must be bounded by X and X, a simple algorithm scheme, the Local Refinement Algorithm (LRA) scheme, can be used to compute a set of tighter lower and upper bounds for X* by applying the local refinement operations beginning with either X or X. We introduce the concept of LR-tight bound in the following. 3.1.

Theorem 2 The STIS problem under the step model is a simple CH-posynomial program with the dominance property.

Definition 7 A lower or upper bound is LR-tight if it can not be tightened any more by a local refinement.

The step model has been used in [9] for transistor sizing and in wiresizing works [7, 12, 4] to model the driver. It was also used in [5] for simultaneous driver and wire sizing. However, the step input is just an ideal assumption and it is well known that the delay under real waveforms will be larger than that under the step input. In order to consider the waveform slope effect on the unit effective resistance for the transistor, we define the following DP-slope model for the transistor.

The LRA scheme is a greedy algorithm based on iterative local refinement operations. If beginning with a solution X = X, the LRA scheme traverses every xi in certain order to perform a local refinement operation on it. Because X is dominated by X' its local refinement is still dominated by X*. This process is repeated and X becomes increasingly closer to and remains dominated by X*. This process is stopped until no improvement is achieved on any ri in the last round of traversal and we obtain a LR-tight lower bound. A LR-tight upper bound can be obtained in the similar way by performing local refinement operations beginning with X = X. In essence, the LRA scheme generalize the greedy wiresizing algorithm GWSA first developed in [7]. If r is

Definition 6 The DP-slope model is a transistor model where the unit effective resistance for the transistor is an increasingfunction of its size. We proved that the STIS problem under a DP-slope model has the dominance property.

37

the maximum number of the possible evaluations for any xi(i = .1,.-. , n}), the LRA scheme will converge in the

in the technology. The allowed transistor widths are {0.5gm, 0.6am,... . 200.0gm } with step of 0.1gm, which are determined by the design rules. Note that the local refinement operation does not depend on how feasible widths are defined, thus our algorithms are applicable to any width scheme for transistors and wires.

polynomial time Q(r * n3).

3.2. Implementation of the DP-slope model We assume a DP-slope model of the most general form with the only requirement to give the unit effective resistance ro for each discrete transistor size and apply a table based method in order to achieve the satisfactory trade-off between accuracy and complexity. In general, the effective unit resistance ro of a transistor is a function of its size, the input waveform slope and the capacitance loading. However, [17] proposed that all the three parameters could be combined into one factor called slope ratio to solely determine the unit effective resistance ro for the transistor. Thus, a one-dimensional table can be used instead of a three-dimensional table. We built a one-dimensional table for every type of transistors based on SPICE simulation results. Our implementation is similar to that in [16].

4.1. Transistor Sizing The dominance property was only used for the optimal wiresizing problem in the past. In this experiment, the STIS algorithm based on the dominance property is applied to the transistor sizing problem. The full adders from 2-bit to 16-bit implemented by complex gates are sized by assuming that all transistors are critical. Although we use an extreme upper bound (200.0 gim) for each transistor, the performance of the STIS algorithm is still quite good. In Table 1, nFET is the total transistor number in a circuit, average nLoc is the average number of local refinement operations for a transistor, time is the total CPU time to size a circuit and average width is the average channel width for all transistors after transistor sizing. A transistor on average reaches its optimal width after 6-8 local refinement operations on it, and the time to size 514 transistors is just 19.78 seconds in a Sparc-10 workstation. The critical delay reduction by the optimal transistor sizing is up to 23.7%.

3.3. Overview of Near-Optimal STIS algorithm The overall STIS algorithm includes three steps: to initialize the coefficient functions, to tighten lower and upper bounds of the optimal solution and to search the optimal solution between the LR-tight lower and upper bounds. Besides, the coefficient functions will be updated during the procedure to tighten lower and upper bounds because the unit effective ro for the transistor under the DP-slope model is a function of the current solution X. In order to efficiently initialize and update the coefficient functions, a circuit containing both transistors and interconnects is pre-partitioned into DCCs. Although the sizes of coefficient function Fo and F. are n x n, their operation complexities are reduced greatly by DCC partitioning because these coefficients are only needed to be computed for transistors and wires within a DCC. It is worthwhile to mention that the LR-tight lower and upper bounds have the zero sensitivity. In other words, the sensitivity based method can not obtain a solution more optimized than the LR-tight lower or upper bound. If the LR-tight lower and upper bounds are identical for every transistor/wire, the optimal solution is achieved immediately, which happens almost all cases in practice. Because both the coefficient operations and the lower and upper bound operations are completed in polynomial-time, the optimal STIS solution is achieved by the polynomial-time in practice. When the LR-tight lower and upper bounds do not meet, it is observed that the gap between the lower and upper bounds are very small, often just of one width in our experiments, and the percent of divergent transistors and wires is also very small, thus enumeration can be carried out in reasonable time. 4.

4.2.

Comparison between STIS and Other Sizing Schemes A 4-bit adder is used to driven a lcm wire in IC technology. Three sizing schemes, i.e., minimum transistor/interconnect width, transistor sizing only, and STIS are used (see Table 2). When compared with the minimum transistor and wire sizing solution, transistor sizing only reduces the maximum delav bv 13.58% and STIS reduces the maximum delav by 27.56%. Clearly, more optimized solution is achieved by the simultaneous transistor and wire sizing. 5.

CONCLUSIONS

We formulated the STIS problem using a distributed RC tree model with consideration of the waveform slope effect for transistors, and developed efficient STIS algorithm based on recursive local refinement computations. The preliminary experiments have shown that the STIS algorithm produces the solution more optimized than that obtained by optimal transistor sizing only. We plan to integrate our STIS algorithm with a timing analysis tool like Crystal [16] and test more circuits in the future. ACKNOWLEDGMENTS The authors would like to thank Professor C.-J. Richard Shi at University of Iowa, Kei-Yong Khoo and Cheng-Kok Koh at UCLA for their helpful discussions and assistance.

EXPERIMENTAL RESULTS REFERENCES

We have implemented the STIS algorithm in ANSI C for the Sun SPARC station environment. Preliminary experiments will be presented in this section. The delays to be reported are computed using HSPICE. The use of HSPICE simulation results, instead of calculated Elmore delay values, not only shows the quality of our STIS solutions, but also verifies the validity of our transistor/interconnect modeling and the correctness of our STIS problem formulation. The MCNC 0.5gm CMOS process technology is used. The wire width choices are { W 1, 2W 1. 3W 1, 4W 1 , 5W 1 }, where WI is the minimum wire width (0.95pm)

[1] M. Berkelaar, P. Buurman and J. Jess, "Computing the Entire Active Area/Power Consumption versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator", Proc. IEEE Int'l. Conf. on ComputerAided Design, 1994, pp. 474-480. [2] W. Chuang, S. S. Sapatnekar and I. N. Hajj, "Timing and Area Optimization for Standard-Cell VLSI Circuit Design", IEEE Tran. on Computer-Aided Design, March 1995, pp. 308-320.

38

Adder

nFET

Average nLoc

Time (s)

Average Width

2bit 4bit 8bit 16bit

66 130 258 514

6.82 7.55 7.90 8.07

0.22 1.23 4.40 19.78

2.030 1.923 1.868 1.840

Critical nin-width 0.6021 1.3511 2.8681 5.8878

Delay (ns) opt-width 0.4597 (-23.7%) 1.0592 (-21.6%) 2.4440 (-14.8%) 4.6227 (-21.5%)

Table 1. Critical delay comparison between the minimum-width solution and the optimal-width solution. min FET + rain Wire opt FET + min Wire STIS Table 2. solution.

Total FET Area 828 1119 1268

Total Wire Area 1000 1000 4493

Critical Delav 2.3159ns(0.007c) 2.0012ns(-13.58%) 1.6776ns(-27.56%o)

Critical delay comparison among minimal sizing scheme, transistor sizing only, and the STIS

[14] N. Menezes, S. Pullela, and L. T. Pilegi, "Simultaneous Gate and Interconnect Sizing for Circuit-Level delay Optimization", Proc. ACM/IEEE DAC, 1995, pp. 690695. [15] N. Menezes, R. Baldick, and L. T. Pileggi, "A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing", Proc. IEEE ICCAD, 1995, pp. 144-151. [16] J. K. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI, " IEEE Trans. on CAD, 4(3) (1983) pp. 336-349. [17] D. J. Pilling and J. G. Skalnik, "A Circuit Model for Predicting Transient Delays in LSI Logic Systems", Proc. 6th Asilomar Conf. on Circuits and Systems, 1972, pp. 424-428. [18] V. B. Rao and I. Hajj, "Switch-Level Timing Simulation of MOS VLSI Circuits", Proc. IEEE ISCAS, 1985, pp. 229-232. [19] J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Trans. on CAD, 2(3) (1983) pp. 202-211.

[3] G. Chen, H. Onodera and K. Tamaru, "An Iterative Gate Sizing Approach with Accurate Delay Evaluation", Proc. IEEE Int'l. Conf. on Computer-Aided Design, 1995, pp. 422-427. [4] J. Cong and L. He, "Optimal Wiresizing for Interconnects with Multiple Sources", Proc. IEEE Int'l. Conf. on Computer Design, Nov. 1995 (full version as UCLA Computer Science Dept. Tech. Report CSD-00031, 1995). [5] J. Cong, and C.-K. Koh, "Simulataneous Driver and Wire Sizing for Performance and Power Optimization", IEEE Trans. on VLSI, 2(4), December 1994, pp. 408423. [6] J. Cong, K. S. Leung, and D. Zhou, "PerformanceDriven Interconnect Design Based on Distributed RC Delay Model", Proc. ACM/IEEE Design Automation Conf., 1993, pp. 606-611. [7] J. Cong and K. S. Leung, "Optimal Wiresizing Under the Distributed Elmore Delay Model", IEEE Trans. on CAD, 14(3), March 1995, pp. 321-336 (extended abstract in Proc. IEEE Int'l. Conf. on Computer-Aided Design, 1993, pp. 634-639). [8] J. G. Ecker, "Geometric Programming: Methods, Computations and Appicaltions", SIAM Review, Vol. 22, No. 3, July 1980, pp. 338-362. [9] J. P. Fishburn and A. E. Dunlop, "TILOS: A Psoynomial Programming Approach to Transistor Sizing", Proc. IEEE Int'l. Conf. on Computer-Aided Design, 1985, pp. 326-328. [10] N. Hedenstierna, and K. 0. Jeppson, "CMOS Circuit Speed and Buffer Optimization", IEEE Tran. on CAD, 1987, pp. 270-281. [11] J. Lillis, C. K. Cheng and T. T. Y. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model", Proc. IEEE Int'l. Conf. on Computer-Aided Design, Nov. 1995, pp. 138-143. [12] S. S. Sapatnekar, "RC Interconnect Optimization Under the Elmore Delay Model", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 387-391. [13] S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, "An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization", IEEE Tran. on CAD, November 1993, pp. 1621-1634.

39

HIERARCHICAL CLOCK-NETWORK OPTIMIZATION Daksh Lehtherl, Satyamurthy Pullela 2 , David Blaauw3, Shantanu Ganguly 4 Somerset Design Center, Motorola Inc., 9737 Great Hills Trail, Austin TX 78759 1 daksh @ibmoto.com, 4 [email protected] Motorola Inc., 6501 William Cannon Drive West, Austin, TX 787352 2 [email protected], 3 [email protected]

ond-order delay model is used to evaluate delays and slopes at the clock-pins. Wire sizing is based on a sensitivity based technique. General network topologies such as clock-meshes and non-binary trees are handled by this tool.

ABSTRACT Clock-distribution network design for high-performance microprocessors has become increasingly challenging in recent years due to lower-skew tolerances, larger networks, and low-power requirements. The design of a typical clock-network entails a substantial amount of designer time and effort to meet these interrelated objectives. The work presented in this paperaims at automating the clock-network design process while being able to achieve near optimal design solutions. Skew optimization is performed by partitioningclock-networks and then hierarchically sizing wires, to reduce overall design time.

The following sections describe the use of this wirewidth optimization tool in a-hierarchical fashion to achieve quicker turnaround time for large networks. The efficacy of the approach is seen in terms of low run times on realistic examples. 2. BACKGROUND The problem of designing clock-distribution networks entails the design of the routing from a clock-source to all clocked-elements, in a manner that minimizes skew between various clocked-elements. This problem has been addressed in the past with a wide range of techniques [1, 2, 3]. The focus of recent approaches has been to reduce skew by balancing the Elmore-delay from a source to various clock-targets. Notable among these is the Tsay's algorithm [4]. This approach aims at achieving "zero-skew", by recursively constructing balanced binary clock-trees. The delay is balanced by selecting a tapping-point on the route between two Elmore-delay balanced sub-trees. The design of clock-trees by the selection of tapping-points in this manner may not always be possible in practice due to constraints on available routing area. An alternative to this approach, was presented in [5] and was based on ensuring Elmore-delay balance by varying wire widths. This approach has the advantage that the widths of wires of a routed clock-network can be optimized for skew, and hence requires minimal changes to existing floor-plan, and placement. In order to consider higher order delay models, the current tool uses the techniques described in [11] to generate the target waveform at the clock-nodes.

1. INTRODUCTION The design of clock-networks for microprocessors has become a formidable task due to contemporary clockspeeds, large die sizes and complexity of clocked logic. Optimality of clock-network design is crucial toward meeting performance criteria of high-speed designs. In addition, considerations for low-power and stability of power supplies dictate that the total network capacitance be bounded. In addition to meeting performance criterion, clock-routing and optimization tools have to account for complex placement configurations. In view of these facts it is becoming increasingly important to develop tools that would optimize general clock trees, as well as meshes. This paper reports on the design methodology being developed at Somerset design center for the automated design of clock-networks of PowerPCTM family of microprocessors. A wire-width based skew-optimization tool CLOSYT (CLOck-network SYnThesis) forms the core of the clock-network synthesis. This tool aims at providing designers with the ability to synthesize near optimal clocknetworks in a reasonable amount of time. Desired slope and delay targets can be specified as parameters to the optimizer. The tool sizes the wires in the clock-net to achieve these delay-slope requirements, while meeting specific constraints on the wire-width. An AWE based sec-

3. DESIGN METHODOLOGY Clock signal is distributed to latches through several layers of buffers or regenerators. Typical design methodol-

40

ogies use tree or mesh type structures to distribute the signal from the central signal source to these regenerators. This network forms the primary clock-network and is main cause of signal skew. The regenerators then distribute the signal to the cells or latches that are geometrically closest to this regenerator through secondary networks. Although skew is effected both by the cell assignment to a regenerator and the relative location of cells, as these auxiliary nets are relatively small, their impact on overall skew is negligible.

not cause the initial network to be excessively unbalanced. This is important because the final wire-width optimization solution has to meet width constraints and a limit on the network capacitance and hence excessive metal cannot be added during the optimization phase. In order to achieve a reasonably balanced load assignment, clock-regenerators are grouped into what will be referred to here as "clusters". The assignment of a regenerator to a cluster depends on the physical location of regenerator and the estimated delay from the cluster source to the regenerator. The locations of the clock-regenerators are known from the placement of the cells. The delay from a particular branch of the central network to a clock-regenerator is dependent on the input-capacitance of a regenerator, the Manhattan distance between the closest central-network branch and regenerator location. The distance to the regenerators is approximated by the Manhattan distance. The delay to every target clock-regenerator is then estimated using RICE[6]. A clock-regenerator is then assigned to a branch of the central network that has the shortest delay. Detailed routing of these clusters, is performed later, based on this assignment. These regenerators are now deemed to belong to their respective auxiliary networks and will henceforth be referred to as "cluster-networks". This entire procedure is automated.

For state-of-the-art microprocessors, given that the size of the primary clock-network is excessively large, for design purposes, it is efficient to further consider them to comprise of two levels (with no intermediate buffers), a central network, and a number of auxiliary networks that are fed by the central network. The auxiliary clock-networks consist of the routing from specific branches of the central network to the input pins of clock-regenerators. The design methodology presented here focuses on the physical design and skew-optimization of the primary clock-network which includes both the central and auxiliary networks. The following steps outline the process that aims at achieving an initial clock-network for subsequent wire-width optimization. 4. INITIAL TOPOLOGY GENERATION The approach described here is primarily used as a post-routing optimization. Therefore it is essential to generate the initial topology of both the central and auxiliary networks. Once the topologies are known both the central and auxiliary networks are considered for skew minimization. The following steps outline the topology generation of an initial clock-network.

4.2.2. Subclustering The regenerators belonging to various clusters are divided into smaller groups termed as "subclusters". This subclustering is performed such that the estimated skew per subcluster is limited to a specific value. Each subcluster is then routed as an individual net, rooted at its assigned branch. The process of subclustering aims at minimizing the skew due to daisy-chaining of clock-pins, that occurs quite frequently with conventional routers that tend to reduce the overall path length. Hence subclustering results in multiple branches from the central network feeding groups of clock-regenerators with in a cluster.

4.1. Central Network The initial design of central network is currently performed manually. The intent here is to give designers the freedom to layout wires optimally with respect to the existing floor-plan and cell-placement. As we do not expect the central structure to be very complicated, this manual step requires very little effort. In addition it helps to fully utilize designers knowledge of the current design and potential changes that the design may undergo.As the tool is capable of handling meshes and non-binary structures, designers have the freedom to chose from a wide variety of design practices.

4.2.3. Routing of Cluster Networks The routing from every branch of the central network to its corresponding targets is performed by a maze routing tool. These wires are routed with the maximum permissible widths, to ensure that router allocates the sufficient blockage-area for the wires. The wire-width optimization tool is permitted to size the wires with this value of width as a maximum width constraint. This ensures that the width-optimization will not violate any design rules. Figure 1. depicts a typical primary clock-network after the clusters have been routed.

4.2. Auxiliary Networks The initial design of auxiliary networks consists of several steps each of which are described below: 4.2.1. Clustering and Load Balancing

It is desirable to ensure that the auxiliary networks that connects to the leaf branches of the central network do

41

-

I

(A +,XI) AP = SI (y -y,)

I

240.00

(1)

220-0

where A = STS and S is the

200-00

n X v Jacobian matrix(i.e.,

Si. = ayilpj ) and y, = f (13), the current solution

5SO OO 160,00

andy is the target solution. X in (1) is the Lagrangianmultiplier determined dynamically to achieve a rapid convergence to the final solution. This method combines the convergence properties of steepest descent methods during the initial stages and the convergence properties of methods based on Taylor series truncation. The method of setting X dynamically is shown in the flow chart Figure 1. k(i) is the value of X at ith iteration.

I4Q,00 120-00 100-00

90.00 60.00

*0,00 20.00

I

SO 0M

100.00

I

I

190.00 -w.00

;:

Figure 1. A Typical Primary Clock-Network 5. 5.1.

CLOSYT OPTIMIZATION

Optimization Parameters

The initial clock-network resulting from the above mentioned steps is described to CLOSYT in terms of a set of wires with their lengths, initial widths and connectivity information. CLOSYT optimizes the widths of the wires for skew subject to the following specifications * * * * * *

The slew-rate/transition-time at the output of the clock-driver. The delay and slope requirements at the clock-pins. The maximum and minimum width constraints on wire segments. Upper and lower bound on the phase-delay of the clock-network. The maximum capacitance allowable for the clocknetwork. Maximum acceptable skew.

5.2. Skew Optimization Approach

The Levenberg-Marquardt algorithm [8,10,12] is utilized to minimize the mean-square error between the desired and actual delays and slopes. Given a set of functions yi = fi (x, 3) , the Levenberg-Marquardt algorithm addresses the problem of finding the vector 1, such that the mean square error between a specified set of vectors yi and the functions yi evaluated at

P is minimized.

The solution is obtained by iteratively finding a vector of increments AP3, incrementing the parameters by AP, and recomputing the Jacobian repeatedly until a satisfactory convergence is obtained. More specifically at each iteration we solve the equation:

For clock-network synthesis, the set of wire-widths form the vector of parameters (AP in (1)) to be determined. The functions fi correspond the evaluation of slope and delay as a function of widths of wires in the network.

42

As one can observe the Levenberg-Marquardt method is an approach for unconstrained optimization as the parameters are allowed to take any value. In order to account for maximum and minimum width constraints, we cast clock-network synthesis as a constrained optimization problem - determine the vector of widths W such that the sum-of-squares error between the 2N target delays and slopes the current slopes and delays at the clock-pins is minimized. The wire widths are increased by AW obtained by solving (1) after each iteration. If, after incrementing, the width of any wire is outside the permissible range, the width is set to the corresponding limit: if

wj(k-1) + AWi < wi

W.i(k) I

if

wi(k-1) +AWI.>Wi-

W-(k) = W. I

networks by partitioning the problem into two or more hierarchical levels. This optimization is performed bottom-up and improves the total run-time of the tool substantially, without significant loss in accuracy. For example if a clock-network divided into a central network with p wires, and m wires at the auxiliary network level partitioned into k-clusters, the time complexity is proportional to ( 3 + m3 /k2) in comparison to (j+m) for the entire network. The following steps outline the hierarchical optimization: 1). As described in Section 4, the networks corresponding to each cluster, form the first level of the hierarchy. The clock-regenerators at the leaves of cluster-networks are modeled as capacitances. All cluster-networks are optimized individually for skew, and a specific value of delayslope target. The widths of wires at this level are constrained to be between the initial routed width and a minimum width.

= Wimin W.ii Im

where w (k) is the width of wire i at kh iteration. The sensitivity of delay and slope at all targets with respect to every wire in the network is computed by the adjoint-sensitivity technique [7]. The wires with the highest sensitivity are selected for width changes.

2). The second stage of optimization involves sizing the wires of the central network to minimize the global skew. Each cluster is replaced by it's equivalent driving point model, and the average delay from the root of the cluster to all its targets is estimated. The wires of the central-network are then sized taking into account the average delays of the clusters. As we assume that the size of the clusters is small, we expect that the signal slope integrity is preserved for propagation through the clusters. Therefore the user specified slope target can be fed directly as slope target to the central network. The delay targets for the central network are generated as follows. Considering a central network feeding n cluster-networks, each with average delay ti, if the delay up to the root of the cluster networks is

5.3. Sensitivity Computation From (1) it is clear that we need the sensitivities of delays and slopes with respect to widths of wires in the network. We obtain these sensitivities in three steps: 1). Form the equivalent circuit of the network using a imodel for each segment of the route. We then compute the moment sensitivities of delay and slope at a target node (a clock-pin or central network branch tip) with respect to the resistances and capacitances in the circuit. 2). These sensitivities are then translated into delay/slope sensitivities [11].

-

\

3). Sensitivities with respect to wire widths are then derived from the resistive and capacitive sensitivities as described in [9]. The resulting sensitivity matrix is used to iteratively solve (1).

-

t151(

\ 'I

-

/ t2, C2

t3, C 3 -

6. HIERARCHICAL OPTIMIZATION Due to the fact that the sensitivity computation has an f

t4 C4 I

-

t, C.

j

As solving the matrix in (1) is an 0 (n 3 ) (where n is the number of wires) operation, this solution is computationally intensive and therefore time consuming. We use heuristics proposed in [10] for identifying the most sensitive wires and then discard the insensitive wires. This results in a dramatic reduction in the size of the matrix and therefore a quick convergence is achieved as evidenced by our results.

0(n 3 ) compjlnn

-

I

-

-

I -

Figure 2. Optimization with Cluster Estimates

is desirable to optimize large clock-

43

required to be Td, then the central network is optimized by settingy in (1) as

hierarchical optimization was found to reduce run-times significantly for large networks. 9.

Yi = Td - ti,

FUTURE WORK

To ensure low-skew values in reality it is desirable to take into account the process variations as a part of the clock tree design. From the reliability perspective it is necessary to be able to take into account certain electro-migration constraints while sizing the wires for skew. Future enhancements to the tool will aim at including these criterion as a part of the optimization.

wherey = (Y], Y2. -n)¾

7. EXPERIMENTAL RESULTS The design methodology and the wire-width optimization was tested with a clock-network design problem of a PowerPCTM microprocessor. The optimization was performed both as a complete network and hierarchically. The estimated capacitance, average delay, skew for individual clusters for this network are summarized in Table 1. The capacitance and delay estimates were used to optimize the wire widths of central network. A global skew of less than 5OpS were achieved with given wire-width constraints. The total run time for the entire design process described above, when performed in a hierarchical fashion was a little more than 3 hours on a IBM RISC System 6000/Model 560. The run-time for the width-optimization was less than 5 minutes on an average for the cluster networks and approximately 15 minutes for optimization of the central network with the estimated capacitance and delay. In comparison the time taken to optimize the wires for the clocknetwork as a whole was approximately 7 hours.

REFERENCES [1] H. B. Bakoglu, J.T. Walker, and J.D. Meindl "A Symmetric Clock-Distribution Tree and Optimized High Speed Interconnection for Reduced Clock Skew in ULSI and WSI Circuits," Proc. IEEE International Conference on Computer Design, pp. 118122, 1986. [2] J. Cong, A. B. Kanhng, and G. Robins, "Matching-Based Methods for High-Performance Clock Routing", IEEE Trans. on Computer-Aided Design of Circuits and Systems," vol. 12, no. 8,

pp. 1157-1169, Aug. 1993. [3] M. A. B. Jackson, A. Srinivasan and E. S. Kuh, "Clock Routing for High Performance ICs," Proc. 27th ACM/IEEE Design Automation Conference, pp. 573-579, 1990. [4] R. S. Tsay, "Exact Zero-Skew," Proc. IEEE International Conference on Computer-Aided Design," pp. 336-339, 1991.

Number Cluster

Nae

Of

Net

regenerat

(pF)

Clock-

Cap

Delay

(nS)

[5] S. Pullela, N. Menezes, L. T. Pillage, "Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization," Proc. 30th ACM/IEEE Design Automation Conference, pp. 165-170, 1993.

Skew

(Ps)

[6] C.L. Ratzlaff, N. Gopal, and L. T. Pillage, "RICE: Rapid Interconnect Circuit Evaluator," Proc. 28th ACM/IEEE Design Automation Conference, 1991. [7] S.W. Director, and R.A. Rohrer, "The Generalized Adjoint Sensitivities," IEEE Transactions on Circuit Theory, vol CT-16, no 3, Aug 1969.

ors fxu-sw

35

6.062

0.1085

19.509

fpu-se

18

3.588

0.1068

17.588

fpu-sw

6

1.273

0.1014

2.3210

biu-lmw

20

3.381

0.1028

7.101

biu umw

16

1.501

0.1027

5.796

biu-sw

16

2.090

0.1019

4.430

[8] Q. Zhu, W.-M. Dai, and Joe G. Xi, "Optimal Sizing of HighSpeed Clock Networks Based on Distributed RC and Lossy Transmission Line Models," Proc. International Conference on Computer Aided Design 1993, pp 628-633 [9] N. Menezes, S. Pullela, and L. T. Pillage, "RC Interconnect

fpu-nw

1

0.230

0.1003

0.000

Synthesis, - A moments Approach," International Conference on ComputerAided-Design, Nov. 1994.

fpu-ne

9

1.117

0.1014

4.407

fxu-nw

12

1.835

0.1069

9.794

[101 S. Pullela, N. Menezes, and L. T. Pileggi, "Skew minimization via wire-width Optimization," Submitted to IEEE Transactions on CAD.

[11] N.Menezes, R. Baldick, and L. T. Pileggi, "A Sequential Quadratic Programming Approach to Concurrent Gate and Wire

Table 1: Summary of Clusters

8. CONCLUSION

Sizing," International Conference on Computer Aided-Design

A clock-network design flow has been developed to facilitate the design of large clock-networks. An overview of this wire-width optimization based tool was presented. The efficacy of the approach has been seen by testing the same with a typical clock-network design scenario. The

44

1995. [12] D. W. Marquardt, "An algorithm for least-squares estimation of nonlinear parameters," J. Soc. Indust. App. Math., vol. 11, no. 2, pp. 431 - 441, June 1963

Making MEMS Kaigham J. Gabriel Deputy Director Electronics Technology Office Defense Advanced Research Projects Agency 3701 N. Fairfax Drive Arlington, VA 22203-1714 [email protected] http://www.darpa.mil

Introduction As information systems increasingly leave fixed locations and appear in vehicles and in our pockets and palms, they are getting closer to the physical world, creating new opportunities for perceiving and controlling our environment. To exploit these opportunities, information systems will need to sense and act as well as compute. Filling this need is the driving force for the development of microelectromechanical systems (MEMS). Using the fabrication processes and materials of microelectronics as a basis, MEMS processes construct both mechanical and electrical components. Mechanical components in MEMS, like transistors in microelectronics, have dimensions that are measured in microns and numbers measured from a few to millions. MEMS is not about any one single application or device, nor is it defined by a single fabrication process or limited to a few materials. More than anything else, MEMS is a fabrication approach that conveys the advantages of miniaturization, multiple components and microelectronics to the design and construction of integrated electromechanical systems. MEMS devices are and will be used widely, with applications ranging from automobiles and fighter aircraft to printers and munitions. While MEMS devices will be a relatively small fraction of the cost, size and weight of these systems, MEMS will be critical to their operation, reliability and affordability. MEMS devices, and the smart products they enable, will increasingly be the performance differentiator for both defense and commercial systems.

45

MEMS Market and Industry Structure

MEMS Market and Industry Structure MEMS Market Forecasts for MEMS products throughout the world show rapid growth for the foreseeable future. Early market studies projected an eight-fold growth in the nearly $1 billion 1994 MEMS market by the turn of the century. More recent estimates are forecasting growth of nearly twelve to fourteen times today's market, reaching $12-14 billion by the year 2000 (Figure 1). While sensors (primarily pressure and acceleration) are the principal MEMS products today, no one product or application area is set to dominate the MEMS industry for the foreseeable future, with the MEMS market growing both in the currently dominant sensor sector and in the actuator-enabled sectors. Furthermore, because MEMS products will be embedded in larger, nonMEMS systems (e.g., automobiles, printers, displays, instruments, and controllers), they will enable new and improved systems with a projected market worth approaching $100 billion in the year 2000.

Projected Growth of Worldwide MEMS Market IA

15

Market Segments

12

n 2000

10

m 8. i!2 0

4. 2 0.

I1993

1994

1995

1996

1997

1998

1999

11-

11

2000

Year

FIGURE 1.

Projected worldwide MEMS market. Note inset pie chart that shows the non-sensor market segments influid regulation and control, optical systems and mass data storage are projected to be about half of the total market by the year 2000.

Present MEMS markets and demand are overwhelmingly in the commercial sector, with the automobile industry being the major driver for most micro-

Making MEMS

46

MEMS Market and industry Structure

machined sensors (pressure, acceleration and oxygen). In 1994 model year cars that were manufactured in the US, there are an average of 14 sensors, one-fourth of which are micromachined sensors, increasing in number at a rate of 20% per year. As one example, a manifold pressure sensor is currently installed in vehicles by all three major US automakers. This amounts to more than 20 million micromachined manifold pressure sensors being manufactured per year.

Production/Revenue Share E us

1.5

0

E

Asia

*

Europe

-

El

Acceleration

.

Pressure

F___1

1

I

Cu

I___

a)

06

*e

0.5-

HI-

C1993

FIGURE 2.

-Hi 1994

1995 (projected)

Worldwide annual pressure and acceleration sensor markets with associated (on top) regional production and revenue percentages for the combined sensor markets. More recently, the market for accelerometers used in airbag deployment systems has also grown. Nearly 5 million micromachined accelerometers for airbag systems were manufactured and installed in 1994 vehicles. Increasingly biomedical sensors, particularly disposable blood pressure and blood chemistry sensors are fast approaching the automobile industry in both sensor unit numbers and market size. Over 17 million micromachined pressure

Making MEMS

47

MEMS Market and Industry Structure

sensors, with a market value of nearly $200 million, were manufactured, used and disposed of in 1994. While the MEMS sensors market will continue to grow, particularly sensors with integrated signal processing, self-calibration and self-test (pressure sensors, accelerometers, gyroscopes, and chemical sensors), a substantial portion of the growth in the next few years (and of the MEMS market by the year 2000) will be in non-sensing, actuator-enabled applications. These applications include microoptomechanical systems, principally in displays, scanners and fiber-optic switches; integrated fluidic systems, primarily in fuel-injections systems, ink-jet printheads, and flow regulators; and mass data storage devices for both magnetic and non-magnetic recording techniques. Two non-sensor markets alone, printing and telecommunications, are projected to match the present sensor market size by the year 2000. MEMS Industry Structure Those companies which have so far been directly involved in producing MEMS devices and systems are manufacturers of sensors, industrial and residential control systems, electronic components, computer peripherals, automotive and aerospace electronics, analytical instruments, biomedical products, and office equipment. Examples of companies manufacturing MEMS products worldwide include Honeywell, Motorola, Hewlett-Packard, Analog Devices, Siemens, Hitachi, Vaisala, Texas Instruments, Lucas NovaSensor, EG&G-IC Sensors, Nippon Denso, Xerox, Delco, and Rockwell. Of the roughly 80 US firms currently identified as being involved in MEMS (Figure 2), more than 60 are small businesses with less than ten million dollars in annual sales. The remaining 20 firms are large corporations distributed across different industry sectors with varying degrees of research activities and products in MEMS (the front cover of the 1993 annual shareholders' report for Hewlett-Packard featured a MEMS flow-valve developed for use in their analytical instruments division). Of the nearly $300 million worldwide market in pressure sensors, US manufacturers account for nearly 45% of production and revenue. In the growing accelerometer market, the US position is very similar. Of the nearly 5 million accelerometers made in 1994, US manufacturers accounted for nearly 50% of the market. Because of the combination of an advanced technology base and a strong manufacturing capability in these two key sensor areas, US manufacturers are poised to expand their MEMS market share and are already beginning to penetrate both the European and Japanese automotive sensors market. Accounting for slightly more than half of the worldwide MEMS manufactured products and revenue, the US MEMS industry is a major player in all key segments of the world MEMS market. One notable distinction in industry structure is that few small businesses in Europe or Japan are involved in MEMS. In the US, nearly 60 of the 80 identified firms with MEMS activities are small businesses, each typically generating on average less than five million dollars in annual revenues. Most of

Making MEMS

48

MEMS Market and Industry Structure

these businesses do not have or need their own dedicated fabrication resources. New approaches to the development of manufacturing resources can both exploit this distinctive structure for DoD-specific needs and accelerate the innovation and commercialization of MEMS products. Given the varied applications of MEMS devices and the most likely evolution of their associated fabrication processes, the development of support and access technologies will be even more important and challenging in MEMS manufacturing than in microelectronics manufacturing. Unlike microelectronics, where a few types of fabrication processes satisfy most microelectronics manufacturing requirements, MEMS, given their intimate and varied interaction with the physical world, will have a greater variety of device designs and a greater variety of associated manufacturing resources. For example, the thin-film structures created using surface micromachining techniques, while well-suited for the relatively small forces encountered in inertial measurement devices, are not adequate for MEMS fluid valves and regulators. Similarly, the thicker structures created using a combination of wafer etching and bonding while well-suited to the higher forces and motions in fluid valves and regulators consume too much power to be used for the fabrication of microoptomechanical aligners and displays. There is not likely to be a MEMS equivalent of a CMOS process like that in microelectronics that will satisfy the majority of MEMS device fabrication needs. These different MEMS fabrication processes will often be developed by larger firms with a particular and large commercial market as the target. Typically the firm developing the manufacturing resources needs to be focused on the production of products for those one or two driving applications. But in most cases, once the manufacturing resource is developed, numerous (hundreds) of products for smaller ( 0 and (s(i -1) + j) modulo 5 = 0 then recompute C(i) for 1 < i < n using S. 8. return P c S with lowest cut. Figure 3. The Genetic Metis Algorithm Step 1 initially sets all codes to 00. . . 0 which causes GMetis to behave just Eke Metis until s solutions are generated. Steps 2 and 3 are loops which cause numgen generations of s solutions to be computed. Next, Step 4 converts the circuit hypergraph into a graph, but this step is performed only once out of every 10 times Metis is called. We perform the conversion with this frequency to reduce runtimes while still allowing a variety of different graph representations; the constant 10 is fairly arbitrary. In Step 5, Metis is called using our version of HEM described above. Step 6 maintains the set of solutions S; our replacement scheme replaces solution Q G S with solution P if P has smaller cut size than Q; other replacement schemes may work just as well and need to be investigated. Step 7 computes the binary code for each module based on the current solution set, but only after the first generation has completed and five solutions with the previous code-based clustering have been generated. As in Step 4, the constant 5 is fairly arbitrary. Finally, the solution with lowest cut is returned in Step 8. 4.

EXPERIMENTAL RESULTS

All of our experiments use a subset of the benchmarks from the ACM/SIGDA suite given in Table 2: hypergraph formats of these circuits are available on the world wide web 2 A clustering pk is a refinement of Q' (k > 1) if some division of clusters in Q' will yield pk.

T/F 10 15 20 25 35 50 100 200 500

1 289(238) 276(231) 320(261) 321(243) 309(243) 316(233) 310(231) 325(252) 471(366)

2 241(184) 224(188) 252(202) 251(189) 248(172) 258(190) 274(184) 265(182) 427(333)

3 239(185) 239(185) 259(180) 250(174) 239(170) 250(177) 256(173) 266(170) 418(318)

4 238(180) 228(184) 258(189) 254(170) 227(168) 251(173) 260(172) 257(174) 412(327)

5 225(176) 222(178) 252(173) 243(169) 249(173) 245(169) 256(173) 288(184) 414(294)

6 228(184) 228(175) 253(187) 238(162) 245(171) 240(167) 254(175) 258(182) 429(295)

8 230(174) 228(165) 261(165) 255(173) 240(166) 255(159) 248(166) 261(187) 399(311)

10 220(169) 215(176) 269(190) 232(162) 247(164) 255(178) 237(170) 260(192) 408(321)

12 225(178) 241(181) 265(176) 245(176) 254(176) 232(162) 245(180) 271(181) 414(296)

15 227(169) 228(174) 253(178) 266(174) 239(169) 240(175) 252(176) 266(186) 411(270)

Table 1. Average(minimum) cuts for the avqlarge test case for 50 runs of Metis shown for various values of T (rows) and F (columns). at http://ballade.cs.ucla.edu/-cheese. Our experiments assume unit module areas, and our code was written in C++ and was compiled with g++ v2.4 on a Unix platform. Our experiments were run on an 85 Mhz Sun Sparc 5 and all runtimes reported are for this machine (in seconds) unless otherwise specified. We performed the following studies:

are better than others), we compare to the best FM results found in the literature.

Test Case balu bml primaryl test04 testO3 testO2 testO6 struct testO5 l9ks primarv2 s9234 biomed s13207 s15850 industry2 industry3 avqsmall avqlarge

* We compare Metis against standard and two-phase FM, to show the effectiveness of the multilevel approach. e We show that the GMetis algorithm is more effective than running Metis multiple times. * Finally, we show that GMetis is competitive with previous approaches while using a fraction of the runtime. Test Case balu bml primaryl testO4 testO3 testO2 testO6 struct testO5 l9ks primary2 s9234 biomed s13207 s15850 industry2 industry3 s35932 s38584 avqsmall s38417 avqlarge golem3

# Modules

# Nets

801 882 833 1515 1607 1663 1752 1952 2595 2844 3014 5866 6514 8772 10470 12637 15406 18148 20995 21918 23849 25178 103048

735 903 902 1658 1618 1720 1541 1920 2750 3282 3029 5844 5742 8651 10383 13419 21923 17828 20717 22124 23843 25384 144949

# Pins 2697 2910 2908 5975 5807 6134 6638 5471 10076 10547 11219 14065 21040 20606 24712 48404 65792 48145 55203 76231 57613 82751 338419

.

f

Minimum cut (100 runs) CPU (s Metis I MIT 2-FM I Metis FM . [6] 1 [9l 1] L91 [ 34 53 55 53 61 99 94 36 107 116 158 49 83 84 62 218 292 175 171

32 55 57 86 72 115 71 45 97 142 236 53 83 92 112 428

171

52 53 56 60 97 68 43 93 121 182

83

124

275 312 373 406

438 328 399 518

56

36

23 22 22 37 39 43 53 41 69 59 90 72 134 111 123 349 399 293 355

21 24 24 41 56 46 50 46 81 115 128 222 296 339 339 727 l

Table 3. Comparison of Metis with FM. Dutt and Deng [6] have implemented very efficient FM code; their exact bisection results for the best of 100 FM runs are given in the third column of Table 3 and the corresponding Sparc 5 run times are given in the last column. Hagen et al. [9] have run FM with an efficient LIFO tie breaking strategy and a new lookahead function that outperforms [17]; their bisection results are reported in the fourth column. Finally, we compare to various two-phase FM strategies. In the fifth column, we give the best twophase FM results observed for various clustering algorithms as reported in [1] and [9]. Metis does not appear to be faster than FM for circuits with less than two thousand modules, but for larger circuits with five to twelve thousand modules, Metis is 2-3 times faster. In terms of cut sizes, again Metis is indistinguishable from FM for the smaller benchmarks, but Metis cuts are significantly lower for the larger benchmarks. We conclude that multilevel approaches are unnecessary for small circuits, but greatly enhance solution quality for larger circuits. For these circuits, more than two levels of clustering are required for such an iterative approach to be effective.

Table 2. Benchmark circuit characteristics. 4.1. Metis vs. FM and Two-phase FM Our first set of experiments compares Metis against both FM and two-phase FM. We ran Metis 100 times with balance parameter r = 0 (exact bisection) and recorded the minimum cut observed in the second column of Table 3. Since there are many implementations of FM (some of which

103

4.2.

Genetic Metis vs. Metis

found that with this implementation, GMetis with r = 0.1 was sometimes outperformed by GMetis with r = 0 (exact bisection). Hence, in Table 5, we present results for GMetis with r = 0.1 and r = 0 (given in parentheses). 3 Since for r = 0.1, GMetis runtimes sometimes increase by 20-50%, we report runtimes for r = 0 in the last column. These experiments used the somewhat arbitrary parameter values of s = log2 in (jVj = n) solutions and 12 generations. Observe that GMetis cuts are competitive with the other methods, especially for the larger benchmarks s15850, industry2, and avqsmall. However, the big win for GMetis is the short runtimes: generating a single solution for avqlarge and golem3 respectively takes 417/(12 log 2 25178) = 2.5 and 450/(21og2 103048) = 15 seconds on average. For golem3, we only ran 2 generations since the results do not improve with subsequent generations; the solution with cost 2144 was achieved after only 210 seconds of CPU time.

The next set of experiments compares Metis with the GMetis. We ran GMetis for 10 generations while maintaining s = 10 solutions so that both Metis and GMetis considered 100 total solutions. The minimum and average cuts observed, as well as total CPU time, are reported for both algorithms in Table 4. Test

[[

Case

|[

balu bml primaryl testO4 test03 testO2 testO6 struct testO5 19ks primarv2 s9234 biomed s13207 s15850 industrv2 industry3 s35932 s38584 avqsmall s38417 avqlarge golem3

min

Metis [avg

CPFU

|min

34 53 55 53 61 99 94 36 107 116 158 49 83 84 62 218 292 55 55 175 73 171 2196

47 65 66 68 76 113 117 52 125 132 195 66 149 90 84 280 408 71 101 241 110 248 2520

26 23 23 37 42 44 59 41 70 59 95 71 145 106 126 336 384 257 310 289 294 318 1592

32 54 55 52 65 96 97 34 109 112 165 45 83 78 59 204 291 56 53 148 74 144 2196

GMetis

11

avg I CPU 38 59 59 58 74 101 121 40 117 116 174 52 134 89 74 230 313 62 67 174 104 181 2648

24 22 21 37 39 42 55 39 69 59 91 68 143 112 125 339 423 265 368 322 301 355 1928

5.

This work integrates the Metis multilevel partitioning algorithm of [15] into a genetic algorithm. We showed (i) Metis outperforms previous FM-based approaches, (ii) GMetis improves upon Metis alone for large benchmarks, and (iii) GMetis is competitive with previous approaches while using less CPU time. There are many improvements which we are pursuing: * Find sparser and more reliable hypergraph conversion algorithms. * Try alternative genetic replacement schemes, instead of simply inserting the current solution into S if it is a better solution. * Tweak parameters such as F, T, s, and the number of generations in order to generate more stable solutions in fewer iterations. * Experiment with various schemes to control cluster sizes in the bipartitioning solution. That GMetis frequently finds better 50-50 solutions versus 45-55 solutions is not acceptable. * Finally, we are integrating our own separate multilevel circuit partitioning code into a new cell placement algorithm.

Table 4. Comparison of Metis with Genetic Metis. The minimum cut, average cut and CPU time for 100 runs of each algorithm are given. On average, GMetis yields minimum cuts that are 2.7%, lower than Metis. and significantly lower average cuts (except for golem3). For the larger benchmarks (seven to twenty-six thousand modules) GMetis cuts are 5.7% lower, with significant improvements for industry2, avqsmall and avqlarge. We believe that GMetis can have the greatest impact for larger circuits. Note that golem3 is the one benchmark in which Metis outperforms GMetis in terms of the average case - the quality of GMetis solutions gradually became worse in subsequent generations instead of converging to single good solutions. 4.3.

CONCLUSIONS

REFERENCES [1] C. J. Alpert and A. B. Kahng, "A General Framework for Vertex Orderings, with Applications to Netlist Clustering", to appear in IEEE Trans. on VLSI. [2] C. J. Alpert and A. B. Kahng, "Recent Directions in Netlist Partitioning: A Survey", Integration, the VLSI Journal, 19(1-2), pp. 1-81, 1995. [3] C. J. Alpert and S.-Z. Yao, "Spectral Partitioning: The More Eigenvectors, the Better," Proc. A CM/IEEE Design Automation Conf., 1995, pp. 195-200. [4] K. D. Boese, A. B. Kahng, and S. Muddu, "A New Adaptive Multi-Start Technique for Combinatorial Global Optimizations", Operations Research Letters, 16(20), pp. 101-13, 1994. 3We attribute this undesirable behavior to improper modification of the Metis code. We believe that a better implementation should yield r = 0.1 results at least as good as those for r = 0 without increasing runtimes.

Genetic Metis vs. Other Approaches

Finally, we compare GMetis to other recent partitioning works in the literature, namely PROP [6], Paraboli [20], and GFM [19], the results of which are quoted from the original sources and presented in Table 5. All these works use r = 0.1, i.e., each cluster contains between 45% and 55% of the total number of modules. The CPU times in seconds for PROP, Paraboli, and GFM are respectively reported for a Sun Sparc 5, a DEC 3000 Model 500 AXP, and a Sun Sparc 10. We modified GMetis to handle varying size constraints by allowing the BGKLR algorithm to move modules while satisfying the cluster size constraints. "Ae

' 04

Test

._

Case

. PROP

balu bml primaryl test04 testO3 testO2 testO6 struct testO5 l9ks primary2 s9234 biomed s13207 s15850 industrv2 industrv3 s35932 s38584 avqsmall s38417 avqlarge golem3

cuts 27 50 47 52 59 90 76 33 79 105 143 41 83 75 65 220

.

l

Paraboli

|GFM |

41

27

53

47

40

41

146 74 135 91 91 193 267 62 55 224 49 139 1629

139 41 84 66 63 211 241 41 47 81

27(32) 48(53) 47(54) 49(52) 62(66) 95(96) 94(93) 33(34) 104(109) 106(110) 142(158) 43(45) 102(83) 74(70) 53(60) 177(204) 243(286) 57(55) 53(53) 144(145) 69(77) 145(144) 2111(2144)

l

CPU

GMetis( bal) | PRP KU 16 20 19 49 51 64 75 42 97 87 139 139 250 177 291 867

araboli

|GEM

16

24

18

16

35

80

137 490 711 2060 1731 1367 761 2627 6518 4099 2042 4135 10823

224 672 1440 1920 2560 4320 4000 10160 9680 11280

|G

ei 14 12 12 21 23 26 32 27 46 39 53 58 95 102 114 245 299 266 397 328 281 417 450

Table 5. Comparison of GMetis with PROP, Paraboli. and GFM for min-cut bipartitioning allowing 10% deviation from bisection. Exact bisection results for GMetis are given in parentheses in the fifth column. [5] T. Bui, C. Heigham, C. Jones. and T. Leighton, 'Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms". Proc, ACMI/IEEE Design Automation Conf., pp. 77578, 1989. [6] S. Dutt and W. Deng. "A Probability-Based Approach to VLSI Circuit Partitioning", to appear in Proc. ACM/IEEE Design Automation Conf., 1996. [7] S. Dutt and W. Deng. "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques", Technical Report, Department of Electrical Engineering, University of Minnesota, Nov. 1995. [8] C. M. Fiduccia and R. M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions", Proc. ACM/IEEE Design Automation Conf., pp. 175-181, 1982. [9] L. W. Hagen, D. J.-H. Huang, and A. B. Kahng, '`On Implementation Choices for Iterative Improvement Partitioning Algorithms", to appear in IEEE Trans. Computer-Aided Design (see also Proc. European Design Automation Conf., Sept. 1995, pp. 144149). [10] S. Hauck and G. Borriello, "An Evaluation of Bipartitioning Techniques", Proc. Chapel Hill Conf. on Adv. Research in VLSI, 1995. [11] B. Hendrickson and R. Leland, "A Multilevel Algorithm for Partitioning Graphs", Technical Report SAND93-1301, Sandia National Laboratories, 1993. [12] B. Hendrickson and R. Leland, "The Chaco User's Guide", Technical Report SAND93-2339, Sandia National Laboratories, 1993. [13] G. Karypis and V. Kumar, "A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs",

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

105

Technical Report #95-035, Department of Computer Science, Universitv of Minnesota, 1995. G. Karypis and V. Kumar, "Multilevel k-Way Partitioning Scheme for Irregular Graphs", Technical Report #95-035, Department of Computer Science, University of Minnesota, 1995. G. Karypis and V. Kumar, "Unstructured Graph Partitioning and Sparse Matrix Ordering", Technical Report. Department of Computer Science, University of Minnesota, 1995 (see http://www.cs.umn.edu/"kumar for postscript and code). B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell Systems Tech. J., 49(2), pp. 291-307, 1970. B. Krishnamurthy, "An Improved Min-Cut Algorithm for Partitioning VLSI Networks", IEEE Trans. Computers, 33(5), pp. 438-446, 1984. J. Li. J. Lillis, and C.-K. Cheng, "Linear Decomposition Algorithm for VLSI Design Applications", Proc. IEEE Intl. Conf. Computer-Aided Design, pp. 223-228, 1995. L.-T. Liu, M.-T. Kuo, S.-C. Huang, and C.-K. Cheng, "A Gradient Method on the Initial Partition of Fiduccia-Mattheyses Algorithm", Proc. IEEE Intl. Conf. Computer-Aided Design, pp. 229-234, 1995. B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., pp. 646-651, 1994. Y. Saab, "A Fast and Robust Network Bisection Algorithm", IEEE Trans. Computers, 44(7), pp. 903-913, 1995. L. A. Sanchis, "Multiple-Way Network Partitioning", IEEE Trans. Computers, 38(1), pp. 62-81. 1989.

MIN-CUT REPLICATION FOR DELAY REDUCTION James Hwang'

Abbas El Gamal 2

1

Xilinx, Inc., USA jim.hwangxtilinx.com 2 Stanford University, USA abbas~isl . stanford. edu

ABSTRACT Min-cut replication has been shown to substantially improve min-cut partitions without substantial increase in network size. This paper addresses the use of min-cut replication to reduce delay in partitioned networks. It is shown that mim-cut replication never increases delay in combinational networks or in sequential networks when registers are not replicated, and demonstrated that in practice, min-cut replication reduces delay significantly. Experimental results comparing a min-cut approach with the results of delay-optimal clustering algorithms indicate that min-cut replication can reduce partition size with modest increases in delay. 1

a,

bh

c,

h,

i,

I

'4I>

2

Ii

k

j I

'

(a)

(b)

Delay minimization example from [8] Figure 1. (node delays subscripted). :/ a

C"

a' "

b',

b

c'

INTRODUCTION

All known network partitioning algorithms that efficiently minimize delay subject to capacity constraints require replication. The problem has been solved for acyclic networks when replication is allowed, by Lawler et al. for the unit delay model [6], and by Rajaraman and Wong [11] for a more general delay model proposed in [9]. These approaches minimize delay subject to any monotone component constraint. Furthermore, it has been observed that the min-delay partitioning problem with the non-monotone pin constraint and no capacity constraint can be solved by the min-depth technology mapping algorithm for lookup table-based FPGAs proposed in [2]. A heuristic that combines elements of [2, 11] was proposed in [12] for the min-delay clustering problem under simultaneous gate and pin capacity constraints, with reported optimal or near optimal min-delay partitions. However, the min-delay clustering algorithms described in [6, 11], despite their elegance, have serious practical limitations. They involve massive amounts of replication, and in practice increase network size by roughly a factor of twenty. Merging heuristics have been proposed to reduce the amount of replication [9, 12], but these heuristics increase the running time substantially, and the resulting partition size is still at least doubled. Such substantial size increases can lead to additional delay, for example, when a multi-chip partition becomes too large to fit on a single PCB. In this paper we show that in contrast, the min-cut replication approaches described in [5, 13] can be effective in reducing delay in a partitioned network without the excessive size increase of min-delay solutions. As a simple example, consider the ISCAS85 benchmark design, c17, shown in Fig. la. A delay-optimal clustering, obtained using the algorithm in [11], is shown in Fig. lb, where the component size limit is three nodes and the cut-edge delay is equal to

Ik,

(a)

(b)

Figure 2. A min-cut approach can minimize delay with fewer components. three. The partition was obtained by merging components in the original solution. By beginning instead with the initial partition without replication shown in Fig. 2a and applying replication to minimize cut size, we obtain the partition in Fig. 2b. This partition is delay-optimal, even though the initial partition was not. Moreover, the it contains one fewer component than the partition in Fig. lb. The paper is organized as follows. Section 2 contains definitions and a brief review of min-cut replication. In Section 3, we prove that min-cut replication never increases delay in combinational networks and sequential networks without replicated registers, and show that when registers can be replicated, delay will never increase by more than one cut edge delay. In Section 4, we show that in practice, min-cut replication often reduces delay substantially. In Section 5, we compare the results of a min-cut approach with partitions obtained using the algorithm in [12], demonstrating that min-cut replication can reduce partition size with modest increases in delay. We conclude in Section 6 by discussing future work. 2 2.1.

PRELIMINARIES

Min-Cut Replication

Let V = {V,, V2 , ... , Vk} be a partition of a graph G = (V, E), where the Vi are not required to be disjoint as long as vertices occurring in more than one component

106

are assumed replicated. The min-cut replication problem is to determine a collection of vertex sets to replicate from each component to every other component which minimizes the cut size in the resulting network. Efficient solutions to this problem, called min-cut replication algorithms, are based on the following three ideas [5, 13]. * The replication problem can be solved by solving the k independent problems of determining the min-cut optimal set to replicate into (or out of) a component Vi from (to) its complement Vi. * Determining the min-cut vertex set to replicate into (or out of) a single component V, from (to) its complement Vi can be done efficiently using flow techniques. * If a replication set found by flow techniques is infeasible because of capacity constraints, the solution can be approximated by using a partitioning heuristic.

Figure 3. Choosing the clone to replicate is essential for minimizing delay.

2.2. A Delay Model for Partitioned Networks The general delay model proposed by Murgai et al. [9], is characterized by two parameters: a function 6, defined on the vertex set, and constant delay D associated with every cut edge in a partition.

Definition 2.5 A combinationalpath p is a critical path if it has maximal combinational delay.

JuI

I

/I -

k

(hj

(a)

We wish to consider sequential as well as combinational networks, assuming only that any cycle in a network contains at least one register node. Definition 2.2 Let X C V be the set of all register nodes in G. where X is empty for a combinational network. A path p = (vo, v, ,em) is a combinational path if vi R 7 for i = 1, m - 1. The gate delay of combinationalpath p, 6(p) -

m

6(vo),

iil

d V(v)

to be the delay induced by applying min-cut replication to the cut V.

Definition 2.6 The cycle time associated with cut V,

max

vev

3

MIN-CUT REPLICATION DOES NOT INCREASE DELAY If implemented properly, min-cut replication will never increase delay in combinational networks or in sequential networks if registers are not replicated. Furthermore, when registers can be replicated, min-cut replication will never increase delay by more than the external delay D. It might first appear that the difference in the delay for two clones can be unbounded, for example by considering the example in Fig. 3a. As can be seen in Fig. 3b, after min-cut replication the delays from w to u3 and Uk differ:

6(P)

...

A(wu)

=

2D+zA(w,u).

Proposition 3.1 If, after min-cut replication, a network with partition V has the property that for every cut edge (ui,,)vj, vertex ui has the minimal delay of all its clones, then for any clones v, v*. we have Idk(v) - d'v(*)l < D. Furthermore, min-cut replication never increases cycle time, i.e., maximal delay in a combinational network or in a sequential network when registers are not replicated.

{ (p) + D c(p,V)})

combinational path p=(,

=

The refinement is: whenever (u,, vj) is a cut edge with dr(ui) > dr(Uk) for some clones ui,uk, simply replace (ui, vj) by the edge (uk, v). It then follows that an edge (ui, v,) is a cut edge only if ui has the minimal delay of any of its clones.

6

max

dV(u,) dr(Uk)

However, as shown in Fig. 3c, a simple refinement of mincut replication ensures that the difference in delay between two clones is bounded above by the external delay D.

Definition 2.4 A cut V = {½l, V2 , ... , Vk} induces a delay function on the vertex set V under the general delay model. Let c(p, V) be the number of cut edges in a combinational path p. The combinational delay, or more simply, the delay of a node v, =

vEV

the cycle time associated with the cut after applying min-cut replication.

p=(u,...,v)

dv(v)

maxdv(v)

is defined to be the maximal combinational delay in a partitioned network. Because every cycle in G contains at least one register node, the cycle time is always finite. We denote by 4I ± maxdt (v)

Definition 2.3 The maximum gate delay along any combinationalpath p from u to v is denoted by combinational path

{ 6 (p) + D cr(p, V)},

max

combinational path p=(u,. .,v)

is the delay from the output of vo to the output of ve.

A(u, v)-

(,)

number of cut edges in p after applying min-cut replication to the partition V, we define

'Dv

Definition 2.1 Given a network G = (V, E), the function 6 : V - N assigns a gate delay 6(v) to every vertex v e V. The external edge delay D E N is a constant delay that is assigned to every cut edge in a partition; non-cut edges have zero delay. Choosing the external delay D to be unity and gate delay 6(v) = 0 for all v E V results in the unit delay model of [6].

/-

k

,v)

is defined to be the maximum combinationalpath delay (gate plus external) to the output of v. Letting cr(p, V) be the

107

Proposition 3.2 Design

i. Min-cut replication never increases delay in combinational networks or in sequentialnetworks if no registers are replicated.

MCNC c1355 c1908 c3540 s1238 c2670 c5315 c6288 c7552 s13207 s15850 s35932 s38584 7 s53 8 s9234 Industrial addresspart cat control lookl240 pdt vrcl biga entmisc gme-a seq avg

ii. If registers can be replicated, min-cut replication can increase the delay by at most D. Hence, 4§r < (v for combinational networks and 4)r (v + D for sequential networks. 4


2 a net is split into np(j)-l segments s(ij) connecting two points of the net. Points can be pins or Steiner points. This process is made unique using the slicing tree. Each segment is assigned to a vertex i of the tree which fully contains the segment. This means that the two points either emerge from the two subtrees of a node or belong to the same cell. Fig. 5 shows an example. A point in the tree is either a cell or another segment of the net. This other segment is represented by its node. Because of the slicing tree the segments of a net build a segment tree that is a subtree of the slicing tree. We distinguish two types of segments: Primary segments connect two cells, secondary segments connect to one or two nodes. If we assume that a net or segment is wired within the bounding box of its pins, then a node or rectangle in the slicing geometry is the smallest node that geometrically contains a segment with all its subsegments. From Fig. 5 it is also clear that, because all 1/0 pins belong to bio, all 1/0 nets are assigned to node BI and in mixed nets all segments to 1/0 pins are also assigned to BI. Since we proceed bottom-up from the leaves to the root, the I/O segments are handled last. In this paper we only handle internal segments. Now we will try to answer the question: Is it possible to estimate netlengths with all the uncertainties of layout? For this purpose we conducted an experiment. We took the circuit "alu", a 32 bit ALU with 1015 standard cells and 1059 nets, and did the layout with a simulated annealing tool 50 times, with different start solutions, different 1/0 pin positions, and different aspect ratios. Then we extracted the lengths of individual nets for all cases and looked at the frequency distribution. Fig. 6 shows two results. Net_123 seems to support our assumption perfectly. Its length distribution is very narrow, which means, that its pins have about the same distance in all layouts. Net-42 does support the assumption not as well, but still good enough, if we consider that the half perimeter length of the "alu" is 1000 grid units. We looked at many nets from this design and the samples are typical. These experiments show the limits of netlength estimation. A predicted netlength cannot be more precise than the inherent variance in the layout method.

Fig. 6. Measured netlength frequencies for different layouts of the "alu". The abscissa is divided in grid units. Half perimeter of the block is 1000 grid units.

v2

C1

c2b

x 'x

Fig. 7. Section length definition for different orientations 3.2 Primary Segment Length Model With these definitions we now come back to the length of segments which is our primary goal. Netlengths and path lengths can be derived from the segment lengths. Let a vertex i have the horizontal and vertical dimension x(i) and y(i) in its geometrical representation. Let each segment s(i, j) be composed of two orthogonal sections with the lengths lx(i, j) and ly(i, j). Since we may not know x and y, we also introduce relative lengths lxr(i, j)=lx(i, j)lx(i) and lyr respectively. Our first goal is the estimation of all relative section lengths. The second goal is the estimation of node dimensions and with these two we can calculate the absolute section and segment lengths. The relative length of a section depends on the position of its node in the slicing tree, in the segment tree and its orientation. Let us start with primary segments. Fig. 7 shows a simple example of a segment connecting cells cl and c2. It is not important what the exact routing is as long as it takes the shortest Manhattan path. There are obviously different rules for sections orthogonal (o) and parallel (p) to the slicing line. Let us therefore rather determine lo, lor Ip, and Ipr accordingly, as long as the orientation is not known. We also cannot know where in nodes v2 and v3 the pins of cells cI and c2 are located, as long as the ordering is not known. We can only assume that they will, on the average, be closer to the slicing line than to the opposite sides. Experiments suggest that this tendency is increasing with the increasing number of cells in the vertex to which the segment is assigned. We do not have sufficient experimental evidence to prove a relation. We therefore assume a lin-

121

x xI

I I I

I x'1 -

-1I

a10x'2

lo

fi

f

2

Fig. 9. Definition of a 2x8 standard cells window and distribution of lo. Average length of 8 cells is 160 grid units.

f.

'I

lo

x'1

x'2 -Yt

fi

f2

p

f "I< x1

Fig. 10. Parallel section length probability distribution

x'2 art

x'1

--- ly

9

'

net is, we use the averages of the distributions as relative lengths lor and 1pr. If the pins are equally distributed in the two sibling areas, loreq =0.5 and lpreq =0.33. Because of routing "detours" the factors can be larger. With increasing numbers of cells in the corresponding nodes, the factors decrease. First experiments indicate the following relation. If nco is the average number of cells orthogonal to the slicing line, we found:

lIo 10

x'2

Fig. 8. Different pin position probability functions and resulting orthogonal section length probability distributions ear probability distribution (by distribution we always mean densities) of pin positions perpendicular to the slicing line. Fig. 8 shows examples with different slopes. Because the pin positions in both sides are assumed not to be correlated and

r=

the length distribution is the convolution of the pin position distributions: f (lo) = conv (fl (x1

x'l),f2

(x'2))

b ) a+ aor nco

(EQ 3)

with a=0.5 and b=2. For 1pr we have no relation yet. Thus we only define with the average number of cells parallel to the slicing line (ncp):

(EQ 1)

lo = (xl -xl) +x'2

eq

ncp) lpr = g (lpr ,eq

(EQ 4)

If x and y are the horizontal and vertical dimensions of a node, we can calculate the primary section lengths for this node:

(EQ 2)

The results are depicted in Fig. 8. Fig. 9 shows some experimental results. They have been achieved by measuring the length of 2-point nets parallel to the rows in a standard cell layout that was placed with simulated annealing. In order to simulate a certain node in a slicing tree, only nets within a window of m rows and 2n cells in a row have been considered that cross a vertical slicing line in the center of the window (n cells in a row on either side). The window was moved across part of the layout to gather statistics. The result seems to fit to the bottom row of Fig. 8. Similar rules apply for the sections parallel to the slicing line. Fig. 10 shows the length distribution in the case that the location of the pins parallel to the slicing line are independent of each other and that the locations are equally distributed. This is a worst case assumption. From these distributions we can gain two results. First, since we cannot know where in the distribution a certain

Ix = lor x;

ly = lpr . y for orientation v

lx = lpr x;

ly = lor- y for orientation h

(EQ 5)

The second conclusion we can draw from the distribution is its width. It is a measure for the variance of lor and lpr and thus for the variance of the segment length. But it is only one component of the variance because uncertainties of the partitioning process have to be added. This is the subject of further research. 3.3 Secondary Segment Netlength Model Secondary segments connect to subnets that belong to the subtree of the corresponding node. This will reduce the length because the secondary segment connects to the nearest point of the subnet. We can either account for this by

122

80

70-

60

so 40 -

Fig. 11. Secondary segment length reduction by bounding boxes and reduced pin position space. another reduction factor or try to model it more precisely. Let us explore the latter possibility. What we need is a geometric representation of the subnet. A bounding box would be a good abstraction. But we did not find a means to calculate it during the estimation process because of the unknown orientations. The bounding box dimensions are related to the sum of lx and ly of the segments of the subnet. The relation will depend on the number of segments in the subnet. We do not know how yet. Instead we use the maximum of the dimensions as dimensions bx and by of the bounding box: bx = max(lx(i)); by = max(ly(i)); is the index of the subnet segments

lys = lpr (y - byI - by 2 ) Ixs = Ipr (x - bx 1 - bx 2) lys = lor (y-byl-by2 )

} for orientation v

}

-0

10

20

30

40

50

60

100

200

300

400

500

600

AO 700

Fig. 12. Netlength frequency distribution of the "alu". Abscissa in grid units.

(EQ6)

It is not known where the bounding box is located in the subnode area. This is the same situation as in the case of the primary segments. The difference is the extension of the "pin". This results in a virtual reduction of the node sizes by the same amount, as Fig. 11 tries to illustrate this effect with a segment that connects to two subnets. The white area in Fig. lib is the worst case area in which the ends of the segment can be located, if we assume that it can connect to any point on the bounding box of the subnets. There are two possibilities to take this reduction into account. In the relative length world we can calculate relative bxr and byr by using the quotient of the square roots of the sum of the cell areas of the corresponding nodes as divisor. The better possibility is to apply the reduction during the bottom-up calculation of absolute section lengths. We use this method because it is more precise. This has the following result on the secondary section lengths lxs and lys: Ixs = Ior (x-bx1 -bx 2 )

10

for orientation h

bxj, by, are the dimensions of one subnet, bx2, by 2 of the other. If only one subnet exists, the dimensions of the other are set to zero. 3.4 Netlength Distribution Test Proving the model correct is impossible. We have to

Fig. 13. Floorplan grid for experiment. make as many tests as possible to convince ourselves that the model is meaningful. One such test is a comparison of a measured netlength distribution with a distribution calculated with the model. Fig. 12 shows the distribution for the "alu" and a 1:1 aspect ratio. The layout was conducted with our own simulated annealing placement tool and fairly good global and detailed routers. In order to calculate the distributions of all net segments, we need a slicing tree and the number of net segments assigned to each node of the tree. This is a typical result of a bipartitioning tool. We therefore asked a colleague to bipartition the alu with his tool which gives excellent results /Mal96/, down to the standard cells. This procedure guarantees that the compared results are really independent. Next we needed cell node dimensions to calculate absolute lengths. For this experiment we used a simplified assumption: All cells have the same size and all vertices have a 1/ F2 aspect ratio and orientations alternate. This results in a very regular floorplan as shown in Fig. 13. As a further assumption we assumed equal distributions of the pins in all vertices and no correction factors. Fig. 13 highlights one node with two subnodes and a net segment. The dimension of each node is proportional to the square root of the number of cells in the node. Since the length I of the segment is I = lo + lp , the probability distribution of I is the convolution of the distributions of lo and ip. The aspect ratio has to be taken into account when defining the two distributions, which are shown in the top rows of Fig. 8. The orientation does not matter because the

123

Step 2. Partition the circuit of the block recursively until only two cells are left in each partition. Create a node no(i) for each partition and build the slicing tree during the recursion. Enter the name of the nets that are cut in each node's segment list. Enter the number of cells nc(i) represented by the node.

Fig. 14. Relative segment length probability distribution under the assumptions made in the text.

Step 3. Generate the shape functions for all nodes (in post order) with the algorithm in /Zim88I. Fig. 4 shows an example. The shape function of each node contains routing space for all net segments of the node. Transparency has been subtracted. Save the added routing space values. Calculate the average number of cells parallel ncp(i, k) and orthogonal nco(i, k) to the slicing line for every corner k of the shape functions. Step 4.

Fig. 15. Theoretical segment length frequency distribution for the alu. aspect ratio does not change if we rotate a node. The relative distribution of ir is shown in Fig. 14. The sum of all these distributions, stretched according to the dimensions of the nodes, for all segments of the alu is the total segment length frequency distribution shown in Fig. 15. It is scaled so that the root node has the same dimensions as the layout. It cannot be directly compared to the measured netlength distribution because nearly 50% of the nets of the "alu" have more than two pins. But the experiment shows that in principle the model shows the right kind of distribution. It has to be pointed out though that this distribution is not based on Rent's rule, but on a realistic slicing tree of the circuit and the number of cuts in each node.

4 LENGTH ESTIMATION METHOD From the above we now arrive at a relative simple segment lengths estimation method. We will describe the individual steps in prose. There exists a little different implementation which we used to develop the stochastic models in chapter 3. Here we explain how we would do it today. Step 1. Enter parameters loreq, lpreq, a, and b for EQ 3 and EQ4.

Distribute the routing space of all nodes to its siblings' shape functions, starting at the root (in pre order). This is necessary to estimate the dimensions of all nodes with all wires ending in or passing through the node as precisely as possible, in respect to the final layout. This step is under development.

Step 5. Traverse the slicing tree in post order to calculate section lengths lx(i, k), lxs(i, k), ly(i, k), and lys(i, k) for all corners k of the shape functions for all nodes, using EQ 3 to EQ 7. Step 6. Calculate individual segment lengths and netlengths, separately for horizontal and vertical components, if necessary, as input for a timing analysis.

5 EXPERIMENTAL RESULTS We experimented with the prototype implementation of the estimator which is built into our toolbox PLAYOUT and used our standard cell place and route and our timing analysis tool. We did estimations for the circuit "alu" for 11 different aspect ratios, ranging from 0.23 to 8.5 and did layouts for these shapes. We compared the estimated netlengths, which are the sum of the corresponding segments, with the extracted netlength individually. We got many results that show that the prototype method and the partitioning had to be improved. Since we have no other published estimations to compare with, it is difficult to say, how good the results are, when do we reach the stochastic limits, and what is a confidence measure. Despite all this we will show here at least one result in Fig. 16, that should be compared with Fig. 12. Although the average netlength is about 100 grid units, the average error is about

124

5 units. We purposely show absolute errors because the path lengths depend on absolute values.

/Feu82/ M. Feuer, "Connectivity of random logic," IEEE Trans. on Computers, Vol. C-31, No. 1, 1982, pp. 29-33. /Han88/ D. Hanson, "Interconnection Analysis," in: Physical Design Automation of VLSI Systems, Bryan T. Preas and Michael J. Lorenzetti (eds.), The Benjamin/Cummings Publishing Company, Inc., CA, 1988, pp. 31-64.

10 !O-

'10

1025

Report 4610), 1979, pp. 272-277.

-20

ln.rnrrlrrn nfllrnHllflEMf -15

-10

-5

0

5

10

15

20

Fig. 16. Distribution of absolute netlength estimation errors for the "alu". Abscissa in grid units.

But there are also some large errors in the shown distribution and we have to keep in mind that the longest path, not the average, decides on the circuit performance. Our goal therefore has to be to try to limit the maximum errors and be able to predict the probability of these.

6 CONCLUSIONS We have shown that the length range of individual nets in many different layouts is relatively small. It should therefore be possible to estimate netlengths, based on the knowledge of the circuit structure. We have shown, that with partitioning important structure information can be extracted and an estimation model can be built with some stochastic assumptions. So, the answer to the questions raised in chapter 3.1 with our current knowledge is: The slicing topology is representative for the estimation of individual netlengths, even without ordering information. This seems true for internal nets. For I/O nets we cannot answer this question currently. To answer the reliability question we need more experiments. The models could only be justified with a few experiments. A prototype implementation of the estimator has been implemented and already shows encouraging results. We are confident that the implementation of the improved models as shown in this paper will also improve the estimation quality. We need benchmarks in the submicron range with the necessary timing parameters to prove our results and to be able to compare with other estimation methods, for example prototype layouts. References /Don79/ W. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. on Circuits and Systems, Vol. CAS-26, No. 4 (IBM

125

/Heb95/ W. Hebgen, "Netzlaengenbasierte Abschaetzung des Zeitverhaltens in einem top-down VLSIEntwurfsystem," Ph.D. thesis, University of Kaiserslautern, FRG, 1995. /Kel89/ W. Keller, "Ein Modell zur entwurfsbegleitenden hierarchischen Behandlung des Zeitverhaltens beim physikalischen VLSI-Entwurf," Ph. D. thesis, University of Kaiserslautern, FRG, 1989. /KuP86/ F. Kurdahi and A. Parker, "PLEST: A Program for Area Estimation of VLSI Integrated Circuits," Proc. of the 23rd Design Automation Conference, 1986, pp. 467-473. /LaR71/ B. Landman and R. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. on Computers, Vol. C-20, No. 12, 1971, pp. 1469-1479. /Mal96/ F.-O. Malisch, private communication, 1996 /PeP89/ M. Pedram and B. Preas, "Interconnection Length Estimation for optimized Standard Cell Layouts," Trans. IEEE Inl. Conf. on Computer-Aided Design, 1989, pp. 390-393. /SaP86/ S. Sister and A. Parker, "Stochastic Models for Wireability Analysis of Gate Arrays," IEEE Trans. on Computer-Aided-Design, vol. CAD-5, no. 1, 1986, pp. 52-65. /Zim88/ G. Zimmermann, "A New Area Shape Function Estimation Technique for VLSI Layouts," Proc. 25th Design Automation Conference (DAC), Anaheim, 1988, pp. 60-65.

EXPLORING THE DESIGN SPACE FOR BUILDING-BLOCK PLACEMENTS CONSIDERING AREA, ASPECT RATIO, PATH DELAY AND ROUTING CONGESTION Henrik Esbensen Ernest S. Kuh Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720, USA esbensen(3eecs .berkeley.edu

ABSTRACT A genetic algorithm for IC/MCM building-block placement is presented. Optimization criteria considered are area, aspect ratio, routing congestion and maximum path delay. Designers can choose from an output set of feasible solutions. In contrast to existing approaches such as simulated annealing, no weights or bounds are needed. Experimental results illustrates the special features of the approach.

rithm for both ICs and MCMs is presented, which supports explicit design space exploration in the sense that 1) a set of alternative solutions rather than a single solution is generated by a single program execution, and 2) solutions are characterized explicitly by a cost value for each criterion instead of a single, aggregated cost value. The algorithm simultaneously minimizes layout area, routing congestion, maximum path delay and the deviation from a target aspect ratio. It searches for a set of alternative, good solutions where "good" is defined by the user in a simple manner. From the output solution set, the designer chooses a specific solution representing the preferred tradeoff. The approach avoids the use of both the weights and the bounds of (1) and consequently eliminates the above mentioned problems concerning weight and bound specification. The approach has three additional significant characteristics:

1. INTRODUCTION During placement of an integrated circuit (IC) or a multichip module (MCM) the objective is to find a solution which is satisfactory with respect to a number of competing criteria. Most often specific constraints has to be met for some criteria, while for others, a good tradeoff is wanted. However, at this point in the design process, the available information as to which values are obtainable for each criteria is based on relatively rough estimates only. Consequently, the designers notion of the overall design objective is rarely clearly definable. Virtually all existing placement tools minimizes a weighted sum of some criteria subject to constraints on others. I.e., if k criteria are considered, the objective is to minimize the single valued cost function

e

* Despite the fact that delay is inherently path oriented, most existing timing-driven placement approaches are net-based. While simple, these approaches usually over-constrains the problem, thereby potentially excluding good solutions from being found. The few existing path-based approaches includes [13, 15, 17], all of which, however, relies on very simple net models (stars and bounding boxes). The approach presented here obtains a more accurate path delay estimate by approximating each net by an Elmore-optimized Steiner tree.

i

C=

wici

s. t.

V

i

+ 1,...,k: ci < Ci

The maximum routing congestion is minimized, thereby improving the likelihood that the placement is routable without further modification. Consequently, the traditional need for multiple iterations of the placement and global routing phases is significantly reduced.

(1)

for some j, 1 < j < k. Here ci measures the cost of the solution with respect to the i'th criterion and the wi's and Chi's are user-defined weights and bounds, respectively. However, in practice it may be very difficult for the designer to specify a set of bounds and weights which makes the placement tool find a satisfactory solution. If the bounds are too loose, perhaps a better solution could have been found, while if they are too tight, a solution may not be found at all. It is also far from clear how to derive a suitable set of weight values from the vaguely defined design objectives, and constant weights may not be sufficient to keep the terms of the cost function properly balanced throughout the optimization process. Furthermore, the minimum of a weighted sum can never correspond to a non-convex point of the cost tradeoff surface, regardless of the weights [11]. In other words, if the designers notion of the best solution corresponds to a non-convex point, it can never be found by minimizing c in (1), even though the solution is nondominated. Our work is motivated by the need to overcome these fundamental problems. A building-block placement algo-

* The approach is based on the genetic algorithm (GA), since it is particularly well suited for design space exploration [12]. We are only aware of three previous GA approaches to building-block placement [4, 5, 10], none of which considers delay or routing congestion or performs explicit design space exploration. Previous work on design space exploration in CAD is still very limited. However, approaches for scheduling and channel routing are presented in [7] and in [6] an approach for FPGA technology mapping is described. Very recently, a combined wire sizing and buffer insertion method, also supporting design space exploration, was presented in [16]. The work presented here is based on significant extensions and improvements of our earlier placement approach described in [8].

126

2. PROBLEM DEFINITION The placement model described in Section 2.1. is relevant for both MCMs and for IC technologies with at least two metal layers available for routing. Section 2.2. characterizes the solution set searched for by the algorithm.

m(s(pi+,)), i = 0,1_ . ., I -2. s(po) or pi-, may be an IO pin. Each path in an MCM will have length I = 1 assuming that all signals are latched at the inputs of the components. m(pi) =

* Technology information: Number of metal layers available for routing on top of blocks and between blocks, denoted by lblock and ,P.,,. respectively. The routing wire resistance r and capacitance c per unit wire

2.1. Placement Model A placement problem is specified by the following input

length, and the wire pitch

* A set of rectangular building-blocks of arbitrary sizes and aspect ratios with a set of pins located anywhere within each block. * A set of IO pins/pads. Constraints on relative IO pin positions are expressed using a two-dimensional array A~xt as illustrated in Fig. 1. Each 10 pin can be assigned to an entry of A and the physical location corresponding to entry (i, j) will be (ix/(s - 1), jy/(t - 1)), where x and y are the horizontal and vertical dimensions of the layout, respectively'. An 10 pin assigned to A by the user is called a fixed IO pin, while the remaining IO pins are flexible. Each flexible IO pin will automatically be assigned to a vacant entry of A not specified as illegal. Since any subset of the entries of A can be specified as illegal, pins can be restricted to placement along the periphery of the layout, they can be uniformly distributed over the entire layout, etc.

Wpit~h.

For simplicity, these

values are all assumed to be constants. Each output solution is a specification of * An absolute position of each block so that no pair of blocks or a block and an 10-pin are closer than a specified minimum distance A > 0. This parameter allow physical constraints (design rules) to be met and is not intended for routing area allocation. Since multi-layer designs are considered, it is assumed that a significant part of the routing is performed on top of the blocks. * An orientation and reflection of each block. Throughout this paper, the term orientation of a block refers to a possible 90 degree rotation, while reflection of a block refers to the possibility of mirroring the block around a horizontal and/or a vertical axis. Changing the orientation of a block generally alters its contour, while reflecting it does Tot. In an IC, each block can be oriented and/or reflected in a total of eight distinct ways. For MCMs, only two distinct reflections exist, since the direction of its pins is fixed, giving a total of four distinct orientations/reflections. * An absolute position of each 10 pin, satisfying the specified constraints on their relative positions.

layout area

IO pin array

2.2.

Figure 1. Specification of constraints on placement of IO pins. Here A has dimensions 8 x 10 and 11 fixed JO pins (white circles) are assigned to specific entries of A while 14 entries (black circles) are illegal. The remaining entries are available for flexible JO pins. A will be oriented and/or reflected and subsequently scaled so that it exactly covers the layout area of the placement. * A specification of all nets, including for each net 1) the capacitance of each sink pin, and 2) a designated source pin p, its driver resistance and an associated internal delay i(p) in the block m(p) to which p belongs. t(p) is the time it takes a signal to travel through m(p) to p. 2 * A specification of a set of paths P. A path connects either two registers of distinct blocks or an IO pin and a register, i.e., it is an alternating sequence of wires passing through blocks and net segments. For a sink pin p, denote by s(p) the source pin of the net to which p belongs. Each path P e P is then uniquely specified by an ordered set of sink pins P = {po ,p ... ,pj- } of distinct nets, such that 'Relative to the building-blocks, the entire set of 10 pins can be oriented and/or reflected in eight distinct ways, while still satisfying the constraints on relative positions specified by A. The given absolute position of entry (i, j) assumes that the IO pin set is positioned on top of the blocks without changing neither the orientation nor the reflection relative to the blocks. 2If p is an 10 pin, m(p) is p itself and if it is also a source, t(p) = 0, i.e., input 10 pins have no internal delay.

What is a "Good" Tradeoff ?

Let II be the set of all placements and R+ = [0, oo[. The cost of a solution is defined by the vector-valued function c : HI _ R4 which will be described in Section 3.2.. This Section describes how to specify what a "good" cost tradeoff is, and how to compare the cost of two solutions without resorting to a single-valued cost measure. The user specifies a goal vector g = (gi, 2,g3,g4) and a feasibility vector f = (f 1, f2, f3, f4) such that g, f E (R+ U{oo}) 4 and 0 < gi < •f• < o for i = 1, 2,3,4. For the i'th criterion, gi is the maximum value wanted, if obtainable, while fi specifies a limit beyond which the solution is unconditionally of no interest. For example, if the i'th criterion is layout area, gi = 20 and fi = 100 states that an area of 20 or less is wanted if it can be obtained, while an area larger than 100 is unacceptable. Areas between 20 and 100 are acceptable, although not as good as hoped for. The vectors g and f defines a set of satisfactory solutions S9 = {x C II I Vi : xi < gy} and a set of acceptable solutions Af = {x E III Vi : xi < fi}, where xi is the cost of x wrt. the i'th dimension, i.e., c(x) = (Xz,X 2 ,X 3 ,X 4 ). The values specified by g and f are merely used to guide the search process and in contrast to traditional, user-specified bounds, need not be obtainable. Therefore, they are significantly easier to specify than traditional bounds. In order for the algorithm to compare solutions, a notion of relative solution quality is needed, which takes the goal and feasibility vectors into account. Let x, y e HI. The relation x dominates y, written X < d y, is defined by X < d Y

127

-

(V i : xi < yi) A (3 i : xi < yi)

(2)

3.

(0,0)

criterion I

g,

The concept of genetic algorithms is based on natural evolution. In nature, the individuals constituting a population adapt to the environment in which they live. The fittest individuals have the highest probability of survival and tend to increase in numbers, while the less fit individuals tend to die out. This survival-of-the-fittest Darwinian principle is the basic idea behind the GA. The algorithm maintains a population of individuals, each of which corresponds to a specific solution to the optimization problem considered. Based on a given cost function, a measure of fitness defines the relative quality of individuals. An evolution process is simulated, starting from a set of random individuals. The main components of this process are crossover, which mimics propagation, and mutation, which mimics the random changes occurring in nature. After a number of generations, highly fit individuals will emerge corresponding to good solutions to the optimization problem. Rather than altering given solutions directly, the crossover and mutation operators process internal representations of solutions. The solution corresponding to a given representation is computed by a function known as the decoder. Section 3.1. outlines our specific GA, Section 3.2. presents the placement representation and its interpretation, and Section 3.3. briefly discuss the selection strategy and the genetic operators.

fl

Figure 2. The sets of satisfactory and acceptable solutions, illustrated in two dimensions. Using gi), assuming a convenient ordering of the optimization criteria. Then z -. y

X*

[(V i > k : xi < yi) A (3 i > k : xi < yi)]

3.1. Overview Fig. 3 outlines our GA. Let D = {9o0, 1, ON-I} denote the current population. The rank r(o) of o E 4 is the number of currently existing individuals which are preferable to X, i.e., r(6!) = I{ E ,vk) where ei=(vi,v1 +1 ) is an edge in the graph and ei•ej for all icj. If vk=vO, the trail is a closed trail. A closed trail which touches every edge of G is an Eulerian trail (e-trail). We may use the shorthand (v0 ,v 1 ,v2 .- v k) for a trail, if we do not discriminate parallel edges. Note that a vertex vi can appear at more than one position in the trail. Each such position is called a terminal. vk and v0 are called the end terminals of the trail. The degree of a vertex v, denoted d(v), is the number of edges adjacent to it. A graph is Eulerian if an e-trail exists on it. It is well known that a graph is Eulerian if and only if all vertices in the graph have even degree. An e-trail for the graph in Figure 3 is

A. Move generation

A move is an operation on an e-trail which converts it into another e-trail. In a good iterative improvement technique it is important that the move set, i.e., the set of moves employed, corresponds to a neighborhood structure which spans the whole search space. Otherwise, there will be some configurations (e-trails or transistor orderings) that will not be reachable, resulting in a sub-optimal solution. In the previous section we have shown that any minimum-width ordering can be represented with an e-trail in the modified diffusion graph. Here, we introduce two moves which are sufficient to ensure that it is possible to transform any e-trail into any other via a sequence of moves: sub-trail modification and rotation.

T1 =(s,2,3,4,5,6,7,4,s,6,2, 1,s).

After G is created, we determine whether it is Eulerian or not. If it is not, we add a vertex, called the super-vertex, vs, to G and make it Eulerian by adding a new edge (vs, vi), called a

super-edge, for each odd-degreed v, (dashed lines in Figure 3). We call the resulting graph the modified diffusion graph. On the modified diffusion graph with m edges, we can find an e-trail using a well known algorithm with O(m2) time complexity [13]. There is also a linear time recursive algorithm for finding an e-trail which can be modified to handle various constraints [14].

A sub-trailis a set of consecutive edges in an e-trail. The subtrail modification move changes the order of a set of adjacent transistors. We first pick an arbitrary sub-trail of the e-trail. Next, we generate a sub-graph, G that has only the vertices

There are exponentially many e-trails in an Eulerian graph [15]. Another e-trail for the modified diffusion graph in Figure 3 is: 72 =(s,1,2,6,s,2,3,4,5,6,7,4,s). There are 176 e-

151

and the edges in that sub-trail (including the super-vertex and super-edges if any). Then, we find a different sub-trail in G '. Figure 4 shows an example. Note that G ' is either Eulerian or it has at most 2 odd-degreed vertices. In either case, the algorithm given in [14] can find an e-trail in O(m), where mis the number of edges in the sub-trail.

5 Results

The transistor ordering technique presented in this paper has been implemented in the C language on an IBM PowerPC 604 workstation running AIX 4.1. We have tested the algorithm on various dynamic CMOS circuits from the industry and literature. Table I lists some of these circuits and shows the results that were obtained.

Figure 4. Sub-trail modification move on the graph of Figure 3. Sub-trail (6, s, 4, 7, 6, 2) is replaced with (6, 7,4, s, 6, 2), where s corresponds to the gap.

a)

Table 1. m is the number of edges in the modified diffusion graph. m' is the number of transistors in the circuit and s is the number of super-edges added. H is the number of routing tracks for the worst ordering. h is the result of our technique.

El~~l bc d e

circuit

h g f a

b c d e g I

f a

The rotation move rotates the transistors in the ordering cyclically without breaking the shared diffusions. Figure 5 shows an example. Figure 5. Rotation move. The e-trail of Figure 4 b), (s,2,3,4,5,6,7,4,s,6,2,1,s), is rotated to obtain a new e-trail: (s,6,2, 1,s,2,3,4,5,6,7,4,s).

f a

m=m +s

H

h

cpu (sec.)

chak I chak2 chak3 ckl ck2 dI d2 d3 dorn3 uvl uvId

8+4 18+8 8+2 9+6 8+4 11+2 14+2 34+2 7+2 16+8 16+8

4

2

0.6

10 3 5 4 5 3 3 3 9 9

3 2 2 2 2 2 2 2 3 3

1.5 0.5 0.8 0.6 0.7 0.9 2.1 0.5 1.4 1.4

uv2

24+12

13

3

13.0

uv2d

24+12

13

3

14.0

Circuits chakl-3 are from [6]; ckl,2 are from [5]; dJ-3, dom3

b cd e g h

are domino CMOS circuits from industry. The last four circuits are from [21]. For all of the circuits, the optimum area is obtained: the number of diffusion breaks (cell width) and the number of routing tracks (cell height) are minimum Figure 6 shows the minimum area result for ckl. Both the number of gaps (2) and the number of routing tracks (2) is less than that reported in [5] (3 gaps, 4 tracks) 2

Note that neither of these two moves violates the Eulerian property of the trail: the trail generated by the move is also an e-trail. Therefore, the corresponding transistor ordering has minimum number of gaps i.e., minimum diffusion area is guaranteed. B. Move evaluation A move is evaluated with respect to the change in the cost of the transistor ordering as a result of the move. The cost of the transistor ordering is the final layout area. Since the moves in our move set do not change the cell width, we only need to look at the cell height to evaluate the new transistor ordering. The cell height is determined by the number of horizontal wiring tracks required to route the diffusion terminals. We denote it as the routing height. To find the routing height, we use the left-edge algorithm [17]. For a one-sided channel with n nets, the left-edge algorithm finds the optimal routing in 0(n). Figure 2 b) and c) show two routing examples generated by the left edge algorithm.

It is asserted in [21 ] that uvl (uvid is the dual), is a "difficult" circuit for row-based layouts. Indeed, when there is no height minimization, the area can be proportional to O(m2 ), for m transistors, whereas the gate-matrix style can produce a layout with O(mlog(m)) area. However, with our area minimization technique the transistor ordering has an area of 0(m). This is a positive result for row-based layouts as compared to gate-matrix. It is also worth noting that the enumeration technique of [8] for sCMOS (it was recently used in [22]) could also be applied to these circuits3 . Unfortunately, for the last two circuits that exhaustive algorithm would require time proportional to

C. Iteration control It is important that an iterative improvement scheme does not get stuck in local minima. We employed simulated annealing, which has been found to be very effective in optimizing many difficult layout problems [18][19]. In our implementation, we use a generic simulated annealing library that provides various effective iteration control mechanisms [20].

1. For verification, the optimum height as well as the worst case height for the last four circuits were found exploiting the special graph structure. For the other circuits we used a backtrack search technique for enumeration [15]. The full search takes around 16 hours for chak2. 2. We should also mention that this is not a complete comparison, since [5] uses a different layout style, called oilding layout. 3. The time complexity of that algonthm is super-exponential, O(h 3 hh). where h is the number of transistors in the longest discharge path [8].

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However, our iterative improvement technique 1 3 3x13x13 was able to find the theoretical optimum in less than 15 sec-

[4] C.T. McMullen and R.H.J.M. Otten, "Minimum Length Linear Transistor Arrays in MOS", IEEE InternationalSymposium on Circuitsand Systems, August 1988, pp. 1783-1786. [5] H.Y. Chen and S.M. Kang, "iCOACH: A Circuit Optimization aid for CMOS high-performance circuits", Proceedings of the

onds. Figure 6. Schematic of a dynamic CMOS circuit, ckl, and the optimum transistor ordering obtained for the nFET circuitry. For illustration purposes the routing is done in the channel, but it can also be done over-the-transistors to eliminate the routing footprint and save area.

IEEE/ACM International Conference on

Computer-Aided

Design, November 1988, pp. 372-375. [6] S. Chakravarty, X. He, S.S. Ravi. "On Optimizing nMOS and Dynamic CMOS Functional Cells", IEEE InternationalSvmpo-

sium on Circuits and Systems, Vol. 3:, May 1990, pp. 1701-4. [7] S. Wimer, R.Y. Pinter, J.A. Feldman, "Optimal Chaining of CMOS Transistors in a Functional Cell", IEEE Transactionson Computer-Aided Design, Vol. CAD-6, September 1987. pp.

795-801.

[8] R.L. Maziasz and J.P. Hayes, Layout Minimization of CMOS 2S 1 A

Cells, Kluwer Academic Publishers, Boston, 1992. [9] A. Stauffer and R. Nair, "Optimal CMOS cell transistor place-

5

31

ment: a relaxation approach", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Novem-

ber 1988, pp. 364-7. [10]C.Y. Hwang, Y.C. Hsieh, Y.-L. Lin, Y.-C. Hsu, "An Efficient Layout Style for Two-Metal CMOS Leaf Cells and its Auto-

2 -

I Z

- M b

matic

a g

Synthesis",

IEEE Transactions on Computer-Aided

Design, Vol. 12, No. 3, March 1993, pp. 410-424. [Il]N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, 1993. [12]T. Uehara and W. M. vanCleemput, "Optimal Layout of CMOS Functional Arrays", IEEE-Transactionson Computers, Vol. C30, No. 5, May 1981, pp. 305-312.

6 Conclusions A new transistor ordering technique was presented for area minimization of dynamic CMOS circuits. It is able to find a minimum area transistor ordering for all the practical circuits we have tested it on. It is very efficient, finding the optimum layout in less then 2 seconds for realistic dynamic CMOS leaf-cells. We are currently working to reduce routing blockages and handle gate connections effectively. We are also ex-

[13]J.A. Bondy and U.S.R. Murty, Graph Theory with Applica-

tions, Elsevier Science Publishing, New York, 1976. [14]B. Basaran and R.A. Rutenbar, "An 0(n) algorithm for transistor stacking with performance constraints", Proceedings of the

tending the cuiTent one-row technique to multi-row and 2-D

IEEE/ACM Design Automation Conference, June 1996. [15iA. Nijenhuis and H.S. Wilf, Combinatorial Algorithms, Aca-

styles by integrating it into a macro-cell style placer for overall area efficiency.

Stretchable Cells", IEEE Journal of Solid-State Circuits, Vol.

demic Press, New York, 1975. [161Y. Tsujihashi, et al., "A High-Density Data-Path Generator with 29, No. 1,Jan 1994, pp. 1-8. [17]A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures". Proceedings of the IEEE/A CM DA C, June 1971, pp. 155-69. [18]S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing", Science, November 83, pp. 671-680. [19]C. Sechen and K. Lee. "An Improved Simulated Annealing Algorithm for Row-Based Placement", Proceedings of the

We are also working on a performance-driven transistor ordering mechanism for parasitic sensitive dynamic CMOS circuits. We hope to extend analog leaf-cell layout techniques that control circuit parasitics in order to meet constraints on the performance of the circuit [14][23][24].

IEEE/A CM ICCAD, 1987, pp. 478-481.

Acknowledgments The authors would like to thank Prof. Ron Bianchini and Aykut Dengi (CMU) for helpful discussions and Dr. John Cohn (IBM) for providing some of the circuits. This work is supporter in part by the Intel Corporation and the Semiconductor Research Corporation.

[20]E. S. Ochotta, L. R. Carley, and R. A. Rutenbar, "Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Convert with ASTRX/OBLX", IEEE Custom Integrated Circuits Conference, May 1994, pp. 15.4/1-4.

[21]C.C. Su and M. Sarrafzadeh, "Optimal gate-matrix layout of CMOS functional cells", Integration, the VLSI journal, Vol. 9,

1990, pp. 3-23. [22]B. Guan and C. Sechen, "An area minimizing layout generator for random logic blocks", Proc. 1995 IEEE CICC, May 1995, pp. 23.1/1-4. [23]E. Charbon, E. Malavasi, D. Pandini, A. Sangiovanni-Vincentelli, "Imposing Tight Specifications On Analog ICs through Simultaneous Placement and Module Optimization", Proc. IEEE CICC, May 1994, pp. 525-28. [24]B. Basaran, R. A. Rutenbar and L. R. Carley, "Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog

References

[1] A. Domic, "Layout synthesis of MOS digital cells", Proceedings of the IEEE/ACM Design Automation Conference, June 1990, pp. 241-5. [2] S. Chakravarty, X. He, S.S. Ravi, "Minimum Area Layout of Series-Parallel Transistor Networks is NP-Hard", IEEE Transactions on Computer-Aided Design, Vol. 10, No. 7, July 1991, pp. 943-949. [3] T. Lengauer and R. Muller, "Linear Algorithms for Optimizing the Layout of Dynamic CMOS Cells", IEEE Transactions on Circuitsand Systems, Vol. 35, No. 3, March 1988, pp. 279-285.

Cells", Proceedings of the IEEE/ACM InternationalConference on Computer-Aided Design, November 1993, pp. 415-421.

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A FAST TECHNIQUE FOR TIMING-DRIVEN PLACEMENT RE-ENGINEERING Moazzem Hossain, Bala Thumma, and Sunil Ashtaputre Compass Design Automation San Jose, CA 95131 moazzem~compass-da.com, balat'compass-da.com, sunilaiDcompass-da.com

ABSTRACT As the VLSI technology is advancing rapidly, the complexity and size of the layout problems is also increasing. As a result, after the initial design cycle, it is getting almost impossible to get a good quality layout satisfying all the design constraints. Therefore, in a typical design flow, if the design has some problem or some of the initial constraints are not met after the initial design cycle, the designer may alter the design specification by changing some of the constraints and/or by adding or deleting some of the modules and/or nets from the design. These changes are known as engineering changes. However, due to the inherent long turn around time for the placement and routing phase, it is not desirable to redo the placement and routing from the scratch on the altered design. This calls for designing a fast layout tool, i.e., layout re-engineering tool, to handle the engineering changes. In this paper, we study the problem of timing driven placement re-engineering. We develop a design-style independent fast algorithm for placement re-engineering. The algorithm has been implemented in C++ and the initial experimental results on industrial designs show the effectiveness of our algorithm. 1.

INTRODUCTION

A circuit; consists of a set of modules and a netlist specifying the interconnections between the modules. The VLSI layout problem is to realize the circuit in a minimum layout surface while meeting the circuit specifications. High performance and minimum layout area are the two most important objectives for a VLSI design layout problem. Traditionally, due to the inherent complexity of the problem, the VLSI layout problem of a circuit has been divided into two sequential phases: placement and routing. The objective of the placement problem is to map the modules of a circuit on a layout surface while optimizing certain objective functions. Once the placement is complete, the routing problem is to realize the interconnections between the modules according to the specifications. The region on the layout area which is not occupied by modules can be used for routing. In a typical design flow, if the circuit has some problem or some of the initial constraints are not met after the initial design cycle, the circuit designer may alter the design specification. These changes are referred to as engineering changes. The process of generating new design the incorporates the engineering changes is referred to as design reengineering[41. There are two forms of engineering changes: (1) structural changes, such as adding and deleting modules and nets from the circuit; (2) specification changes, such as changes in the timing constraints. In this paper, we address

154

the problem of placement re-engineering. The input to the placement re-engineering is a completely placed circuit and the engineering changes. The output is a placed circuit that incorporates all the structural changes and maximum number of specification changes. In an ideal situation, all the specification changes will be met in the final placement. However, if some of the specification changes are not met, the designer may make further engineering changes to meet all the design specifications. In [4], timing-driven placement re-engineering problem for regular architecture, such as FPGAs, has been addressed. In [2], an algorithm for minimizing the disturbance on the original placement while handling placement engineering is presented. Engineering changes during circuit simulation has been presented in [3]. In this paper, we address the problem of timing-driven placement re-engineering. The algorithm is design-style independent and wroks equally well on both standard cell and gate array designs. The nets are assigned weights based on the timing requirements. For each added module in the circuit, the algorithm first computes its target window and places the module within its target window. After all the added modules are placed, the algorithm iteratively moves modules based on target window of each module to satisfy all the timing constraints. The algorithm has been implemented in C++ and preliminary experimental results show good results on timing-driven layout on both gate-array and starndard cell designs. The remainder of the paper is organized as follows: Section 2 presents the formal definition of the re-engineering problem and some related definitions. Section 3 presents our algorithm. Some preliminary experimental results have been presented in Section 4. Conclusion is presented in Section 5. 2. PRELIMINARIES Engineering changes can be classified into two categories: 1. Structural changes: These changes modify the structure of the circuit. Addition and deletion of modules and nets fall into this category. 2. Specification changes: Changing the timing constraints or adding new timing constraints, changing the delay of a module are considered specification change of a circuit. When a module or a net is deleted from a circuit, it is easy to see that it will not cause an increase in the delay on a constrained signal. Therefore, it is easy to implement the deletion of a module or a net. However, adding new modules or nets to the netlist may cause the violation of

the existing timing constraints. As a result, addition of new modules or nets is more difficult and important in the placement re-engineering problem. We, therefore, address the problem of adding new modules, nets, and constraints into the circuit. A circuit consists of a set of modules M = {j1, /12-., itn}, a set of nets AV = {V1,v2,...,vm}, and a set of timing constraints T. The timing constraints are specified by the maximum allowed time from a primary input to a primary output. Associated with each net vi, we define a weight function w(vi) be a positive integer value. The netlist can be described as a binary relation 7R = JK x M. A pin of a net v C Y on a module it e M is represented by (v, t) E R. The set of modules connected by a net v is defined by M, = f E MI(v,p) E 7Z}. Similarly, the set of nets with a pin on module it is defined by A' = {v e N(l(V, ,) E 7Z}. For a net v E A, the bounding-box, B., of v is defined by the minimum rectangle enclosing all the pins of v. The weighted net length of v, L>, is estimated by half-perimeter length of B, times the weight w(v). In the remainder of the paper, we use net length to mean weighted net length. Since in most of cases, the interconnections between the modules are realized by rectilinear wires, the weighted net length of a net can bie considered as the summation of weighted length in x and y-direction. The weighted lengths in x- and ydirection are also called x-length and y-length, respectively. For a net, v, if L,>(x) and L>,(y) are x-length and y-length, respectively, then L, = Lv(x) + L, (y). For a net v and a module p, if (v. it) E 7Z, then we define BO be the boundingbox of v without the pin (v, i). The total net length is the sum of the lengths of all nets in K. Let f (x) be a piece-wise linear unimodal function. We define the domain of minimum, [xi, x,], of f (x) as the subset of the domain of f (x) such that f (x) reaches its minimum if and only if i < x <xr. In our algorithm, we use the notion of multiset. Just like a set;, a multiset is a collection of elements; however, unlike set, a multiset can have multiple occurences of the same element. Let a, and be be the number of occurences of element e in multisets A and B, respectively. The operation union of two multisets A and B results in a multiset C in which the occurences of e is ae + be. The operation intersection of two multisets A and B results in a multiset C in which the occurences of e is min{ae,be}. Let C = A n B and ce be the number of occurences of element e in C. The operation A - B results in a multiset D in which the occurences of e is ae + ce, Given a placement of all the modules in M, we are to find an optirnal location for a module M. The optimal location for pi is a location on the layout area such that placing ,u in that location results in a minimum total net length for all the nets with a pin on it. A target window, W,, for a module Adis a rectangular region (XI, yb, Xr, yt) such that placing it at (x, y) results in a minimum L, if and only if xi < x < x, and yb < y < yt. For ,i, if Wa can be computed then jt can be placed inside W, to minimize the total net length.

Initial placement of added modules

I

Figure 1. The main flow of our algorithm are assigned based on the criticality of the nets and how far off the signals are from their timing constraints. The overall flow of our algorithm is almost similar to the one presented in [4]; however, we use target window to place each added module. We develop a very efficient linear time complexity algorithm to compute the target window for each module to be placed. The target window gives a region in which placing the module will result in a minimum total weighted netlength for all the nets with a pin on the module. Target window is also used to iteratively improve the placement to meet the timing requirements. Figure 1 gives an overall flow of our algorithm. The target window based initial placement of new modules places the modules within the target window while minimizing the number of overlaps. However, in a very highoccupancy design, there may be some overlaps of modules after the initial placement. The second phase of our algorithm iteratively moves the overlapping modules based on the target window of each module to be moved to remove the overlaps.

3. OUR ALGORITHM The input to our algorithm is the modified netlist for a circuit along with the placement of the modules that are not replaced or modified. The output is the final placement with all the engineering changes incorporated in the design. Based on the timing constraints and timing analysis, we assign weights to nets to meet the timing constraints. Weights

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Once the overlaps are removed, we iteratively do the timing analysis and improvement of the placement by moving modules based. on the target window At each step we assign weights on nets based on the timing analysis. As can be noted from the above discussion that target window computation is the key to our algorithm. For each added module we compute its target window to place the module. Target window is also used to iteratively improve the placement to unoverlap and meet the timing constraints. We now present the detailed algorithm to compute the target window for a module.

.,

3.1. Target Window Computation For a given a module ps e M, we are interested in computing its target window W, = (xv, y', x ', yt). The target window is computed using the nets with a pin on p. The x-span and y-span of the window are (xr, xz) and (y", yt), respectively. The x-span is computed using the x-length. Similarly, the y-span is computed using the y-length. It is easy to see that the two can be computed independently. We only present of the computation of x-span of the target window. The computation of y-span is similar. Let k ok > 1) be the number of nets with a pin on p, Then 1 = {ZAP' ,... ,v'}. Also let w(vi') > 1 be the weight and BP,, = (li,.bi, ri, ti) be the bounding box of vr without

I Y(~L. ) I

Figure 2. window.

the pin (vAip). Let the placement of all the modules in M - {p} be fixed and we need to find a placement location for p. Let Lx(zi4',,) be the weighted length function for net vz? in the x-direction with respect to the placement location of p. [t is easy to see that Lx (vi, p) is a piece-wise linear unimodal function. Then the domain of minimum of Lx (vi, p) is [li,ri]. If L( (p) is the x-length function for 1 all the nets with a pin on A, then L. (p) _- Lx(z4v p). Since the sum of piece-wise linear unimodal functions is also piece-wise linear unimodal function, L. (p) is a piece-wise linear unimodal function. Therefore, the domain of minimum of Lx,(p) will give the x-span of the target window of p . Figure 2 gives an example of a length function L(,(pi) and L,(p'i) for medule p1i for one net. Three modules /11,112, and p3 are connected by a single net. Also note that Wi is the target window for pi. Based on the above discussion, a straight-forward algorithm to compute the x-span of the target window of a module p E M can be computed by first computing the functions Lx (V,,, p), for 1 < i < k and then by algebraically adding Lx(v. p) and computing the domain of minimum of the resultant function. However, the time complexity of such an algorithm is 0(k 3 ), where k is the total number of nets with a pin on p. We make use of the piece-wise linear unimodality of Lz (vi', p) to develop our linear time complexity algorithm. For Lx (vt, p) with domain of minimum [li, ri] and for a point (x, y), we say that the domain of minimum of L1 ,(v',p.) is on the left side of x if ri < x, and the domain of minimum of Lx (vi l If W1 > W2, then for any value 1', xi < l' < 1, Lx(pi) will decrease, thus the assumption that 1 is the boundary of the domain of minimum of Lx(,u) is not true. Similarly, if w, < w2 then then for any value 1', 1 < l' < rr, Lx(11 ) will decrease, thus 1 is not in the domain of minimum of L. (1 ). Therefore, wi must be equal to w2. Since, w, = W2, the value of L. (p) will be same in 1 and in zi. Now for any value I' < xi, the net length of k 2 nets will increase by W2, the net length for k 1 - 1 nets will decrease by Wi - 1 and the net length for k3 + 1 nets will remain the same. Therefore, L,(pi) will increase. Thus xi is the boundarv of the domain of minimum of L,(p). Therefore, 1 must be equal to xi; as a result 1 E S. Similarly, we can show that r E S. The algorithm, TARGET-WINDOW, presented below is based on the above lemma. The input to the algorithm is the module p for which the target window should

Lemmea 1 Given a module p E M, let A'p = {zV, Vi,...,VAz}. Let w(vl) > 1 be the weight of net Vz/. If for 1 < i < k, Lx(vZI, p) is the function of x-length of ZiA with respect to the placement of pi with domain of minimum [1,, rj, let S = U_ Ul( ')

x

{li, ri} be a multiset. Also

156

be computed. For k nets (k > 1) connected to ju, their domain of minimum with respect to the placement of p is computed first. A multisets S. and S, are constructed from the boundary the domain of minimum of Lx(zvt,jL) and Lzx(vj,',p, respectively, for all the nets with a pin on p. The median two values in Sx and S, gives the domain of minimum of Lx(ti) and L 5 (p). We now formally present the algorithm.

Table 1. Specifications of Benchmark Examples circuit r#modules #nets structure constraint changes changes cl 1204 1309 17 5 c2 6372 7268 15 10 c3 14115 14930 __ 25 14 c4 14332 15339 57 29 c5 34965 36643 151 12

procedure TARGET-WINDOW(p) 1. compute , . 2. Let S. = ; S=. 3. Let m = 0 4. for each net vo E Af(, do 4.1. Let w(vt) be the weight of v4' 4.2. compute Bog = (li, bi, ri, ti). 4.3. for j = 1 to w(v,") do 4.3.1. Sx = Sx U {li,ri}. 4.3.2. S, = S, U{bi, t } 4.4. m=m+2*w(vi). 5. Let I = mth smallest element in Sx Let b = Ath smallest element in S, Let r = Xj + 1)th smallest element in S. Let t = (m + 1)th smallest element in S, 6. return (, b, r, t);

Table 2. Comparison with mincut based placement circuit mincut placement our algorithm time(sec) delay(ns) time(sec) delay(ns) cl 20 48.4 3 49.3 c2 112 75.0 9 74.7 c3 815 152.5 22 155 c4 718 143.9 18 145.1 c5 8631 284.0 105 285.3 As can be seen from the experimental results that our algorithm is extremely fast and produces very result timing constrained placement.

According to [1], the mth smallest element in Sx (Sy) can be computed in 0(m) time. Since the bounding box of nets are computed incrementally, we can assume that the bounding box is already computed and stored in the data structure. Thus the overall time complexity of the algorithm TARGET-WINDOW is dominated by the computation of the - th and ( - + 1)th smallest element in Sx and in S1,. Therefore the time complexity of the algorithm TARGETWINDOW is 0(m) = 0(k) where k is the number of nets connected to mu. Following theorem shows that the bounding box [1, b, r, t] computed by the above algorithm TARGET-WINDOW is the target window for the given module p.

5. CONCLUSION In this paper, we have presented a design-style independent algorithm to solve the timing-driven placement reengineering problem. The algorithm is based on a linear time complexity target window computation for each module to be placed. Initial experimental results on both standard cell and gate array designs show the effectiveness of our algorithm. REFERENCES [1] M. Blum, R. Floyd, V. Pratt, R. Rivest, and R. Tarjan, "Time Bound for Selection." Journal of Computer and System Science, vol. 7, pp. 448-461, 1972. [2] C. Choy and T. Cheung, "An Algorithm to Deal with Incremental Layout Alteration", Proc. 34th Midwest Symposium on Circuits and Systems, vol. 2, pp. 850853, 1991. [3] Y. Ju, "Incremental Circuit Simulation and Timing Analysis Techniques", Ph.D. Thesis, University of Illinois at Urbana-Champaign, 1993 [4] A. Mathur, K. C. Chen, and C. L. Liu, "Re-engineering of Timing Constrainted Placements for Regular Architectures", Proc. IEEE Intl. Conf. Computer-Aided Design, pp. 485-490, 1995.

Theorem 1 The bounding box [1, b, r, t] computed by the algorithm TARGET-WINDOW is the target window for a given module p. Furthemore, the time complexity of the algorithm TARGET-WINDOW is 0(k), where k is the total number of nets with a pin on p. Proof: Directly follows from the proof of lemma 1. U 4. EXPERIMENTAL RESULTS We have implemented our algorithm in C++. We have tested the performance of our algorithm on some industry circuits and compared our results with the constructive placement algorithm to handle to enginnering changes. As mentioned earlier that the placement re-enginering should be very fast compare to the actual placement from the scratch. Our experimental results demostrate that our algorithm is very fast. It is important to note that the algorithm takes longer time in very high-density design. This is due to the fact that the algorithm has to perform more number of iterations to unoverlap the modules during iterative improvement phase. Table 1 gives the specification of the circuits on which the experiments were conducted. Table 2 gives the comparison between mincut based placement to incorporate all the engineering changes and our algorithm. The column of time specifies the run time for both mincut placement and our algorithm and the column delay specifies the delay on the critical path after the final placement.

157

OVER-THE-CELL ROUTING WITH VERTICAL FLOATING PINS Ines Peters, Paul Molitor'

Michael Weber 2

'Computer Science, University Halle, Germany petersginformatik.uni-halle. de [email protected] 2 Deuretzbacher Research GmbH, Berlin, Germany [email protected]

ABSTRACT We present a generalized center terminal cell model and propose over the cell routing algorithms, utilizing the new feature of the model, i.e., Vertical Floating Pins. First we approach the problem by linear integer programming, and second by dynamic programming. For further channel density reduction, both approaches have been combined with linear channel pin assignment, that has been studied by the authors before. Experimental results show a resulting channel density reduction by about 35% compared to the over-the-cell routing algorithms for center terminal cells proposed in [19] and [26].

Next we adapt the Over-the-Cell (short OTC) routing problem to the PARD model and present algorithms to utilize the new features in order to minimize final layout area. We propose algorithms for two different goals. The first is to maximize the number of segments routed over the cell and the second is to minimize the resulting channel density. We approach the problem by linear integer programming and by dynamic programming. Experimental results on benchmark testsets are given at the end of the paper. They show a resulting channel density reduction by about 35% compared to the over-the-cell routing algorithms for center terminal cells proposed by [19] and [26].

2. 1.

THE PARD CELL MODEL

INTRODUCTION

The channel and over-the-cell routing problems play an important role in the physical design of VLSI circuits. They have been extensively studied in the past ([1], [4], [5], [7], [8], [11], [12], [15], [16], [17], [19], [21], [26], [27], [28]). The routing strategies depend on the underlaying cell mode].. Many cell models have been proposed in the past ([1], [13],[131, [14], [16] [18]', [24], [25], [26]).

connecte pins

:al ing

We distinguish between two major classes of cell models: 1. Margin terminal cell models (MTCM): The cells termia als are located along the top and bottom cell boundaries ([6], [13]) and 2. Middle or Center terminal cell models (CTCM): The cell terminals are located within the cell area ([14], [24], [25], [26]). In this paper we deal with CTCM cells. The main problem of CTCM cell design is, where exactly to place the terminals. Practical observation in industrial cell design shows, that very often the terminal placement allowed in the cell models is more restrictive than necessary. So we present in this paper the routing features - vertical floating pins - of a new generalized CTC-Model, i.e., the PARID-Cell model ([20]). Note that the PARD-Cell model has already been applied in two industrial chip projects.

When designing a new cell catalogue in a double metal 0.8 micron CMOS technology 2 we observed, that terminals can

'There a transparent cell model - TRANCA - was presented. It provides terminal access points in spite of fixed terminal positions. Unfortunately this model is hardly to manage by discrete optimization technics.

2 Note that we focus on double metal because more metal technologies are still too expensive for smaller ASIC manufacturers. The model presented in [1] uses a three metal layer technology where the third layer is essential for the algorithm proposed.

Figure 1. Vertical floating pins of PARD-cells

158

be looked at to be floating in vertical direction (see figure 1). Power-Ground lines are done in METI along the cell boiders. POLY and METi are used for internal connections. MET2 is preserved for OTC routing. The new routing features of the PARD cell model are the Vertical Floating Pins. They are a sort of prerouting we get immediately from cell design. Their basis are internal connections in MET1. Where in other models the cell designer decides where to place vias from METI to MET2 for OTC routing, we leave this decision to the OTC router itself. Thus MET2 is completely free for OTC routing. Vertical floating pins give the router more flexibility. Figure 2 shows an interesting routing pattern. We have a pin-net ordering of (1, 2, 3, 1, 2, 3). This ordering cannot be routed over the cell in other (two metal layer) cell models for planarity reasons. The "implicit tunneling" of the vertical floating pins obviously enables an OTC routing.

1 vertical floating pin of net 1 ,,

3

1

2

,,

:: =

.--

. .2

:

.

1

Figure

2

II

::t t I

2

1. The net segment does not cross any forbidden zone of other nets and 2. the horizontal constraints are fullfilled, i.e., the net segments of different nets do not overlap. Note that unlike in [16] the problem cannot be solved by simply applying maximum k-independent set algorithms because tracks are not necessarily contiguous and the sets of nets that can be assigned to these tracks are different.

3

:

to the top, to the bottom or to the top and to the bottom of its cell.To ensure the routability we introduce "forbidden zones". One zone runs from the desired cell boundary directly to the nearest point of the vertical floating pin, where a via can be placed for connection This zone is forbidden for all other nets. The OTC routing problem can now be described as follows: Find for every net an OTC-track, which realizes the net such that:

::

3

1

*

2

4.

3

2. An interesting routing pattern

In this section we will decribe how to use (0, 1) - linear integer programming for solving the OTC-routing problem. In the first part we will give an integer program in order to maximize the number of nets routed over the cell. In the second part we will expand this program in order to minimize the resulting channel density. 4.1.

3.

In the following we assume two-pin nets. All operations can easily be adapted to multi-pin nets (just allow overlap of segments that belong to the same original net). top pin

Assigned Nets Maximization

Given a set NET = {n,_ . ..,rr} of nets and a set TRACK = {ti tq} of (OTC-) tracks. For the following definitions let 1 < i, k < p be net indices and let 1 < j < q be a track index. Let f : NET -e 2TRACK be the function which assigns to all nets the set of non-forbidden track numbers. In these tracks the net can be connected to the corresponding vertical floating pins without crossing forbidden zones. We will use the notation

OTC ROUTING PROBLEM

vertical floating pins

LINEAR INTEGER PROGRAMMING

forbidden zone

I/

1, tj fi

A\

-------

i.

I

.

- - - - - - -

1

1

- - - - - -

iii l11 1 l

1'1l

1

1~~~'' -1

- - - -

-

- - - I

E

f(ni)

otherwise

in the following. From a given OTC-routing problem we can derive the horizontal constraints defined by o : NET x NET -* {0, 1} with

1-.

I.

0,

-

----

'

o(n,,nk) =

f

1, 0,

"overlaps" nk, nj 7L nk otherwise

kni

Once again we will use the notation oik

=

o(ni, nk).

In our integer program we have the following variables bottom pin

top-bottom pin t7

Figure 3. Forbidden zones in a cell row

{

1, ni "assigned to" tj -t 0, otherwise I

i.e., vij denotes whether net ni is assigned to track tj. Next we define the constraints of the integer program:

The global routing phase gives us an information for every (vertical floating) pin, whether it has to be connected

159

1. Nets can only be assigned to allowed tracks, i.e.,

vij < fi,

Vi,k E {I_._ p}. The variables are given by

vj =

has to hold Vi, j. 2. Every net can be assigned to at most one track. Thus

{

1, ni "assigned to" tj otherwise

0,

t

Vi E {1,...,p},j E {1,...,m+q} and

q

< 1

EV,

1,

U

j=1

=

has to hold Vi. 3. No two overlapping nets can be assigned to the same track, i.e.,

tj "is free" otherwise

I 0,

Vj e {1, . . ., m}. The v-variables are similar to these of the first integer program. The u-variables indicate whether a certain outer track is free or not.

Vij + Oik + Vki < 2

Next we define the constraints:

Vi, j, k.

1. All nets can only be assigned to allowed tracks: Vi E .mp},j e { +q}

Finally we define the optimization goal, namely P

max

vij < fij,

q

3

Vij. 2. Every net has to be assigned to exactly one track (OTC or outer): Vi E {1... ,p}

,=i j=1 Thus the integer program assigns as many nets as possible to OTC-routing tracks. The complexity of (0, 1) - linear integer programs is determined bv the number of variables and constraints. The presented program consists of pq variables and pq + p + p2q constraints. We can reduce the number of allowed track variables by setting the variables vij to 0 for fij=o and by eliminating Vij + Cik + Vki < 2 for Oik = 0. 4.2.

Evij =1 j=, 3. No two overlapping nets can be assigned to the same track: Vi, k E {1, .. ,p},j E {1,. ., m + q} Vij + Oik + Vki

4. Free outer track condition: The u-variables have to be 0 when at least one net is assigned to the corresponding outer track and they have to be 1 when no net is assigned to this track.

Channel Density Minimization

Given a set NET = {ni,. .. ,np} of nets and a set TRACK TRACKot U TRACKotc of tracks with TRACKot = {ti,.. ,tm} and TRACKotc= {tm+i, . . . ,tm+q}. According to the actual OTC-routing problem we can decide to minimize the channel density locally or globally. In the local case the OTC-tracks (TRACK0 tc) are the tracks of one certain cell row and the outer tracks (TRACKo.t) are the tracks of the two channels below and above this cell row. In the global case we extend the OTC-tracks to the tracks of all cell rows of a given standard cell placement. The outer tracks are the tracks of all channels inbetween these cell rows. Because the number of channel routing tracks needed is not fixed at the beginning of the routing phase, we just preserve "enough" tracks to complete the routing. Our integer program has the goal to "clear" as many outer tracks as possible. So we reduce the channel density of the nets not routed over the cells. Let f: NET - 2 TRACK and


Vij + uj > 1.

Finally we define the optimization goal:

max

1, tj (Ef (ni) 0, otherwise

f 1, n, "overlaps" nk, 0, otherWise

Vi

* Force u-variables to 1: Vj E {1, . .. , m}

E

u,.

j=1

Thus the integer program clears as many outer tracks as possible. The extended program consists of p(m + q) + m variables and p(m + q) + p + pt (m + q) + pm + m constraints. The allowed track and overlap constraints can be reduced in a similar way as above.

Vi e 41. p},j E {1,..-., m + q4 This function assigns a net the OTC- and outer tracks allowed. The overlap function is defined by o: NET x NET {0, 1} and Oik

< 2.

ni :

nk

160

5.

DYNAMIC PROGRAM

names in the second. (A number of n channels for a circuit indicates a n + 1 cell row placement.) Not OTC-routed nets have been routed in channels between the cell rows. We achieved densities Dl, D2 and D3 for these channels. DI results from the PDCPA OTCrouting, D2 from linear integer programming in order to maximize the number of segments routed over-the-cell combined with PDCPA, and D3 from dynamic programming in order to minimize the resulting channel density combined with PDCPA. Note that D2 results are in some cases better than D3 results. That is why the "preconditions" for PDCPA channel density minimization after net segment assignment seem to be better in these cases. It will be part of future work to investigate this relationship in more detail. The improvements are given in percent. The D3-results for PRIMARY1 were achieved by a heuristic (left edge based) approach. The other examples could be computed with an exact algorithm. We achieved an average improvement by about 35% in both assigned track maximization and in remaining nets density minimization. The density minimization led to slightly better results. The linear integer program needed a run time of some seconds. The dynamic program took a bit longer, but less than ten minutes in all cases. We also tried the global minimum density integer programming approach (for the smaller examples). The results were the same in fact as for the other approaches, but the running time was much longer, up to one hour. So we would suggest the dynamic programming approach to minimize the resulting density. In future work we will examine the influence of the selection of nets to be routed over the cell to the succeeding channel pin assignment step for further density improvement.

In order to speed up the OTC-routing we present a dynamic programming approach. Let NET = {nl,...,n,} be a set of nets and TRACK = {ti, . . .,tq} a set of (OTC-) tracks. Let f N ET -. 2 TRACK and oij be defined as above and let 9: TRACK -* GRAPHS be a function defined by g(j) = (Vj, Ej) with Vj

=

{Vk I j E f(Vk)}

E5j

=

{(vi,vz)

I vi,,vL

and Vj AOil

=

1o

We assign an OTC-track a graph whose nodes represent the set of allowed nets of this track and whose edges represent the horizontal constraints of these nets. As the maximal independent sets are of interest for our routing problem we consider the sets Lj = {,N; Nj C Vj,Nj ma-. indep. set of g(j)} Vj E {1,... , q} in the following. The computation of all maximum independent sets of a graph is known to be NP-hard. Depending on the actual OTC-routing instance, we therefore decide for an exact algorith:m or a fast (for instance left edge based, [21], [28]) heuristics in order to compute the maximum independent sets. Now we can start with our dynamic program: For every OTC-track 1,starting with the lowest, we compute a set of net seits, which can be routed over the cell using the tracks 1 to 1. This can be done by combining the sets of the track - 1 with the maximum independent net sets of track l.

ml for do

:-

L1 :=

ml

:=

2toq

{m I 3mi E Ml-i1m m

2

E Li:

:= ml U m2}

[1]

od Let S, c- Mq with I Si I is of maximum size. Obviously Si is a solution which assigns most nets to over cell tracks. Let S2 E Mq with minimum resulting channel density. So S2 is obviously a solution which assigns nets to over-cell-tracks such that the remaining nets have minimum density. 6.

[2]

[3]

[4]

EXPERIMENTAL RESULTS

We implemented the proposed algorithms in Modula-2 language on PC and combined them with the PDCPA algorithm proposed in [19] as a postprocess. We used the Public Domain Integer Linear Program Solver of Michel Berkelaar (see [22]). The data include Primaryl and ISCAS benchmarks mapped to PARD-Cells. Note that PARD-Cells areas compare favourably to other (industrial) cell models. Layout data have been generated with HULDA ([9], [10]). The lengths of the vertical floating pins vary from 4 to 10 tracks. Most of them have a length of 6 or 7 tracks. The experimental results are summarized in Table 1. The circuit names are given in the first column and the channel

[5]

[6]

[7]

[8]

1

61

REFERENCES S. Bhingarde, R. Khawaja, A. Panyam, N. Sherwani, " Over-the-Cell Routing Algorithms for Industrial Cell Models," Proc. 7th International Conference on VLSI Design, pp.143-148, Jan. 1994. Y. Cai, D.F. Wong, "Minimizing Channel Density by Shifting Blocks and Terminals," Proc. ICCAD,pp.524527, 1991. Y. Cai, D.F. Wong, "On Shifting Blocks and Terminals to Minimize Channel Density," To appear in IEEE Trans. on CAD, 1992. Y. Cai, D.F. Wong, "Optimal Channel Pin Assignment," ICCAD, To appear in IEEE Trans. on CAD, 1990. H.H. Chen, E.S. Kuh, "Glitter: A Gridless VariableWidth Channel Router," IEEE Tlrans. on CAD, Vol. CAD-5, No. 4, pp.459-465, Oct. 1986. J. Cong, B. Preas, C.L. Liu, "General Models and Algorithmns for Over-the-Cell Routing in Standard Cell Design," Proc. 27th DAC, pp. 709-715, 1990. S.C. Fang, W.S. Feng, S.L. Lee, "A New Efficient Approach to Multilayer Channel Routing Problem," Proc. 29th DAC, pp.579-584, 1992. T. Fujii, Y. Mima, T. Matsuda, T. Yoshimura, "A Multi-Layer Channel Router with New Style of Overthe-Cell Routing," Proc. 29th DAC, pp.585-588, 1992.

Table 1. Experimental results

_UTu-it -

-CE7

CM;13O CM:150

chl chl ch2 ch3 ch4 chl chl chl chl chl chl ch2 chl ch2 chl ch2 ch3 ch4 chl ch2 chl ch2 chl chl ch2 ch3 ch4 chl chl ch2 chl ch2 ch3 ch4 ch5 ch6 ch7 chl ch2

CM/[151 CM/1162 CMV.163 CIVM42 CM/182 CM485 GMB CORDIC

CU DECOD II MUJX

PARITY PM1 PRIMARY1

X,! average -

-

D1

7 8 8 10

12 19

16 15 9

12 13 9

13 11

15 15 8 16 12 13 10

7 14 16 15 10

21 14 13 12 16 18 18 19

23 24 32 15 12 1:

D2 2 5 6 6

28.6 62.5 75.0 60.0 9 75.0 11 57.9 5 31.2 6 40.0 2 22.2 5 41.7 7 53.8 5 55.6 8 61.5 8 72.7 12 80.0 12 80.0 4 50.0 11 68.7 7 58.3 6 46.2 6 60.0 2 28.6 7 50.0 12 75.0 12 80.0 8 80.0 16 76.2 6 42.9 8 61.5 8 66.7 12 75.0 14 77.8 15 88.9 18 94.7 21 91.3 22 91.7 29 90.6 8 53.3 6 50.0 64.6 9

D37 3 5 6 6 9 10 4 5 5 6 9 5 8 6 11 12 5 10 6 6 6 2 7 11 11 8 16 6 9 9 15 15 16 17 22 22 30 7 7 9

--

T

42.8 62.5 75.0 60.0 75.0 52.6 25.0 33.3 55.6 50.0 69.2 55.6 61.5 54.5 73.3 80.0 62.5 62.5 50.0 46.2 60.0 28.6 50.0 68.7 73.3 80.0 76.2 42.9 69.2 75.0 93.7 83.3 88.9 89.5 95.6 91.7 93.7 46.7 58.3 64.2

[9] T. Hecker, I. Peters, B. Wartenberg, M. Weber, "An Integrated Synthesis Tool for the Generation of Space Efficient Standard Cell Layouts," Proc. 37th IWK, IImenau, Sept. 1992. [10] T. Hecker, I. Peters, M. Weber, "A New Integrated Approach to Global and Detailed Routing of Standard Cell Layouts," Dagstuhl Seminar 9343: Combinatorial Methods for Integrated Circuit Design, Oct. 1993. [11] T.T. Ho, "New Models for Four- and Five-Layer Channel Routing ," Proc. 29th DAC, pp.589-593, 1992. [12] C.Y. Hou, C.Y.R. Chen, "A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing," Proc. 29th DAC, pp.594-599, 1992. [13] N. Holmes, N. Sherwani, M. Sarrafzadeh, "Algorithmns for Three-Layer Over-the-Cell Channel Routing," Proc. ICCAD, pp. 428-431, 1991. [14] E. Katsadas, E. Kinnen, "A Multi-Layer Router Utilizing Over-Cell Areas," Proc. 27th DAC, pp.704-707, 1990. [15] M.S. Lin, H.W. Perng, C.Y. Hwang, Y.L. Lin, "Channel Density Reduction by Routing Over the Cells," IEEE Trans. on CAD, Vol 10, No. 10, Aug. 1991. [16] S. Madhwapathy, N. Sherwani, S. Bhingarde, A. Panyam, "A Unified Approach to Multilayer Over-theCell Routing," Proc. 31st DAC, pp.182-187, 1994. [17] S. Natarajan, N. Sherwani, N.D. Holmes, M. Sarrafzadeh, "Over-the-Cell Channel Routing For High Performance Circuits," Proc. 29th DAC, pp.600-603, 1992. [18] M. de Oliveira Johann, R.A. da Luz Reis, "A Full Over-the-Cell Routing Model," Proc. VLSI'95, pp.845-850, 1995. [19] I. Peters, "Priority Driven Channel Pin Assignment," Proc. 5th GLS VLSI, pp.132-135, 1995. [20] I. Peters, M. Weber, "The PARD-Standard Cell Model," to appear. [21] B. Preas, M. Lorenzetti, ed., "Physical Design Automation of VLSI Systems," The Benjamin/ Cummings Publishing Company, Inc., Menlo Park, CA 1988. [22] M.J. Saltzman, "Mixed Integer Programming Survey," OR/MS Today, pp.42-51, April 1991. [23] C. Sechen, A. Sangiovanni-Vincentelli, "The TimberWolf Placement and Routing Package," IEEE Journal of Solid-State Circuits, vol. sc-20, no. 2, April 1985. [24] M. Terai, K. Takahashi, K. Nakajima, K. Sato, " A New Model for Over-The-Cell Channel Routing with Three Layers," Proc. ICCAD, pp.432- 4 35, 1991. [25] M. Tsuchiya, T. Koide, S. Wakabayashi, N. Yoshida, " A Three-Layer Over-the-Cell Channel Routing Method for a New Cell Model," Proc. ICCAD, pp. 4 3 2 435, 1991. [26] T. Wang, D.F. Wong, Y. Sun, C.K. Wong, "On Overthe-Cell Channel Routing," Proc. EuroDAC, pp.110115, 1993. [27] B. Wu, N. Sherwani, N.D. Holmes, M. Sarrafzadeh, "Over-the-Cell Routers for New Cell Modell," Proc. 29th DAC, pp.60 4 -60 7 , 1992. [28] T. Yoshimura, E.S. Kuh, "Efficient Algorithms for Channel Routing," IEEE Trans. on CAD, Vol CAD-1, No. 1, pp.25-35, Jan. 1982.

16 2

Congestion-Balanced Placement for FPGAs* Yachyang Sun Altera Corporation Rajesh Gupta C. L. Liu Department of Computer Sciences University of Illinois at Urbana-Champaign Abstract In this paper, we propose to use routing congestion as a criterion in solving the FPGA placement problem. Based on the notion of congestion balance, we propose a placement algorithm that spreads out evenly routing congestion while minimizing the total wire length. This algorithm is based on the min-cut strategy which balances the numbers of interconnections in the two portions during each application of the min-cut partitioning procedure. The algorithm also minimizes the actual number of nets crossing horizontal and vertical cut-lines instead of using an estimated number of interconnects as was commonly done. We also propose an alternative way of employing the cut-line that allows the examination of a larger number of solutions to enhance the quality of the final solution. It also obviates the need for conventional terminal propagation techniques that are inherently less accurate in estimating net congestion. Based on our experiments, we propose a novel ordering according to which the cut-lines are applied. The ordering is related to the distance of a cut-line from the center of the chip. The cut-line closer to the center is applied earlier. This avoids the occurrence of a cut-line that has a large cut size and is close to the center of the layout area (as it often happens in a traditional top-down min-cut based placement). Experimental results show ;L reduction of up to 23% in maximum cut size and wire congestion, compared with the traditional min-cut placement algorithm.

1

Introduction

In most CAD tools for FPGAs the placement stage has traditionally employed algorithms originally developed for other technologies such as printed circuit boards and custom integrated circuits. Most placement tools use a min-cut algorithm [1, 9, 13] that employs a recursive top-down bipartitioning procedure to minimize the number of interconnecticns crossing the cut in each recursive step [5, 8]. This algorithm rins fast and is easy to implement. The objective of a rnin-cut based placement algorithm is to optimize the placement by putting communicating blocks close together. Therefore, the total wire length is the dominant component of the cost function in traditional placement algorithms. However, total wire length alone is not a good metric for architectures with limited routing resource such as FPGA and Complex Programmable Logic Device (CPLD) with partially connected interconnect matrix. Since the algorithm tries 1.o place connected blocks close together, it is likely to generate a placement with congested areas where a feasible routing is difficult to find, if not impossible at all. We propose an improved min-cut based placement algorithm which not only minimizes the total wire length, but 'This work was done while the first author was with Department of Computer Science, University of Illinois at UrbanaChampaign.

163

also spreads out the congestion uniformly across the channels, thus maximizing the possibility of finding a feasible routing for FPGA implementations. Further, most traditional placement algorithms use an approximation scheme to estimate the number of interconnections crossing a cut line. An example is to use the bounding box for a multiterminal net to estimate the probability that the route of the net will cross a cut-line. In contrast, our proposed algorithm minimizes the actual number of interconnections crossing a cut-line, as will be explained in Section 3.2. The proposed algorithm also obviates the need for a terminal propagation step [4] by using a novel procedure to implement the cut lines. Based on the results of our placement and routing experiments, we also propose a sequential order according to which the cut-lines are applied. Such a sequential order significantly reduces the possibility of net congestion near the center of the chip (as it often happens in the traditional top-down min-cut based placement). Finally, the proposed algorithm treats multi-terminal nets directly without dividing them into equivalent two-terminal nets.

2

FPGA Placement Problem

The two-dimensional FPGA layout model proposed in [3, 11, 14] contains an array of logic blocks as shown in Figure 1. Each logic block represented by a square implements logic functions. The terminals of a block are located on the boundaries of the block and are connected to wire segments called terminal segments. Terminal segments are connected to wire segments in the routing channel through switches at their intersections, which are shown as black circles in Figure 1. The switch matrix makes connections between wire segments in horizontal and vertical channels. In the switch matrix, each wire segment can be connected to a subset of the wire segments on the other sides of the matrix. Suppose there is a two-terminal net connecting two logic blocks, one at the lower left corner and the other at the upper right corner. A routing example of this two-terminal

net is shown in bold lines in Figure 1. In commercial FPGA products, routing resource is fixed and fairly limited. The placement problem is especially important in designs using such devices, because a placement is not routable if the number of nets in a channel exceeds the channel capacity. In order to develop an effective placement procedure a metric is needed to measure channel congestion. One way of measuring net congestion is the cut size, that is, the number of nets crossing a cutline in the chip. There are a horizontal cut-lines and b vertical cut-lines in an FPGA with (a + 1) x (b + 1) logic blocks, with each cut-line corresponding to a routing channel. We define the cut size of a cut-line to be the number of nets that have terminals on both sides of the cut-line. The cut size is a lower bound on the number of tracks needed for a complete routing solution. Thus, if the cut size of a

horizontal (vertical) cut-line is larger than the number of vertical (horizontal) tracks, then it is impossible to have a routable design. Moreover, a cut-line cutting through a connection-congested area usually has a large cut size. If the maximum cut size, the cut size that is the largest among all horizontal cut-lines and vertical cut-lines, decreases, the opportunity of the occurrence of connection-congested area decreases accordingly. Therefore, to avoid the occurrence of connection-congested area, we desire to minimize the maximum cut size. Note that, as was indicated in [10], the sum of the cut sizes over all a horizontal cut-lines and b vertical cut-lines in an (a + 1) x (b + 1) layout area gives the exact total wire length when the wire length of a multi-terminal net is estimated by half the perimeter of the bounding box. Thus, there is a close correlation between cut sizes and total wire lengths. In fact, the experimental results in Section 4 show that minimizing the maximum cut size produces a placement with a smaller total wire length in most cases, compared with the traditional min-cut based placement algorithm. Also note that the placement problem of minimizing the maximum cut size is NP-complete, since the linear arrangement problem [6] can be reduced to the placement problem when there is only one row or one column of logic blocks.

3

the two portions obtained in the first bi-partitioning step are bi-partitioned recursively and the placement obtained is that shown in Figure 2(a). The maximum cut size of this placement is eighteen. However, if we consider the distribution of the interconnections, a better placement with the maximum cut size being eleven can be obtained as shown in Figure 2(b). In this section, we propose a modified min-cut bi-partitioning algorithm that not only balances the size of the two portions, but also evenly distributes the connections among them. 3.1 Congestion-balanced Bi-partitioning In order to qualify the effect of congestion unbalance between the two portions of a given bi-partition, we define the following terms. Multiple terminal nets are represented by a hyper-graph model. For instance, consider a seventerminal net shown in Figure 3. The cut-line currently used is shown as the dotted line. Suppose the bi-partitioning result is such that there are three terminals in the left portion and four terminals in the right portion. This net will contribute a count of one in the cut set. Moreover, we know that two connecting paths are needed to connect those three terminals in the left portion and three connecting paths are needed in the right portion. In general, maf{k - 1, 0} connecting paths are needed to connect k terminals. We define the unbalancing number of a net to be the number of connecting paths needed to connect all the terminals in the left portion minus the number of connecting paths needed in the right portion. The unbalancing number of a bi-partition is defined to be the sum of the unbalancing numbers of all nets. The absolute value of the unbalancing number of a bi-partition counts the difference between the numbers of connecting paths needed in the left portion and the right portion. Therefore, it is a good measure of the unbalancing situation in a bi-partition. Given an initial bi-partition, we can compute its unbalancing number in O(ITI) time by examining all the nets, where T is the set of all terminals. Without loss of generality, we assume that there are more interconnecting paths in the left portion than in the right portion, that is, the unbalancing number of this bi-partition is positive. If node v is moved from the left portion to the right portion, then f(v, e), the amount by which the unbalancing number of the net e decreases, is equal to 1 if either the number of terminals belonging to net e in the left portion is equal to 1 (shown in Figure 4(a)) or there is no terminal of net e in the right portion (shown in Figure 4(b)); 2 otherwise (shown in Figure 5); and the gain in reducing the unbalancing number of the bi-partition is defined as

Congestion-Balanced Placement

Placement algorithms based on hierarchical min-cut partitioning [10, 12] have been studied and used extensively in both the academia and the industry. Given a layout region and a circuit represented by a graph (or hyper-graph), each node representing a logic block and each edge representing a net, the algorithm recursively bi-partitions both the circuit and the region until the graph is simple enough (for example, a graph with one node) to be placed in the region. The objective of each application of the bi-partitioning step is to minimize the cut size subject to the constraint that the sizes (the number of the nodes) of the two resultant portions are roughly equal. This approach has the advantages of producing placements of good quality, a short running time, and easy implementation. However, the bi-partitioning algorithms based on the Kernighan-Lin algorithm [5, 8] suffers from the lack of control on wire congestion because cut size iE the only metric in the cost function to be minimized. Consequently, it is possible to obtain a partition with a small cut size, with one portion being heavily connected and the other being very sparse. In other words, although these two portions have approximately the same number of nodes, the numbers of connections within them can differ significantly. Therefore, such a placement would likely contain unroutable channels. Clearly for FPGA applications, min-cut based placement algorithms must be modified to take into account not only the sizes of the two portions, the size of the network crossing the cut-line but also the distribution of interconnections within the two portions. Figure 2 shows an example to illustrate the need of such modification. A placement obtained by the traditional min-cut based placement algorithm is shown in Figure 2(a). There are sixteen nodes in the network to be placed in a 4 x 4 array, Note that each of the two groups of four nodes connected by six bold dotted edges represent a completely connected 4-node clique. That is, if we label these four nodes by a, b, c, and d, then there are eleven hyper-edges connecting them which are {a, bl, {b, c}, {c, d}, {a, d}, {a, c}, {b,d), {a,6,c}, {a,b,d}, {b,c,d}, {a,c,d}, {a,b,c,d}. The traditional min-cut based placement algorithm first divides the network into two portions of equal size, one placed in the left half and the other placed in the right half of the array. Since minimizing the cut size is the only objective in the bi-partitioning process, the first bi-partition obtained is shown in Figure 2(a), where the cut size is one. Then,

F(v) =

f(v,e). E V

t,

(1)

se

If node v is moved from one portion to the other portion, it takes only O(JN(v)J) time to update the values of the gain function that are changed by examining N(v), the set of all neighbors of v. When a node v in one portion is swapped with another node u in the other portion, if there is no edge connecting these two nodes, the gain in reducing the unbalancing number of the bi-partition is the sum of F(v) and F(u). If there are edges connecting both nodes, for each of such edges, e, we subtract the amount f(u,e) + f(v,e) from the sum of F(v) and F(u), since the swapping, in fact, contributes no reduction in the unbalancing number of the net e. The following cost function is used to incorporate the effect of congestion distribution in a given partition

164

CUT.SIZE + WEIGHTXUNBALANCING NUMBER

where WEIGHT is a constant. If WEIGHT is set to zero then the algorithm is the same as the conventional min-cut bi-partitioning algorithm. By setting the value of WEIGHT appropriately, we can control the importance of balancing the congestion. For the example in Figure 2, if WEIGHT is set to be greater than -, then the better placement in (b) is obtained. Note that a linear combination of cut size and unbalancing number is chosen to allow incremental computation of the cost function as new bi-partitioning solutions are constructed. It should be noted that a new definition of the unbalancing number of a bi-partition is needed if the ratio of the sizes of the two resultant portions is required to be, r, where r is not equal to one. Suppose we require that the left portion have x nodes and the right portion have y nodes such that X = r. Given a bi-partition and a net e, if the number of connecting paths needed to connect all the terminals of net e in the left (right) portion is a (b), then the normalized unbalancing number of the net e is defined to be

4

ax - bbx 4Y That is, we normalize the number of connecting paths needed to connect all the terminals in the left (right) portion by multiplying the ratio of half of the number of nodes to the number of nodes in the left (right) portion. The unbalancing number of the net is defined to be the resultant value for the left portion minus the resultant value for the right portion.

3.2 Slicing Line In conventional min-cut based placement, the layout region is bi-partitioned in a top-down fashion in accordance with a recursive application of the min-cut bi-partitioning. A frequently used strategy is to bi-partition the region into two halves with equal size in alternating directions as shown in Figure 6 [10], where the cut-lines depict the sequence in which they are applied. In this figure, dashed cut-lines are vertical cut-lines and solid cut-lines are horizontal cutlines. Such a hierarchical bi-partitioning process suffers from the problem of the external pin connections [4] as will be explained next. Suppose the layout region is first partitioned vertically into two equal parts such that each part will accommodate one portion of the bi-partitioned circuit. Then, for these two regions, the bi-partitioning process is repeated, except that horizontal cut-lines are now applied. Suppose that bi-partitioning is first carried out for the right region. The bi-partitioning result for the right region should be taken into account during the bi-partitioning process for the left region. The reason is that the signals entering the logic blocks in the left regions from the logic blocks in the right region might effect where each logic block in the left region should be placed just as much as the internal connections among the logic blocks in the left region. In [4], a technique called terminal propagationwas proposed. In this approach, all nodes to the right of the vertical cutline are projected horizontally on the cut-line, as shown in Figure 7. We then process the left region, regarding these projected nodes as fixed nodes'. This terminal propagation technique has the advantage of taking into account the bi-partitioning result in the right region. However, it suffers from two disadvantages. First, the left and right regions are processed in sequence. There is no clear reason as to which region should be processed first. Secondly, the net in the cut set computed using the terminal propagation technique does not necessarily cross the cut-line, as will be explained below. Consider a two-terminal net with 'Fixed nodes are those that are not allowed to be moved in the bi-partitioning process.

one terminal connected to a logic block placed in the lower right region shown in Figure 8(a). Assume that the other terminal is connected to a logic block placed in the upper left region. After the process of the right region and the terminal projection, this net contributes a count of one in the cut size for the left horizontal cut-line. However, there are two possible routes for this net and it does not cross the cut-line if the routing in Figure 8(c) is chosen. Therefore, counting this net in the cut set for the left horizontal cut-line is not accurate. One common way of solving this problem is to assume even probabilities for all cut-lines that overlap with the bounding box of the net [7]. That is, in our example of Figure 8, the probability for the net to cross each horizontal cut-line is one half. Therefore, one half of a net is contributed to the cut size of each cut-line. We solve this problem by considering only the cut-lines that span the width or the height of the layout region. To distinguish the cut-lines that cut through the entire layout area from the cut-lines used in the traditional min-cut placement algorithm, they are referred to as slicinglines. After the first vertical slicing line is applied, we apply one horizontal slicing line, instead of two half horizontal cut-lines in sequence. During the bi-partitioning process, we consider movement of nodes in both the left and the right regions at the same time. We honor the bi-partitioning result for the first vertical slicing line by prohibiting any movement of nodes across the vertical slicing line. It is not hard to see that the cut set obtained in this way constitutes exactly those nets that have terminals in both sides of the slicing line. 3.3 Slicing sequence Based on the observation mentioned previously, slicing lines which cut through the entire layout region are used in our algorithm. There are a horizontal slicing lines and b vertical slicing lines in an FPGA with (a + 1) x (b + 1) logic blocks. The sequence in which slicing lines are applied plays an important role. The conventional hierarchical min-cut placement always chooses the cut-line at the center of the region and such a choice is carried out recursively. If we order the slicing lines to be applied in this sequence, then Figure 9 (a)-(d) depict the sequence of slicing lines to be applied, where slicing lines currently applied are shown as dashed lines and slicing lines applied earlier are shown as solid lines. "Assume that the current slicing line I shown as the dashed line is immediately next to the center slicing line in Figure 10, where the remaining solid lines are those slicing lines that are applied earlier. Slicing line I will cut four regions and their corresponding sub-networks into halves. Note that in each move of this min-cut bi-partitioning, we can swap a pair of nodes such that one is in A and the other is in E, one is in B and the other is in F, one is in C and the other is in G, or one is in D and the other is in H. However, since we honor the bi-partitioning results for the slicing lines applied earlier, any swapping of nodes that crosses the slicing line applied earlier is not allowed. We know that the number of nodes that reside in a region is proportional to the area of the region. Since the slicing line I is immediately next to the center slicing line, the four regions that I cutting through are fairly small. Therefore, the numbers of nodes that are placed in regions A-H are small. Consequently, The number of possible pairs that we can choose from for a move in this bi-partitioning process is, thus, limited. This usually results in a relatively large cut-size for the slicing lines close to the center due to a small number of possible moves. Especially, for the two horizontal and vertical slicing lines immediately next to the center, a larger cut size is usually observed. Based on this observation, we propose another sequence of slicing lines in which they are applied to reduce the chance of congestion near the center. The horizontal slicing lines and vertical slicing lines are applied alternatively

165

TABLE 1 O

t

w

is

in the array, and thus, 13 vertical and 15 horizontal slicing lines. For the smallest circuit, f5lm, there are 8x8 logic blocks in the array, and thus, 9 vertical and 9 horizontal slicing lines. Figure 13 (a) and (b) show the distribution of the cut sizes of the slicing lines in alu2. Figure 13 (c) and (d) show the distribution of the cut sizes of the slicing lines in f5lm. The distribution of the cut sizes in the placement obtained by our algorithm is shown as a solid curve and the distribution of the cut sizes in the placement obtained by the traditional min-cut algorithm is shown as a dashed curve. In addition to a reduction in the maximum cut size, we also observe that the cut sizes in our placement are distributed more uniformly than those in the placement obtained by the traditional min-cut algorithm. Also, the large cut sizes next to the central horizontal slicing lines illustrate the need of a new slicing sequence in the traditional min-cut placement algorithm. The slicing sequence adopted in our algorithm solves this problem and the values of cut size near the center of the chip are not particularly large. We used the Xilinx Automated Placement and Routing (APR) program for XC3000 series to obtain the routing results. In each routing experiment, we count the number of wire segments passing through each channel and refer it as the wire density of the channel. According to Figure 13, there is a almost-linear relationship between the cut size and the wire density. In fact, the ratio between wire density and cut size is approximately uniform in our experiments. Table 4 lists the average ratios of wire density to cut size over all slicing lines in each circuit and the values of the corresponding standard deviation. The standard deviation is at most between 10%-.20%. Consequently, we can conclude that cut size is a good measure of wire congestion. The curves for the wire density in Figure 13 also show that the placements obtained by the traditional min-cut algorithm have higher wire congestion than those obtained by our algorithm, which is consistent with the fact that there are 19 unrouted nets in the placement of alu2 obtained by the traditional min-cut algorithm, whereas there are only 3 unrouted nets in the placement obtained by our algorithm.

w

OUNIMARY OF THE EIGHT MUCNU CIRCUITS

Circuit 1 Chip f5lm miseX2

comp 9sym

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8x8 8x8 lOxlO 10x10 lOxlO 12x12 12x12 16x14

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I Nets

58(42) 101(40) 101(66) 105(95) 139(66) 160(116) 209(123) 229(213)

50 83 98 104 107 150 183 223

Terminals 224 309 340 518 427 621 677 833

as before. However, for the slicing lines of the same orientation, those slicing lines that are closer to the center are applied earlier as shown in Figure 11, where horizontal slicing lines are not shown for clarity. We compare the vertical slicing lines, denoted by 1, which are immediately next to the center in Figure 12 (a) and (b). Since the size of the area of a region is proportional to the number of nodes that reside in the region, we can compute the ratio of the number of possible pairs that we can choose from for a move in (a) to that in (b). By computing the areas of the regions, we can obtain the ratio as 2.(9 x 3 + 3 x 1): 4.(2 x 2) = 60: 16. There is a substantially larger number of possible pairs of nodes that we can choose from for a move in (a) than in (b). Therefore, it is expected that the cut size for a slicing line close to the center is smaller, if the sequence in (a) is adopted, instead of that in (b).

4

Experimental Results

Our congestion-balanced min-cut placement algorithm was implemented in the C language and run on a SPARC10 Sun workstation. We used eight MCNC circuits to test the efficiency of our algorithm and compare the results with that obtained by the traditional min-cut algorithm when congestion balance and the other features proposed in this paper were not taken into consideration. We used Xilinx 3000 series chips as the target FPGAs. The circuits were first synthesized and transformed into the XNF (Xilinx Netlist Format) format. Then, the circuits were mapped into the 3000-series logic blocks and the results were used as inputs to the placement program. The circuits are listed in the order of increasing number of logic blocks in Table 4. The first column of Table 4 shows the dimensions of the FPGA chip on which a circuit is implemented. The second, third, and fourth column shows the number of blocks, nets, and terminals in each circuit, respectively. Note that the number of logic blocks shown in the second column is the total member of I/O blocks and logic blocks. The number of logic blocks is shown in parentheses. The results are summarized in Table 4. We observe that our algorithm yields a reduction in the maximum cut-size by up to 23%, when compared with the traditional min-cut placement algorithm. We also computed the sum of the cut sizes over all slicing lines. As was mentioned earlier, the sum gives the total wire length according to the estimate of wire length by half of the perimeter of the bounding box. In six of the eight circuits, we obtained a placement with a smaller sum of the cut sizes. For the other two circuits, the sum of the cut sizes in the placement we obtained is roughly the same as that in the placement obtained by the traditional mincut algorithm. Therefore, we can conclude that reduction in the maximum cut size in our algorithm also gives the benefit of reducing the total wire length. The running time for our algorithm is comparable with that for the traditional min-cut placement algorithm. For the largest circuit, alu2, there are 14 x 16 logic blocks

5

Conclusions

In this paper, we propose an important criterion in the FPGA placement problem, balancing the congestion, which used to be overlooked, if not neglected, in the past. We propose an improved min-cut based placement algorithm which spreads out the congestion, while minimizing the total wire length. Therefore, the placement obtained maximizes the possibility of finding a complete routing in FPGA, if one exists. The algorithm balances the numbers of interconnections in the two portions during each application of the min-cut bi-partitioning algorithm. In the meantime, the algorithm minimizes the actual number of interconnections crossing each vertical cut line and each horizontal cut line, instead of the probabilistically estimated number of interconnections. We introduce the concept of slicing lines which span the entire chip and are useful for the bi-partitioning process where a larger solution space can be examined, compared with the terminal propagation technique. The sequence of the cut lines is determined according to the distance from each cut line to the center of the chip. The cut line closer to the center is applied earlier. This avoids the possibility of the occurrence of a cut line with a large cut size close to the center of the layout area (which happens in the traditional top-down min-cut based placement). The experimental results show a reduction of up to 23% in the maximum cut-size and the wire congestion, compared with the traditional min-cut placement algorithm. In the largest circuit, 19 unrouted nets in the traditional min-cut placement are eliminated with only 3 unrouted nets left in our placement which can be manually completed easily.

166

TABLE

Max. Cut-size Circuit . Name .t Our Aig. Mn-cut =Reduc. 19 24

f5lm-

9sym c499 term c880

alu2

38 48

24 31 32 27 43 47 55

48

59

31 23

= 40 -

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2

SUMMARY OF THE PLACEMENT

-_

Our Alg. I Min-cut

20.8% 22.6% 3.1% 14.8% 7.0% 19.1% 12.7% 18.6%

198 284 377 370 540 692 803 1167

234 313 372 352 543 730 860 1176

CPU Time (seconds) Our Alg. | Mm-cut 0.73 1.72 1.48 18.6 2.42 14.2 14.6 213.3

0.76 2.63 1.25 16.4 2.38 24.2 12.5 311.6

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[Circuit | ______

f5lm misex2

comp 9sym c4 99 terml

c880 alu2

References

Our Algorithm Avg. Rat~io Std. Dev. 2.17 2.58 1.81 2.88 2.62 2.17 1.95

2.46

0.30 0.45 0.28 0.29 0.30 0.36 0.25 0.22

[1] M. A. Breuer. Min-cut placement. Journal of Design Automation and Fault Tolerant Computing, 1(4):343362, October 1977. [2] S. Brown, R. Francis, J. Rose, and Z. Vranesic. FieldProgrammable Gate Arrays. Kluwer Academic Publishers, 1992. [3] S. Brown, J. Rose, and Z. Vranesic. A detailed router for field-programmable galte arrays. IEEE Transactions on Computer-Aided Design, 11(5):620-628, May 1992. [4] A. E. Dunlop and B. W. Kernighan. A procedure for placement of standard-cell 'VLSI circuits. IEEE Transactions on Computer-Aided Design, 4(1):92-98, January 1985. [5] C.. M. Fiduccia and R. M. Mattheyses. A linear-time heuristic for improving network partitions. In Design Automation Conference, pages 175-181, 1982. [6] M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NVPCompleteness. W. H. Freeman, 1979. [7] S. Goto and T. Matsuda. Partitioning, assignment and placement. In T. Ohtsuki, editor, Layout Design and Verification, chapter 2, pages 55-97. Elsevier Science Publishers B. V., North-Holland, 1986. [8] B. W. Kernighan and S. Lin.. An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, 49(2):291-307, February 1970. [9] U., Lauther. A min-cut placement algorithm for general cell assemblies based on a graph representation. Design Automation Conference, pages 1-10, June 19,79. [10] T. Lengauer. Combinatorialalgorithms for integrated circuit layout. John Wiley & Sons, 1990.

Traditional Min-cut Avg. Ratio [Std. Dev. 2.00 2.71 1.80 2.81 2.25 2.31 1.84 2.67

0.20 0.51 0.39 0.40 0.27 0.32 0.18 0.56

[11] M. Palczewski. Plane parallel A* maze router and its application to FPGAs. In Design Automation Conference, pages 691-697, 1992. [12] B. Preas and P. G. Karger. Placement, assignment and floorplanning. In B. Preas and M. Lorenzetti, editors, Physical Design Automation of VLSI Systems, chapter 4. The Benjamin/Cummings Publishing Co., 1988. [13] N. Togawa, M. Sato, and T. Ohtsuki. A simultaneous placement and global routing algorithm for symmetric FPGAs. In second International Workshop on FPGA, Berkeley, CA, 1994. [14] Xilinx Inc. XC4000 Logic Cell Array Family, Technical Data, 1990. w;-

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Fanout Problems in FPGA Kum-Han Tsait, Malgorzata Marek-Sadowskat, Sinan Kaptanoglu4 t Department of Electrical Engineering and Computer Sciences University of California, Santa Barbara, CA 93106, USA

t

Actel Corporation, Sunnyvale, CA 94086, USA

Abstract

ited. Ideally, the number of free logic blocks (i.e. the difference of the number of total logic blocks on the chip and the number of mapped blocks occupied by the target circuit) is the maximum number of buffers which can be used. However, increasing the percentage of mapped blocks may cause the circuit routability degradation and/or increase the routing delay. So some times not all free logic blocks can be used.

This paper proposes a heuristic algorithm to improve the performance of FPGA circuit by inserting buffers and duplicating nodes. Since FPGA chips come in discrete sizes, almost all of the circuits are mapped with some logic blocks unused. By configuring these free logic blocks into buffers and properly inserting them to the mapped circuit, the maximum delay of the circuit could be reduced significantly without any extra hardware cost. We show the experimental results and compare the improvement in both logic level estimation and in the physical level.

1. Introduction Buffer insertion is one of well-known methods to minimize the network delay. The basic idea is to spread the fanout load and balance the fanout tree by inserting the proper size buffers at the right positions such that the maximum delay is minimized. Fanout tree buffering problem has been studied by several authors. CL. Berman, et.al, [1] first showed that to determine whether there is a fanout circuit meeting the given timing and area constrains is an NP-complete problem in the unit delay fanout model. They also proposed a heuristic algorithm called Two-Group Algorithm which runs in quadratic time. Touati [6] introduced dynamic programming approach to construct a balanced criticality fanout buffered tree. Singh eLal in [5] and Lin at al. in [4] proposed algorithms inserting single buffer per iteration. Recently, Carragher et. al [2], combined tree construction and single buffer operation to get more improvement. All these methods can be categorized into pre-layout buffer insertion. The other methods involve the post-layout approaches (e.g. [3]), which insert buffers based on the physical level information. They allow to calculate accurately the circuit element delays and the wiring delays.

If the post-layout strategy is used, not only the number, but also the positions of the free logic blocks are fixed and additionally the routing resources are less flexible. In this case, it's very unlikely to find a free buffer as well as required routing resources (wires and switches) to insert the buffer appropriately. On the other hand, the gap between technology independent (logic synthesis) and technology dependent processes (place and route) make pre-layout insertion inaccurate. In other words, because of the unpredictable wiring delay, the buffers inserted before the layout is completed may not be after all beneficial for the circuit's performance. A possible solution to overcome these difficulties is to have a two phase process. The first phase performs the prelayout insertion according to a unit delay fanout model. This delay model is based on the observation that routing delay is roughly proportional to the number of fanouts. After the first phase insertion, the modified circuit is placed and routed. The second phase modifies the first phase based on the timing analysis of the routed circuit. Since the timing estimation before the place and route may not reflect the real delay, the buffers inserted previously may not improve the performance as much as we have predicted. They may even degrade the performance. The second phase examines the inserted buffers and may either relocate or delete them. These incremental adjustments need to take the current available routing resources into account and may involve partial replacement and rerouting process.

Traditionally, the free logic blocks in FPGA are of no use after the circuit has been placed If we configure these free logic blocks as buffers and use the buffer insertion technique to speed up the network, we can improve the performance at no cost to the user. Two properties make the buffer insertion in FPGA different from the previous works. First, there is only one buffer size available what limits the possible inserting positions to reduce the delay, and second, the number of buffers is lim-

169

The other possibility to utilize the free logic blocks to improve the performance is node duplication which splits the fanouts of the duplicated node into two groups, one driven by the original node and the other driven by the new(duplicated) node. In the standard cell design style, buffer insertion is typically more effective than the node duplication since buffers are usually better designed for driving signals. This condition is no more true for the FPGA since buffers are also implemented by the logic blocks. By adding the node dupli-

cation to the fanout problem, we have more chance to find the beuer performance of the target circuit. This paper proposes a buffer insertion/node duplication technique in FPGA which involves the first phase (prelayout) process. We also show the delay after routing to see how close the delay prediction of the pre-layout level to the real physical delay.

delay to primary output of g, which is the local goal we like to minimize. Given a net net(g), with source g and sinks h1, h2 ,...hk, mpo(g) can be calculated as follows. mpo(g) = max {mpo(hl), mpo(h 2 ),..., mpo(hk)) + A + B(k-1) + D If we assign a weight to each sink W(hj) as follows: W(h^) = mpo(hi) + delay from input pin of g to input pin of hi

2. Problem Formulation We assume the circuit is combinational and can be represent as a DAG (directed acyclic graph). Each vertex in the graph represents a gate in the circuit. The gates in the circuit are assumed to be single output. There is a directed arc e from g to h if gate g directly fans out to gate h. In this case g is the source vertex of arc e and h is the sink vertex of e. The directed arcs which share the same resource vertex g form a multi-net net(g). The delay of the circuit depends on its longest delay path(s). The delay of a path is calculated by summing up the delays of vertices and arcs. Each vertex has a constant intrisic delay D. The directed arcs in the same multi pin net net(g) have the same delay which is a linear function of the number of fanouts of g and can be expressed by the following equation:

then mpo(g) = max {W(hl), W(h 2 ),... W(hk,)1. We sort the sinks by the non-decreasing weight order and then mpo(g) is W(hl). Now, suppose a vertex is inserted to net(g) at the yth fanout position such that the sinks h). hy+ ,... hk are buffered (see Fig 1). The weight of a sink hi is changed to W(hi)' as follows: W(hi)' = W(hi) - B(k-y) for 0 < i < y and W(hi)' = W(hi) + D + A for y 2 4. mark all edges in the segment 5. if (two sets are created by removing the segment) 6. find a shortest path between the two sets 7. if (the new weight is lower) replace the old segment with the new path 8. I 9. * Example The paths graph shown in Figure 3 is sent to Improve-route. There are a few segments in that graph. Only the segment between the bottom pin (A) and the right pin (B) can be improved. That segment is removed and a shorter path between the two separated sets is found. Hence the original segment is replaced by the new path. The improved paths graph is shown in Figure 4.

(a)

(a)

(b)

Figure 4. Improved paths graph. 4.d Remove-cycles To remove the cycles in the paths graph, all segments in the paths graph are generated. The segments are sorted according to the weight of the segment. Starting from the largest-weight segment, the segment is removed. If this action causes the graph to be divided into two sets, restore the segment. Otherwise, remove the segment from the paths graph permanently. This is done sequentially for all segments. The procedure of Remove-cycles is as follows: (b) Figure 3. Paths graph of a net and its top view. 4.c Improve-route To improve the routing, all the segments in the paths graph are examined. First, all the edges (in the paths graph) are put in an array. One starting edge is chosen from the beginning of the array. This edge, i.e. its two endpoints, is extended in both directions to form a segment. The end points of such a segment are either a required node (pin) in the original routing graph or a node with degree more than two. For example, in Figure 3(a), the edge (el) is selected as a starting edge. The edge is extended from both end points and forms a segment from !dto a. We mark all edges in the segment. so that the edges will not be used as starting edges later on. The segment is removed from the paths graph. If the paths graph is now divided into two disconnected sets, find a shortest path between the two sets. If this new path has a lower weight than the original segment, the new path is used instead of the original segment. The process continues until all edges are marked. The procedure of Improve-route is as follows:

Remove-cycles(graph) I. sort the segments of the paths graph according to their weights 2. the sorted segments are put into a queue with the largestweight segment in the front 3. for (all the segments in the sorted queue) remove the segment 4. if (the graph is not divided into two sets) 5. if (two other segments can be merged due to the 6. removal of the segment) ( merge the two segments 7. adjust the queue 8. 9. continue 10. 11. restore the segment 12. 13.

* Example Figure 5 shows that the cycle in the paths graph has been removed and an optimal route tree is obtained.

stage. 1-.

3 f

0

s:~77777:7'1-

(a)

A

I

-

I

-

2

i

C

4

(b)

Figure 5. Final route for a net. Figure 6 is used to show how lines 6-9 of Remove-cycles work. The largest-weight segment may be B-C-F, so it is removed first. Originally, there are two segments A-B and B-E. Because of the removal of B-C-F, A-B and B-E are connected to form a new segment.

A

B

c

D

E

F

I

l

_1

6 5 Figure 8. Example of the 3-pin net after improvement. r

Figure 9 shows another problem we encountered. Figure 9(a) is the paths graph for a 4-pin net. There are two equal-weight paths between each pair of pins. This is not unusual for a multi-layer layout. Segments 3-4-D and 7-8-D are the largest-weight segments. Segments A-1-2 and A-5-6 are the second largest-weight segments. During the cycle-removing stage, it is possible that segment 3-4-D and A-5-6 are removed. The tree, after the cycles have been removed, is shown in Figure 9(b). Obviously, this is not the Steiner minimum tree. With the second execution of Improve-route, the Steiner minimum tree is found. The result is shown in Figure 9(c).

Figure 6. Example of a paths graph.

I

For this example, the second execution of Improve-route does nothing. For some other cases, the optimal tree might not be obtained after Remove-cycles has been executed. A second execution of Improve route is needed for those cases. This will be shown in next sub-section.

1 6

-7'

2

3

B

C

4 8(a)

4. e Discussion Figure 7 shows the importance of keeping multiple paths in the paths graph and the first improvement stage. 2

1 A

C

5

; L

rn I

I

r ~ ~

4M D7

.

6'

7

8 (b)

1C

2

3

B7

C7

6

7

4

E

4: 8' (c)

Figure 9. An example of the need for the second execution of

6 Figure 7. Example of a 3-pin net before improvement.

Improve-route.

It is an example of a 3-pin net. Nodes A, B, and C are the required nodes. The path between B and C is formed first, because it is shorter than the path between A and B. Then, paths between A and B are found. The paths graph is shown in the bold lines. If the paths graph directly goes to the cycle-removing stage, segment A4-B may be removed. Without node 4, it is not possible to find the Steiner minimum tree. Figure 8 shows the improved paths graph. The remove cycle procedure will remove segment A-S-B now. The minimum Steiner tree was found. If multiple paths were not kept, the Steiner minimum tree may not be found. For example, the tree ,4-5-B-6-C may be found as the route. This tree cannot be improved by Improve-route. The example shows the advantage of retaining; multiple paths and why we need the first improvement

The key to our algorithm is that we incorporate more Steiner points for the later improvement stages to work on. But if there are too many equivalent-weight paths, it could cause efficiency problems and make the cycle-removing part less effective. Two methods are used to prevent the algorithm from incorporating too many paths. One is that we try to keep the outside paths only, i.e. the paths which are enclosed by other paths are discarded, because the inside paths don't provide useful Steiner points. The other is that we directly limit the number of paths which can be incorporated. In current implementation, the limit is 20. On the other hand, for some graphs, we found that there hardly exists any equivalent paths. We therefore retain and treat the paths which are slightly higher in weight (up to 1% higher than the minimum

222

weight path) as equivalent-weight paths.

Minimum wire length does not mean minimum chip area. For macro-cell designs, the congestion can be solved by pushing the cells away so the regions can accommodate more tracks. The chip area is usually the main concern. Our global router can also be used to achieve the goal by using the rip-up and re-route method. First, we use a directed graph to compute the size of a chip. For example, Figure II shows the graph which we use to compute the height of the chip. We place nodes on the top and bottom sides of the cells. So a rectangular cell has one node on the top boundary and one node on the bottom boundary. For non-rectangular rectilinear cells, there may be more than one top or bottom boundary. We place one node on each horizontal boundary segment.

4f Time complexity We now examine the time complexity. The routing graph is G=(VE,c). Because there are at most six edges connected to a vertex, the relation, IEl < 61VI holds. We route a net ni with p pins. For Remove cycles, the sorting has a time complexity of O( ISI log ISI ), where ISI is the number of the segments. In the loop, the worst case occurs when we must update the queue every time, so the time complexity for the loop is O( IS12 ). The complexity of Remove- cycles is 0( ISI2 ). The end point of a segment has a degree greater than 2 if the end point is not a terminal (pin). A theorem from [6] says that for a Steiner minimum tree the number of such vertices is less than two times the number of terminals (pins). The number of segments is proportional to the number of vertices. So ISI is proportional to p. To find the shortest paths between the sets, we use an algorithm similar to Dijkstra's algorithm. The difference is that we have multiple sources instead of one. We start from multiple sources and update the weight for the vertices and put the vertices into a priority queue. Because the routing graph is sparse, according to [5], the time complexity is O( (IVI+ 1Et) log IVI ). For our case, it can be simplified to O( IVt log IVt). So the Improve -routesubroutine has the time complexity of O( ISII VI log IVI ). For Generate-route,the main loop has a time complexity of O(plV1 log lVt ). So for the subroutine, 2the dominant parts are O( plyV log 1V)+O( ISItVt log IV )+O SI ) for net ni. Therefore, the time complexity of our program is O( IPIIVI log IVI ), where IPFis the total number of pins. 5 Solving Congestion Problems and Area Minimization After the global routing is done for all nets, the following information is obtained: the number of tracks used for each layer in each region, the number of via used, and the wire length of each net. The path for each net consists of not only the topological information but also the layer and via information. The information can facilitate the detail routing process. If a certain region is congested due to the capacity of the region, a rip-up and re-route method is used to eliminate all the overcongested regions. Starting from the most congested region, it seeks to re-route all the nets using that region while avoiding the creation of additional congestion problems. Then all the new routes are sorted according to the increase of the wire length (or weight). The program chooses the new routes needed to relieve the congestion problems by selecting those new routes which minimize the increase in total wire length (or weight). Then it moves on to the next most congested region. It continues until all the overcongested regions have been processed.

Figure 11. Height graph for the example of Fig. 1. For example, the L-shaped cell in Figure 11 has two nodes on the top side. In addition, we have one source node on the top and one sink node at the bottom of the chip. Our height graph is directed from the source node to the sink node. Since our routing model divides the chip area into rectangular regions, we have columns, which may consist of a series of regions, between the cells or between the cells and the source/sink node. In Figure 10, the columns are shown by the directed arcs. To simplify the graph, only one directed edge is needed to represent the columns between any pair of nodes. The weight of the edge is determined by the highest column of the columns corresponding to the edge. The height of a column is decided by the horizontal layer which requires the most space. Figure 11 shows the final height graph. For illustration purposes, we placed the edges into the highest columns between the nodes, if there is more than one column. But they actually represent a set of columns. Inside the cells, each node on the top has an edge to each node at the bottom. The weight of such an edge is the distance between the boundaries. For a rectangular cell, it is the height of the cell. The longest path from source to sink determines the height of the chip. A similar directed graph is also created to compute the width. If there are layers which can go over the top the cells, a congestion-removal stage is needed before we can correctly estimate the chip size. All the congestion problems on the top of the cells must be removed first, because only the routing regions between the cells can be expanded. The size of a cell, however, is fixed. If a layer gets overcongested on regions over the cells, some tracks in the regions have to be moved to the non-cell regions. To minimize the chip area, we try to reduce the height and the width of the chip sequentially. We re-route those nets which use the critical regions. The critical regions are defined as the regions corresponding to the edges of the longest paths of the height and width graph. The edges inside cells are not included. To reduce the height and width of the chip, we re-route the nets in the critical regions to see if there is a new route which can reduce the size of the critical regions. In particular, we dynamically set the

Figure 10. Column graph for the height of the example of Fig. l.

223

weights of graph edges in critical regions and re-execute Generate-route.An edge's weight is set to infinity if the use of the edge does not reduce the size of the critical region. If such a new route exists, the new chip size is calculated according to the route change. If the chip size is reduced, the new route is accepted, otherwise it is rejected. The algorithm is as follows: 1. for (all nets in the critical regions) { 2. try to find a new route which reduces the size of critical regions /* Set the weights of the edges in critical regions to infinity if the use of those edges don't reduce the size of critical regions */ 3. if (no such a new route exists) continue 4. if (the new route does not increase the weight and reduces the chip size) accept the new route and continue 5. if (the new route increases the weight) put the new route in a priority queue according to the increase of the weight 6. } 7. for (each new route in the priority queue in order) 8. if (the new route reduces the chip size) accept the new route The re-calculation of the chip size is necessary, because a new route which reduces the size of critical regions may not reduce the chip size. New critical regions can be generated when a new route reduces the original critical regions. To speed up the calculation of the chip size, an M-longest-path method is used to calculate the new size. That means we store the longest M paths for both height and width. When a new route is found, we calculate only the new length of those paths instead of searching for the new longest paths in the graphs. The new longest path of the M paths determines the new chip size. We modified the Dreyfus method[18] for M shortest paths to find M longest paths. In current implementation, instead of using a fixed number, we store all the paths which have length greater than 90% of the length of the longest path. The algorithm shown above is one iteration of the re-routing process. It repeats until no further size reduction is possible, i.e. no new route is found or accepted during an iteration. And it is also necessary to obtain the new set of M longest paths and the new set of critical regions before each iteration.

usage was reduced by a factor of nearly nine. number of

We compared our Steiner tree algorithm with two other graphbased algorithms capable of handling irregular graphs. One is the MST on the distance network Steiner tree heuristic. This method has been used in several other routers[2][3]. The second algorithm we compared against is the M-route method introduced in Mickey[2] is an improvement over the first algorithm. It has been known as a fast and very good method for the routing problem. It can usually find the Steiner minimum tree for a net. In fact, it is the best performing public-domain graph-based global router previously known. The drawback is that it requires too much memory and is therefore impractical for large circuits. We tested the programs on some industrial circuits. Those circuits are shown in Table 1. The placements were generated by TimberWolfMC v.3.1. We ran the programs on the same two-layer global routing graph. The wire length results for the three algorithms are shown in Table 2. Our Steiner tree algorithm outperforms the other two algorithms. Table 3 shows the memory usage and run time of Mickey and our Steiner tree program. They both were run on a DEC 3000 APX Model 400 workstation. The results in Table 3 show our algorithm uses much less memory, while having a comparable (or slightly better) run time. For the largest circuit (intel), the memory

224

nets n

p P

nodes of graph

edges of graph

hp

11

83

309

26

39

ami33

33

83

376

64

101

qpdm-b

17

121

645

37

58

xerox

10

203

696

21

30

amd ami49

17 49

288 408

837 953

39

57

108 20 586 1,576 64 62 570 4,309 161 Table 1. Circuit information.

172

4832 intel

MST on the distance network hp

Mickey M-route

98 243

NewNe Steiner aig. vs. teag.MST on tedn

Nw Mickey

176,808

171,430

170,063

-3.81%

56,770

55,865

55,815

-1.68%

-

0.09%

qpdm-b

633,540

626,907

625,930

-1.2%

-

0.16%

xerox

568,480

561,935

561,935

-1.15%

0

amd

261,478

259,856

259,843

-0.63%

-0.01%

ami33

- 0.8%

arni49

371,362

361,378

360,592

-2.9%

4832

1,934,200

1,894,400

1,891,390

-2.21%

intel

6,087,362

5,942,640

5,925,695

-2.66%

-0.29%

-2.03%

-0.22%

average

0.22% -

0.16%

Table 2: Wire length comparison.

Mickey memory (bytes) hp

6 Results

cells

New Steiner tree algorithm time (se

memory (bytes)

time (se

memory reduction factor

666K

3.1

355K

1.7

1.88

ami33

1,855K

2.3

438K

6.3

4.24

qpdm-b

2,124K

2.2

784K

5.9

2.71

xerox

1,269K

4.2

735K

2.6

1.73

amd

4,594K

25.0

1,272K

4.7

3.61

ami49

6,228K

20.0

1,316K

5.4

4.78

9,032K

16.7

2,142K

8.9

4.22

4832 intel

50,642K 224.7 5,707K 203.9 Table 3: Memory and run time comparison.

8.88

The two percent improvement over the very simple minded MST heuristic may, at first glance, appear small. However two items are noteworthy: (1) the MST heuristic always finds the minimum length routes for two-pin nets and usually dues for three-pin nets. The majority of the nets in these benchmarks (or any real circuit) have three or fewer pins. (2) Nets with many pins have minimum enclosing rectangles (bounding boxes) which are huge. Although a route generated by the MST heuristic for such a net may look very poor to an experienced layout designer, the percentage dif-

ference between the length of a poor route and the optimal route may be small. However, for performance and density reasons, it is imperative to make each net as short as possible. To demonstrate the global router's ability to minimize the area of a macro cell layout, as well as its ability to handle multi-layer technologies, we considered the same benchmark circuits for three layers of metal. The first and second layer were not available over the cells. Only the third layer could be used everywhere. The first and third layer were for horizontal tracks, and the second layer was for vertical tracks. Table 4 shows the area reduction results. The column initial is the initial area when the shortest route is used for every net. The column final is the final area after the area reduction process. Some circuits exhibit large reductions, while a couple do not. It depends on the circuits. If the chip area of a circuit is dominated by actual cell area, the re-routing process can do little to reduce the chip size. On the other hand, if the chip area after routing has significant routing regions between the cells, the reduction percentage can be huge, as for the circuit amd. Note that the area reduction is quite significant for most of the circuits.

Mickey for the intel circuit.) Since VLSI circuits contain more and more transistors, this is an important factor in designing a feasible global router for the circuits of today and the future.

[1] [2] [3] [4] [5] [6]

initial

final

hp

3618 X 3132

ami33 qpdm b

reduction

:3608 X 3082

1.9%

1850X 1890

1840X 1850

2.6%

3943 X 4017

3873 X 3857

5.7%

xerox

7060 X 7700

6990 X 7290

6.3%

amd

2007X 1588

1930X 1343

18.7%

ami49

7232 X 6830

'7142 X 6810

1.5%

15110X 11350 14660X 11060 11370X 10940 11210X 10910 Table 4: Area reduction results

5.5% 1.7%

4832 intel

[7] [8]

[9]

[10]

Table 5 shows the results of our global router for two very large industrial circuits. Four routing layers were available for both circuits. The lowest horizontal and vertical layer are blocked by the cells and the other two, one for horizontal and one for vertical, are available over the cells. Because Intel2 has so many cells, the routing graph is very complicated. The results demonstrate that our global router can handle modern large industrial circuits, whereas Mickey could not be successfully applied to these large circuits. cells nets Intell Intel2

pins

memor wirerun m(byteosr) lewnigteh vias (byts) lngth(sec)

[11]

[12] [13]

time 1,430.6

[14]

189 9,497 31,647 104,607K 24,290,738 58,612 63,930.4 Table 5: Results on two industrial circuits.

[15]

37 7,285 17,578

37,725K 42,299,146 49,806

7 Conclusion We have presented a new chip-level global router which operates on a new, more accurate routing model. The routing structure is flexible and suitable for multi-layer VLSI technology. Its 3-dimensional irregular routing graph accurately models the multi-layer routing problem. So it gives a good estimate for the routing resources needed. It can meet different design needs. It can minimize the number of vias or the chip area, while minimizing total wire length. It can also be used to minimize the total wire length under channel capacity constraints. T:) achieve the goals, a practical and effective algorithm for finding the routes was also developed. Previously, Mickey was the best performing graph-based global router available in the public domain. However, our algorithm yields better results. In the mean time, we avoid the main drawback which the M-route algorithm has, namely, we use much less memory. (less than one eighth of the memory needed by

225

[16] [17] [18] [19] [20]

Reference Sherwani, N., "Global Routing," Chapter 6 in "Algorithms for VLSI Physical Design Automation," Kluwer Academic Publishers, 1993. Chen, D. and Sechen, C., "Mickey: A Macro Cell Global Router," Proceedings of the European Conference on Design Automation, pp. 248-252, Feb., 1991. Sechen, C., "VLSI Placement and Global Routing Using Simulated Annealing," Kluwer Academic Publishers, 1988. Kou, L., Markowsky, G., and Berman, L., "A Fast Algorithm for Steiner Trees," Acta Informatica 15, pp. 141-145, 1981. Cormen, T. H., Leiserson, C. E., and Rivest, R. L., "Introduction to Algorithms," McGraw-Hill, 1992. Hwang, F. K., Richards, D. S., and Winter, P., "The Steiner Tree Problem," North-Holland, 1992. Sherwani, N., Bhingarde, S., and Panyam, A., "Routing in the Third Dimension from VLSI Chips to MCM," IEEE Press, 1995. Chiang, C., Sarrafzadeh, M., and Wong, C. K., "Global Routing Based on Steiner Min-Max Trees," IEEE Transactions on Computer-Aided Design, Vol. 9, No. 12, pp. 13181325, Dec., 1990. Chiang, C., Wong, C. K., and Sarrafzadeh M., "A Weighted Steiner Tree-Based Global Router with Simultaneous Length and Density Minimization," IEEE Transactions on Computer-Aided Design, Vol. 13, No. 12, pp. 1461-1469, Dec., 1994. Griffith, J., Robins, G., Salowe, J. S., and Zhang, T., "Closing the Gap: Near-Optimal Steiner Trees in Polynomial Time," IEEE Transactions on Computer-Aided Design, Vol. 13,No. Il,pp. 1351-1365, Nov., 1994. Heisterman J, and Lengauer T., "The Efficient Solution of Integer Programs for Hierarchical Global Routing," IEEE Transactions on Computer-Aided Design, Vol. 10, No. 6, pp. 748-753, Jun., 1991. Lin, Y.-L., Hsu, Y.-C., and Tsai, F.-S., "Hybrid Routing," IEEE Transactions on Computer-Aided Design, Vol. 9, No. 2, pp. 151-157, Feb., 1990. Miriyala, S., Hashmi, J., and Sherwani, N., "Switchbox Steiner Tree Problem of Obstacles," IEEE International Conference on Computer-Aided Design, pp. 536-539, Nov., 1991. Garey, M. R. and Johnson, D. S., 'The Rectilinear Steiner Tree Problem is NP-complete," SIAM J. Appl. Math., Vol. 32, No. 4, pp. 826-834, Jun., 1977. Margarino, A., Romano, A., De Gloria, A., Curatelli, F., and Antognette, P., "A Tile-Expansion Router," IEEE Transactions on Computer-Aided Design, Vol. 6, No. 4, pp. 507 -5 17, July, 1987. Tsai, C.-C., Chen, S.-J., and Feng, W.-S., "An H-V Alternating Router," IEEE Transactions on Computer-Aided Design, Vol.11, No. 8, pp. 9 7 6 -99 1 . Aug., 1992. Xiong, J.G., "Algorithms for Global Routing," 23rd Design Automation Conference, pp.824-830, June, 1986. Lawler, E. L., "Combinatorial Optimization: Networks and Matroids," Holt, Rinehart, and Winston, 1976. Luk, W. K., Tang, D. T., and Wong, C.K., "Hierarchical Global Wiring for Custom Chip Design," 23rd Design Automation Conference, pp. 4 81 -489, June, 1986. Nishizaki, Y., Igusa, M., and Sangiovanni-Vincentelli, A., "Mercury: A New Approach to Macro-cell Global Routing," Proceedings of VLSI 89 Conference, Munich, Germany, pp. 411-420, Aug., 1989.

CHIP AND PACKAGE CO-DESIGN - ON CRITICAL BACK END DISCONNECTS Wayne Dai Computer Engineering University of California at Santa Cruz Santa Cruz, CA 95064 [email protected]

ABSTRACT

will approaximately remain the same. However, the resistance per unit length is inversely proportional to the area of the line cross-section. The interconnect scaling theory implies that with all other factors the same, thicker film results in the lower signal delay [2]. Interconnect delay is composed of two terms: the timeof-flight delay and the distributed RC delay. While the time-of-flight delay is not dependent on the area of the line cross-ssection, but set by material parameters and proportional to the line length, the distributed RC delay is inversely proportional to the area of the line cross-section, and proportional to the square of the line length. This suggests that it is more beneficial to place long lines on the package layer instead of the chip layer.

In this position paper, I will highlight some key points on one of the critical back end disconnects: physical design of chip and its package. I believe that the chip and its package should be designed concurrently to achieve the better performance and lower costs. This call for an integrated layout synthesis and electrical analysis tool and an early analysis tools fot making the trade-offs between chip and package routing. 1.

INTERCONNECT DOMINATED ICS

According to the National Technology Roadmap for Semiconductors [1], the IC feature sizes for the period from 1995 to 2001 will be decreased from 0.35u to 0.18u. The total number of transistors will be in the range of 28 to 64 million. The clock rates of ICs will be in the range of 300 to 600 MHz. The interconnect delay may account for about 70% to 0%o of the total gate to gate delay for long nets. 2.

5.

I/O BOUNDED ICS

The increase in die size is much slower than the increase in I/O count and the shrink of die size is much faster than the reduction in pad pitch. It become more and more difficult to accommodate all I/Os with peripheral pads. 3.

FLIP CHIP PACKAGE AND AREA I/O

The flip chip package is the most promising method for the first level packaging in the future. This method places solder bumps on the dice, flipping the chip over, aligning them with the contact pads on the substrate, and reflowing the solder balls in the furnace to establish the bonding between the chips and their packages. This method provides area pads which are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most TAB technologies. 'This method increases the maximum number of I/O and power/ground pads available for a given die size, such that it may liberate the current I/O pads constrained VLSI design. This also provides a large number of low-capacitance and low-inductance electrical interconnections between the die and the substrate. 4.

CHIP AND PACKAGE CO-DESIGN

The general trend in digital VLSI circuits is certainly towards higher complexity and faster clock frequency. Further, as more circuitry is integrated into a single silicon chip and wider length words are processed in parallel, larger registers are more frequently employed. These registers require precise clock signals to synchronize local activity with the global signal. Design of a clock distribution network is critical to high speed and high performance microprocessors and other synchronous VLSI systems. It is very hard to achieve tolerable skew and short rise time in a complex VLSI chip with millions of clocked elements. This becomes more difficult in a VLSI system with multiple clock phases and several chips with different technologies. The first candidate for chip and package co-design is the clock network. The global clock wires may be routed on a dedicated package layer and the local clock wires may be distributed from the area pads to clock terminals. A case study [3] indicates that this scheme dramatically reduces the clock skew and the path delay of the clock network due to the very low interconnect resistance on the package layer. It also significantly reduces the power consumption since the package has lower capacitance per unit length. On-chip power/ground distribution also becomes more challenging as integration density increases and devices get faster. When minimum feature size is scaled down, resistance of the wires goes up. In addition, the total current going through these wires increases, due to raised clock frequency and increased circuit counts. This results in two problem: higher voltage drops along the power/ground nets and increased electromigration rate due to large current densities. For the novel VLSI chip with low voltage supply, the problem is more serious, because the magnitude of the voltage drops that can be tolerated becomes smaller. Power/ground nets are global nets which are over the whole chip. Due to the performance requirement, these nets are

INTERCONNECT SCALING THEORY

The interconect scaling is different from the device scaling. For a multilayer embedded microstripline, the capacitance per unit length and the inductance per unit length are scale invariant. If we uniformly scale the interconnect cross-section of a line as well as the dielectric thickness, the capacitance per unit length and inductance per unit length

226

usually pre-routed before other nets. When a chip becomes more dense and employs more circuits, these global nets make the routing of other nets harder. The power/ground net distribution can also make use of area pads of the flip dice. The flip chip technology provides a 10-20 times reduction in lead inductance compared with wire bonding. Exclusive package layers can be used for power and ground and area I/Os provide many more connection points to them. The more the power and ground pads, the less the effective inductance of the power and ground network, and the less the simultaneous switching noise. Other global connections may also be pull out from the chip to the package. This scheme not only improves the performance but also saves the on-chip routing resource and may even reduce number of layers on chip. Currently there is no physical design tool available to handle the area I/O design effectively. REFERENCES [1] Available from the Semiconductor Industry Association, 4300 Stevens Creek Blvd., Suite 271, San Jose, CA 95129. [2] R. C. Frye, "Physical Scaling; and Interconnect Delay in Multichip Modules," IEEE Trans. on Components, Packaging, and Manufacturing Technology. PartB: Advanced Packaging, Vol. 17, No. 1, 1994, pp. 30-37. [3] Q. Zhu and W. Dai, "Chip and Package Co-Design Technique for Clock Networks," Proc. of 1996 IEEE MultiChip Module Conf., 1996, pp. 160-163.

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The Emergence of "Physical Synthesis" - Optimization of a System's Physical Implementation During Design Planning Peter A. Sandborn, Chet Palesko, Dave Gullickson, and Ken Drake Savantage, Inc. 3925 W. Braker Lane, Suite 325, Austin, Texas 78759-5321 Tel: (512) 305-0053 Fax: (512) 305-0060

Abstract -Traditionally, electronic system design automation tools have focused on logical and behavioral partitioning and synthesis with little or no formal treatment of the physical implementation of a design. ASICs and other complex ICs are synthesized with little understanding of how they impact the physical construction and performance of the system into which they are inserted (system size, routability, thermal performance, reliability, cost, etc...). Lack of methodologies and tools that enable the physical implementation of systems t o be studied and optimized during the planning and specification phase of design is causing a serious disconnect in the design process for high density systems (e.g., PCMCIA cards, cellular phones, laptop computers, etc.). ]In order to meet the demands produced by miniaturization, performance, and market window constraints, designers must adapt their design processes to address the physical implementation of systems as early in the design process as high-level logic design, i.e., "physical synthesis". Physical synthesis is the translation from the structural description of a system to the physical implementation of that system. This paper discusses the unique problems associated with automating the determination of the physical implementation of a system during design planning and specification, and suggests a methodology that addresses design-forpackagability of components. I. INTRODUCTION

Designers must make optimum physical implementation choices early in the design process. Electronic systems are composed of components (active and passive), substrates or boards that interconnect components, and enclosures that contain and protect the boards and components. The physical implementation of a system is often a barrier to realizing the full value of high performance ICs (Fig. 1). The widening gap shown in Fig. I is requiring system designers to use new higher-density packaging techniques (e.g., MCM, Chip Scale Packages, etc...). The use of non-traditional high-density packaging shifts more of the design liability from the ICs to the interconnections between the ICs. Therefore, physical partitioning and the selection of packaging and interconnect technologies are critical decisions for inserting IC's into today's electronic products. Large high performance ASICs need to be synthesized for the appropriate package and interconnect type. System designers need to concurrently

balance a large number of cost and performance views (electrical, thermal, size, reliability, etc...) of a system in order to optimize the physical implementation. 1996 .,J.

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Electronic system design automation (ESDA) tools have focused on logical and behavioral partitioning and synthesis with little or no formal treatment of the physical implementation of a design. In order to meet the demands produced by miniaturization, performance, and market window constraints, designers must adapt their design processes to address the physical implementation as early in the design process as high-level logic design. The way to incorporate physical aspects into the design process is to adopt a top-down system planning methodology that addresses design-for-packagability of components.

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II. THE IMPACT OF PHYSICAL IMPLEMENTATION DECISIONS

Traditionally, designing the physical implementation of a system has waited until logic synthesis and chip physical design is completed. After the chips are completed and the system architecture determined, the system packaging design begins. Many high-density designs are less than optimal because of a failure in understanding and characterizing the

physical system environment and system manufacturing realities when designing the ICs. For years, the best approach was to always make a. larger chip and put more functionality in the silicon. However, the packaging and electrical requirements of these large chips today often make the system cost higher than it would have been with two smaller chips. Ideally, the physical implementation of the system should be addressed as early as behavioral and logical synthesis. Critical physical implementation decisions, made within the first 20% of the total design cycle time, can ultimately commit 80% or more of the final product cost and performance. Therefore, making the most appropriate choices early in the design cycle will significantly increase the chances of finding an optimal or near optimal system design solution.

level. Sub-500 ps rise times and 40 W power dissipations may be common by the year 2000. The trends in integrated circuits complicate an already challenging system design problem. Systems that were implemented on large printed circuit boards only a few years ago are now being forced into PCMCIA cards. Market windows that used to be years are now months. Shrinking product windows mean more efficient system design is required, and system optimization must receive automated support in the physical as well as behavioral and architectural domains. The physical aspects of high performance system that must be managed early in the design process include: I. Highly Interdisciplinary Design Space - One of the most difficult and frustrating problems in high-density system design is the concurrent management of a large number of interdisciplinary performance constraints and requirements. High-density systems have many important views (i.e., electrical, thermal, economic, size, manufacturability, etc...). Most engineers have become specialized in a single view of the problem and are not well equipped to balance highly technical design concerns against economic and manufacturing realities.

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The limiting factors for many next generation systems will be the physical packaging and interconnect of multiple components to implement the design. Increases in IC performance are outpacing the ability of designers to implement systems that can properly exploit such advances. Furthermore, it is often the physical implementation of a system that ultimately sets the cost and performance of the design. The primary system implementation cost drivers are the physical packaging technologies, partitioning, assembly, test, and rework of the system. III. MANAGING PHYSICAL IMPLEMENTATION DECISIONS

The amount of functionality fabricated into integrated circuits is increasing rapidly. Increased functionality is resulting in more I/O per chip and increased die sizes. Already, high-performance components are appearing with more than 1000 1/0, and die dimensions on the order of one inch. The Semiconductor Industries Association (SIA) roadmap predicts that die with over 2000 1/0 will appear before the year 2000. Along with greater functionality on a chip comes increased performance demands, i.e., higher clock rates and increased power dissipation. Higher clock rates mean shorter rise and fall times for digital systems, which result in additional switching noise problems at the board

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Fig. 3 - The interdisciplinarynature of the design problem results in every aspect of system cost and performance being sensitive to every other aspect of system cost and performance.

III. Large Tradeoff Space - The number of technologies, processes, materials and approaches is substantial (Fig. 4) and selecting optimums is arduous and non-trivial if one truly wants a balance in cost and performance. Alternative technologies include: substrates (printed circuit boards, ceramic, thin-film), assembly methods (surface mount, through-hole, bare die - MCM), bonding techniques (wirebond, TAB, flip chip), test techniques, and manufacturing methods. The designer may not be aware of all the technology choices that exist, and few designers can comprehend all the interdependencies and ramifications the technologies and materials chosen may have on a particular design's cost and manufacturability. Further complicating the large tradeoff space is the reality that system optimums are often mixtures of technologies, i.e., not every chip on a board is necessarily assembled into the system using the same technologies and materials.

Methodologies and software tools that perform logical synthesis activities associated with translating behavioral to structural have been widely accepted in recent years. Unfortunately, synthesis activities associated with creating the physical specification of a system beyond a single die are virtually unknown. Because of the interdisciplinary and technology centric focus required to perform early physical synthesis, methodologies for attacking it do not necessarily follow from behavioral or logical synthesis. A top-down system planning methodology consists of physical synthesis coupled with physical design (see Fig. 5). Figure 6 shows a detail of the possible information transfer between a physically oriented system planning tool and system architectural and behavioral modeling. ,11 ... 1

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IV.

PHYSICAL SYNTHESIS

Design synthesis is the process of creating new design representations, or providing refinement to existing design representations. Traditionally, synthesis produces an artifact that satisfies some high-level behavioral or structural specification via the translation from a behavioral (functional) description into a structural description and the translation of a structural description to a physical description. Translation from a functional description to the structural description generates structures that are not generally bound in physical space. The translation from the structural definition to the physical definition (physical synthesis) adds the physical information necessary to produce a working version of the object. System-level physical synthesis is not as concisely defined as logical synthesis activities. There are no well-developed languages analogous to a hardware description language or Boolean equations to define and represent system-level functionality.

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Fig. 5 - A top-down system planning methodology that couples physical implementation design (physical synthesis) with high-level behavioraland structuralspecification.

Central to the realization of physical synthesis are automated tradeoff analysis and physical partitioning of systems. Ten years ago companies had the luxury of assigning large numbers of engineers with detailed simulation tools to conduct physical tradeoff analysis and partitioning problems in order to find optimum system solutions. Unfortunately, economic pressures rarely allow this type of time and manpower intensive solution today. Today, engineers accomplish these analysis activities using a

combination of committees of experts (an electrical expert, a testing expert, a manufacturing expert, etc...), experience, and back-of-the envelope guesses.

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Fig. 6 Detail of possible information transfer between a physically oriented system planner (SavanSys - see Appendix) and traditionalsynthesis activities. In tradeoff analysis the selection of an optimum combination of technologies depends on several drivers: 1) the characteristics of the components to be integrated; 2) the application for which the system will be used (i.e., performance requirements, cost, operating environment, and support requirements); and 3) the availability of previously designed structures and their design history. The implementation of tradeoff analysis can be approached several different ways. Physical tradeoff analysis activities could be carried out using detailed point solution simulation tools. However., because not enough information about the system is available during the conceptual design phase the usefulness of detailed simulators during this portion of the design process is limited. Relying on detailed simulations to provide the information necessary to make system-level implementation decisions can be a dangerous, resource intensive undertaking. Providing intelligent assistance and system-level estimation and predictions to the designer in the synthesis process often proves to be more useful than simulation in the early stages of design. The term "Design Advisor" has been used extensively in the recent literature to describe CAD tools which aid engineers in a complex design process, primarily tradeoff analysis. Design advisors can serve two purposes: l) observe the state of a design and assess its appropriateness against a defined set of constraints, an activity that could be used throughout the design process, and 2) supplement specification and synthesis activities at the conceptual design level. Specific "design advisors" should not be confused with

their management functions. Design advisors provide quantitative and/or qualitative design assistance for a particular design view. The tool that provides the framework within which many different views of a design can be considered is a tradeoff analysis tool. Estimation-based design advisors use a mixture of predictive analysis approaches: heuristic models (using the results of empirical studies to model a system), analytical models (closed-form formulations derived from basic principles), and simulation. Heuristic approaches are useful for some types of tradeoff analysis but may not be applicable to the analysis of new systems that are not similar to the system for which the heuristic was derived. Analytical models mixed with intelligently managed simulations generally represent the best approach for physical tradeoff analysis. Estimation-based tradeoff techniques are not intended to replace detailed simulation, but to provide support for early (conceptual) specification design when simulation may not be practical. Most physical tradeoff analysis is done in a "what-if' mode as opposed to performing automated optimization. The automatic searching of the design space has been done using numerical optimization techniques and design-of-experiments techniques, however, the system packaging design space is often too large for practical optimization. More practical methods consist of knowledge-base paring of the solution tree coupled with local sensitivity analyses. If multiple advisors are operating in an automated optimization mode, the opportunity for conflicts between advisors exists, i.e., different advisors may provide opposing advice. For example, a thermal advisor might suggest removing wiring layers in order to decrease the thermal resistance through a board while a size advisor might advise adding wiring layers to decrease the board area. The design system must be able to determine which advisor's suggestion should be implemented based on user provided constraints and their associated weighting. Recently several software tools for pre-layout physical design of boards and multichip modules have appeared. These tools are auto-placement centric and while they provide useful functionality to the single board/module physical design process, they do not address the early physical synthesis. By the time the netlists are defined and layout process begins, it is often too late to perform significant physical synthesis activities such as technology selection and physical partitioning.

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V. A SYSTEMS

VIEW OF PARTITIONING

Present design methodologies address the partitioning of behaviors and architectures into chips and only consider packaging technology tradeoff analysis after the partitioning (if at all). The optimum number of packaging entities (MCMs, boards, etc.), and the best distribution of the candidate components among them, has not yet been addressed in an automated fashion. A systems view of partitioning requires the consideration of several issues: 1) modified partitioning objectives, 2) the treatment of

additional technologies such as connectorization and enclosures, and 3) connection topology. Module partitioning is essentially analogous to its chiplevel counterpart although more interdisciplinary physical constraints must be considered and the basis for partitioning becomes broader. The use of objective functions designed to help partition functionality into chips may be appropriate for traditionally packaged systems (surface mount and throughhole) but is dangerous for high-density packaging systems such as multichip modules. In traditionally packaged systems, the cost of the system tracks the accumulated cost of the fabrication of the chips, however, in advanced systems where bare die are used and/or extensive test and rework of modules is required, the system costs often do not track the component fabrication costs. High-density packaging systems that contain bare die must include cost modeling that can assess the impact of Known Good Die (bare die test and burn-in) and the possibility of performing repair and rework operations. If these critical (and difficult to model) processes are not included then automated partitioning exercises are of little more than academic interest. One critical element of system-level physical partitioning that has no analog in chip-level partitioning is connection topological relationships. Connection topology is the physical orientation of one board or module to another. There are three topologies which are applicable to intermodule or board connections: plane-in-plane (single chip package, can, or 3D stacking), edge-to-plane (edge connector), and edge-to-edge. The connection topology used has no relationship to the number of connections required, but will determine the number of interconnect crossovers (a crossover is created when one connection between modules or boards crosses over another). Crossovers tend to add complexity that penalizes the system's size, cost, reliability, and electrical performance. Figure 7 shows the magnitude of the potential crossover problem. The number of connection crossovers can be minimized by appropriately partitioning the system. VI. DISCUSSION In this paper we have focused on system physical planning as it relates to a single board/module or a multiple board/module system. Unfortunately, in the future, system planning solutions will not have the luxury of treating a single product in isolation. The required solution for the present product will be the solution that optimizes the family of products it is in. In other words, tradeoff analysis and optimization will have to span multiple products and find the best solution for the present product based on its transition to future products. It is also evident that only considering the cost of manufacturing the system is insufficient for understanding the real cost of the system to the company. Lifecycle analysis is required to obtain true system costs during planning and will ultimately need to be used in system physical partitioning as well. Lifecycle costs include the costs associated with the product development and design, sales and marketing of the

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product, of support and maintenance, waste disposition, etc. The system design community is eagerly awaiting the introduction of software tools that address system physical synthesis. Tools that can provide automated tradeoff analysis and partitioning at a "what-if" level that allows designers to perform system optimization are becoming more common. The future will see the introduction of tools that perform automatic optimization of system designs moving towards

the concurrent design of chips and systems. Tm APPENDIX-THE SAVANSYS SYSTEM PLANNING TOOL

SavanSys is a software tool for enhancing the manufacturability and decreasing the design risk associated with the selection of packaging technologies for integrated circuits. The SavanSys software tool performs system packaging tradeoff analysis. SavanSys concurrently computes physical (size, weight, interconnect routing requirements, escape routing), electrical (delays, attenuation, dc drops, effective inductance), thermal (internal and external thermal resistances, air cooling), reliability (MTMF), and cost/yield performance metrics for multichip systems. The outputs from SavanSys are the physical implementation strategy and the partitioned design. Multichip modules (MCMs) and traditional packaging (through-hole and surface mounting) technologies treated by SavanSys include: traditional and fine-line printed circuit boards, low temperature cofired ceramic, and thin-film (chipfirst and chip-last). Component assembly approaches include wirebonding, TAB, flip chip, and single chip packages. Materials are also available for bare die attach, encapsulation, attaching extrusions, and for defining the bonding and substrate technologies. SavanSys provides the user the ability to compute the cost of assembled electronic systems, including component costs, component preparation (wafer and die level bum-in,

232

bumping), single chip package costs, surface mount and through-hole assembly costs, bare die attach costs (TAB, wirebond, flip chip), tooling costs associated with the processes above, substrate costs, repair and rework costs, and test costs. In addition, learning curves may optionally be defined for any or all steps in the processes that describe the above operation, and handling costs may be defined for all steps that involve the insertion of components into the process flow. The SavanSys tradeoff analysis tool is specifically designed to allow the impact of technology, material, and design rule variations on the cost and performance of a board or system of boards. SavanSys enables designers to make optimum physical implementation and physical partitioning choices early in the design process to facilitate successful implementation decisions. SavanSys is integrated into the Mentor Graphics and Cadence physical design frameworks and is compatible with Aspect and DIE format databases.

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A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven Placement Problems * Gustavo E. Tellez, David A. Knol, and Majid Sarrafzadeh Department of Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208 email: gus,[email protected]

Abstract In this paper we present a new, general approach to the problem of computing lower and upper bounds on net delays. The upper bounds on the net delays are computed so that timing constraints between input and output signals are satisfied. The set of delay lower and upper bounds is called a delay budget. The objective of this work is to compute a delay budget that will lead to timing feasible circuit placemerit and routing. We formulate this problem as a convex programming problem with special structure. We utilize the special structure of this problem to propose a linear programming formulation of the problem. A n:ivel, simple, and efficient graph-based algorithm is proposed to solve the linear programming problem. We present experimental results for our algorithms with the MCNC placement benchmarks. Our experiments use budgeting results as net length constraints for the TimberWolf placement program, which we use to evaluate the budgeting algorithms. We obtain an average of 50% reduction in net length constraint violations over the well known ZSA algorithm. We also study different delay budgeting objective functions, which yield 2X performance improvements without loss of solution quality. Our results and graph-based formulation show that our proposed algorithm is suitable for modern large-scale budgeting problems.

1

Introduction

As integrated circuit technology advances, circuit performance becomes heavily dependent on connecting wire delays. Placement of circuits on an IC is known to have a major impact on connecting wire lengths, and "This work was supported in by NSF grant MIP9207267 and by the IBM Ph.D. Resident Study Program.

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thus on connecting wire delays. It is therefore important that modern placement algorithms consider timing objectives directly. Similarly, given a placement that satisfies timing objectives, it is equally important that the routing algorithms satisfy the timing objectives. Such algorithms are known as timing-driven placement and routing algorithms. Traditional placement and routing algorithms have focused on minimizing total wire-length and maximizing routability. However, these objectives are not necessarily compatible with timing-driven objectives. A number of timing-driven approaches have been proposed. Timing-driven placement approaches can be grouped into two major categories: 1. Path-based algorithms: Analyze path delays explicitly during the physical design. The algorithms try to satisfy both timing requirements and physical requirements simultaneously[10]. 2. Net-based algorithms: In a net-based algorithm, timing requirements are first translated into physical requirements that may be translated into net weights [8], and/or net length upper bounds [11]. This paper focuses on the problem of translating path timing constraints into physical design upper bounds. Utilization of upper bounds simplifies the placement and routing algorithms by translating timing requirements into physical constraints. However, the choice of physical constraints is not unique. Ideally, one ould costheiupper boundsuch thatlth pae would choose the upper bounds such that the placement objectives are optimized, but this problem seems to be hard to solve. The alternative approach is to choose the upper bounds so that the placement algorithms have maximum flexibility. In addition, since

the budgeting results are heuristic in nature and may be overly tight, it is necessary to provide a method by which the budgeting algorithm can adjust the timing budget based on information such as results from a failed placement. In this paper we propose a general formulation for the delay budgeting problem, an efficient algorithm that solves our formulation and different delay budgeting functions that satisfy the above objectives. The first to use net budget approach for placement is the popular zero-slack algorithm (ZSA) [7]. ZSA has no global optimization criteria and is a greedy algorithm that assigns budgets to nets on long paths. ZSA ensures that the net budget is maximal, meaning no more budget could be assigned to any of the nets without violating the path constraints. Most other budgeting algorithms are off-shoots of ZSA. In [12] the ZSA algorithm is improved by allowing for budget distribution in proportion to the net-weights. In [4] the delay budgeting problem is formulated as a convex programming problem. A logarithmic function is chosen to maximize the size of the timing feasible region. A method of adjusting the functions parameters based on placement results is also proposed in [4]. This paper is organized as follows. In Section 2, we introduce some terminology and we introduce our representation of the timing constraints using a timing constraint graph. In Section 3 we formulate the convex delay budgeting problem (CDB) using a timing graph representation, we then convert this problem into a linear programming problem by approximating the CDB problem with the piece-wise linear budgeting problem (P WLDB), and finally we propose a simplified version of these problems, the linear delay budgeting problem (LDB). Next, in Section 4 we introduce the Graph-Based Simplex (GBS) algorithm, and we show how to use it to solve the LDB problem. In Section 5 we propose two algorithms: the PWL-GBS algorithm is an extension of the GBS algorithm that can handle the PWL cost functions, and the iPWL-GBS algorithm iteratively increases the accuracy of the PWL to yield a more time efficient solution to the PWLDB problem. In Section 6 we use the iPWL-GBS algorithm to solve the CDB problem, and we propose and discuss the merits of several slack cost functions. Final]y in Section 7 we present our experimental results and. conclusions.

2

Figure 1: Sample circuit. The module delays, earliest signal arrival time and latest signal arrival time are also given.

modules M = {Mili = 1,..., M[}, a set of nets = {Nii = 1,..., IA}, a set of primary inputs PI = {PlIli = 1,. .. , PI} and a set of primary outputs PO = {POiJi = 1,..., IP1}. The timing constraints for the circuit are given as an input arrival time ai for each primary input Pli, and as a required arrival time rk at each primary output POk. We assume that the output(s) of a module will reach a steady state after all the module inputs have reached a steady state. We let xi and Di denote the latest input arrival time and propagation delay, respectively, for module Mi. A sample circuit is given in Figure 1. This circuit will be used as an example throughout the paper. Let an output of module Mi drive an input of module Mi, and let the latest arrival time at Mj be xj, then the latest arrival time at Mj must satisfy the propagation delay constraint xj > xi + Dj. The delay slack of a connection between an output of module Mi to an input of module Mj is denoted sij =xj - xi - Di. The arrival times of the primary inputs and outputs must satisfy the timing constraintsimposed by the input arrival time and the required arrival time: xi = as and xk = rk The delay budgeting problem seeks to assign values to the delay slacks (and thus to the signal arrival times of the modules). The values of the delay slacks are said to be feasible if they satisfy the timing constraints and the delay propagation constraints. A placement is timing feasible if it satisfies these equations with delay slacks bounded by 0 < sij < siax, where 5s ax is an upper bound on the delay slack. The delay budgeting problem seeks to allocate delay slacks before the placement and routing steps. Thus as a result of delay budgeting, the performance-driven placement and routing steps are given net delay bounds. Since the delay slacks equate with wiring delay it is natural to expect all nets to have non-zero slacks. Furthermore. the distribution of these slacks determines the diffiX

Terminology

Some of the terminology for the following discussion is described next. In this paper we will assume that we are working with a combinatorial circuit C(M,AN, PI, PO), which consists of a set of

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culty of finding a feasible placement (and/or routing) solution. As a result, the objective of the delay budgeting problem is to maximize an increasing function of the delay slacks.

maximizes C(s) = EeiE Cij(sij) subject to: sij = xj - xi - aij, Veij E E, xo = 0, x > 0, s > O. s E sm. X E Rn. The CDB formulation is a convex programming (CP) problem. Next, we convert the CDB problem into a linear programming (LP) problem. We linearize the function Cij (sij) with a piece-wise linear function (PWL) Ci (sij) of H linear segments, as follows:

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Figure 2: Timing graph for the sample circuit. Graph does not contain the timing constraint edges. Lower bounds are shown with the edges. Solid edges have weight mij = 1 and dashed edges have weight mij = 0 The timing budget problem will be formulated using a graph-based timing model. Given a circuit C(M ,Ag, Pi, PC) we construct an edge-weighted, directed graph G(V, E), where V and E denote the set of vertices and edges in the graph, respectively. The vertices of the graph represent the modules. We will denote the number of vertices and edges in the graph as IVI = n and El = m. For each vertex vi, we assign a variable for the latest input arrival time, xi. The edges of the graph model represent the timing constraints on the latest arrival times. Each edge eij E E, with weight aij, represents an inequality xj -- xi > aij. Delay propagation edges are added for each output/input pin pair of every net with cij = Di. Timing constraint edges are added so that the signal arrival times at the primary inputs and outputs are fixed. The graph G(V, E) is called a timing constraint graph. The timing constraint graph for the sample circuit is given in Figure 2.

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= ,... ,H, such that = si~" and th- 1 < th.

Formulation

In the following formulations we assume that we have the circuit C(M,A(, P1, PC) represented as a timing constraint graph G(V, E). The general delay budgeting problem can be formulated as follows: Convex Delay Budgeting Problem (CDB): Given a convex function Cij(sij), and a timing constraint graph G(V, E), find a set of slacks s that

236

Cij(th) - Cij(th.-.1)

th

-

t

h-1

th-lCij(th) -thCij(th-1) th -

th-1

(1) (2)

Now we define the PWL function C(sij ) = minh=,(mzh.sij +b0). Let cij represent the delay slack cost for a delay slack siJ. The delay budgeting is formulated as a linear programming problem. H-PWL Delay Budgeting Problem (H-PWLDB): Given a piece-wise linear delay slack function CH(sij) - minH 1 (mk sij + Oj), and a timing constraint graph G(V, E), find a set of slacks s that maximizes C(c) = e,ieECi subject to: cij < mk sij + O., h = 1,...,H, Veij E E sij = xj - Xi -aij, foralleij E Eo E = 0, x > 0O s>0

C>0 S C E

m X ER.

The H-PWLDB problem is equivalent to the CDB problem if H is sufficiently large. A special case of budgeting problem which can be solved efficiently results when the objective function is linear, i.e. C(x) = Zv"iEV wixi. This problem is called the Linear Delay Budgeting Problem (LDB). The LDB problem can be made equivalent to the H-PWLDB problem by letting Qij = th-1 and ¾ij = th such that th-1 < sij acij. The problem can be converted into standard form by introducing a slack variable sij for each edge: sij = xj-i-aij. An edge with sij = 0 is called a tight edge. A spanning tree T(V, ET) of tight edges ET C E, rooted at vertex vo, of G(V, E) represents the basic solution of the LDB problem. The initial basic feasible solution can be computed efficiently by computing the As Soon As Possible (ASAP) signal arrival times. This problem is the well known Longest Path Problem in a directed graph which can be solved using one of several algorithms [2]. These algorithms can be modified to generate the initial tight edge tree. The pivoting strategy in the GBS algorithm takes advantage of the tight edge tree T(V, ET) representation of the basic solution. A pivot consists in replacing a tight edge eij e ET with an edge that is not in the tree, say eib 0 ET such that the resulting solution remains basic feasible, i.e. can be represented by a new tight edge tree. Further details on the GBS pivoting algorithms can be found in [5].

5

Solving the H-PWLDB Problem

We now turn our attention to the H-PWLDB problem. The H-PWLDB problem is with the GBS algorithm, with a modifed pivoting strategy. We call the modified algorithm the PWL-GBS algorithm. The following changes to the GBS pivoting strategy are made for the PWL-GBS algorithm: 1. Given a tight edge eij, such that sij = Pij, with = th-1, 3ij = th, mij = mj, wi and wj, a forward flip of edge eij, changes these values to aij = th, 3ij = th+1, Mij = MZtl, Wi wi +mz - m+1 and wj = wj-~mh + mh. -ij

2. Given a tight edge eij, such that sij = aij with Ceji = th, ij = th+ wi and wj, 1 , mij = mr, a backward flip of edge eij, changes these values to aij = th-1, 3 ij = th, mij = M h-11, i -W +w M Zm3 ._ -~

237

=h-i and wj=w

~.+M.1

cii(s) I

GA) s.

m(.. ..+)

m

.-

th.,

th

S

SuS

Su

Figure 4: Illustration of a backward flip.

Figure 5: Illustration of a forward flip.

The test for a cost improving pivot remains unchanged if it is performed after a flip. Since a flip only affects the pivot cost of that edge, then the remaining GBS pivoting strategy remains unchanged. Illustrations of the forward and backward flips are shown in Figures 4 and 5. The above procedure is consistent with a pivot on the original H-PWLDB LP problem and thus eventually leads to an optimal solution. With the modified pivoting strategy, the PWL-GBS algorithm retains the memory complexity of the GBS algorithm, namely O(n + m). However, the number of pivots, and thus the time complexity, of the PWL-GBS algorithm increase by at least a factor of H. We will next improve the time complexity of this algorithm. We use the following algorithm to reduce the number of pivots required by the PWL-GBS algorithm. Begin by using a single segment approximation of the problem, hence setting H = 1. The problem initially simplifies to the LDB problem. At each subsequent iteration the number of segments in the PWL cost functions is doubled. Then we re-compute the PWL approximation so that the solution of the previous iteration can be used as the initial basic feasible solution for the current iteration. The PWL-GBS algorithm is then run on the more accurate problem. We call this new algorithm the iterated PWL-GBS algorithm or iPWL-GBS. The iPWL-GBS algorithm requires O(log H) PWL-GBS iterations to solve the H-P'WLDB problem. Our experiments indicate that each iteration takes time similar to the problem with H 1=(see Figure 7).

6

J

L

t&l 4

Solving the Convex Delay Budgeting Problem

The CDB problem can be solved directly using the iPWL-GBS algorithm, given a choice of objective

238

function. The main objective of the delay budgeting algorithm is to produce a budget that will yield a feasible and hopefully optimal placement. This objective is difficult to obtain directly so instead we propose of compatible heuristic objectives: maximize the volume of the timing feasible region, allocate non-zero slacks to all nets, if at all possible, and allow for some control over the assigned slacks during a potential postplacement feedback step. In addition to the above objectives, we are also free to choose functions that are amenable to optimization. With these objectives in mind, we propose three functions: QUAD: C(s) = -(2 - i), LOG: C(s) = log(s+a)/log(p +a), and QUAD+ZSA: use the QUAD function with p equal to ZSA algorithm slack values multiplied by a factor, 2. The method by which we linearize the objective function has a significant impact on the performance and the results of the algorithm. For this reason an optimal algorithm for linearizing the cost function is used.

7

Results and Conclusions

We implemented our algorithms using C++ on an Sun machine. Our experiments used the MCNC placement benchmarks. Since most of these benchmarks do not contain timing information, we have budgeted wirelengths directly instead. The formulation is identical to the timing budget formulation, except that instead of timing values we use wire-lengths. In our experiments we compute a single upper bound for all PI to PO pairs from the longest PI to PO path. The single upper bound is obtained by multiplying the length of the longest path times an upper bound factor 77 (we used 1.5-3.0). We then take the net budgets and convert them into constraints for the placement program. We used the TimberWolf V1.2 placement program for

5

10000

Ph'PI , 3

p

.. . . . . .

..

1

1

100

10000

m

.

.

..- 7.. .- .-

.

-.. - -.- .-

.N..

- - . - .- .-

.

No. of net bounds b33 1707

TesI:04

755

.05

1689

Tesi,08

2403

Upper Bound _____I

1.5 3.0 15 3.0 1.5

22.33 9.94 37.14 23.49 15.36

2

3

5

Figure 7: Pivot ratio versus iteration, for the iPWL - GBS algorithm. Plot shows min, max and average values for the QUAD (lower curves) and LOG (upper curves) functions.

evaluation of the timing budgets.

Te

.

h

Figure 6: Plot of number of pivots vs number of edges. Each point is obtained from one of the iterations of the iP WL- GBS algorithm.

rir.Tary2

. .

0

1

Prn-aryi

.

2

100

Example

..

functions.

Net Bound Volations (%) QUAD LOG QAD+ ZSA 19.14 8.26 7.50 23.26 1.69 4.69 22.14 11.78 16.40 24.25 6.33 7.03 23.58 9.01 7.47

3.0

3.58

19.60

4.5

2.25

1.5 30 15

18 .29 4.09 21.39

3.0

14.44

20.72 23.92 15.90 11.15

7.76 2 72 6.87 2.51

5.21 3.43 4.81 2.35

Table 1: Table of budgeting and placement experimental results, showing percentage of bad nets. Figures 8 and 9 show a plot of the net violations for a ZSA and a QUAD+ZSA budgeted and placed benchmark. The percentage of bad nets (nets which violated length constraints) for each benchmark is shown in Table 1. The results in this table indicate that the proposed algorithms offer a significant improvement over the traditional ZSA algorithm, reducing the number of bad nets an average of 50%. Furthermore, these results also indicate that there may be more than one suitable cost budgeting function, as the results for the LOG and QUAD+ZSA functions are virtually identical in quality. This result is of practical importance, since the performance of the algorithm differs depending on the cost budgeting function. In our experiments (see Figure 7) we observed as much as 2X difference in the number of pivots between the QUAD and LOG

239

Next, we provide experimental evidence for our average time complexity claims. For the following results we ran the iPWL-GBS algorithm on various MCNC benchmarks for the QUAD and LOG function, for H = 32 segments. Each data point for Figures 6 and 7 was obtained from one PWL-GBS iteration. In Figure 6 we show the number of pivots as a function of the number of edges. The plot shows that, for these benchmarks, the average number of pivots grows linearly with m. In addition Figure 7 also shows that the number of pivots remains bounded during successive iPWL-GBS iterations. Our implementation of the iPWL-GBS algorithm can handle large problems. The largest MCNC benchmark, for example, contains 25,000 cells and 33,000 nets, resulting in a graph with n =25,000 and m =58,000. Using the LOG objective function, this problem problem took 1 hr. 32 min. to solve on an SS10 workstation. In this paper we have studied the problem of computing a delay budget for placement and routing problems. We have formulated the problem as a convex programming problem. We then modified the problem formulation into an LP problem by modifying the objective functions into piece-wise linear functions. We have proposed a space and time efficient algorithm. iPWL-GBS, to solve these problems by taking advantage of the special structure of the LP formulation. We have implemented and tested our proposed budgeting algorithm. Our experiments use published MCNC benchmarks for data and the Timberwolf placement

Figure 9: Net violations for placement using constraints generated by iPWL-GBS with the GBS+ZSA function.

Figure 8: Net violations for placement using ZSA budget constraints. for Primaryl example with 7- = 2.0.

Design Automation Conference, pages 123-130. IEEE/ACM, 1986.-

program for evaluation of the budgeting results. Our experiments show that the proposed budgeting algorithm obtains results that provide significant improvement over previous approaches both in quality and in efficiency.

[7] R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. "Generation of Performance Constraints for Layout". IEEE Transactions on Computer Aided Design, CAD-8(8):860-874, August 1989.

References

[8] Y. Ogawa, T. Ishii, Y. Terai, and T. Kozawa. "Efficient Placement Algorithm Delay for HighIn DeSpeed ECL MasterSlice LSI's". sign Automation Conference, pages 404-410. IEEE/ACM, 1986.

[1] R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. "Network Flows: Theory, Algorithms, and Applications". Prentice Hall Inc., Englewood Cliffs, NJ, 1993.

[9] S. Plotkin and E. Tardos. "Improved dual network simplex". In Ann. ACM-SIAM Symp. on Discrete Algorithm, pages 367-376. ACM-SIAM, 1990.

[2] T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. McGraw-Hill Book Company, 1991. [3] G. B. Dantzig. "Linear Programming and Extensions". Princeton University Press, Princeton, NJ, 1963.

[10] A. Srinivasan, K. Chaudhary, and E. S. Kuh. "RITUAL: An Algorithm for Performance Driven Placement if Cell-Based IC's". In Third Physical Design Workshop, May 1991.

[4] T. Gao, P. M. Vaidya, and C. L. Liu. "A New Performace Driven Placement Algorithm". In International Conference on Computer-Aided Design, pages 44-47. IEEE/ACM, 1991.

[11] M. Terai, K. Takahashi, and K. Sato. "A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint". In dac, pages 96-102. IEEE/ACM, 1990.

[5' J. F. Lee and C. K. Wong. "A PerformanceAimed Cell Compactor with Automatic Jogs". IEEE Transactions on Computer Aided Design, CAD-11(12):1495-1507, December 1992.

[12] H. Youssef and E. Shragowitz. "Timing ConIn Interstraints for Correct Performance". national Conference on Computer-Aided Design, pages 24-27. IEEE/ACM, 1990.

[6]1 S. L. Lin and J. Allen. "Minplex - A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout". In

240

REDUCED SENSITIVITY OF CLOCK SKEW SCHEDULING TO TECHNOLOGY VARIATIONS Jose Luis Neves and Eby G. Friedman University of Rochester Department of Electrical Engineering Rochester, New York 14627 email: [email protected] Abstract - A

methodology is presented

in this paper

for

determining an optimal set of clock path delays for designing high performance VLSIIULSI-based clock distribution networks. This methodology emphasizes the use of non-zero clock skew to reduce the system-wide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, the difficulty in controlling the delays of the clock paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local data path while incorporating process dependent delay values of the clock signal paths. Graph-based algorithms are presented for determining the minimum clock period and for selecting a range of processtolerant clock skews for each local data path in the circuit. These algorithms have been demonstrated on the ISCAS-89 suite of circuits. Furthermore, examples of clock distribution networks with intentional clock skew are shown to tolerate worst case clock skew variations of up to 30% without causing circuit failure while increasing the system-wide maximum clock frequency by up to 20% over zero skew-based systems. 1.

INTRODUCTION

Clock skew occurs when the clock signals arrive at sequentially-adjacent storage elements at different times. Although it has been shown that intentional clock skew can be used to improve the clock frequency of a synchronous circuit [1, 2, 3, 4, 5. 6], clock skew is typically minimized when designing the clock distribution network, since unintentional clock skew due to process parameter variations may limit the maximum frequency of operation, as well as cause circuit failure independent of the clock frequency (i.e., race conditions). In this paper, the clock skew of a local data path Lj is defined as Tskemij(Lij) = TcDi - TcDj. where TCDi and TcDj are the clock signal delays of registers Ri and Rj. The clock skew is described as negative if TcDi precedes TcDj (TcDt < TCDj) and as positive if TcDi follows TcDj (TcDi > TcDj). It is shown in [ 1,2] that double clocking (the same clock pulse

triggers the same data into two adjacent storage elements) can be prevented when the clock skew between these storage elements satisfies Tsge.ij 2 - TpDin, where TpDmin is the minimum propagation delay of the path connecting both storage elements. Furthermore, it is also shown in [1,2] that zero clocking (the data reaches a storage element too late relative to the following clock pulse) is prevented when Tskeij < Tcp - TpD., where Tcp is the clock period and TpDm,, is the maximum propagation delay of the data path connecting both storage elements. The limits of both inequalities, TSkeij(mti,) = -TPDmin and TskeCij(x) = TCP - TPDdefine a region of valid clock skew for each pair of adjacent This research was supported by Grant 200484/89.3 from CNPq (Conselho Nacional de Desenvolvimento Cientifico e Tecnol6gico) Brazil, the National Science Foundation under Grant No. MIP-9208165 and Grant No. MIP-9423886, the Army Research Office under Grant No. DAAH04-93-G-0323, and by a grant from the Xerox Corporation

241

storage elements, called the permissible range [7] or certainty

region [8]. as shown in Figure 1. A violation of the lower bound leads to circuit failure while a violation of the upper bound limits the clock frequency of the circuit. Based on these observations, the process variation tolerant optimal clock skew scheduling

problem can be divided into two sub-problems: determining a minimum clock period that defines a valid permissible range for any two storage elements in the circuit, and determining a minimum width for each permissible range such that unacceptable variations in the target clock skew remain within the bounds of a permissible range. In this paper, a solution for this problem is presented. Localdatapath R

im,

Race Candtttat.

Peetterne C Ti,,=kTk-

ClackPertad Lmnttaian

-gT,,,,

C,

dlock thetarange (itm'et

Figure 1: Permissible range of a local data path. The problem of determining a minimum clock period has been previously solved [1, 3-6] in which a set of timing equations is used to determine the optimal clock period and the clock delay to each register in the circuit, thereby defining the local clock skews. However, in order to better control the effects of process parameter variations, it is advantageous to determine the permissible range of each local data path, select a clock skew

value that permits the greatest variation of skew within the permissible range and, finally, determine the clock delays to each register.

This paper is organized as follows: in Section 2, a localized clock skew schedule is derived from the effective permissible range of the clock skew for each local data path considering any global clock skew constraints and process parameter variations. In Section 3, techniques for determining the set of clock skew values that are tolerant to process parameter variations are presented. In Section 4, these results are evaluated on a series of benchmark circuits, demonstrating performance improvements while tolerating process parameter variations. Finally, some conclusions are drawn in Section 5. 2. OPTIMAL CLOCK SKEW SCHEDULING

A synchronous digital circuit C can be modeled as a finite directed multi-graph G(VE), as illustrated in Figure 2. Each vertex in the graph, vj E V, is associated with a register, circuit input, or circuit output. Each edge in the graph, eij E E, represents a physical connection between vertices vi and v1, with an optional combinational logic path between the two vertices. An edge is a bi-weighted connection representing the maximum (minimum) propagation delay TpD.a. (TpDmin) between two sequentiallyadjacent storage elements, where TPD includes the register, logic,

and

interconnect

delays

of

a

local

data

path

[7],

TPD = TC -Q + TLg,,i, + T1,nt + T,,, * A local data path L0j is a set of two vertices connected by an edge, Lij = (vi, erj, vjl for any vi, vj E V, as shown in Figure 2. A global data path, PkI = Vk -- P- vI, is a set of alternating edges and vertices {vb ekh, v,, e 12, ..., en l/ v,}, representing a physical connection between vertices Vk and vl, respectively (see Figure 2). A multi-input circuit can be modeled as a single input graph, where each input is connected to vertex v0 by a zero-weighted edge. Pl(Lij) is defined as the permissible range of a local data path and Pg(Pkl) is the permissible range of a global data path.

Local data path LI

range of each cascaded local data path between Vk and v1 , independent of the global path between vk and v,. Therefore, a clock skew between the vertices Vk and v,exists if the intersection of the permissible ranges of the paths connecting Vk and v, form a non-empty set, where the intersection of the permissible ranges is determined by the recursive application of the intersection operation applied to a set [10] and a set is the collection of clock skew values within a permissible range. The following example illustrates two circuits, one with two parallel paths and one with one forward path in parallel with a feedback path. Note that determining the permissible range of each local data path is not a sufficient condition for both circuits to work. Example 1: An example of applying the concept of a permissible range of a clocked system to a circuit composed of multiple paths is illustrated in Figure 3, where the numbers assigned to the edges are the maximum and minimum propagation delay of each Lij, and the register set-up and hold times are arbitrarily assumed to be zero. Furthermore, the pair of clock skew values associated with a vertex (in bold and italic) are the minimum and maximum clock skew calculated with respect to the origin vertex vo for a given clock period. The pairs in italic are determined with Tcp = 6 tu (time units) while the pairs in bold are determined with Tcp 8 tu.

Figure 2: Graph model of a synchronous circuit in terms of local and global data paths

Parallel Path

2.1 Timing Constraints

Skew

The timing behavior of a circuit C can be described in terms of two sets of timing constraints, local constraints and global constraints. The local constraints ensure that the data signal is correctly ]latched into the registers of a local data path in order to prevent double and zero clocking. The local timing constraints are represented by the following equation [1-6] to prevent zero clocking,

Skewe

TSk,, (Lij ) 2 THOId)

TPD(m.if) +

-

Ci

I

-

T,. = 8 tu Tcp =

(0,o) (0,0)

6 tu

-

TPD(m)

I

(-10,-2) (-10-6) 11 (-2,-2)

(.2,0)

Permissible range: v,-.

-7If

| -10

-6

-10

(1)

I

T,-,,,

-2

time

-2

and the following equation to prevent double clocking, TSke (Lii ) < TCP

(-4,1) (-4,-) 7F

6

0 rime

(a)

(2)

Feedback Path

where ,ij is a safety term introduced in [7] to prevent race conditions due to process parameter variations, as described in Section 3. Besides satisfying the permissible range of a local data path Pl(Lij), it is also necessary to ensure the existence of a permissible range for each global data path Pg(Pk,) to guarantee a race-free circuit, particularly when there are multiple feedback and parallel paths between the two vertices Vk and v1. Two paths with common vertices are said to be in parallel when the signal data flows in the same direction in both paths. Likewise, a path is a feedback path when the data signal flows in a direction that is the reverse direction Df the data signal flowing from the input of the circuit to the output of the circuit. To illustrate a circuit configuration where it is necessary to provide a permissible range for each global data path, consider a circuit composed ef several global data paths connecting two common vertices * and v,. The vertices Vk and v, represent two registers, each register driven by a single clock signal. The two clock signals define a unique clock skew value between Vk and v, independent of the path connecting Vk to va.Therefore, a valid clock skew between Vk and v, only exists if the clock skew is common to all the global data paths connecting Vk and v,. Since the clock skew between vertices vk and v/ is also the sum of the clock skew of each cascaded local data path connecting Vk to vI [9], the resulting sum is independent of the global path between vk to v,. Alternatively, the permissible range of each of the paths connecting the vertices vk and v/ is the sum of the permissible

242

Skew - T_ = 8 tu

(0,11) (0,0()

Skew - Tc, = 2 tr

-

(-3,4) (-3.-2) 3 (010) (4,'10)

12 Permissible range: , 3

-3

2

.3

4 Tp = 8 < T,,,.

-v

lo

Tr2 ,

10

time

-2

lortime = 12

(b)

Figure 3: Example circuits describing the process for matching permissible clock skew ranges by adjusting the clock period Tcp. (a) System composed of two forward flowing parallel paths; (b) System composed of a single forward path and a single feedback path. The minimum clock skew of each local data path Lij is obtained by applying the maximum permissible negative clock skew to the local data path, or Tskewij = TPDmi, from (1). The maximum bound is obtained directly from (2), given that the clock period Tcp is known. Adding the minimum (maximum) clock skew of each cascaded local data path, the permissible range of each global data path connecting v] to V 3 is obtained, as illustrated in Figure 3. Observe that in Figure 3a, for a clock

period Tcp = 6 tu, no value of clock skew exists that is common to the two paths connecting vertices v/ and v3, since the permissible range of the path v1 -v2-v3 is [-10,-6] and the permissible range of the path v1 -v3 is [-2,-2], and these permissible ranges do not intersect (or overlap) in time. A common value of clock skew is only obtained when the clock period is increased to 8 tu. Note that Tcp = 8 tu is less than the minimum clock period determined with zero clock skew, which is 11 tu. Therefore, a reduction of the minimum clock period from 11 tu to 8 tu is obtained with the application of negative clock skew. From the example in Figure 3, in order to prevent circuit failures at the global level, circuits with parallel and feedback paths must have a non-empty permissible range composed of the intersection or overlap among the permissible ranges of each individual parallel and feedback path. Therefore, a new set of global timing constraints are required and formalized below. The concept of permissible range overlap of a global data path Pk. can be stated as follows:

Tsk,.

k(Flj)•0

MAX I mi~n[T_(l)mz] *kw

Imi~nn

(

,k (4)n

and the lower bound of Pg(Pk,) is given by TW. (Pk).i. =MAX{max[TSk(

J

(p)

j}.(5) (m5ax[

Observe that both bounds of a clock skew region given by (3) are dependent on the clock period in the presence of feedback paths between vertices Vk and v1. This recursive characteristic is used to increase the tolerance of the clock distribution network to process parameter variations, as explained in Section 3. For a non-recursive data path (either local or global), the lower clock skew bound is independent of the clock period, as shown in (1). 2.2

Theorem 1: Let Pkl E V be a global data path within a circuit C with m parallel and n feedback paths. Let the two vertices, Vk and v, E Pk,, which are not necessarily sequentially-adjacent, be the origin and destination of the m parallel and n feedback paths, respectively. Also, let Pg(Pkl) be the permissible range of the global data path composed of vertices Vk and v1. Pg(Pk,) is a nonempty set of values iffthe intersection of the permissible ranges of each individual parallel and feedback path is a non-empty set, or

Pg(P'k)=(flPg(PI'))n j lP n

(Pklmn

(3)

Proof =>: The clock skew between vertices Vkand vi, TSkekl, is

unique and independent of the number of paths connecting the two vertices. Also, the clock skew TSke,,k, of a single path that connects both vertices is the sum of the clock skew of each local data path along the path. Assuming that a value of clock skew exists between vertices Vk and v1, this value is always the same independent of the path connecting vk and v1. Furthermore, for each path connecting vertices vk and v1, the minimum (maximum) clock skew value is the sum of the minimum (maximum) clock skews of each local data path along the path defining the permissible range of the global path. Therefore, a valid clock skew between vertices vk and v, must be within the permissible range of clock skew of each and every path connecting both vertices. In other words, the intersection of permissible ranges must be a non-empty set. 4=: Assume that Pg(Pkl) = 0 and there exists a valid clock skew value between vertices Vk and v1. If this value of clock skew exists, it must be contained within the permissible range of all the paths connecting the vertices Vkand v1. If a clock skew value exists for all the paths, the result of the intersection of all the permissible ranges cannot be an empty set. Therefore the valid value of clock skew contradicts the initial assumption. U

Optimal Clock Period

Without exploiting intentional clock skew, the minimum clock period is determined from (2) for the local data path with the maximum propagation delay. However, applying intentional negative clock skew to a local data path permits the circuit to operate at higher clock frequencies. The minimum clock period of a circuit operating with intentional clock skew must simultaneously satisfy (1), (2), and (3) for every local data path. The minimum clock period to safely latch data through a local data path Lqj can be determined by the differences in propagation delay of the combinational logic block within L4j, assuming that the timing parameters of the registers (TSetr-ap THo ld, and Tc-Q) are constant. When the maximum possible negative clock skew [2] is applied to Lij, the clock period is the difference between the propagation delays, since the maximum negative clock skew is the minimum propagation delay within L,1 . The maximum negative clock skew defines the lower bound of the clock period of Lj. The upper bound of the clock skew can be any value defined by the minimum clock period. Similarly, the clock period of a circuit is bounded by two values, Tcpmi and Tcpmt, determined from the differences in propagation delay within the local data paths of the circuit, as shown below and independently demonstrated by Deokar and Sapatnekar [6]. The lower bound of the clock period, Tcpmin is the greatest difference in propagation delay of any local data path Lj E C, TCP~mn = MAXFmin(TPDmaxij-TPDminiJ),max(TP~,,ii)l

(6)

L jEV

I jv

and the upper bound of the clock period, Tcpm_, is the greatest propagation delay of any local data path Lij e G, TCmp

= MAX[max (TPDmx.j)i

fmax (TPD

~ii )]

.(7)

The second term in (6) and (7) accounts for the self-loop where the output of a register is connected to its input through an optional logic block. Since the initial and final registers are the same, the clock skew in a self-loop is zero and the clock period is determined by the maximum propagation delay of the path connecting the output of the register to its input. Observe that a clock period is equal to the lower bound in circuits without parallel and/or feedback paths. Furthermore, the permissible ranges determined with a clock period equal to the upper bound

Similar to the permissible range of a local data path, the permissible range of a global data path is bounded by a minimum and maximum clock skew value. These values, the upper and lower bounds of the permissible range Pg(Pkl), can be determined as a function of the upper and lower bounds of the permissible ranges of each independent parallel or feedback path connecting

TCPma will always satisfy (3) since the permissible range of any

local data path in the circuit contains zero clock skew. Although (7) satisfies any local and global timing constraints of circuit C, it is possible to determine a minimum clock period that satisfies (3) while including intentional clock skew. This transformation leads to the optimal clock period problem which is stated in the following theorem:

vertices Vk and v1.

Lemma 1: Let the two vertices, vk and v, E POk,be the origin and destination of a global data path with m forward and n feedback paths. If Pg(Pkl) • 0, the upper bound of Pg(Pk1 ) is given by

243

Theorem 2: Given a synchronous circuit C modeled by a graph G(V,E), there exists a clock period Tcp satisfying (3) and bounded by Tcpmin < Tcp < Tcpm. The clock period is a minimum if the permissible range resulting from (3) contains only a single value of clock skew. Proof: For a local data path, if the clock period increases (decreases) monotonicaly, the upper bound of the permissible range always increases (decreases) monotonicaly due to the linear dependency between the clock skew and the clock period. The lower bound does not change since it is independent of the clock period. Therefore, starting with Tcp = Tcp,,m, and progressively reducing the clock period is equivalent to constraining the permissible ranges to narrower regions. In the limit, the minimum clock period is determined when a single value of clock skew within the permissible range is reached, since, due to monotonicity, a further reduction in the clock period would result in an employ permissible range, violating (3). M

three registers symbolized by v, v,, and Vf with combinational logic within each local data path. It is assumed for simplicity in this example that the timing parameters of each register (Tse,.,p, THld, and Tc-Q) are zero. The minimum clock period Tcpmin is determined from (6) and is 7 tu, which is the difference in propagation delay within the logic block of the local data path vi-vf . The maximum clock period Tcpa. is the maximum propagation delay through a logic block in the circuit, which is 12 tu. Starting with Tcp1 j, the permissible ranges of each local data path are used to calculate the permissible range of each global data path connecting vertices vi to Vf . Since a unique clock skew must exist between vertices v, and Vp, this value of clock skew must exist within the permissible range of each global data path connecting both vertices. Hi~Tc,_j

= 7 tu T__, = 12 tu

A graph-based algorithm is presented in Figure 4 to determine the minimum clock period that ensures that each of the permissible ranges in the circuit satisfy (3). The initial clock period is given by (6) and, for each pair of registers in the circuit C, the local and global permissible ranges are calculated, as illustrated in Figure 4 in the lines 4-13. The content of the permissible range is evaluated (line 14) and if empty, the clock period is increased (line 25), otherwise the clock period is decreased (line 26). A binary search is performed on each new

To1 = Path v, v,-

- v,

7 tu

FTUJ

Path v,- f

F}Tpl) -5

Path v/ - V;_

_

rime

-3 _

_

1

_ 4

Pg(Pd) = Pg(Pt,) - Pgq(P,,) , Pg(P,.) = 0

clock period within the algorithm Intercept until the minimum

clock period has been reached.

Te = 1] tu

Tp= 9tu

1. Intercept( G(VE), TCp) 2. for each v, E V do 3. for each vy E V and v se v, do

4.

for i MAX[p(Lij)]. This violation is corrected by increasing the

clock period Tcp, since due to monotonicity the effective permissible clock skew range for each local data path is also increased (Tskewj(,,,) is increased). The new clock skew value may also violate the lower bound of a local data path, i.e., Tskeij`< 7Skeij(min),

where

TSkwij(min) C p(Lj).

Upper bound violation: Assume, for example, that the worst case variation of the clock skew results in an upper bound violation. For example, the nominal clock skew is TskeI3 = -I tu while the clock skew caused by the worst case variation is 0.5 tu. By increasing the clock period to 9.5 tu, the width of the permissible range between vertices v, and V3 is increased to Pg(P;3 ) = [-2,1]. The new upper bound is greater than the worst case variation of clock skew and the circuit will now operate correctly. (-4,2)

(0,0)

(-10,0)

Permissible range: v, - v,

1111111111111MI 1, -10

-2 9< T

T=

VL Circ Des

Upper bound violation Tsk-w13:

Cy

TSI.. 3:

Solution: Increase Tc, to 9.5 New permissible range: =

Pg(P,,)= [-2,0]

Chosen =-I

Worst case = -2.5

Solution: Increase C,, to 1.0 Increase Tp to 10.0 New permissible range:

[-2,1]

-10 T

Figure 7: Synthesis methodology of clock distribution networks tolerant to process variations

1 time 11

Lower bound violation

Pg(P13 ) = [-2,0] Chosen = -I Worst case = 0.5

Pg(P73)

0 =

=

-I 10 < Tc

=

2 time 11

Pg(P73 ) = [-1,2] Chosen T,_,,,3 = 0.5

Two compensation techniques are used to prevent lower bound violations, depending on where the effective permissible range of a local data path p(Lij) is located within the permissible range of the local data path, P1(L4j). If the lower bound of p(Lij) is greater than the lower bound of P1(Lj), the clock period Tcp is increased until the race condition is eliminated, since the effective permissible range will increase due to monotonicity. However, if after increasing the clock period, the clock skew violation still exists and the lower bound of the effective permissible range is equal to the lower bound of the local data path (MIN[p(L 1j)] = MIN[PI(I4)]), any further increase of the clock period will not eliminate the violation caused by not satisfying (1). Rather, if the lower bound of p(L5j) is equal to the lower bound of PI(Lij), a safety term Cjj > 0 is added to the local timing constraint that defines the lower bound of Pl(Lj) [see (1)]. The clock period is increased and a new clock skew schedule is calculated for this value of the clock period. The increased clock period is required to obtain a set of effective permissible ranges with widths equal to or greater than the set of effective permissible ranges that existed before the clock skew violation. Observe that by including the safety term j,, the lower bound of the clock skew of the local data path containing the race condition is shifted to the right, moving the new clock skew schedule of the entire circuit away from the bound violation and minimizing the likelihooi of any race conditions. This iterative process continues until the worst case variations of the selected clock skews no longer violate the corresponding effective permissible ranges.

Figure 8: Example of upper and lower bound clock skew violations and strategy to remove these violations Lower bound violation: Now assume that for the same circuit shown in Figure 8, the worst case variation causes the clock skew

to be -2.5 tu, rather than a nominal value of the clock skew of -I tu, violating the lower bound of the permissible range Pg(PI3 ). In this case, increasing the clock period does not remove the violation since the lower bound of Pg(P13 ) is independent of the clock period. Rather, the safety term 4 13 is increased arbitrarily from 0 to I tu and the clock period Tcp is increased to 10 tu. As discussed previously, a revised schedule of clock skew values is calculated by applying the top-down design system to re-design the clock distribution network. The topology of the clock distribution does not change, although the delay values assigned to the branches must change to reflect the new clock skew schedule. In Figure 8, increasing Tcp to 10 tu will create a new permissible range Pg(P13 ) = [-1,2]. A new clock skew is selected from this permissible range and the worst case clock skew variations are calculated. Assuming that the worst case variation is still 1.5 tu of the nominal value (see Figure 8), this new target clock skew is within Pg(P13 ) and the violation is eliminated.

246

4.

SIMULATION RESULTS

Table 2: Worst case variations in clock skew due to process parameter variations, IDO = 15%

The simulation results presented in this section illustrate the performance improvements obtained by exploiting non-zero clock skew while considering the effects of process parameter variations. In order to demonstrate these performance improvements, the suite of ISCAS-89 sequential circuits is chosen as benchmark circuits [14]. A unit fanout delay model (one unit delay per gate plus 0.2 units for each fanout of the gate) is used to estimate the minimum and maximum propagation delay of the logic blocks. The set-up and hold times are set to zero. The performance results are illustrated in Table 1. The number of registers and gates within the circuit including the I/O registers are shown in Column 2. The clock period assuming zero clock skew is shown in Column 3. The clock period obtained with intentional clock skew is shown in Column 4. The resulting performance gain is shown in Column 5. The clock period obtained with the constraint of zero clock skew imposed among the 1/0 registers is shown in Column 6 while the performance gain with respect to a zero skew implementation is shown in Column 7.

circuit Tcpo1TcPi permissible selected Simulated range clock skew (ns) skew nom worst case I

cdn cdn 2 cdn 3

exl s27 s298 s386 s444 s510 s838

size #reg./#gates 20/7/10 23/119 20/159 30/181 32/211 67/446

TCP. Tskcwi = 0

Tcpi Tsk.i;• 0

11.0 9.2 16.2 19.8 18.6 19.8 27.0

6.3 5.4 11.6 19.8 11.1 17.3 13.5

gain (%) 43 41 28 0 41 13 50

T5sk-

TCP gain - 0 ( 10o

7.2 6.2 11.6 19.8 11.1 17.3 15.6

[-8,-2] [-6.8. -1.4] [-14, 2.3]

-3.0 -4.2 1.1

-3.0 -41 1.14

-2.10 -3.3 13

nom

worst

-

case

0.0 2.4 3.6

30.0 21.4 18.2

5. CONCLUSIONS

Table 1: Performance improvement with non-zero clock skew circ.

-

11/9 18/15 27/18

Error (%)

35 33 28 0 41 13 42

The results shown in Table I demonstrate reductions of the minimum clock period of up to 50% when intentional clock skew is exploited. The amount of reduction is dependent on the characteristics of each circuit, particularly the differences in propagation delay between each local data path. Note also that by constraining the clock skew of the 1/0 registers to zero, circuit speed can be improved, although less than without this constraint. Examples of clock distribution networks which exploit intentional clock skew and are less sensitive to the effects of process parameter variations are listed in Table 2. The clock trees are synthesized with the system presented in [7,9]. The clock skew values are derived from a circuit simulation of the clock path delays of a clock tree using SPICE Level-3 assuming the MOSIS SCMOS 1.2 gLm fabrication technology. The minimum clock period assuming zero clock skew TcpO and intentional clock skew Tcpi is shown in Column 2, respectively. The permissible range most susceptible to process parameter variations is illustrated in Column 3. The target clock skew value is shown in Column 4. In Columns 5 and 6, respectively, the nominal and maximum clock skew are depicted, assuming a 15% variation of the drain current IDO of each inverter. Note that both the nominal and the worst case value of the clock skew are within the permissible range. The per cent variation of clock skew due to the effects of process parameter variations is shown in column 7. A 20% improvement in speed with up to a 30% variation in the nominal clock skew, and a 33% improvement in speed with up to an 18% variation in the nominal clock skew are observed for the example circuits listed in Table 2.

The problem of scheduling clock path delays such that intentional localized clock skew is used to improve performance and reliability while considering the effects of process parameter variations is examined in this paper. A graph-based approach is presented for determining the minimum clock period and the permissible ranges of each local data path. The process of determining the bounds of these ranges and selecting the clock skew value for each local data path so as to minimize the effects of process parameter variations is described. Rather than placing limits or bounds on the clock skew variations, this approach guarantees that each selected clock skew value is within the permissible range despite worst case variations of the clock skew. The clock skew scheduling algorithms for compensating for process variations have been incorporated into a top-down, bottom-up clock tree synthesis environment. In the top-down phase, the clock skew schedule and permissible ranges of each local data path are determined to allow the maximum variation of the clock skew. In the bottom-up phase, possible clock skew violations due to process parameter variations are compensated by the proper choice of clock skew for each local data path and the controlled increase of the clock period Tcp. The clock period of a number of ISCAS-89 benchmark circuits are minimized with this clock scheduling algorithm. Scheduling the clock skews to make a clock distribution network more tolerant to process parameter variations is presented for several example networks. The results listed in Table 2 confirm the aforementioned claim that variations in clock skew due to process parameter variations can be both tolerated and compensated. 6.

[1] J.

P.

Fishburn,

"Clock

Skew

Optimization,"

IEEE

Transactions on Computers, Vol. C-39, No. 7, pp. 945-951, July

1990. [2] E. G. Friedman, Clock DistributionNetworks in VLSI Circuits and System, IEEE Press, 1995.

[3] K. A. Sakallah, T. N. Mudge, and 0. A. Olukotun, "checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits," Proceedings of the IEEE/ACM Design Automation Conference, pp. 111- I 17, June 1990.

[4] T. G. Szymanski, "Computing Optimal Clock Schedules," Proceedings of the IEEE/ACM Design Automation Conference,

pp. 399-404, June 1992. [5] N. Shenoy and R. K. Brayton, "Graph Algorithms for Clock Schedule Optimization," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 132-136, November

1992. [6] R. B. Deokar and S. Sapatnekar, Approach to Clock Skew Optimization," IEEE

International Symposium

pp. 407-410, May 1994.

247

REFERENCES

on

"A Graph-theoretic Proceedings of the

Circuits and Systems,

[7] J. L. Neves and E. G. Friedman, "Design Methodology for Synthesizing Clock Distribution Networks Exploiting Non-Zero Localized Clock Skew," IEEE Transactions on VLSI Systems, Vol. VLS'[-4, No. 2, June 1996. [8] D. G. Messerschmitt, "Synchronization in Digital System Design," IEEE Journal on Selected Areas in Communications, Vol. 8, No. 6, pp. 1404-1419, October 1990. [9] J. L. Neves, Synthesis of Clock Distribution Networks for High Performance VLSI/ULSI-Based Synchronous Digital Systems, Ph.D. Dissertation, University of Rochester, December 1995. [10] D. F. Stanat and D. F. McAllister, Discrete Mathematics in Computer Science, Prentice Hall, 1977. [11] E. L. Lawler, Combinatorial Optimization: Networks and Matroids, Holt, Rinehart and Winston, 1976. [12] T. Sokurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid State Circuits, Vol. SC-25, No. 2, pp. 584-594, April 1990. [13] M. Shoji, "Elimination of Process-Dependent Clock Skew in CMOS VLSI," IEEE Journalof Solid State Circuits, Vol. SC-21, No. 5, pp. 875-880, October 1986. [14] S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0," Technical Report, Microelectronics Center of North Carolina, January 1991.

248

Multi-layer Pin Assignment for Macro Cell Circuits Le-Chin Eugene Liu and Carl Sechen Department of Electrical Engineering, Box 352500 University of Washington, Seattle, WA 98195 Abstract

N, (ncx(N), ncy(N)), is defined as follows:

We present a pin-assignment algorithm based on a new multi-layer chip-level global router. Combining pin assignment and global routing has been an important approach for the pin-assignment problem. But there are many difficulties when combining the two processes. In the past, only specialized global routing methods were used in the combined process. In our pin assignment program, we use an actual global routing algorithm. To meet the requirement of pin assignment while keeping the routing quality, we dynamically adjust the weights in the routing graph during the routing stage. In addition, the multi-layer technology has introduced new challenges for the pin-assignment problem. Our algorithm can also handle the modem technology to provide pin assignment for multi-layer layouts. To our knowledge, no other pin assignment program can handle multi-layer layout. Tests on industrial circuits show that our pin-assignment algorithm is quite effective at reducing the demand for routing resources.

m (x) ncx(N

=m(N)

N) IMa (N)I|

m (y) ny (AN)

mea

Ma (N)t

The position of a pin in net N is determined by the intersection of the periphery of m and the line which connects the center of m and the center of the net N. So the approximate pin assignment assigns a pin to some segment of the boundary of a macro. Then global routing is performed on a channel intersection graph. The global routing results are used to decide the exact position for the pin. A channel intersection graph was used in [2] to perform the global routing. The pin assignment is decided by the global routing results. The weight function of the routing graph consists of two terms. One is how crowded the pins are in a macro's boundary segment. The other is the rectilinear distance between the center of a net and the center of a channel. Both of the above algorithms rely on using the center of a net. This approach suffers from the same drawbacks which the block-by-block method has. The center of a net contains no information about blockage in the path or possible channel capacity violations. Hence, the pin assignment may cause difficulties in the actual global routing. A channel connection graph was used as the global routing graph in [4], and feed-through paths inside macros are also allowed in the algorithm. A channel graph was used in [3] to perform the routing and allowed block re-shaping. From reviewing the above algorithms, we can learn the following points. First, accurate global routing results are the basis for good pin assignment. Second, as the technologies advance, more flexibility is needed for the pin assignment. The global routing is formulated as the Special Steiner Minimum Tree (SSMT) problem in the above four algorithms. SSMT is a Steiner minimum tree of a net in which all the pins are leaves. This is because in traditional pin assignment, each macro can have only one pin for one net. Therefore, restricted Steiner tree heuristics were used for the global routing. A restricted Steiner tree heuristic usually yields worse results than the general heuristics, but the general heuristic can not guarantee that the pins are all leaves. Another problem for the above algorithms is that the routing graphs they used are not suitable for multi-layer layouts. As the VLSI technologies advance, the number of routing layers keeps increasing. The new technologies introduce many difficulties for old physical design models. To handle the multi-layer layout pin-assignment problem, we have developed an algorithm based on an effective multi-layer global router[l]. The pin assignment is closely combined with an actual global router. We use the same general Steiner tree algorithm used in the global router for pin assignment. Since a general Steiner tree heuristic does not guarantee the pins to be leaves, the results imply that we may have multiple pins assigned to a macro for a net. Although this is not acceptable in traditional pin assignment. this may actually be needed in multi-layer layouts. Because there are more routing layers, more layers are available for the routing inside macros. Having more than one pin on a macro is often a virtue for multilayer layouts. So our pin assignment program initially generates a multiple-pin assignment solution. If the internal routing resources are not available to implement the multiple-pin assignment, we

1 Introduction The macro-cell design style is one of the most important VLSI design approaches. A circuit is partitioned into a set of functional blocks (also called macro cells). Usually, the physical design process for macro cells is divided into the following steps: floorplanning/placement, pin assignment, global routing, and detailed routing. In the floorplanning/placement step, the dimensions and locations of the macro cells (macros) are determined. In the pin assignment step, the locations of pins on the macro boundaries are determined. Global routing assigns the routing regions for connecting the pins of the same net. Detail routing generates the actual geometric layout for the interconnections. In early research on the pin-assignment problem, the pins are assigned on a block by block basis[6][7][8]. To determine the pin locations for a macro, [6] used two concentric circles for the current macro to assist the assignment. A nine-case (or nine-zone) method was used to decide the pin locations in [7]. A "radar sweep" arm based on the current block was used to determine the topological pin assignment in [8]. The disadvantage of the blockby-block method is obvious. The total wire length and chip area are the two most important objectives to be optimized for the macro-cell physical design. Neither of them can be estimated accurately without carrying out the global routing step[2]. Processing the assignment block by block simply neglects too many important factors. In additional to the methods mentioned above, [9] used a physical analogy for the pin-assignment problem. But the method assumed the pins on a macro have a fixed relative order. The limitation is not practical for general applications. Since pin assignment and global routing are closely related, combining the two steps has been a necessary approach for the recent research on the pin-assignment problem[2][3][4][5]. The center of a net was used to do an approximate pin assignment in [5]. Given a net N, Ma(N) denotes the set of macros containing at least one pin connected to net N. |Ma (N) I is the size of the set, i.e. the number of macros which belong to a net. Given a macro m, m(x) and m(y) are the coordinates of the center of m. The center of a net

249

will remove the extra pins and allow only one pin on a macro for a net. We Jeveloped an algorithm to convert a multiple-pin assignment to a one-pin per macro assignment while maintaining the routing quality. The rest of the paper is organized as follows. Section 2 briefly reviews the multi-layer macro-cell global routing model which our pin assignment algorithm is based on. Section 3 describes our pin assignment algorithm. Section 4 shows experimental results on some industrial circuits. Section 5 concludes the paper.

vertical layer is available over the top. If there is one more layer available, one more layer of nodes can be added, and the edges are added accordingly. This routing structure is flexible and accurate for multi-layer technology.

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Every edge except the via edges in the routing graph is assigned a weight according to the wire length which the edge represents. Usually, the wire length is the distance between the nodes which the edge connects, i.e. the distance between the centers of two adjacent regions. For different layers, the weights can be adjusted due to the resistance difference. The weights of the via edges can be specified by the users. Usually, it reflects the equivalent resistance of a via. To route a net on the routing graph, all the pins of the net are mapped to the nodes corresponding to the layer specified and the regions where the pins reside. For the pins on the boundaries of the cells, we map them inside the cells. Then the global routing problem is formulated as finding a Steiner minimum tree on the routing graph. The definition of the Steiner tree in networks is as follows[10]: * GIVEN: An undirected network G=(YEc) where c: E -4 R is an edge length function, and a non-empty set N, N 5 V , of terminals. * FIND: A subnetwork TG(N) of G such that: there is a path between every pair of terminals, total length TG (N) = E c (e) is minimized. es TG(N)

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Figure 2. Global routing graph for the example of Fig. 1.

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2 The Multi-layer Global Routing Model Since our pin assignment program is based on our global router, it is necessary to understand our global routing model before we can introduce our pin assignment algorithm. In [1], we presented a multi-layer chip-level global router based on a 3-dimensional routing graph. The routing graph closely models the multi-layer macro-cell layout. It contains not only the topological information but also the layering and via information. Therefore, the global router can give a very accurate estimate for the routing resources needed. In addition, the global router can be used for many objective functions, such as solving the congestion problems due to the channel capacity limits, minimizing the number of vias, or minimizing the chip area. We assume that all macro cells are rectilinear. Given a placement of macro cells, the chip area is divided into small regions by cut lines which are the extension lines of the boundaries of the macro cells. Figure 1 shows how the regions are defined. The cut lines are shown as the dashed lines.

I:I -- - --- :- -

K.'

0\

adjaentnodso

Figure 1. Three macro cells and cut lines.

TG(N) is called a Steiner minimal tree of G. We developed a Steiner-tree algorithm based on a shortest path heuristic which in turn is based on Kruskal's algorithm for finding a minimum spanning tree[10]. The original algorithm can be described in three steps. First, each terminal forms a set. Second, a shortest path between any two sets is found to merge the two sets into one set. Third, if there are more than one set, go to the second step. Otherwise, the Steiner tree is found. The key difference between our algorithm and the original algorithm is that we retain multiple shortest paths between two sets. Hence, there may be cycles in the routes. A stage for removing cycles is necessary to guarantee the result to be a valid route. Also, a straightforward improvement stage is also added. Each segment in the route is ripped up and rerouted. If a better segment is found, the old segment is replaced by the new one. The test results show our algorithm outperforms other graph-based Steiner tree heuristics which can handle irregular graphs[l]. The same heuristic was used in our pin assignment algorithm. To meet some special requirements for pin assignment, we added some weight-adjusting steps into the heuristic. The details will be introduced in the next section.

In each region, we place a node for each layer. The nodes for different layers in the same region are connected by via edges. If a layer is uIsed for horizontal tracks, horizontally adjacent nodes of the layer are connected by edges. That means each node of the layer has horizontal edges connected to the nodes of the adjacent regions. Similarly, for layers used for vertical tracks, vertical edges are presented between the adjacent nodes. Furthermore, if a certain layer cannot go through the cells, there will be no edges connecting the nodes of the layer inside the cells. The only exceptions are the boundary regions inside the cells. The nodes in the regions adjacent to cell boundaries still have edges connecting to regions outside the cell. That is because the pins on the cell's boundaries are mapped inside the boundary regions. So the edges across the boundaries on a cell-blocked layer are needed for the pins to exit. But those edges are directed edges. They can only be used for the pins to exit and are not used for any other routing purposes. The directed edges make route searching on the blocked layer efficient. Figure 2 is an example of a routing graph. There are two layers. One is for horizontal and the other is for vertical routing. The horizontal layer is not available inside the cells. The

250

3 Pin Assignment Algorithm

13.

3.a Introduction To combine pin assignment and global routing, we have added some extensions to the global routing graph. For pin assignment, each pin on a macro is mapped to the center of the macro. According to this concept, we added one node for each macro. But the nodes do not necessarily represent the centers of the macros. It is just where the pins are mapped to. Those nodes are connected to the nodes in the boundary regions of the macros by directed edges.

'nose directed edges are called connection edges. Connection

edges only connect the macro nodes to the nodes of the layers which arc permitted for pin placement. Figure 2 shows the modified routing graph. The round nodes are the "macro" nodes. The connection edges are directed, because they are only used to let the pin get to the boundary regions and are not used for other routing purposes. Initially, the weights for the connection edges are all set to a minimal value (e.g. we use 1) to show that a pin can be placed on any segment of the boundary of a macro. The weights of the other edges are set the same way as for global routing. M; , lk~~~

I

1

I

~

1

M

I JIl

I--

I M '1 1 ,-ml El-4.--

14. } 15. for (each macro) 16. for (each segment of the boundaries) I 17. if (the segment is not over-congested) continue 18. Solve-pin congestion(scgment) 19.} 20. assign exact pin locations 3.b Routing for multiple-pin assignment After the stage I global routing, a minimum-weighted Steiner tree (a minimum wire length route) is generated for a net. This is the initial routing for the net. Since the Steiner-_minimum tree subroutine searches for a general Steiner minimum tree, it does not guarantee that every pin is a leaf of the tree. In the route, a macro may have more than one edge crossing its boundaries. Such a case implies that more than one pin should be placed on the macro for the net. Figure 5 shows an example. In the example, Macro-A requires one pin on the right side and one pin on the bottom side. Since we have cut lines in our routing model, we therefore know which segment of the boundary a pin should be placed on according to the route.

-

\

Steiner-Minimum tree(net) /* perform stage 3 global routing */ -

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[

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After the routing graph is constructed, we route each net on the graph sequentially. The pins of a net are mapped to the corresponding macro nodes. Then, we use the algorithm mentioned in section 2 to search for a Steiner tree connecting the terminals. During the routing, the channel congestion and chip area factor are not considered, since they are handled as a post-processing step[ 1]. IThe pin assignment algorithm is as follows: Pin-assignment()

1.buil d the routing graph (an example is in Figure 3) 2. for (each net) ( 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

l

i- -- -- t- ----

Initialize the weights of the edges Steiner-minimum-tree(net) /* perform stage I global routing */ if (no macro has more than one pin assigned) continue if (multiple-pin assignment is allowed) continue calculate the macro centers for the macros with multiple pins assigned update the weights of the edges Steiner-minimum-tree(net) /* perform stage 2 global routing */ if (no macro has more than one pin assigned) continue examine routing results and set proper direction for macros

I

- -4 - - -

Figure 5. The route of the example in Figure 4 before the cycle is removed. As we mentioned in section 2, our Steiner tree algorithm allows multiple paths in the middle of the process. Figure 5 shows the route of the example in Figure 5 before the extra path is removed. During the routing, path I-A-B-C-2 and 1-D-E-F-2 have the same weight, so both paths are used to connect pin I and pin 2. If neither path is connected in the middle as the routing progresses, one of the paths will be removed to make a valid route. Since the weight is the same, the cycle-removing step randomly removes

update the weights of the edges

25 1

one path. The route shown in Figure 5 is not the only possible result. Path 1-D-E-F-2 could be removed instead of path 1-A-B-C2. For global routing, both routes have the same wire length. But for pin assignment, the route in Figure 5 is the only optimal solution, because it reduces the internal (to the macro) routing conges-

one pin on the macro, some long wires are needed to go around the macro.

tion.

One important issue for multiple-pin assignment is that internal routing congestion needs to be considered as well. But wire length inside a macro is not a static parameter. It changes as the routing progresses. For example, in Figure 5, path 1-A-B-C-2 and 1-D-EF-2 have the same weight initially. But when path 1-G-H-I-3 is connected, their weights should be different. Hence, for each net, before the cycle-removing step. we examine the routing, and adjust the weights of some edges so that proper segments are removed. We select a comer as the basis for adjusting the weights. When pins are needed on two adjacent sides of a macro, moving pins closer to the corner where two adjacent sides meet saves the routing resources needed inside the macro. In the example, the lower right corner is chosen. The weights of the edges crossing the boundaries are incremented by an amount equal to their distance to the corner. The edge D-E is closer to the lower right corner than the edge A-B, so its weight is less than that of edge A-B during the cycle-removing step. This adjustment results in the removal of

Figure 6. Example of a multiple-pin on a macro If the multiple-pin assignment does not cause any routing congestion problems inside the macros, the initial routing is sent to the pin-congestion-solving step (line 15-19 in pin -assignment in section 3.a), then to the final stage (line 20) to assign the exact location of the pins. However, since some internal routing congestion problems may occur, we need to be able to re-route the nets which have more than one pin on some macros and cause the internal routing congestion problems. More processing is needed to convert the multiple-pin assignment to a single-pin assignment for those macros having internal routing congestion problems. 3.c Routing for single-pin assignment Before the stage 2 routing. the weights of the edges have to be adjusted according to the initial routing results. Here, we introduce the definition of "macro center." In multiple-pin assignment, a macro could have more than one pin for a net. For a net N, a macro M has a set of pins, P(N, M). IP (N, M) I is the size of the set, i.e. the number of pins of N on M. Given a pin p, p(x) and p(y) denote the coordinates of the pin. The macro center of a macro M for a net N, (mcx(NM), mcv(NM)). is defined as follows:

path 1-A-B-C-2.

For a macro with pins on three adjacent sides, there are two corners which can be chosen from. Either one of the corners can be used. For all other cases, the edge weights are not adjusted. After the initial routing is done, to make a valid pin assignment, we need to solve two more issues. First, a segment of a boundary may be over-congested because it is assigned too many pins. Second, the multiple-pin assignment could cause routing congestion problems inside the macros. To solve the first issue, a re-routing technique is used. The method is as follows: Solve.-pir-congestion(segment-of -a-boundary) 1. for (each net using the segment..of -.a-boundary) { 2. search for an alternate route for the net which avoids any over-congested boundary. 3. difference=the weight of the new route minus the weight of the initial route 4. the net is inserted into a priority queue according to difference. 5. 6. while (the segment-of -a-boundary is still over-congested) I get the minimum-difference net from the priority queue. 7. replace the initial route of the net by the new route. 8. remove the net from the list of those nets using the 9. segmentf.-.a-boundary.

10. I This method is used to solve the most over-congested boundary segment, then the second most over-congested one, and so on. It proceeds until all the over-congested boundary segments are processed. The method is not totally net-ordering independent, but it does solve some of the net-ordering problem. For the second issue, multiple pins on a macro, it is usually not a problem. In traditional pin assignment, one macro can only have one pin for one net. However, for today's multi-layer technology, there are more layers available for the internal routing inside the macros. This also means that inside the macros the routing resources may not be fully used for internal connections. Some of the routing resources may be used to provide more than one pin on the boundary for some signals. Besides, this may save the overall routing resources. Figure 6 shows an example. For a long rectangular macro, if a signal is needed on both long sides, it would consume less routing resources to have a pin on both sides. With only

252

mcx(N, M)

E p (x) pE P(N,M) IP(N,M)LI

E(N MA) mcy (NM) M) = (N,

E P(N,M) P (N,M) I

Unlike other pin assignment algorithms, our initial routing does not consider the center of a net. But during the second routing stage, we take the macro centers into consideration. (In contrast, the center of a net is calculated from the position of the macros. It is decided before the routing is performed.) The macro center is calculated from the information obtained from the initial routing. According to the initial routing, we place the pins at the middle of each corresponding boundary segment, so we can calculate the macro center for those macros with more than one pin for a net. During the second stage routing, this information is used to calculate the weight of the edges which cross the boundaries. For the initial routing, an edge's weight is the wire length between the two nodes which are connected by the edge. During the second stage, an edge which crosses the boundary of the macro by means of a macro center has its wire length calculated from the macro center to the outside node. Figure 7(a) shows how a macro center is decided. The small triangle shows the macro center. Figure 7(b) shows how the wire length is calculated to one of the possible pin locations. During the second routing stage, the macro centers help reduce the pins required on a macro. But only the macros with more than one pin in the initial routing have a macro center. The reason is that those macros with only one pin still need the flexibility (i.e. the possibility of having more than one pin for a net on a macro) during the second stage to get the best results. Since the macro center method does not guarantee to totally remove the internal

congestion, we need a third stage to further limit the number of pins on a macro for a net. I

111. I (0)

(a)

Figure 8 shows an example. Figure 8(a) is the initial routing. Figure 8(b) shows that the direction of the center macro is decided incorrectly. In Figure 8(c), the middle macro is excluded in the beginning of the routing. The route between the two outer macros is connected first. Then the middle macro joins them. Our algorithm yields the optimal result in this case. The reason why we use the three-stage approach is to allow the maximum freedom for the routing to get better results. The later the stage, the more limitations. Stage 2 uses the information obtained from the initial routing to limit the routing. Stage 3 uses the information from the results of the two previous routing results to further limit the routing. This is a time-quality trade-off. The more information we obtain, the less possibility for setting incorrect limitations.

Figure 7. Example of a macro center. For those nets which still have multiple pins on macros after the second stage, they are processed by one more stage. We use a forced-direction method in the third stage. We force the direction of the pins on some macros. The direction is decided by the following rules. For a net, those macros which have only one pin are forced to the direction of the only pin. For example, if a macro has one pin on the right side according to the second routing, the macro can only have a pin on the right side during the third routing stage. For those macros which have more than one pin, the direction is decided by the macro center calculated before the second routing stage. The side closest to the macro center is the direction for the macro. It is possible that one macro has one pin for the initial routing, but has more than one pin in the second routing. For those macros, the direction is decided by the initial routing. For some cases, the macro center does not prefer any side. For example, if a macro has two pins, one on the right side and one on the top side, and the macro center has the same distance to either side. In this case, the direction is chosen randomly from among both sides. Another case is that two pins are on opposite sides. This causes the macro center to be at the middle of both sides. For this case, it is not good to randomly choose a direction from either side. This is because when a macro has two pins on opposite sides, it usually means the signal wants to pass through the macro. Those macros are held during the third routing stage. They do not join the routing until all other macros are connected. Then they are connected to the existing route one by one. This approach guarantees single-pin assignment for the macros and usually yields better results. To efficiently implement this method, we take the advantage of the nature of our Steiner tree heuristic. Our Steiner-tree algorithm is based on a shortest path heuristic which in turn is based on Kruskal's algorithm for finding a minimum spanning tree[l0]. The shorter paths between the terminals are found first. The connection edges, which are introduced in section 3.a, connect the terminals to the routing graph. We set a large weight (we use the wire length of the initial route of the net) to the connection edges of those macros which have pins on opposite sides. The large weights naturally delay the connection to those macros. Those macros won't get connected until all other macros are connected.

F_`

(a)

(b)

3.d Example A more complicated example will be shown to demonstrate a complete three-stage routing progress.

Figure 9. Result of the first stage routing.

(c)

Figure 8. Example of reducing the number of pins on a macro with two pins which are on the opposite sides.

Figure 10. Result of the second stage routing.

253

Figure 9 shows the initial routing of a 4-pin net. This is also the multiple-pin assignment for the net. If there is an internal congestion problem, the process will proceed to the next stage. Figure 10 shows the result after the execution of the second stage routing. The number of pins on macro MAA is reduced by the macro center of MAA. The pin assignment for MDD also changes boundaries. But the number of pins on MBB is increased. This is because the assignment for MBB is not restricted, yet. According to the information from the two stages of routing, we can force the proper direction for each macro. During the final stage, the weights of the edges which cross the incorrect boundaries are increased, so the edges of the proper direction are favored. Figure 11 shows the final result. This is the result of single-pin assignment. The result is optimal for the four-pin net.

macros. We used our global routerri] to obtain the wire length and area of three pin assignments. The first one is the original assignment. The second one is the traditional single-pin assignment. The third one is the multiple-pin assignment. We have the wire length comparison results in Table 2 and Table 3. On average, the original wire length is reduced by 35% using our singlepin assignment algorithm, and by 53% using our multiple-pin assignment algorithm. Note that allowing more than one pin per net per macro reduces the total wire length by an average of 27% over allowing only a single pin per net per macro (the traditional approach). number of

cells

nets

-

hp ami33

11 33

83 83

qpdm-b Xerox

17 10

amd ami49 4832

20

intel

pins -

309

nodes of graph -

edges of graph

26

39

376

64

101

121 203

645 696

37 21

58 30

17

288

837

39

57

49

408

953

108

172

586

1,576

64

98

62 570 4,309 161 Table 1. Circuit information.

243

Original pin

Single-pin assignment

assignment

wire length (wil)

wire length (w12)

w12 / wi]

238,265

138,771

0.582

91,500

61.315

0.670

793,388 1,082,177

635,573 570,563

0.801 0.527

amd

501,507

351,236

0.700

ami49

895,149

0.588 0.746

hp ami33 Figure 11. Final result.

qpdm-b xerox

3.e Exac epin location To decide the exact locations of the pins, we divide the pin connections into four cases. Figure 12 shows the four cases. The thick line is a segment of a macro boundary. Although they are shown horizontally, the vertical boundary is treated similarly. For case (a), the pin is assigned to the leftmost available position, for case (b), the rightmost available position. For case (c) and (d), they are assigned randomly after the other cases are processed. Please notice one difference in our routing model. A routing region is not necessarily a channel. It can have one side bounded by a macro and the other side open.

4832

4,736,701

526,103 2,703,249

intel

7,948.858

5,927,195

average

0.648 Table 2. Wire length comparison. Multiple-pin assignment wire length (w13)

hp ami33 (a)

0.571

(b) Figure 12. Four cases of the pin connection. 4 Results

We tested our program on some industrial circuits. Those circuits are shown in Table 1. They already came with a pin assignment. We used our program to re-do the pin assignment. The placements were gererated by TimberWolfMC v.3.1. We used a two-layer technology, one for horizontal tracks and the other for vertical tracks. BDth layers are not available for global routing inside the

w13 I w12

78,024

0.327

0.562

33,820

0.370

0.552

qpdm-b Xerox

365,374 439,095

0.461 0.406

0.575 0.770

amd ami49

287,553 449.984

0.573 0.503

0.819 0.855

4832

2,334,710

0.493

0.864

intel

4,765,700

0.600

0.804

0.467 Table 3. Wire length comparison.

0.725

average

254

w13 I wi]

Table 4 and Table 5 show the area comparison results. Our program saves, on average, 23% of the area for the single-pin assignment and 28% for the multiple-pin assignment. Again, note that allowing multiple pins on a macro for a net yields an average area reduction of 9% over the traditional single-pin restriction. For multi-layer technologies, only a multiple-pin assignment can take the full advantage of it. To our knowledge, no other pin assignment program can handle multi-layer layout or assign multiple pins to a macro. Original pin assignment area (a])

Single-pin assignment

area (a2)

a2 / al

References Liu, L. E. and Sechen. C.. "A Multi-layer Chip-level Global Router," Fifth ACM/SIGDA Physical Design Workshop, 1996. [2] Cong, J., "Pin Assignment with Global Routing for General Cell Designs," IEEE Transactions on Computer-Aided Design, Vol. 10, No. 11, pp. 1401-1412, Nov. 1991. [3] Koide, T., Wakabayashi, S., and Yoshida, N., "An Integrated Approach to Pin Assignment and Global Routing for VLSI Building-Block Layout," European Conference on Design Automation with the European Event in ASIC Design, pp. 24-28, Feb. 1993. [4] Wang, L. Y., Lai, Y. T., and Liu, B. D., "Simultaneous Pin Assignment and Global Wiring for Custom VLSI Design," IEEE International Symposium on Circuits And Systems, Vol. 4, pp. 2128-2131, 1991. [5] Choi, S.-G., and Kyung, C.-M., "Three-step Pin Assignment Algorithm for Building Block Layout," Electronics Letters, Vol. 28, No. 20, pp. 1882-1884, Sep. 1992. [6] Koren, N. L., "Pin Assignment in Automated Printed Circuit Board Design," 9th Design Automation Workshop, pp. 72-79, June 1972. [7] Mory-Rauch, L., "Pin Assignment on a Printed Circuit Board," 15th Design Automation Conference, pp. 70-73, June 1978. [8] Brady, H. N., "An Approach to Topological Pin Assignment," IEEE Transactions on Computer-Aided Design, Vol. 3, No. 3, pp. 250-255, July 1984. [9] Yao, X., Yamada, M., and Liu, C. L., "A New Approach to the Pin Assignment Problem," 25th ACM/IEEE Design Automation Conference, pp. 566-572, June 1988. [10] Hwang, F. K., Richards, D. S., and Winter, P., "The Steiner Tree Problem," North-Holland, 1992. [1]

hp

3618 x3620

3528 x3138

0.845

ami33

1910 x 2050

1670 x 1900

0.810

qpdm..b

3933 x4877

3749 x4097

0.810

xerox

7230x 7990

6680 x 7220

0.835

amd

2379 x 2325

1827 x 1411

0.466

ami49

7572 x 7490

6992 x 6900

0.851

4832

15360x 12330

13760x 11160

0.811

intel

11710 x 12200

10320 x 11160

0.805

average

0.779 Table 4. Area comparison.

Multiple-pin assignment area (a3)

a3 a]

a3 / a2

hp

3458 x 2968

0.784

0.927

ami33

1660 x 1790

0.759

0.936

qpdmr-b

3274 x 3577

0.611

0.762

xerox

6520x 7190

0.812

0.972

amd

1694 x 1182

0.362

0.777

ami49

6982 x 6750

0.831

0.977

48'32

13630 x 11050

0.795

0.981

intel

10040x 11050

0.775

0.963

0.716

0.912

average

past, combining pin assignment and global routing means that only an inferior global routing method could be used. We overcame the difficulties and actually combined the two stages. Since our global router is capable of handling multi-layer layout, our pin assignment can also work for multi-layer technology. All the objective functions which can be performed by the global router can be performed for the pin assignment. In addition, our algorithm is the first one reported which can assign multiple pins on a macro for a net. When the internal routing resources are available, this can greatly reduce the overall routing resources needed. The test results show that our pin assignment algorithm is quite effective at reducing the demand for routing resources.

Table 5. Area comparison.

5 Conclusion We have presented a new pin assignment algorithm which is closely combined with a multi-layer global router. Near-optimal global routing results are used for the pin-assignment task. In the

255

CONSTRAINT RELAXATION IN GRAPH-BASED COMPACTION Sai-keung Dong'

Peichen Pan2

Chi- Yuan Lo3

C. L. Liu 4

'Silicon Graphics, Inc., Mountain View, CA 94043 ([email protected]) Department of Electrical and Computer Engineering, Clarkson University, Potsdam, NY 13699 3 Lucent Technologies, Murray Hill, NJ 07974 4 Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801 2

ABSTRACT Given a weighted, directed graph G with positive cycles, we study the problem of modifying the edge weights of G such that G (with new edge weights) has no positive cycles. The total change in edge weights and the length of the longest path from a "source" vertex to a "sink" vertex should be kept to a minimum. This problem arises in graph-based compaction where a constraint graph with positive cycles means that the positions of some circuit elements cannot be decided because of the existence of over-constraints. To eliminate such over-constraints, previous approaches examine positive cycles in G one at a time and apply heuristics to modify some of the edge weights. Such a local approach produces suboptimal results and takes exponential time in the worst case. We show that the problem can be solved in polynomial time by linear programming. Moreover, we show that a special case of the problem has a linear program whose dual corresponds to that of the minimum cost flow problem and hence can be solved efficiently. 1.

INTRODUCTION

A common approach to the solution of the symbolic layout compaction problem is to express the constraints on the positions of circuit elements in terms of a system of linear inequalities S; and then find a feasible solution for S that minimizes a certain linear objective function, e.g. the width of a cell [Boye88, Marp9O, BaVa92, LeTa92, YaCD93]. S may contain various types of constraints: hierarchical, pitchmatching, separation and connectivity (design rules) and user-defined constraints. Consequently, we often find that S is an over-constrained system of linear inequalities, i.e. there is no feasible solution for S. In the presence of over-constraints, a compactor can either: (i) identify some or all of the inequalities that are too restrictive and ask the circuit designer to manually modify the layout; or (ii) use some heuristics to relax some of the inequalities; so as to remove the over-constraints in S incrementally. These two strategies, however, are "local" in nature since the over-constraints are not resolved all at the same time. Both strategies have been used by different compactors, for example: * in hierarchical compaction, where over-constraints occur because of interaction among cells at the same as well as different levels of the hierarchy, a graph-theoretic technique was proposed to identify some of the inequalities that cause over-contraints. These inequalities are then recorded in a database to provide feedback for the circuit designer

256

[BaVa93]. * in leaf cell compaction, the system of linear inequalities, S, is modeled by a weighted, directed graph Gs. It is well-known that the system S has a solution if and only if the constraint graph Gg has no positive (directed) cycles [LiWo83]. In other words, over-constraints among circuit elements within the same cell appear in the form of positive cycles in Gs. In [LiWo83], for those edges with negative weights and whose corresponding inequalities cannot be satisfied, all the positive cycles that contain these edges are exhaustively enumerated. Such information is presented to the circuit designer who will decide the inequalities to be relaxed. In [King84], edges in a constraint graph are prioritized according to the kind of constraints they represent: user-defined constraints are less important than design rule constraints which are less important than abutment constraints etc. When a positive cycle is detected, the weights of those edges in the cycle with the lowest priority will be modified. In [Schi88], jog generation and edge weight modification are used to remove positive cycles. The latter selects the edge with the smallest weight in the cycle and decreases its weight by the weight of the cycle. In this paper, we focus on graph-based compaction. We consider the problem of removing over-constraints in a constraint graph. The "local" strategy of removing one positive cycle at a time which we mentioned earlier [King84, Schi88] has two drawbacks: (i) the removal of a positive cycle is carried out independent of the removal of other positive cycles. Since positive cycles might have edges in common, this might lead to "suboptimal" results and require computation that might otherwise be unnecessary. (ii) there could be an exponential number of positive cycles in a constraint graph. This limits the size of the problem that can be handled by a compactor using this strategy. A possible "global" strategy is to first find a subgraph of the constraint graph which has the most number of edges and contains no positive cycles; and then modify the weights of those edges not in the subgraph so as to remove the positive cycles. Unfortunately, finding such a largest subgraph is NP-complete (Section 3). We propose an alternative strategy and consider the Constraint Relaxation Problem: the problem on how to change the edge weights of a constraint graph minimally such that all positive cycles are removed and the length of the longest path is minimized. We show that this problem can be solved in polynomial time by the method of linear programming. In Section 2, we discuss two situations in layout compaction which motivate this work. In Section 3, we show that finding a largest subgraph that contains no positive cycles is NP-complete. In Section 4, we state the Constraint

Relaxation Problem and solve it by the method of linear programming. We give three linear programming formulations for this problem. The three formulations differ in the objectives they try to achieve. In particular, the dual linear program of the third formulation is that of a minimum cost flow problem and hence can be solved quite efficiently. Section 5 gives the experimental results and Section 6 is the conclusion. 2.

for the removal of positive cycles. Figure 2 shows two cells A and B where pin P, is to be connected to pin Qi, i = 1, 2, 3, by abutment.

MOTIVATION

One way to eliminate positive cycles in a constraint graph is to change the weights of some of its edges. We discuss two situations in layout compaction where a minimal change in edge weights is meaningful. We then give an example of a constraint graph in which different changes in the individual edge weight have different effects on the length of the longest path. This example demonstrates the difficulty in deciding how edge weights should be changed. For submicron technology with high source to drain resistance, it is important that spacings between circuit elements be tightly controlled. For example, consider Figure 1 where parts of three transistors are shown: C1, C2, C3 are contact cuts and G1 , G2 , G3 are gates. Suppose compaction is carried out in the x-direction. We are interested in min-

Figure 2. These requirements can be expressed as: Pi.r - Qi. = 0 P 2 .r - Q 2 .r= 0 P 3 .r - Q 3 .r = 0 where P,.r (Qi.r) is the 1-coordinate of pin Pi (Qi), i = 1. 2, 3. These abutment constraints together with the intracell constraints of cell A and cell B might create positive cycles in the constraint graph. In this case, it is necessary to relax some of the abutment constraints. For example, the circuit designer might decide to keep the abutment constraints between the pairs of pins (Pi,Qi) and (P 2 ,Q 2 ) but connect P3 and Q3 by river routing instead of by abutment [LiCS93]. To minimize the length of the connecting wire, it is desirable to have IP 3 . r - Q3.rl be as small as possible. This corresponds to: min a P1 .r - Qi.r = 0 P2 .X - Q2.X = 0

olysihicon

G0

G2

G3

Figure 1. imizing the x-dimension of the diffusion region. Let Gi.r and C,.r be the unknown r-coordinate of gate G, (i = 1, 2, 3) and contact C, (j = 1, 3) respectively. It is desirable that the spacing between Ci and G1 , G1 and G2 , G2 and G 3 , and G3 and C3 be as small as possible. These requirements can be expressed as: Gi.x - Cl.x = a G2.1 - Gl.r = 2a + b G 3 .r - G2. =C C3.x - G 3 .x = a where a is the minimum spacing between a contact cut and polysilicon, b is the minimum width of a contact cut, and c is the minimum spacing between polysilicon and polysilicon, respectively. These four equations (or eight inequalities), together with other compaction constraints, might form an over-constrained system of inequalities. In this case, some of these inequality constraints need to be relaxed and be satisfied as strict inequality constraints. Since we want to minimize the "stretching" of the diffusion region, the problem becomes that of: min ca+ + + a Gi xr- C x = a G 2 .r - Gi.x = ,

P 3 .r - Q3.r < a Q3. - P3.X < a

A minimum adjustment in edge weights will minimize the length of the connecting wire used in river routing. The two situations above show the need for an algorithm that can remove positive cycles from a constraint graph with as little change to the edge weights as possible. However, deciding the set of edges and by how much their weights should be changed is a non-trivial problem. Consider the constraint graph G shown in Figure 3 where

Figure 3. G the edge weights are shown next to the edges. G has a positive cycle

V2 -4 V3 -+

V4

-+

V5

-*

V 2.

To remove this cycle,

the minimum amount of change in edge weights is 4, the weight of the cycle. In the mean time, we want to minimize the length of the longest path from vi to V6. Of course, one could choose to change the edge weights by a large amount. In Figure 4, the total amount of change in edge weights is 7; and the length of the longest path from v1 to v6 is 0 (edges on the longest path are shown in bold arrows). Figure 5 gives four different ways to remove the positive cycle in G. They all introduce the same total amount of change in edge weights, namely 4, but with different effects on the length of

G3.r - G 2 .r = -y C3.x - G 3 .r = a 2a+b and y > c. A minimum adjustment

where a > a, 3 > in edge weights in the constraint graph will correspond to a minimum increase in the r-dimension of the diffusion region. Cell compaction with abutment constraints is another situation in which a change in edge weights may be necessary

257

such that G'(V, E', w'), where w' is w restricted to E', has no positive cycles ? 1'

We shall show that the Largest Feasible Subgraph problem is NP-complete by reduction from the Feedback Arc Set problem. The latter is defined as:

I

_

I

FEEDBACK ARC SET [GaJo79, p. 192] INSTANCE: Directed graph H = (V, A), positive integer K < JAI.

Figure 4. the longest path from v 1 to Ve, l(vi, v.), and on the lengths of the longest paths between other pairs of vertices.

0

Theorem 1 LARGEST FEASIBLE SUBGRAPH is NPcomplete.

0

Proof By reduction from FEEDBACK ARC SET. Given an instance H = (V, A) and integer K, of FEEDBACK ARC SET, consider the instance of LARGEST FEASIBLE SUBGRAPH G = (V,A,w) where w, = 1 for every edge (vi,v3 ) E A and M = IAI - K. Then H has a subset of edges with size at most K and constains at least one edge from every directed cycle in H if and only if G has a subgraph with at least M edges and which does not have any positive cycles. 0

(b) I (v ,v6) = 2

(a) I (vlv6) = 3

0

QUESTION: Is there a subset A' C A with IA'I < K such that A' contains at least one edge from every directed cycle in H ?

Corollary 1.1 Given a system S of linear inequalities, the problem of finding a largest (in terms of the number of inequalities) consistent subset of S is NP-complete.

I

(c) 1(vl~v6)

-

(d) I (v1,v6) = I

1

Figure 5. .3.

Proof By reduction from LARGEST FEASIBLE SUBGRAPH. D

A'P-COMPLETENESS RESULTS

In this section, we show that given a constraint graph, the problem of finding a largest subgraph which has the

4.

PROBLEM STATEMENT AND SOLUTIONS Since finding a largest subgraph that has no positive cycles is NP-complete, we propose an alternative approach for removing over-constraints in graph-based compaction. Instead of minimizing the number of edges whose weights will be changed, the alternative approach tries to minimize the total amount of change in edge weights used in the removal of positive cycles. We define the Constraint Relaxation Problem as follows: given a constraint graph G = (V, E, w) with positive cycles, modify the edge weights of G such that all positive cycles are removed, the change in edge weights is minimal and the length of the longest path from vi to v. is minimized. We shall give three linear programming formulations for the Constraint Relaxation Problem. The first formulation requires the solution of a sequence of two linear programs (LPs) (Section 4.1). We then argue that some of the generality in the first formulation is not necessary and derive a formulation that can be solved by a single LP (Section 4.2). Finally, we consider a special case of the second formulation and show that its dual corresponds to that of a minimum cost flow problem and hence can be solved efficiently (Section 4.3).

most number of edges and contains no positive cycles is NP-complete. Thus, it is not likely that the approach of retaining the largest number of edges intact and modifying the weights of the remaining edges will lead to an efficient algorithm for the removal of over-constraints. The NP-completeness result can be extended to the problem of finding a largest consistent1 subset of inequalities in a given system of inequalities. This shows that in the case where a system of general linear inequalities is used, e.g. hierarchical compaction, finding a largest subset of inequalities that are not Dver-constrained is a difficult problem. Let C = (V, E, w) be a constraint graph where V =

{v,

..., vt,} is the set of vertices, E is the set of (directed)

edges and w : E -e R is the edge weight function, respectively. WVe shall adopt the convention that v, and v, represent the left and the right cell boundary, respectively (assuming the direction of compaction is along the x-axis) and that wi, denotes the weight of edge (vi, v,). We define the Largest Feasible Subgraph problem as follows: LARGEST FEASIBLE SUBGRAPH INSTANCE: Constraint graph G = (V, E, w), positive integer M < JEl.

4.1.

First Formulation For a given constraint graph G = (V, E, w), its corresponding LP is [PaDL93]: min X, - XI X -xi > Wij, (vi, vj) E E

QUESTION: Is there a subset E' C E with IE'l > M 1A consistent set of linear inequalities is one in which the solution set it defines is non-empty.

258

where variable xi is the unknown x-coordinate of vertex vi E V. In the presence of positive cycles, some the edge weights in the constraint graph need to be modified. For each edge (vi, v 1) of weight wi,, a variable ei, is introduced and the new edge weight will be wtj + eij, where li, < ei, < u,1 . li, and ui, are constants given by the circuit designer to limit the amount of change in the weight of edge (vi, v,). For example, if ui) < 0, it means that the weight of edge (vi, v 1 ) may decrease but cannot increase. If an edge weight wi, should not be changed because it corresponds to some important compaction constraint, one can set lij == uij = 0. (In this case, a simpler way is not to create the variable ei, for this particular edge at all.)

A = min lj - Ii-

( ivj)eE

1

-

, -E ij > EiŽ7 > -ei, >

Wij, 1

1i, -uij,

>

-Uij,

Xj -5 xi-

Ei+

+

- 4

E(vivj) EE

E E

min A

a new lower bound -J and a new upper bound p-. The '1 ' new lower and upper bounds are defined as:

j-

p+ = max{0, uij} M7 = max{O, -lij}.

(eij3

+Ei _)

=

Case 3 li < 0 and 0 < uj. 0 = A+i -+r < +

-7- >

The validity of these new lower and upper bounds can be seen by analyzing the following three cases (assuming lij < Uj):

0 =A,-j < Eij


(vi, vj)

(vi, V2 )

-Pii ,

Ei-j >

EF

A

A\+= max{O,

A+l,(vi,v

>

min

(Vi, Vj) E E (vi, vi) e E

(Vi V3)

WijI

>

P1'

If P1 has a solution, the mathematical program P2 below will determine the minimum longest path length from vl to vn and how much the weight of each edge should be changed subject to the condition that the total change in edge weights is A. min XI - xi j- xi - ei, > Wij, (vi, v1) E E eij > lij (vi, v 1 ) e E -ij,

>

- >

P1

)-(v,,vj)EE Jeij

E

-EiŽ

lEji

(Vi,,vj)

+

Cy

To determine, A, the minimum amount of change in edge weights that is necessary to remove all positive cycles, consider the following mathematical program P1:

A = min

(E% + Ci)

Z(vi,vj)EE

e+

0.-j=

=-li l

~==-i.

P1 and P2 can now be formulated as two bona fide linear programs:

259

4.3. Third Formulation In this section, we show that a special case of P3 has a dual LP that corresponds to that of a minimum cost flow problem. The minimum cost flow problem [Tarj83] is a network flow problem in which there is a cost ci, associated with an edge (vi, vj) in the network and such that a unit of flow along that edge will have a cost of ci,. The objective is to obtain a flow of a pre-specified quantity from

some supply vertices to some demand vertices that has the minimum total cost. The minimum cost flow problem can be solved in low order polynomial time and it has been used in the solution of other problems. For example, the problem of determining the minimum number of delay elements inserted into a pipelined system for achieving synchronization has been formulated as a linear program whose dual corresponds to that of a minimum cost flow problem [WoDF89, HuHB91, BoHS92]. We consider the case when the constraints -e > li, ,j (vi, va) e E, are absent from P3. In other words, the linear program looks like: min A (e,) + B(x,- xi) 3 dual

variables YJ

xJ - Xi + c- > e-3>

2ij

,,j)EE v

0.9 3

CQ0

-0.2

03

-0.6

0 -0.2

C

-0.5 allow the weights of edges (Cl,GC) , (G 3 , C3) , (G,

CO) ,(G2, GI) , (G3 , G1 ) and (C3 , G3 ) be changed and we re-

quire that the distance between contact Cl and gate GI is the same as that between gate G3 and contact C3 . By introducing the e's required by our first formulation, we obtain a new constraint graph G' (Figure 7). 0.9 02+

02 +rc

50.3

(W'JY'1 + (-u'J)z,3 )

T(.""OEE ypi-

Yiq i)EE=

0

(1pss')eE Ypl

=

B

(v~p,')E YPn

T(vq)EE Ynq = Yij + zij =

B A

Yu3 >

0 0

Ziu >

for for for for

xi, i 0 1, n so In

-

E3

Figure 7. G'

A = min

In D4, the variables yi 's and zi,'s are related by the equations y,, + zi, = A. By substituting zt, = A - yij into the objective function of D4; and replacing the equation yi, + zij = A by the inequality yi, < A (since zij is nonnegative), we can eliminate, for each (vi, vi) e E, the variable Zi, from D4. The resultant LP is D4' shown below: (.i,.)EE ((wij + uij) yi

-0.5-

The corresponding LPs are:

E.,,

D4

max

EXPERIMENTAL RESULTS

Figure 6. G

From P4, the new weight of an edge satisfies Wj - 6- < wij + uJ, i.e. the new edge weight, wi,-ei, has an upper bound but not a lower bound. The difference between P3 and P4 is that the latter does not have control on how small the weight of an edge will become. Consider D4, the dual LP [PaSt82] of P4 (the dual variables Ytj and Zi, used in D4 are shown in P4 next to the inequalities to which they correspond):

Z

5.

We first give an example similar to the one shown in Figure 1 and its solution produced by our first formulation. Consider the following constraint graph G (Figure 6) which contains more than one positive cycles: Suppose we only

(vi,v1 ) E E (vi,vj) E E

wi, -uij,

P4

max

inequalities specify that the flow on each edge must be no more than A and non-negative, respectively.

A uij)

2E1 + 62 + 63

Gi.x - C1 .x - ei > 0.2 Ci.x - Gli. + el > -0.2 G 2 .X - Gi.x G 3 .r - G 2 .r G2.x - C 1 .r

C3 .x - G3.x - El G3.r - C2.x + El G0.x - G2.r + 62 Gi.x - G 3 .r + e3 31, 62, 63

> 0.5 > 0.3 > 0.9 > 0.2 > -0.2 > -0.6 > -0.5 > 0

Q1 (,Vq)CE (vp, E~v,

)eE Ypl n~iEYpn_

Z(vl,vq)EE

yiq =

Ylq = Z(wnVq)EE Ynq= -yi, > yi, >

0 for pi, i 0 1, n min C 3 .x - C 1 .x

-B for xi B for In -A for e0

D4' In D4', the second term in the objective function - E A uij can be dropped since it is a constant. Since maximizing a linear function f is the same as minimizing -f, D4' is a minimum cost flow problem where the cost of each edge is -(wij -- ui,) and the flow on each edge is the unknown yi,. The first equation in D4' is the flow conservation constraint for vertices v2, ... ,v_: the second and the third equations specify that the outgoing flow at v1 is B and the incoming flow at vn is B, respectively; and the fourth and the fifth

260

G.x - C 1 .x - E C,.r - G,.x + El G2 - Gi.r

> 0.2 > -0.2 > 0.5

G3.x - G2

>

X

G2.x - C 1 .r C 3 .x - G 3 .x -G3.x - C3 .x + el G.x - G2.x + e2 G,.x - G3.- + e3 2E,

+ 62 + 63

61,E2,

3

0.3

> 0.9 > 0.2 > -0.2 > -0.6 > -0.5 = A > 0

Q2 Solving the linear program Ql, we obtain an optimal solution with El = 0.1, 32 = 0 and E3 = 0.4 which minimizes A

(= 0.6). In this case, the length of the longest path from C, to C'3 is 1.5. If we set A = 0.6 and solve the linear program Q2, we obtain el = 0, 62 = 0.1 and 63 = 0.5. In

[BoHS92]

E. Boros, P. L. Hammer and R. Shamir, "A Polynomial Algorithm for Balancing Acyclic Data Flow Graphs," IEEE Transactions on Computers, Vol. 41, No. 11, pp. 1380-1385, Nov. 1992. [Boye88] D. G. Boyer, "Symbolic Layout Compaction Review," Proceedings of 25th Design Automation Conference, pp. 383-389, June 1988. [GaJo79] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP- Completeness, Freeman and Company, New York, 1979. [HuHB91] X. Hu, R. G. Harber and S. C. Bass, "Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems," Proceedings of 28th Design Automation Conference, pp. 758763, June 1991. [King84] C. Kingsley, "A Hierarchical, Error-Tolerant Compactor," Proceedings of 2lth Design Automation Conference, pp. 126-132, June 1984. [LeTa92] J. F. Lee and D. T. Tang, "HIMALAYAS - A Hierarchical Compaction System with a Minimized Constraint Set," Digest of Technical Papers, International Conference on ComputerAided Design, pp. 150-157, Nov. 1992. [LiCS93] A. Lim, S. W. Cheng and S. Sahni, "Optimal Joining of Compacted Cells," IEEE Transactions on Computers, Vol. 42, No. 5, pp. 597-607, May 1993. [LiWo83] Y. Z. Liao and C. K. Wong, "An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints," IEEE Transactionson CAD, Vol. CAD-2, No. 2, pp. 62-69, April 1983. [Marp90] D. Marple, "A Hierarchy Preserving Hierarchical Compactor," Proceedings of 27th Design Automation Conference, pp. 375-381, June 1990. [PaDL93] P. Pan, S. K. Dong and C. L. Liu, "Optimal Graph Constraint Reduction for Symbolic Layout Compaction," Proceedings of 30th Design Automation Conference, pp. 401-406, June 1993. [PaSt82] C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity, Prentice-Hall, N.J., 1982. [Schi88] W. L. Schiele, "Compaction with Incremental Over-Constraint Resolution," Proceedings of 25th Design Automation Conference, pp. 390395, June 1988. [Tarj83] R. E. Tarian, Data Structures and Network Algorithms, Society for Industrial and Applied Mathematics, Philadelphia, Pennsylvania, 1983. [WoDF89] D. Wong, G. De Micheli and M. Flynn, "Inserting Active Delay Elements to Achieve Wave Pipelining," Digest of Technical Papers, International Conference on Computer-Aided Design, pp. 270-273, Nov. 1989. [YaCD93] S. Z. Yao, C. K. Cheng, D. Dutt, S. Nahar and C. Y. Lo, "Cell-based Hierarchical Pitchmatching Compaction Using Minimal LP," Proceedings of 30th Design Automation Conference, pp. 395-400, June 1993.

this solution, the total amount of change in edge weights remains unchanged, namely, 0.6. However, the length of the longest path from C, to C3 becomes 1.4 which is the shortest possible given that A = 0.6. To demonstrate the quality of the solutions produced by our linear programming formulations, we apply the second formulation on four test examples. Each example is a constraint graph with some positive cycles. The number of vertices and the number of edges in each constraint graph are listed in Table 1. We compare our approach with a heuristic. The heuristic examines each positive cycle in a constraint graph one by one and decreases the smallest edge weight in the cycle by the weight of the cycle. In Table 2, AH and ALP is the total amount of change in edge weights introduced by the heuristic and by LP, respectively; 1H and ILP is the length of the longest path from a1 to v. achieved by the heuristic and LP, respectively. From the four test examples, we see that there is more than 40% difference in the amount of change in edge weights and more than 30% difference in the length of the longest path from v, to vn between the two approaches. This shows that our linear programming formulations indeed produce very good results. Example lE| 7V 1 6r 7 - 2 10 12 3 20 24 4 32 45 Table 1 LFaLP - AH ALP AH ILP . . 6 4 4 -43% -56% 8 6 10 26 16 16 -47%c .-4. 64% 13 30

1

Heuristic £ xamp1e I

-

-

I

2

1

3 -

- -1

4

T

AH

7 18 30

84

'H

- -

LP -

1H

3H

-33%o -4-

-40% -38% -46%

Table 2 6.

CONCLUSION

We study the problem of removing positive cycles in a constraint graph by modification of edge weights. Previous attempts to solve this problem examine the positive cycles one at a time and use heuristics to determine which edge weight to be modified. We show that the problem can be solved in polynomial time by the method of linear programming. We give three linear program formulations for the problem. In particular, the third formulation has a dual whose linear program is that of a minimum cost flow problem and hence can be solved efficiently. REFERENCES [BaVa92]

C. S. Bamji and R. Varadarajan, "Hierarchical Pitchmatching Compaction Using Minimum Design," Proceedings of 29th Design Automation Conference, pp. 311-317, June 1992.

[BaVa93]

C. S. Bamji and R. Varadarajan, "MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction," Proceedings of 30th Design Automation Conference, pp. 389-394,

June 1993.

261

An 0(n) Algorithm for Transistor Stacking with Performance Constraints Bulent Basaran and Rob A. Rutenbar Department of Electrical and Computer Engineering Carnegie Mellon University, Pittsburgh, PA 15213, USA {basaran,rutenbar} @ece.cmu.edu Abstract

results on industry-quality circuits are given in Section 4. Finally, Section 5 offers some concluding remarks.

We describe a new constraint-driven stacking algorithm for diffusion area minimization of CMOS circuits. It employs an Eulerian trail finding algorithm that can satisfy analog-specific performance constraints. Our technique is superior to other published approaches both in terms of its time complexity and in the optimality of the stacks it produces. For a circuit with n transistors, the time complexity is O(n). All performance constraints are satisfied and, for a certain class of circuits, optimum stacking is guaranteed.

2 Basic stacking strategy A stacking methodology is needed to model the circuit schematic in a format appropriate for a graph algorithm to solve the layout problem effectively. Our strategy is similar to that introduced in [6] and earlier in [4] in more general terms: I . Divide the circuit into partitionswith respect to device type and bias node (body node in MOS transistors).

1 Introduction

2. Perform device folding: split large transistors into smaller parallel transistors. These are called "fingers" by designers; we refer to these more generally as modules as they are the component pieces of our solution. -

In the layout of custom CMOS cells, stacking is defined as merging the diffusion regions of two or more transistors that have a common node, e.g., series-connected transistors have one node in common which can share a diffusion and save area. Since stacking has a dramatic impact on the total diffusion area and therefore on chip yield, there has been an extensive amount of research on optimizing leafcell layout through stacking. The original work of Uehara and van Cleemput [1] first posed the problem and offered a heuristic solution for digital circuits. For this important two-row P-over-N layout style, polynomial time algorithms were later discovered to arrange series-parallel dual CMOS ([2] is a good survey here). When more general aspects of the layout are to be optimized, e.g., wiring as well as stacking, a variety of combinatorial search algorithms have been used with success, e.g., [3]. In the analog domain, stacking is critical not only for area, but also for circuit performance due to parasitic diffusion capacitances. Unfortunately, the wider range of device sizes, and requirements for device matching and symmetry render the simpler row-based digital layout styles inadequate for analog. To address this, Cohn et al. introduced a free form 2-D stacking strategy integrated with device placement [4]. Charbon et al. later introduced a technique to satisfy performance constraints through constraint-driven stacking during placement [5]. Both tools can generate high-quality layouts, however., neither can guarantee a minimum diffusion area. More recently, [6] introduced a new stacking style and a novel technique to generate optimum stacks that satisfy performance constraints, using a path partitioning algorithm. However, because it attempts to enumerate all optimal stacks, runtime can be extremely sensitive to the size of the problem. Symmetry and matching constraints can greatly prune the search, but the basic algorithm has exponential time complexity [6]. In this paper, we present a new algorithm to perform stack generation in linear time. For a large class of circuits, our algorithm is optimum with respect to total diffusion area and a cost function modeling circuit performance. The cost function ensures that performance constraints are, if possible, met. Device matching is also guaranteed through symmetry and proximity constraints. The paper is organized as follows. Section 2 describes the basic stacking strategy. Section 3 explains how the circuit performance is modeled. In Section 4, the new stack generation algorithm is presented. Some

3. Perform further partitioning to reduce the variation on the module widths in a partition, 4.

Generate stacks that implement each partition. In analog CMOS circuits, as in digital standard-library leafcells, only transistors of the same type (e.g., NMOS), which share a common well, can be stacked (i.e., their common diffusion nodes can be merged in the layout to minimize diffusion area). In addition in analog circuits, it is fairly common to have transistors of the same type which require distinct body potentials, for example, to optimize noise performance. Such transistors have their own isolated wells and cannot be stacked with other transistors of the same type. Therefore in the first step, we put such transistors in different partitions. We also allow the designer to specify explicitly to have two or more transistors in the same stack. In the second step, large transistors are folded into fingers to minimize the diffusion capacitances as well as to balance the aspect ratio of the resulting module. This can either be done automatically [6] or manually by the designer. It is important to note that, in this stacking strategy, transistor folding is done a priori.The stack generation algorithm is given fixed-width modules as input - it does not dynamically fold transistors. This is in contrast to tools such as KOAN [4], in which the overall optimization loop treats stacking, folding and placement simultaneously. Of course, such a separation of design tasks is sub-optimal. One of our main motivations in this paper is to devise a stacking strategy that is fast enough to be used in the inner loop of a placement tool like KOAN. In the third step, the partitions are examined again to account for variations in module widths. If it is requested, modules with widths significantly larger, or smaller, than others in a partition can be put in a separate partition. This will result in a better utilization of space, but it will have suboptimal diffusion sharing. If such a partitioning is not acceptable for performance reasons, this step may be skipped. In the fourth step, the stack generation algorithm (Section 4) operates on each circuit partition separately. We note that a pair of phases before and after the stacking algorithm may handle special

262

patterns required by some analog circuits: module interleaving (i.e., common-centroid or inter-digitated device pairs); devices with ratio constraints to obtain precise current ratios (e.g., current mirrors) [6]; multi-fingered devices with proximity constraints [7].

During stack generation, it is required that certain performance specifications are considered and, if possible, met. The input to the stack generation algorithm (Section 4) is a cost function based on criticalityweights on circuit nodes and symmetry constraintson the devices. In this section, we will briefly review how these parameters are obtained from performance specifications. Our approach follows [8] and [9]. The process of translating high-level circuit performance specifications into bounds on low-level layout parameters is called constraint generation. This process is traditionally done manually by circuit designers. Recently, techniques have been proposed to automate this process using sensitivity analysis [8]. Constraint generation starts with small signal sensitivity analysis of performance functions at the nominal operating point. Performance constraints are defined as maximum allowed variations of the performance functions around the nominal operating point. These constraints can be mapped to parasitic capacitance constraintson certain nodes and matching constraintson devices. The parasitic capacitance constraints, together with bounds on estimated parasitic capacitances, can further be translated into criticality weights, denoted w, on nodes. The tighter the constraints, the closer the minimum allowed performance to the estimated nominal value, the higher the weights. A cost function evaluating a stacking solution is introduced in [6] that minimizes the parasitic capacitance of critical nodes. We will use the same cost function to guide our stack generation algorithm. It is shown in Eq. (I) for the sake of completeness. Cost (stacking) =

w (diff) .k (diff)

(1)

diff

Here, the summation is carried over all diffusion regions in the stacks. w(dif]) denotes the criticality weight on the node that corresponds to diff k(diff) is I if diffis a merged diffusion in the stacking. Otherwise it is given by Ce,/Cit where Cest and Cint (Cext >in are the capacitances of an unmerged (external) and a merged (internal) diffusion, respectively. Note that when w is 1, the cost function minimizes only the total diffusion area. w is an effective way of prioritizing critical nodes during stacking. Matching constraints are translated into symmetry constraints on devices and wiring and also to device proximity constraints. In order to match devices, our stack generation algorithm employs symmetry constraints on the devices of the circuit. The stacks obtained with a stack generation algorithm should be symmetric around a symmetry axis with respect to the twin transistors in them (Fig. 1) [ 14]. Further matching can be enforced earlier in the partitioning step of our stacking strategy as in [6] as well as later during placement and routing [4][15]. The next section describes in detail how the cost function in Eq. (I) is optimized and how the symmetry constraints are satisfied in the stack generation algorithm.

M4 M2

IM1

M.m

(b)

A

3 Modeling performance constraints

M1 M3

M

M

d

M3--

Ml M3

>1-4r' (a)

M2 M4

, (C)

.

I

i

01

Fig. 1. Two symmetric transistor pairs (a) and their layout with symmetric stacks. Stacks in (b) and (c) are mirror symmetric and perfect symmetric, respectively.

4 Stack generation algorithm As introduced in [1], finding an Eulerian trail in a diffusion graph is equivalent to minimizing the diffusion area of series-parallel static CMOS circuits. Later [10] presented a simple linear time Eulerian trail finding algorithm for dynamic CMOS circuits consisting of only one type of network (e.g., an nFET logic network). In our algorithm, we use a similar algorithm for finding an Eulerian trail. The main contributions of this algorithm are twofold: 1. Performance: We optimize.a cost function that considers not only area but also circuit performance - this was previously achieved in exponential time [6], 2. Generality: Without any symmetry constraints, the algorithm is optimum. With symmetry constraints, it is still optimum for a large class of circuits. Given a circuit partition, our algorithm first generates a modified diffusion graph, G, that represents the circuit partition. G incorporates the performance constraints in the form of criticality weights as defined in Section 3, as well as the symmetry constraints among transistors. Next a trail cover on G is found that satisfies the symmetry constraints in the circuit. In the final step each trail in the trail cover is converted to a transistor stack for layout. The outline of our algorithm is given in Fig. 2. procedure stack(circuit-partition ckt) I generate the modified diffusion graph, G, from ckt 2 trail-cover = sym-trail-cover(G) 3 convert trail-coverinto transistor stacks 4 return(transistor stacks) Fig. 2.

The stack generation algorithm.

Next we describe the modified diffusion graph and the symmetric trail cover finding step in detail and give an analysis of the algorithm.

A

The modified diffusion graph, G

Let ckt be the circuit partition for which we wish to generate the transistor stacks. ckt can be represented with an undirected graph G'(possibly with parallel edges) called the simple diffusion graph. Each vertex in G 'corresponds to a diffusion node in the circuit, and each edge in G'corresponds to a transistor (Fig. 3). Let v be a vertex in G': v is labeled with w(v) and s(v). w(v) denotes the criticality weight on the node that corresponds to vertex v. s(v) denotes the symmetric twin of v. Let e be an edge in G'; e is labeled with s(e) = e ', where (e, e ) is a symmetric edge pair. s(e)=e ' > s(e )=e. Note that a diffusion graph with symmetry constraints

263

must be fully symmetric: all the edges must have symmetric twins. Otherwise, the circuit must be partitioned further so that each partition is fully symmetric (Fig. 4 (a)). A vertex is called self-symmetric, if s(,) = v. A self symmetric vertex is on the symmetry axis which curs the graph into two halves (vertex v7 in Fig. 4 (a)). A pair of symmetric edges are called cross-symmetric, if they cross the symmetry axis.

an trail on it. The degree of a vertex v, denoted d(v), is the number of edges adjacent to it. It is well known in graph theory that a graph is Eulerian if and only if it is connected and all vertices in the graph have even degree [13]. Obviously in an Eulerian graph we can always find a trail cover of cardinality 1, since there is an Eulerian trail on it. It is also easy to see that in a graph that has nodd vertices with odd degree, the minimum trail cover has a cardinality of n,,dd/ 2 (It is known that ndd is always even). Note that in general the simple diffusion graph G 'is not Eulerian. Let nodd denote the number of vertices with odd degree in G'. If ndd > 0, we add a vertex, called a super-vertex, vs, to G ' and we make it Eulerian by adding a new edge (v, vi), called a super-edge, for each odd-degreed vi. We set w(v1 ) to 0, since its criticality, by definition, is zero. The graph obtained from the simple diffusion graph, G-, by the addition of (1) the super-vertex and (2) the superedges is called the modified diffusion graph and is denoted as G (Fig. 4 (b)).

v1

e3

e2

e4 v4

B Finding a symmetric trail cover If there are no symmetry constraints, we can find an Eulerian trail, te, in G, using a recursive Eulerian trail finding algorithm [13]. Let te be (vS,v],v 2 ,. ,vk,v,). If we delete the super-edges in te, we obtain a set of trails, Te, that has a cardinality of n~ddI2 . Therefore, T, is a minimum trail cover for G, the simple diffusion graph. However, when there are symmetry constraints, an arbitrary Eulerian trail, in general, does not yield a feasible solution. Here, we propose an algorithm which can be used to find a minimum trail cover in the presence of symmetry constraints. Our symmetric trail cover algorithm employs the same recursive algorithm for finding an Eulerian trail with modifications to handle perfect and mirror symmetry constraints. The outline of the algorithm is given in Fig. 5. The algorithm symntrail cover () starts by selecting the vertex, v0, with the lowest criticality weight. Next it finds a set of trails, cover-left, in Line 2 with the call to the recursive procedure eul.er() (Fig. 6). Here we note that the first trail euler() generates, first-trail, has v0 at its end terminal; more on this in Section C. The trail cover, coverIleft, includingfirsttrail, covers only half of the edges in the modified diffusion graph, since at each iteration of Line 10 in euler() we not only delete the edge that is inserted in the trail but also its symmetric twin.

e5 vS

Fig. 3. A circuit partition and its simple diffusion graph. Each node in the circuit, n, is mapped to a vertex v in the graph; each device, d, is mapped to an edge e. First we introduce some terminology from graph theory that will be used in the following sections. A trail on a graph is a set of edges (v 0 ,e 0 ,vj,e1,v 2 . - Vk-l, ek.1,vk), where ei=(v,,vi+1) is an edge in the graph and eidej for all iwj [12]. We may use the shorthand (vO,vl,v 2 ,. V.,vk)or (e0 ,e1 ,e2 ,...,ek-4) to denote a trail. Note that an edge in a trail can not appear more than once but a vertex can appear at more than one position. Each such position is called a terminal of the vertex. vk and v0 are called the end terminals of the trail. The trail is a closed trail, if Vk=VO.

el

v'5

Ie6 v

e3

e2

procedure symjtrail-cover(G) I pick v0 s.t. w(v 0 ) • w(vi) for all i#0 2 first-trail=euler(vo) / inserts open trails in cover-left

e4 v5

v6

K

Vs (a)

(b)

Fig. 4. (a) A simple diffusion graph with symmetry constraints. Note that pairs of edges with symmetry constraints are drawn symmetrically around the vertical symmetry axis. (b) The modified diffusion graph obtained from (a). Gray lines are the super-edges. A set of trails, T=Iti}, on G is called a coverfor G,if Ve e G, 3ti st. e E ti and e X tI , Vj * i . Tis called a minimum trailcover if the number of the trails in T, or the cardinality of T, IT1 , is the smallest among all possible set of trails. For example, for the graph of Fig. 4 i'a), two trails (vleJ,v3,e5,v7) and (v5,e3,v3) together with their symmetric twins (v2,e2,v4,e6,v7) and (v6,e4,v4) cover the whole graph. Let T1 denote the set of these trails. Note that ITIT= 4. Joining the first and the third trails at v7, their common end terminal, we can reduce the cardinality of T1 to 3 which is the minimum for this graph. A closed trail is an Eulerian trail, if it touches all the edges in the graph. A graph is called Eulerian if there exists a closed Euleri-

3

insertfirst-trail in cover-left

4 5 6 7 8 9 10 11 12 13 14 15

remove the super-edges at the end terminals join-trails(cover -left) if there are symmetry constraints foreach trail tr in cover -left construct the symmetric trail tr' if tr and tr'have a common end terminal join tr and tr' at the common end terminal insert the result into cover-all else insert tr and tr' into cover-all decompose all the trails by deleting the super-edges

Fig. 5.

return(cover-all)

Finding a symmetric trail cover.

In Line 5 of syrn.trail-cover (, the procedure join-trailso) concatenates the open trails in cover.-.left at their end terminals if possible (Fig. 7). This step is required due to the existence of cross-symmetric edges in the modified diffusion graph.

264

recursive procedure euler(vertex vin) I if d(vin) = 0 // no edges 2 return vin 1 trivial trail 3 /,' starting from vin create a random trail tr: 4 vtemp = vin 5 do 6 if d(vtemp) = 0; 7 break; // open trail 8 insert vtemp into tr 9 pick an edge on vtemp, e=(vtemp, vneigh) 10 delete e, s(e), if exists, from G 11 vtemp = vneigh; 12 while vtemp # vin /1iterate until a closed trail is found 13 let tr = (vin,vJ,v2,...vk) 14 find tr2 = euler(vin),euler(vl),euler(v2),...,euler(vk) 15 if vtemp = vin 11 closed trail 16 return concatenation of tr2 and vin: (tr2, vin) 17 e]lse / open trail 18 insert tr2 into tcover 19 return vin Fig. 6.

(a) v5

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v5

v3

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v6

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Fig. 8. (a) Perfect and (b) mirror symmetric trail covers; T7=((v5,v3,v7), (v6,v4,v7), (vl,v3), (v2,v4)], Th=[(v5,v3,v7,v4,v6), (vl,v3), (v4,v2)1 and the corresponding stacks for the graph of Fig. 4 (a). C Analysis of the algorithm Time-complexity: The do-while loop in Line 5-Line 12 of euler () encounters each edge of the graph at most once, therefore it has complexity 0(n), where n denotes the number of edges. The two foreachloops in join-trails () operate on each trail only for a constant number of steps. Hence the complexity is 0(m), where m denotes the number of trails. But since m = 0(n), the complexity of join-trails () is 0(n). It follows that the overall complexity of the algorithm is 0(n). Optimality: If there are no symmetry constraints, it is easy to see that the algorithm minimizes the cost function defined in Eq. (1): euler() returns an Eulerian trail which is laterdecomposed by deleting the super-edges (if any). Let us assume that the trail cover has k trails after the decomposition; k = max II, n,, /2} . Also note that every vertex v in G must have at least Fd(v)/2f1 terminals in a trail cover T. First assume nodd>> 0. If d(v) is odd, then v has d(v)/2 + I terminals in the trail cover. Otherwise it has d(v)/2 terminals. In either case the number of terminals is equal to the low-

Finding an Eulerian trail with symmetry constraints.

procedure join-trails(cover left) I if there is only one trail in the list 2 return // no pairs to join 3 foreach trail tr=(vl.,vk) in cover-left 4 let tr=(a,...,b) I/ a and b are end terminals 5 insert tr in list(a) and list(b) 6 foreach end terminal x 7 join trails in list(x) pair-wise at x 8 update effected list 9 return(cover-left) Fig. 7.

v3 v7

Joining open trails.

Next, in Line 7-Line 13, symmetric twins of the trails in cover-left are constructed. This is possible, since as a trail in cover-left, tr. was being generated in euler 0, the edges required to construct its symmetric twin, tr, were preserved by deleting them from the graph. This process can also be viewed as simultaneously generating two trails that traverse the two halves of the graph in a synchronous and symmetrical way. Line 8 can construct either a mirror symmetric trail or a perfectly symmetric trail. In Line 9-Line 10 the trail tr and its symmetric twin tr' are joined, if they have a common end terminal and if the operation does not violate a perfect symmetry constraint. Fig. 8 shows an example. As a consequence of deleting both of the edges in a symmetric pair, euler () may encounter a vertex of zero degree while it is trying to find a closed trail in the do-while loop, Line 5-Line 12. When such a vertex is reached, euler () detects that the current trail has to be an open trail. For an open trail, euler () first recurses on the vertices of the open trail, as is the case with closed trails, but when the recursion terminates, it inserts the open trail in the trail cover cover-left and returns the initial vertex as a trivial trail to the previous recursion level (for more details and some examples see [18]). Note that in an Eulerian graph without symmetry constraints there is always a closed trail; no open trails are detected and euler () returns an Eulerian trail.

er-bound given by Fd(v)/21. Now assume nodd

=

0. The previ-

ous argument still holds for all vertices except the one at the end terminals (Note that k = I ). But the vertex at the end terminal was chosen to be the one with the lowest criticality weight, therefore the cost function is minimized and the stacking is optimum. The cost function in Eq. (1) is also minimized for a class of circuits with symmetry constraints for which the corresponding modified diffusion graph satisfies two conditions: (1) no cross-symmetric edges (2) number of self-symmetric vertices with degrees d (v) = 2 (2k + 1) , k > 0 is less then 4. Given these conditions the optimum can be found in linear time by adding a post-processing step to the algorithm which recombines certain trails to reduce the cardinality further. The proof is rather long and will be presented in another paper. When the second condition is waived, the optimum can still be found via a similar post-processing step, but with a penalty in the time-complexity of the algorithm. Currently we are working on a sufficient condition for optimality in the general case. It is also worth noting that we do not evaluate the cost function given in Eq. (1) in sym traibcover (). After stacking, the performance of the circuit can be evaluated using estimates on parasitic diffusion capacitances and device matching, looking at the generated stacks [6]. If there is an unsatisfied performance constraint, then the stack generation step indicates that the performance specifications were too tight and it is infeasible to meet them during the layout phase; hence either the design or the specifications must to be modified.

265

4 Results The stack generation algorithm presented in this paper has been implemented in C++ on an IBM PowerPC 604 (133MHz) based workstation running AIX 4.1. We have tested the algorithm on various circuits from the literature. Table I lists some of these circuits that we obtained from the literature [4][15][6] and shows some results. For all of the circuits the number of stacks is optimum and hence equal to the results obtained by [6]. Again note that the technique presented in [6] is enumerative and has exponential time complexity. We note that in theory our algorithm can guarantee optimality for only some classes of circuits. But still it could find the optimum results for all the circuits that were available to us, since most practical circuits indeed fall into the class for which our technique is proved to be optimum. Sensitive circuit nodes are maximally merged, and estimated performance degradation, as computed by Eq. (1), is equivalent to that in [6]. The run time is very low (less then 100ms per circuit). This compares favorably to [6] which employs an exponential-time algorithm; e.g., for Comp3, our optimum stack generation algorithm found a solution in less than I00msec while the technique in [6] reports 7.5 sec, a difference of approximately two orders of magnitude1. For bigger circuits, higher savings can be expected.

Fig. 9.

The Mult circuit. MIIS

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p'amTF Opamp2 Opamp3 Opamp4 Opamp5 AB Comp2 Comp3 Mult Buffer

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Fig. 9 shows a multiplier circuit [15]. It is a typical analog circuit that was used as a benchmark in KOAN [4] as well as in other constraint-driven layout research [15]. The stacking solution generated with our algorithm is shown in Fig. 10. The number of stacks found is 3, which is the theoretical optimum. As a comparison, the number of stacks found in the KOAN layout is 72. Fig. 11 shows another analog cell, a comparator which is highly sensitive to device mismatch and parasitic capacitance [4][15][6][16]. The stacking generated by our algorithm is shown in Fig. 1'2. Again, compared to KOAN, our algorithm found a better stacking, with 3 fewer stacks.

1. Also note that in [6], an enumerative algorithm is utilized which can find all optimum solutions whereas our technique finds only one. 2. We note that this is not a fair comparison, since KOAN integrates stack generation with placement.

M125

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Fig. 10.

The optimum stacking generated for Mutt.

Fig. 11.

The Comp circuit.

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Fig. 12. The optimum stacking generated for Comp.

5 Conclusions First-generation custom analog cell layout tools relied on simultaneous stacking, folding and placement of devices to achieve acceptable density and performance. The disadvantage of these approaches is the lack of any guarantees on the achievable circuit performance, and (due to their annealing-based formulations) the variability in layout solutions, run to run. Second-generation tools have focused on two-phase approaches, in which a partition of the devices into optimal stacks is performed first, and subsequent placement manipulates a palette of alternative stacks. The advantage is more predictable circuit performance, and these techniques can be fast for small circuits. But the runtime to generate all stack partitions can be extremely sensitive to circuit size due to the exponential algorithms at the core of these approaches. In this paper we introduced an effective stacking strategy that is fast enough to be exploited in the inner loop of a device placer, yet still respects analog node criticality information. In comparison with the 2-D freeform stacking style of [4], our approach is faster and can find better results. In comparison with the branch-and-bound technique of [6] which enumerates all optimum solutions, our approach can find a single solution of equivalent cost, for most practical circuits, but in linear-time with respect to the circuit size. Our long term goal in this work is to integrate this stacking algorithm into a device placer in the style of [4], replacing random search for good merges with directed search among local clusters of devices. Instead of finding all stacking alternatives a priori, we only stack those local sets of devices that the placer tells us ought to be stacked. This should yield improved analog cell layout tools, and digital cell layout tools as well. Complex dynamic-logic CMOS cells are increasingly analog in character, and we believe that a combination of aggressive search (for device placement and folding) coupling with simultaneous, dynamic stacking proposed in [17] (to optimally arrange local clusters of devices) is an attractive strategy here. Acknowledgments We are grateful to Prof. Ron Bianchini and Pinar Keskinocak (CMU) for helpful discussions on Eulerian trails. We thank Prof. Rick Carley (CMU) and Dr. John Cohn (IBM) for giving us some of the circuits used in this paper. We thank Mehmet Aktuna for fruitful discussions. Pinar Keskinocak and Aykut Dengi also helped to improve the presentation by reading an earlier draft of the paper. We would also like to acknowledge MPI, Germany for their LEDA library which was of great assistance in prototyping with graph algorithms and basic data structures. This work is supported in part by the Intel Corporation and the Semiconductor Research Corporation.

267

References [I] T. Uehara and W. M. vanCleemput, "Optimal Layout of CMOS Functional Arrays", IEEE Transactions on Computers, Vol. C-30, No. 5, May 1981, pp. 305-312. [21 R.L. Maziasz, J.P. Hayes, Layout Minimization of CMOS Cells, Kluwer Academic Publishers, Boston/London, 1992. [3] S. Wimer, R.Y. Pinter, J.A. Feldman, "Optimal Chaining of CMOS Transistors in a Functional Cell", IEEE Transactions on Computer-Aided Design, Vol. CAD-6, September 1987, pp. 795-801. [4] J. M. Cohn, D. J. Garrod, R. A. Rutenbar and L. R. Carley, "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", IEEE Journalof Solid-State Circuits, Vol. 26, No. 3, March 1991, pp. 330-342. [5] E. Charbon, E. Malavasi, U. Choudhury, A. Casotto. A. Sangiovanni-Vincentelli, "A Constraint-Driven Placement Methodology For Analog Integrated Circuits". IEEE Custom IntegratedCircuits Conference, May 1992, pp. 28.2/1-4. [6] E. Malavasi, D. Pandini, "Optimum CMOS Stack Generation with Analog Constraints", IEEE Transactions on ComputerAided Design, Vol. 14, No. 1, Jan. 1995, pp. 107-122. [7] M.J.M. Pelgrom et al., "Matching Properties of MOS Transistors", IEEE Journalof Solid-State Circuits, Vol. sc-24, October 1989, pp. 1433-1440. [8] U. Choudhury and A. Sangiovanni-Vincentelli, "Automatic Generation of Parasitic Constraints for Performance-Constrained Physical Design of Analog Circuits", IEEE Transactions on Computer-Aided Design, Vol. 12, No. 2, February 1993, pp. 208-224. [9] E. Charbon, E. Malavasi, A. Sangiovanni-Vincentelli, "Generalized Constraint Generation for Analog Circuit Design", Proceedings of the IEEE/ACM ICCAD, Nov. 1993, pp. 408414. [10]S. Chakravarty, X. He, S.S. Ravi, "On Optimizing nMOS and Dynamic CMOS Functional Cells", IEEE InternationalSymposium on Circuits and Systems, Vol. 3:, May 1990, pp. 17011704. [Il]S. Chakravarty, X. He, S.S. Ravi, "Minimum Area Layout of Series-Parallel Transistor Networks is NP-Hard", IEEE Transactions on CAD, Vol. 10, No. 7, July 1991. [12]J.A. Bondy and U.S.R. Murty. Graph Theory with Applications, Elsevier Science Publishing, New York, 1976. [13]C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity, Prentice-Hall, Inc., Englewood Cliffs, New Jersey 07632, 1982. [14]J. M. Cohn, "Automatic Device Placement for Analog Cells in KOAN", PhD dissertation, Carnegie Mellon University, February 1992. [15]B. Basaran, R. A. Rutenbar and L. R. Carley, "Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 1993, pp. 415421. [16]E. Charbon, E. Malavasi, D. Pandini, A. Sangiovanni-Vincentelli, "Simultaneous Placement and Module Optimization of Analog IC's", Proceedings of the IEEE/ACM Design Automation Conference, June 1994, pp. 31-35. [17]B. Basaran and R. A. Rutenbar, "Efficient Area Minimization for Dynamic CMOS Circuits", IEEE Custom Integrated Circuits Conference, May 1996. [18] B. Basaran and R. A. Rutenbar, "An O(n) Algorithm for Transistor Stacking with Performance Constraints", Research Report No. CMUCAD-95-56, Carnegie Mellon University, 1995.

Efficient Standard Cell Generation When Diffusion Strapping Is Required Bingzhong (David) Guan and Carl Sechen Department of Electrical Engineering University of Washington Box 352500, Seattle, WA 98195-2500

Abstract In [31, we proposed a single contact layout style (SC style) for CMOS standard cells with regular and compact structure., based on the assumption that a single diffusion contact is sufficient. In reality, the assumption is not always true. We therefore propose a partial strapping style (PS style) for use when diffusion strapping is required. The PS style keeps all the features of the SC style. The structure uses less area for individual cells, allows easy embedding of feedthroughs in the cell, and enables output pins to occur at any grid location. Using an exact algorithm to generate static CMOS cells with a minimum number of diffusion breaks ensures that the width of the cells is minimized. For the PS style, a constructive routing algorithm is used to perform the intra-cell routing. An exhaustive search among the minimum width cells produces the minimum height cell. Our results show that cells in the PS style have cell height very close to those in the SC style. Furthermore, cells using either layout style achieve significant area savings compared to cells using the traditional full strapping style.

Introduction Layout generation, also known as silicon compilation, transforms the logic description of a system into physical

masks for silicon fabrication. Since the problem is so vastly complicated, over the past two decades, the standard cell design methodology gained popularity because it solves the problem in a reasonable fashion with the divide-and-conquer approach. The layout generation process typically has been divided into subtasks of logic synthesis and technology mapping, cell generation, placement, global and detail routing, and compaction. The ultimate goal is to minimize chip area while satisfying performance requirements. The building blocks of this approach are these standard cells. Layout minimization depends a lot on the structures of individual cells (cell layout style) and also the structure of the standard cell library (mainly, the content and the size of the library). Since Uehara and vanCleemput [12] proposed a layout style (UvC78) for static CMOS cells in 1978, almost all cell layout styles have followed UvC78 with minor variations [1][7][9]. In the style of UvC78 and its variations, the power lines run parallel to the diffusion rows. However, the original style was targeted for a one metal layer process. This style is disadvantageous with respect to layout area [5]. In layout generator THEDA.P, a new layout style was introduced to target 2-layer metal CMOS processes [6]. However, in this style, the pins are not aligned and the metal-2 layer is not obstacle free.

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268

via

In [3], we proposed a single contact layout style (SC style) for CMOS standard cells. In this paper, we propose a new partial strapping style (PS style). In designing our styles, the main goal was integration with place and route tools so that the total chip area is minimized after the cells are placed and routed.

New Layout Styles The traditional fabrication process typically mandates that the drain and source regions be fully contacted (called full strapping, as shown in Figure l(c)) to improve performance and ensure reliability. With advanced processing technology, self-aligned silicide (salicide) can make the sources and drains very low in resistance. With either a local interconnect being available to strap the diffusion areas or salicide being available, connecting to diffusion with a single contact does not effect performance much. One industry source, based on the latest 0.25gim processing technology, found that the performance degradation is minimal when moving from full strapping to a single contact style. The worst case degradation is less than 5%, when only having one minimum size contact driving a 10tm transistor from one end of the diffusion. In [3], we proposed the SC style for CMOS standard cells (Figure 1(a)) based on the single contact assumption. The style is applicable to the processes where a single contact is sufficient due to salicide. It is also applicable to the processes where a local interconnect (LI) layer is available to accommodate full strapping of diffusion area. The SC style has a regular yet compact structure. The structure uses less area for individual cells, makes routing problems straightforward and allows easy embedding of feedthroughs in the cell. Using that new style, we developed a cell generator using an exact algorithm to minimize cell width and height. Unfortunately, only a few semiconductor manufactures currently support such advanced fabrication processes (either salicide or LI). In this paper, we therefore propose a partial strapping style (PS style, Figure l(b)). Although different from the SC style due to the strapping requirement, the PS style follows the same discipline of maintaining the cell structure as compact and regular as possible. The strapping requirement however creates a quite different intra-cell routing problem. We developed a constructive heuristic algorithm for the intra-cell routing problem. This algorithm has been integrated into our area minimizing cell generator. Figure l(a) shows a complex cell in the SC layout style. Figure l(b) shows the same complex function cell in the new PS layout style. Both new layout styles only use metal1 for intra-cell connections. They have same configuration for input and output pins or terminals. Pins are aligned in a row between the diffusion regions and are equally spaced between the poly gates. The differences between the two styles are power bus positions and intra-cell routing schemes. In the SC style, the power lines are over the diffusion area, running horizontally near the middle of the cell to facilitate cell abutment. In contrast, in the PS style, the power lines are partially overlapping the diffusion area on the top and bottom boundaries of the cell. In addition, in the SC style, the intra-cell routing scheme will use the horizontal tracks that are close to the center of the cell. Those regions over the diffusion area, but not used for intra-cell routing are outside the power buses and can be grouped together with the channel to form one routing region for

inter-cell routing. In contrast, the intra-cell routing and partial strapping of diffusion area uses up all the area in between power buses in the metal-I layer. The features of these styles are: I) The output pins can be at any grid position. The freedom of putting the output pin at any grid offers the potential to reduce the number of tracks needed to route all intra-cell nets. Reducing the number of tracks means the portion of the height of a cell used for intra-cell routing is reduced. 2) The pins are at the cell center, aligned in a row, on a uniformly spaced grid. This regularity made the inter-cell routing problem easier. The only obstacle for routing the inter-cell connections are the regions used for intra-cell routing in the metal-l layer. Thus the routing region in the metal-l layer is a rectilinear area between two rows, including the routing channel and the area over the cell which is not used for intra-cell connections in SC style. In PS style, the routing region will just be the channel area in the metalI layer. The metal-2 and metal-3 layers are obstacle free. Over-the-cell routing is simple with a uniform pin grid. 3) These styles provide a lot of built-in feedthrough positions. After place and route, the connection directions of pins in a cell are known. Two neighboring pins having opposite direction connections can be moved into one pin column, thus one column is free to be used as a feedthrough position. For example, in Figure 2, pin f only connects upward, and pin e connects downward. Pins e and f can share the same pin grid, while a straight feedthrough position is created. These layout styles also provide dog-leg feedthroughs.

Cell Generation Functional cell generation is the process of translating a design from the transistor circuit level to the transistor layout level. The process of generating a minimum area cell has been proved to be NP-hard [2]. The primary goal in

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269

optimization is normally to minimize the cell area (width times height). One important aspect in reducing cell width is to utilize diffusion abutment. This abutment can be achieved when the source and drain diffusions of adjacent transistors are electrically equivalent. If they are not electrically connected to each other, a diffusion gap is needed to isolate these transistor terminals. In our layout styles, a diffusion gap forces the separation between neighboring poly gates to be twice as large as that needed by diffusion abutment. In fact, one of our goals is to maximize diffusion abutment. Exact Algorithm to Minimize Cell Width and Height In [8], an exact algorithm, HR-TrailTrace, was proposed to minimize cell width by minimizing the number of diffusion breaks. The algorithm utilizes the transistor reordering (also called delayed binding) technique. An exhaustive search among all minimum width cells produces a minimum height cell. The algorithm only counted the density of intracell nets as the height. The algorithm was shown to be feasible for all cells of practical size. We implemented that algorithm with a few modifications and extensions. Modifications include utilizing logical equivalence to drastically reduce the number of permutations we need to consider and increasing the efficiency of the algorithm [3]. This algorithm can handle series-parallel connected transistor netlists. For the SC style, a modified left edge algorithm (LEA) has been implemented to route the intra-cell connections. The modification stems from the necessity of determining the output pin location and having the output net always on the first track from the middle. Among all these routed minimum width cells, those which have the least number of tracks are picked as the minimum height cells. As an example, corresponding to the complex function shown in Figure 1, the minimum height layout is shown in Figure 3. This area minimum cell only needs four routing tracks, while the

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Function FindViolations&Flip(Tracks,FlipFlag) / While (ViolationsExist) ( 10 Find all segments with violations; 11 Calculate costs for all these segments; /* Three costs are associated with a given configuration: CostOrig is the number of violations in its current location; CostDest is the number of violations if the segment is flipped to the other side; And CostDiff is the difference of the previous two (CostDiff= CostOrig - CostDest). *l

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270

Intra-Cell Routing for PartialStrappingStyle For the PS style, because of the strapping requirement, the LEA algorithm in itself cannot be applied. The routing problem becomes how to route all connections so that there are the fewest number of intersections between nets. If we don't have any (metal-1) intersections between nets, all routing can be placed over the diffusion regions. Otherwise, some nets will have to be routed in the area between the diffusion and the power bus, not only increasing the cell height, but also requiring some segments of poly wires to be used (as used in Figure l(c)). For example, the corresponding PS style layout of Figure 3 will have the segment shown on top to have one intersection with one of the power connections. That intersection forces the top segment to be routed in the area between the power bus and the diffusion, which results in a taller cell than the one shown in Figure l(b). This complication renders both HR-TrailTrace's density counting algorithm and LEA not applicable. The intra-cell routing problem for each of the PMOS and NMOS sections actually is a single-row-planar-routing

(SRPR 110]) problem with some constraints. One constraint is the power connections which block one side entirely, while the connection for the output pin blocks partially the other side. The other constraint is that vertical tracks between nodes are quite limited, and sometimes even do not exist. We developed a heuristic to solve this routing problem. Listed in Figure 4 is the intra-cell routing algorithm for the PS style Shown in Figure 5 is the step-by-step flow to generate intra-cell routing for the cell in Figure 1(b). The PS style routing starts from the results of the LEA (step 1). The track that contains the output net is assigned to the middle (step 2) and all other tracks are assigned to the outside (step 3). At this time, all violations (intersections), if any, are in the OT. Figure 5(bl) shows that the initial intersections are (ni, n2) and (n2, n3). Step 4 calls the function FindViolations&Flipwith the AlwaysFlip Flag to resolve all these violations in OT. This function first finds all segments which have violations (step 10) (nets ni, n2, and, n3 in Figure 5(b I)) and then calculates (step 11) the costs associated with these segments: CostOrig is the number of intersections the segment has in its current location; CostDest is the number of intersections if the segment is flipped to the other side; And CostDiff is the difference of the previous two (CostDiff = CostOrig - CostDest). Step 12 orders these segments according to CostDiff, with CostOrig as the tie breaker. In Figure 5(bl), the ordered list of segments is (n2, ni, n3) with the corresponding (CostDiff CostOrig) list as (1, 2), (1, 1), and (0,1). When the FlipFlagis AlwaysFlip, we will flip the segment with the largest CostDuff to the other side, even when it means an increase in the total number of intersections (step 14). The function returns when all violations are resolved on that side. When the FlipFlag is CostReductionOnly, the function will return when the cost cannot be reduced (steps 13 and 14). In Figure 5(b 1), n2 will be flipped to the middle tracks, and that resolves all violations in OT. Afterwards, during the while loop in steps 5 through 7, the algorithm cycles through from side to side to resolve any violations we may have. The flipping is only done when the moving net will not be causing more violations. In Figure Out

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move resolves all violations as shown in Figure 5(b3). If

there are any remaining intersections, they have to be placed outside (step 9). This concludes the intra-cell detail routing. The intra-cell routing is performed over all minimum width cells of a given function, then the layouts which have the least intersections will be picked. Experiments have shown that the algorithm is very effective in routing nets over the diffusion area. The algorithm finds that all 87 cells having no more than 3 transistors in series in both the NMOS and PMOS sections have layout implementations in which all the intra-cell routing is over the diffusion.

Results We studied the layout area and circuit performance as a result of utilizing a large library of standard cells [4]. We built libraries of all static CMOS cells having a chain length of up to 7, and this was made possible by our new cell generator's capability of generating any static CMOS cell with a user-specified limit on the number of series transistors. We used the TimberWolf place and route tools [11] to generate the actual chip layout. We used an industrial timing analyzer, which included wiring parasitics, and state-of-the-art 0.25 pgm design rules, to provide performance information. We refer to a library of all possible cells having a chain length limit of n as sn. We experimented on 13 MCNC benchmark circuits, ranging from 124 to 2090 cells, 165 to 2135 nets. Our results (Table I) show that compared to using library s2, in terms of chip area, s3, s4, s5, s6, and s7 saves 16%, 22%, 24%, 25%, and, 26% respectively. For larger designs, the area savings amounted to 50% when using s7. In the meantime, since a netlist which uses larger cells will have fewer cells on each critical path, we found that the average worst path delay is quite similar for libraries s3 through s7. We concluded that using a very large library (e. g., s7) is optimal in terms of area and delay. Due to the sheer sizes of these large libraries, it is not possible to draw all those possible cells by hand. An efficient automatic standard cell generator is necessary to make this approach feasible and to realize the chip area savings. As can be seen from Figure 1, while the SC, PS and FS style cells all have the same width, their height is quite different. Compared to the SC style cells, the PS style cells are taller due to partial strapping. For FS cells, intra-cell connections use some more area. Table II shows the cell height comparison between the three styles. The cells in the SC style are 12% shorter than those in the PS style, while the cells in the FS style are 30% taller than those in the PS style. Table II also shows the comparison of metal-I blockage. Since the unblocked area can be used in the SC style, the height of the metal-i blockage can be considered as the effective cell height. We can see from Table II that relaxing the partial strapping requirement could potentially reduce metal-i usage by 43%. In summary, the PS style is very close in matching the area savings offered by the SC style, while satisfying the strapping requirement. The area savings that a semiconductor manufacturer can gain from using a more advanced fabrication process (e. g., salicide or local interconnect) is quite clear. Nonetheless the PS style is very dense as can be seen by the very high metal-l usage in the cells. Further, the PS style represents a significant area improvement over the

Vdd

lf

TF-

5(b2), n4 has the most CostDiff, and thus is flipped. This

(b2)

(b3) (b)

Figure 5: Intra-cell routingflowfor the cell layout in Figure i'(b). The cross indicates the intersectionviolation. (a) shows the routing steps for the NMOS section. (b) shows the routing steps for the PMOS section.

271

Table I Comparison of total standard cell area, normalized to the s2 case. s2

s5

s6

s7

.938 .875 .722 .791 .776 .836 .868 .786 .737 .788 .656 .809 .504

.926 .857 .717 .774 .743 .831 .858 .750 .709 .766 .611 .790 .499

.926 .843 .714 .779 .702 .826 .850 .739 .697 .752 .592 .776 .492

.926 .840 .710 .769 .697 .824 .849 .725 .696 .750 .580 .768 .472

.776

.756

.745

.739

s3

s4

C1355 C1908 C2670 C3540 C432 C6288 C7552 b9 dalu des k2 rot t481

1 1 1 1 1 1 1 1 1 1 1 1

.950 .890 .777 .851 .844 .870 .897 .828 .846 .854 .740 .860 .695

Average

1

.839

References

conventional FS style. [1]

Table H Cell height comparison, normalized to PS case. Cell Style .

Effective Cell Height

Cell Height

(Metal-i Blockage)

-_ PS

FS;

_

__

IJ__I_

_

[2]

0.57

0.88

SC

_

1.30

[3]

1.30

S. Bhingarde, A. Panyam. and N. A. Sherwani, "Middle terminal cell models for efficient over-the-cell routing in high performance circuits." IEEE Trans. on VLSI, vol. 1, pp. 462-472, December 1993. S. Chakravarty, X. He, and S. S. Ravi, "Minimum area layout of series-parallel transistor networks is NP-hard," IEEE Trans. Computer-Aided Design, vol. 10, pp. 943-949, July 1991. B. Guan and C. Sechen, "An area minimizing layout generator for random logic blocks," Proc. of Custom Integrated Circuits Conference, Santa Clara, CA, May 1995.

[4]

In [3 1,we presented chip area comparison between the SC style and the Mississippi State University (MSU) library and an industrial library. Our results show that circuits using the SC style cells achieve significant area savings (as much as 50%) compared to the use of these manually laid out compact cells. Since the PS style is very close in matching the height of the SC style, similar area savings can be achieved.

[5]

B. Guan and C. Sechen, "Large standard cell libraries and their impact on layout area and circuit performance," submitted to the International Conference on Computer Design, 1996. Y-C. Hsieh, C-Y. Hwang, Y-L. Lin, and Y-C. Hsu, "LiB: A CMOS

[6]

cell

compiler,"

IEEE Trans. Computer-Aided

Design, vol. 10, pp. 994-1005, August 1991. C. Y. Hwang, Y-C. Hsieh, Y-L. Lin, and Y-C. Hsu, "An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis", IEEE Trans. Computer-Aided Design,

Conclusions

[7]

We presented a partial strapping style for use when diffusion strapping is required. The PS style keeps all the features of the SC style. The structure uses less area for individual cells, allows easy embedding of feedthroughs in the cell, and enables output pins to occur at any grid location. Using an exact algorithm to generate static CMOS cells with a minimum number of diffusion breaks ensures that the width of the cells is minimized. We developed a constructive routing algorithm to perform the intra-cell routing. An exhaustive search among the minimum width cells produces the minimum height cell. Our results show that cells in the PS style have cell height very close to those in the SC style. Furthermore, cells using both layout styles achieve significant area savings compared to cells using the traditional full strapping style.

272

[8] [9]

vol. 12, pp. 410-424, March 1993. S. M. Kang, "Metal-metal matrix (M3 ) for high-speed VLSI layout," IEEE Trans. Comp.-Aid. Design, vol. 6, pp. 886891, Sept. 1987. R. L. Maziasz and J. P. Hayes. Layout Minimization of CMOS Cells. Kluwer Academic Publishers, 1992. S. S. Sapatnekar and S. M. Kang. Design Automation for Timing-Driven Layout Synthesis. Kluwer Academic Publishers, 1993.

[10] N. Sherwani. Algorithmsfor VLSI Physical Design Automa-

tion. 2nd Edition. Kluwer Academic Publishers, Boston, 1995. [11] TimberWolf Systems, Inc. TimberWolf: Mixed Macro/Standard Cell Floorplanning, Placement and Routing Package

(Version 1.0). Obtained from Bill Swartz at TWS, Dallas, TX, 1994. [12] T. Uehara and W. M. vanCleemput, "Optimal layout of CMOS functional arrays," Proc. 16th ACM/IEEE DAC, pp. 287-289, May 1978.

Author Index Alexander, M. J. Alpert, C. J. Ashtaputre, S. Bart, S. F. Basaran, B. Berg, E. C. Blaauw, D. Carrabina, J. Chen, C.-P. Chen, Y.-P. Cheng, C.-K. Chiluvuri, V. K. R. Cohoon, J. P. Colflesh, J. L. Cong, J. Cowen, A. Dai, NV. W.-M. Deng, W. Dong, S.-K. Drake, K. Dutt, S. El Gamal, A. Entrena, L. A. Esbensen, H. Fedder, G. K. Friedman, E. G. Gabriel, K. J. Ganguly, S. Guan, B. Gullickson, D. Gupta, R. Hagen, L. Harr, R. He, L. Hebgen, W. Hossain, M. Hwang, J. Jess, J. A. G. Kahng, A. B. Kang, M. Kaptanoglu, S. Karro, J. Knol, D. A. Koakutsu, S. Koren, I. Kuh, E. S. Lee, H[. J. Lehther, D.

142 100

154 71 150, 262 67 40 176 21 21 7

198 142 142 1, 34 61 134, 226 92 256 228 92 106 13 126 53, 76 241 45 40 268 228 163 100

81 34 118 154 106 111 100

134 169 142 234 134 207 126 67 40

Lillis, J. Lin, T.-T. Liu, C. L. Liu, L.-C. E. Lo, C.-Y. Lo, N. R. Mahadevan, R. Maher, A. C. Maly, W. Marek-Sadowska, M. Marin, X. Molitor, P. Morison, R. Mukherjee, T. Neves, J. L. Nijssen, R. X. T. Okamoto, T. Olias, E. Palesko, C. Pan, P. Parrish, P. T. Peset, R. Peters, E. L. Peters, I. Pister, K. S. J. Pullela, S. Riera, J. Robins, G. Rutenbar, R. A. Sandborn, P. A. Sarrafzadeh, M. Scheffer, L. Sechen, C. Simon, J. N. Sun, Y. Tanner, J. E Tellez, G. E. Thumma, B. Tsai, K-H. Tseng, H.-P. Uceda, J. Velasco, A. J. Vittal, A. Wang, K. P. Weber, M. Wong, D. F. Yee, G. Zimmermann, G.

7 7 163, 256 218, 249 256 67 61, 83 86 190

27, 169, 190 176 158 86 53 241 111 1

13 228 256 86 176 142 158 67 40 176 142 150, 262 228 234 89 183, 210, 218, 249, 268 67 163 86 234 154 169 210 13 176 27 190

158 21 183 118