Trading off Reliability and Power-Consumption in Ultra-Low Power Systems AtulMaheshwari Wayne Burleson Russell T...
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Trading off Reliability and Power-Consumption in Ultra-Low Power Systems AtulMaheshwari Wayne Burleson Russell Tessier ! " #%$'&(#) +*, .-/+ /.01/2# 3 /546798: #3 3; =,*?3;5!3 @"AB= 3!@C8DAFE$*
Abstract
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PARITY
ENABLE
T
Q
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T
TFF
Q
T
TFF
Q TFF
CLOCK
a) Binary Counter using T−Flip Flop T1 T2 T3 T4
PREDICTED PARITY D
Q1 Q2 Q3 Q4
Q
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CLOCK
b) Parity prediction logic
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overflow
overflow
4 − bit Gray counter
.....
4 − bit Gray counter
overflow
a) Segmented Gray counter using 4−bit Gray counters
ENABLE
0
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CLOCK
b) Output of a Segmented Gray counter
DFF
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BIT 1
½ © > ¼ º Segmented Gray counter
DFF
BIT 2
BIT 3
½ © > »,º Binary counter using a D-Flip flop
2.2. Gray counter
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BIT0 BIT0 BIT1 BIT1 . . . . BIT3
Logic to generate the bit for next state Similar for other bits
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INPUTS
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.
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0.07
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Power consumed (in mW)
R,C
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Binary Counter Gray Counter
0.065 0.06 0.055 0.05 0.045 0.04 0.035
Clk
½ L § W¯ © ]> M© > fk > x¡ T
5. Conclusions and Future work ½ M§ ¨ ¨ £ ¡ ¨ L !© £5M ; L § p¯ © s M f¸!½ © > Ã^¼ ¹ ] §x¦ L> µ§ > §e>L © > Lµ 5/]D M $#*,TI $ + 4 § © p ¦+h ¡ ¨ §>µL ¡ M W¦ f>m b£ ¡ >#µYM§ !© £5M L ; >§ , ML « ¿ ¨ \ § ¨ M§ \MWbb> ,© T U>L § p¯ © T:© ¡ M© ] 6© ¡
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
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140 Binary Counter Gray Counter
Fault Vulerability
120
100
80
60
³ § ¨ >¢ ¨
©¡ ¡ Acknowledgment: ¡ U¦ ²?§ ¡ ` «
40
20
1
2
3 4 Size (time original size)
5
6
6. References
½ Ã;% > Counter #' Design,” M! ;3 @&Oin/ M *,/!3Y #%$+4X3dY3 , 1999, pp. 16591662.
0.1 Binary Counter Gray Counter
Power Consumed (in mW)
0.09
[2] Su C. L., Tsui C. Y. and Despain A. “Saving M^power > $#/?in -#3:the 7 control path Ma(t ;3e-of:embedded #%$:n;3(processors,” 7&CU %*,din 3 , 1994, pp. 24-31.
0.08 0.07
0.05
0.04 0.03
1
2
3 4 Size (times original size)
5
6
[6] Iyer R. and Rosetti D., load of CPU >L“A statistical $#/.-3Y7 vcnadependency &" errors at SLAC,” in , 1982.
0.085
6X Size
0.08
Binary Counter Gray Counter
6X Size
0.075
[7] Messenger G. C., “Collection charge junction M(a n of
M 3 !on 9*3h # # nodes from ion tracks,” in % !+ , 1982, pp. 2024-2031.
0.07
10K Res
0.065 0.06 0.055
10K Res
[8] Laguna G. and Treece R. “VLSI M^ > modeling $/.-3cand >((design ; ;for
I radiation environments,” in + !+ &CL; M+ 6&(#) +*, ; Bb3e- , 1986, pp. 380-384.
Normal
0.05 0.045
Normal
0.04 0.035
[4] Hakenes R. and Manoli Y., “A segmented Gray code Y 0 86 #for & lowpower microcontroller address buses,” in &(#^;; M+ , 1999, pp. 240-243. [5] Ball H. and Hardy F., “Effects and M^detection >$/.-& 3bof s 7\ &1intermitv@ tent failures in digital systems,” in A)v">`k #^;; >;% > , 1969, pp. 329-335.
½ © > Ã^»,º Effect of sizing on power
Power Consumed (in mW)
[3] Mehta H., Owens R. M. and
M^ >Irwin $/.-M. 3{7J.6“Some Teq ;% >
&CU %*,d \b;3 e- , Oct 1993, pp. 538–542. [12] Singh M., and Koren I., “Reliability Enhancement >(( Td of+Analog !+ # to-Digital Converters (ADCs),” in T4#) X3/*, 6; ;s #+$v *, Z\nT O#? M #% 9/
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
T4X3 ;3
, Oct. 2001.
