Transient and Permanent Error Control for Networks-on-Chip

Transient and Permanent Error Control for Networks-on-Chip

Qiaoyan Yu

l

Paul Ampadu

Transient and Permanent Error Control for Networks-on-Chip

Qiaoyan Yu University of New Hampshire Durham, NH 03824, USA [email protected]

Paul Ampadu University of Rochester Rochester, NY 14627, USA [email protected]

ISBN 978-1-4614-0961-8 e-ISBN 978-1-4614-0962-5 DOI 10.1007/978-1-4614-0962-5 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011939749 # Springer Science+Business Media, LLC 2012 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.

Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

Preface

Reliability has become one of the most important metrics for on-chip communications infrastructures in nanoscale technologies. Reduced supply voltages and high clock frequencies exacerbate the impact of noise sources such as particle strikes and crosstalk, which can cause transient errors in transmitted data. Additionally, manufacturing defects, electromigration, and aging can cause permanent errors in communication links. Unfortunately, transient and permanent error management techniques typically result in increased power consumption, latency and area overhead, further challenging large-scale system design. Consequently, cost-effective techniques for improving onchip error resilience are needed. The purpose of this book is to address the reliability and energy issues of nanoscale on-chip networks. Since the noise environment is not constant in real applications, the worst-case design approach often used results in wasted energy, particularly when the noise condition is favorable. To address the variable error rates, we present a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. To further improve energy efficiency, the adaptation on ECC is extended to the network layer. We demonstrate that the proposed dual-layer cooperative error control achieves better reliability, latency, and energy efficiency than other solutions in a wide range of noise and traffic conditions, at moderate area costs. We further extend these methods to tackle joint transient and permanent error correction, exploiting redundant resources already available. This approach reduces the need for energy-consuming fault tolerant routing to minimize latency and energy overhead introduced by error control. The proposed approach is particularly applicable to scenarios where only a small number of permanent errors exists on the on-chip links. To evaluate performance and energy consumption of large networks-on-chip (NoCs), we also describe a flexible parallel NoC simulator. The simulator is designed to facilitate evaluating the impact of various error control methods on NoC performance.

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Key features of this book include l

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A detailed overview of various error control schemes commonly-used in on-chip interconnect networks Analysis of error control in various NoC layers, as well as presentation of an innovative multi-layer ECC technique Configurable error management solutions and their hardware implementation details for variable noise conditions Detailed description of a flexible and parallel NoC simulator This book should be of interest to

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Researchers interested in error control and fault tolerance techniques Networks-on-chip, systems-on-chip and chip-multiprocessor designers Engineers involved in parallel simulation tool development

Durham, NH, USA Rochester, NY, USA

Qiaoyan Yu Paul Ampadu

Acknowledgments

The original research work presented in this book was made possible in part by grants from the U.S. National Science Foundation (NSF) under grants ECCS0733450, ECCS-0903448, ECCS-0925993, CAREER Award ECCS-0954999, Cyberinfrasturcture Experiences for Graduate Students Supplement ECCS0609140, and the Semiconductor Research Corporation award SRC-2009-HJ-2000. We would like to express our special appreciation to our friends and colleagues Professor Wendi Heinzelman, Professor Chen Ding, Professor Thomas Tucker and Professor Kai Shen for their invaluable suggestions on improving the quality of Dr. Yu’s dissertation leading to this book. We are grateful also to our exceptional colleagues, Dr. Bo Fu (now at Marvell), Dr. David Wolpert (now at IBM), Meilin Zhang and Tony Broyld, for their enjoyable collaborations and support. Our deepest gratitude goes to our families for their unwavering encouragement and support. Many thanks also to our friends at the University of Rochester and to Charles B. Glaser from Springer for his support and assistance throughout the writing of this book. We welcome any suggestions, comments or constructive criticism on this book. Such feedback would be used to improve forthcoming editions. Additional material can be found at http://www.ece.rochester.edu/projects/edison. Durham, NH, USA Rochester, NY, USA

Qiaoyan Yu Paul Ampadu

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Contents

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Networks-on-Chip (NoCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Fundamental Elements in NoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 NoC Layer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 NoC Switching Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 NoC Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Reliability Challenges in Scaled Technology . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Transient Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Permanent Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Intermittent Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Reliability, Performance and Energy Tradeoffs . . . . . . . . . . . . . . . . . . . . 1.4 Book Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 1 2 4 5 5 6 9 10 11 11 14

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Existing Transient and Permanent Error Management in NoCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Error Control Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Automatic Repeat Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Hybrid Automatic Repeat Request . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Error Control Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Single Parity Check Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Cyclic Redundancy Check Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Bose-Chaudhuri-Hocquenghem Code . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Product Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Spare Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Split Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Fault-Tolerant Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Redundant-Packet-Based Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Redundant-Route-Based Routing . . . . . . . . . . . . . . . . . . . . . . . . . . .

19 19 19 21 21 22 23 23 26 26 28 29 30 30 31 31

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2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Adaptive Error Control Coding at Datalink Layer. . . . . . . . . . . . . . . . . . . . 3.1 Adaptive Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Architecture for Sender and Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Configurable Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Two-phase Configurable ECC Encoder . . . . . . . . . . . . . . . . . . . . 3.3.2 Configurable Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Configurable ECC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Evaluation of Adaptive ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Error Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Average Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Energy Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Simulation Using an H.264 Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Performance Evaluation Using Dependent Error Model . . . . . . . . . . . 3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37 38 39 41 41 42 44 46 46 47 48 51 54 56 56 60 61 62

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Transient and Permanent Link Errors Co-Management . . . . . . . . . . . . . 4.1 Dual-Layer Co-Management Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Co-Management Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Transmitter and Receiver Architecture . . . . . . . . . . . . . . . . . . . . . 4.2 Packet Re-Organization Approach. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Re-Organization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Input Port and Output Port Architecture. . . . . . . . . . . . . . . . . . . . 4.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Average Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Energy Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Area Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65 66 66 66 69 69 70 71 71 72 73 76 76 78 79

5

Dual-Layer Cooperative Error Control for Transient Error. . . . . . . . . 5.1 Existing Hop-to-Hop Error Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Existing End-to-End Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Dual-Layer ECC Switching Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 ECC Mode Switching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Network Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Router Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Dual-Layer Information Exchange . . . . . . . . . . . . . . . . . . . . . . . . .

81 81 82 84 84 86 88 90

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5.4

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Codec for Dual-Layer ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Dual-Layer ECC Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Dual-Layer ECC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Codec Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Energy Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Average Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Codec Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.6 Codec Area Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.7 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 91 91 95 95 95 97 102 106 110 111 111 115 116

A Flexible Parallel Simulator for Networks-on-Chip with Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Existing Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Platforms for Error Control Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Overview of the Proposed Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Error Control Modeling in Router and Network Interface . . . . . . . 6.4.1 Error Control in Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Error Control in Network Interface . . . . . . . . . . . . . . . . . . . . . . . 6.5 Flexible Fault and Traffic Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Fault Injection Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Fault Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Faulty Flit Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 Multiple-Frequency Traffic Injection . . . . . . . . . . . . . . . . . . . . . 6.6 Parallel Fault and Traffic Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Fault Injection on Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Fault Injection Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 Parallel Traffic Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Energy Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Speed and Memory Consumption for Fault Injection . . . . . . . . . . . . 6.9 Error Control Exploration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 Experimental Setup and Evaluation Metrics . . . . . . . . . . . . . 6.9.2 Impact of Packet and Fault Injection Rate . . . . . . . . . . . . . . . 6.9.3 Impact of Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.4 Impact of Faulty Flit Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.5 Impact of Fault Injection Location . . . . . . . . . . . . . . . . . . . . . . . 6.9.6 Impact of Fault Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Memory Consumption and Time for Fault Injection . . . . . . . . . . . . 6.11 Investigation of NoC-Based CMP System . . . . . . . . . . . . . . . . . . . . . . . 6.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

117 117 118 118 121 121 123 124 125 125 126 126 127 127 127 129 129 130 133 133 134 135 140 140 141 144 145 147 148

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Conclusions and Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Book Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Adaptive Error Control Codec Design. . . . . . . . . . . . . . . . . . . . . 7.1.2 Error Co-Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Dual-Layer Cooperative Error Control . . . . . . . . . . . . . . . . . . . . 7.1.4 NoC Simulator Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

151 151 151 152 153 153 154 155 157

Chapter 1

Introduction

1.1

Networks-on-Chip (NoCs)

Thanks to the rapid advancement of technology in semiconductor device fabrication, billions of transistors can be integrated to a single die [1–5]. Although the increasing chip density potentially facilitates systems-on-chip (SoCs) and chip multiprocessor (CMP) integrating hundreds or thousands of processing element/ memory cores, several challenges prevent system further progress, such as design complexity, high-performance interconnect and scalable on-chip communication architecture [6–9]. Networks-on-chip (NoCs) becomes a promising paradigm, which manages the increasing interconnect complexity and facilitates the integration of various intellectual property (IP) cores [10–15].

1.1.1

Fundamental Elements in NoC

NoC is a new infrastructure for on-chip communication. Figure 1.1a shows the three fundamental components of NoCs – links, network interfaces (NIs), and routers. Links facilitate communication between routers. NIs transform streams of bits from intellectual property (IP) cores into packets for transmission to routers and vice versa. Routers extract the destination address from each received flow control unit (flit) and pass the flit to its intended destination. Nodes in the NoC can be connected with the various topologies, as shown in Fig. 1.1b [16]. NoC survey shows that over 60% of NoCs employ mesh or torus topology [14]. These regular topologies provide better scalability than buses, crossbars and ad-hoc networks. Bolotin et al. have proved that the complexity of NoC connectivity is O(n), while the complexities pffiffiffi of simple pffiffiffi buses, point-to-point pffiffiffi connectivity and segmented buses are Oðn3 nÞ, Oðn2 nÞ and Oðn2 nÞ, respectively, as shown in Fig. 1.2 [16]. Here, n is the number of nodes in the network. Q. Yu and P. Ampadu, Transient and Permanent Error Control for Networks-on-Chip, DOI 10.1007/978-1-4614-0962-5_1, # Springer Science+Business Media, LLC 2012

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1 Introduction

Fig. 1.1 (a) Fundamental NoC elements, (b) topologies for NoCs

Unlike other interconnect architectures that use direct wiring, NoCs route data through several hops via routers. As a result, the interconnect fabric can be shared with all the IP cores attached to the NoC; significantly improving the efficiency of interconnect utilization. The multi-hop feature of NoCs helps to divide a long link into several short segments, each segment using a router to pass the data over the network. This segmentation also helps to manage the increasing delay and power consumption caused by link resistors. NoCs separate communication and computation and provide a feasible framework for reusing IP cores, as well. NoCs provide attractive benefits for on-chip communication. meanwhile this new infrastructure also brings new challenges – (1) Minimize area and power overhead induced by router and network interface, (2) Need for new design methodologies for NoC-based systems, (3) Need for new circuit and system design tools.

1.1.2

NoC Layer Model

Similar to other networks, the Open Systems Interconnection model (OSI model) is used to provide guidelines for NoC implementation [7, 16]. The layered structure shown in Fig. 1.3 is utilized to hide the implementation details of each layer from the other layers, simplifying system design.

1.1 Networks-on-Chip (NoCs)

3

Fig. 1.2 Scalability comparison of different interconnect topologies: (a) NoC, (b) simple bus, (c) point-to-point interconnection, (d) segmented bus

Fig. 1.3 Open system layer model for on-chip communication

4

1 Introduction

The physical layer transmits unstructured bit streams and deals with the electrical properties of the physical access mediums (i.e., wires), such as signal voltage, pulse shape, synchronization, delay and signal integrity issues. The datalink layer offers packetized data blocks with reliable transmission over physical links with necessary flow control and error control schemes. In this layer, an arbitration scheme for the access of the shared physical links significantly affects the delay, throughput and power consumption of the NoC. The network layer provides the upper layers with independence from the topology, data transmission and switching techniques. This layer is responsible for establishing, maintaining and releasing connections using static or dynamic routing algorithms. Congestion control methods are employed in this layer to balance the traffic load over the entire network. The transport layer ensures reliable and transparent end-to-end communication. In this layer, bit streams from the upper layers are segmented into packets or reconstructed from packets. Packet loss checking and packet reordering are performed in the transport layer, as well. The session layer typically synchronizes message transmission, which is useful for the multi-core systems that are running parallel programs. The presentation layer converts diverse data from the upper layers into a compatible format for the lower layers. This layer is especially necessary for heterogeneous multi-core systems, because heterogeneous IP cores may use different data formats (e.g., big-endian or litter-endian format, floating point or fixed point format). The application layer informs the components in SoCs/CMPs of the underlying communication structure; thus, the system components can communication with each other without considering the implementation details. This layered-stack model facilitates the separation of communication and computation and assists IP-reuse design methodologies, as well as fine-grain optimization of NoC components.

1.1.3

NoC Switching Techniques

Switching techniques determine how data flows through the routers and define the granularity of data transfer. Three switching techniques have been used in NoCs – circuit switching, packet switching and a hybrid version. In circuit switching, a circuit is set up from source to destination using a resource reservation method. Thus, there is no network contention during data propagation. Packets of different flows (i.e., circuit paths) attempting to use a link at the same time result in contention. Circuit switching has high initial latency, but it is appropriate when data is sent very often (e.g., SOCBus [17]). Circuit switching reserves a complete path before data is sent. As a result, it is easy to guarantee the quality of service (QoS).

1.2 Reliability Challenges in Scaled Technology

5

Packet switching can be divided into three categories – store and forward (SAF), virtual cut through (VCT) and wormhole (WH) switching. SAF checks the availability of the next hop and stores the overall packet until the packet is entirely received. VCT only checks the availability of the next hop and does not wait for the packet to be entirely received. In a packet switching network, large buffers are needed to meet performance requirements. Typically, the more buffers are used, the better performance can be obtained. Both SAF and VCT require a buffer space that is sufficient for at least one packet. WH switching has been widely employed in NoCs to reduce the area cost induced by buffers. The hybrid switching technique leverages the advantages and disadvantages of the circuit and packet switching techniques [18].

1.1.4

NoC Flow Control

Flow control defines the way that packets traverse the network. It usually involves buffer location, buffer management and network resource allocation. Efficient flow control can speed up the packet propagation over the network and can also reduce network resource idle time. Flow control methods can be categorized into withoutmemory [19–21] or with-memory [22–29]. Credit-based flow control once used in ATM networks is commonly adopted in NoCs now, at the cost of buffer resources [22–24]. Based on credit-based flow control, other techniques are also applied to some NoCs, such as Paris, NoCGEN and Xpipes. Paris [25], an extended version of SoCIN [26], utilizes handshake signals to create connections between sender and receiver. NoCGEN [27] uses a request, grant and ready handshake to enable flow control in point-to-point connections. Xpipes NoC [28] employs the ACK/NACK flow control method to pipeline links; the received NACK feedback requests retransmission. In Ref. [29], Tamhankar et al. proposed the T-error protocol to deal with timing errors caused by aggressively tackling timing constraints (to improve performance). Straight forward flow control, STALL/Go, T-error and ACK/NACK flow control schemes have been compared in Ref. [30].

1.2

Reliability Challenges in Scaled Technology

Relaxing the requirement for 100% correctness in both transient and permanent failures of signals, logic values, devices, or interconnects may reduce the cost of manufacturing, verification, and testing. – ITRS 2003 [31]

Deep submicron technology (DSM) makes the integration of billions of transistors on a single die possible. In such infrastructure, more and more IP cores are available for parallel processing, which dramatically improves the speed of signal processing.

6

1 Introduction

Fig. 1.4 Alpha particle strike on a transistor

Unfortunately, these benefits are optimistic. Although NoCs bring the advantage of structural regularity, scalability, modularity and efficient communication, they still face considerable reliability challenges. Because of various noise sources, the reliability issue becomes increasingly important in current technology and for the future.

1.2.1

Transient Errors

Transient errors involve unexpected changes to data rather than damages to the physical media (e.g., interconnect link [32–36], storage elements and computation logic paths [37–43]). These errors may have a very short lifetime; thus, if the operation (transmission, write/read or computation) is repeated, the output of the physical media may become correct. Transient errors may be caused by supply voltage fluctuation induced voltage glitches, crosstalk coupling [44–53], particle strike induced single-event upsets (SEU) [54–58] and single-event transients (SET) [57, 59]. Impurities in electronic materials contain high density atoms, which emit alpha particles through radioactive decay [61]. The induced alpha particles inject charges, changing logic values at circuit nodes, as shown in Fig. 1.4 [60]. Some chip packaging materials contain radioactive contaminants, emitting alpha particles. Packaging materials with alpha particle emissions greater than 0.001 counts per hour per cm2 (cph/cm2) should not be used for reliability-critical circuits [61]. Approximately 0.004% of the alpha particle strikes caused by package materials induce logic upsets [62]. As technology scales, the increasing number of circuit nodes and decreasing critical charge will increase the probability of alphaparticle-induced errors.

1.2 Reliability Challenges in Scaled Technology

7

Even with the improvement of packaging materials, soft errors cannot be eliminated. If an energetic neutron at the Earth’s surface is captured by the nucleus of an atom in a chip and this process produces an alpha particle and oxygen nuclei, there is a ~95% probability of causing a soft error [63]. In modern devices, neutrons induce more soft errors than chip packaging materials, especially in aerospace applications. Computers working on mountain tops experience over 10 times soft errors than those at sea level [64]. The soft error rate for the electronic devices in an aircraft increases to 300 times over sea level [64]. In addition, neutrons interacting with their surroundings to reach thermal equilibrium lead to soft errors, as well. This is significantly important for electronic devices in medical applications. For example, high energy cancer radiation therapy using photon beams emits neutrons. The scattered neutrons do not disappear; instead, they are bounced between walls, resulting in the thermal neutron flux in the treatment room 4  107 higher than that in a normal environment [65, 66]. Electromagnetic interference (EMI) is caused by outside electronic devices or on-chip materials (e.g., RF components of mixed signal ICs) [67]. On-chip interconnect wires are relatively long compared to most other on-chip wires, and they are thus more likely to be the EMI victims. With increased integration of complex blocks on a single chip, the circuit will be susceptible to larger EMI levels. In addition to external noise sources, circuit normal operation is interfered by internal noise sources, such as power/ground voltage fluctuation and crosstalk coupling. In a real chip, the power (ground) is not ideally equal to Vdd (Vss). Fluctuation on power (ground) affects the charging capability (discharging capability) of PMOS (NMOS), resulting in the delay uncertainty [68]. If the uncertainty is large enough to be captured by a register, there occurs a logic error. Because of shrinking wire width and pitch size, the coupling noise interferences are getting worse [44, 45, 49, 53]. In DSM and nanometer regimes, crosstalk becomes one of the major noise sources for interconnect [69, 70]. As shown in Fig. 1.5 [71], the peak noise voltage induced by crosstalk can be more than 20% of the supply voltage. Consequently, the voltage glitch caused by crosstalk has a potential to create a logic error. Design for the worst case is simple and safe, but not cost-effective. In reality, the error rate of transient errors varies with location and time. The experiments performed in the UoSAT-2 spacecraft launched into a polar orbit of altitude 700 km in 1984 indicated that the system experienced more soft errors in the South-Atlantic Anomaly region than in other regions, as shown in Fig. 1.6a [72]. The relationship between the particle flux and the altitude has been summarized in Ref. [76]. By examining the number of captured soft errors over time, HarboeSørensen et al. observed the error rate in October is higher than that in other months, as shown in Fig. 1.6b [72]. This is because the sunspot activity inversely influences the magnitude field of the Earth; the more solar flux provides the Earth with more additional shielding effect against the high-energy cosmic rays. Modeling and experiments performed by IBM also demonstrate that soft error rates in different cities are different, as shown in Fig. 1.7.

Fig. 1.5 Noise waveforms of crosstalk coupling between two coupled lines

Fig. 1.6 Soft error rate varies with (a) location and (b) time

Fig. 1.7 Alpha-particle and cosmic contributions to the signal-event-upset rate

1.2 Reliability Challenges in Scaled Technology

9

Fig. 1.8 Error rates for different supply voltages and noise variances

The error rate also changes with the operation conditions, such as supply voltage and temperature. Li et al. [73] use a single Gaussian noise source to model the different noise sources impacting the bus line. As shown in Fig. 1.8, a lower supply voltage or a larger noise interference voltage results in a higher bit error rate [73]. Transient errors are typically managed by error detection with retransmission, forward error correction or muted in the datalink layer. Reviews for transient error management will be provided in Chap. 2.

1.2.2

Permanent Errors

Transient errors disappear after a certain time, while permanent errors do not vanish until the sources of permanent errors are removed. Imperfect manufacturing process [74–78] and device wearout [79, 80] induce faults such as stuck-at faults – where the output is stuck at logic ‘0’ or ‘1’, regardless of the input [74]; bridging faults – two adjacent signals shorted together [81, 82]; open faults – an interconnect is broken [75, 83]; delay faults – signal arrival time is slower than normal, exceeding the timing requirement. Device wearout typically occurs later in the lifetime because of various mechanisms, for instance, electromigration, hot carries degradation, and time-dependent dielectric breakdown.

10

1 Introduction

Fig. 1.9 Permanent and intermittent error sources: (a) bridging faults, (b) mousebite, crack, metal sliver, and hillock

Bridging between two lines (shown in Fig. 1.9a [77]) causes bridging faults. Electromigration, mousebites and hillock in the metal wires as shown in Fig. 1.9b eventually result in open circuits and short circuits, respectively. The mousebite wire has a narrower wire width than normal, resulting in a higher current density than other places and leading to more severe electromigration (eventually causing an open circuit). In contrast, the hillock leads to a lower current density than other normal places; it deteriorates through electromigration and finally results in a shorted circuit. Permanent errors are typically managed by replacing the unusable components with spare devices, or detouring around the broken region. Permanent error management extends chip lifetime and improves chip yield rate, reducing manufacturing cost. State-of-the-art permanent error management methods are summarized in Chap. 2.

1.2.3

Intermittent Errors

Intermittent error occurs repeatedly at the same location; it typically appears in a burst way and lasts several cycles. This type error can be caused by factors, such as temperature variation, voltage fluctuation, process variations and manufacturing residuals [38]. Changing the operation environment or replacing the faulty component can eliminate the intermittent error. Intermittent error sometimes precedes the presence of permanent errors, if the error is induced by device aging. It is notoriously difficult to identify and recover the intermittent errors, because its occurrence depends on the inputs and unpredictable operation environment, as well as the similarity to transient and permanent errors. Since most of intermittent error typically precedes the permanent errors, we regard it as permanent errors here.

1.4 Book Organization

1.3

11

Reliability, Performance and Energy Tradeoffs

Spatial, temporal and information redundancies have been exploited to manage transient and permanent errors in different types of reliability-aware systems [11]. As shown in Table 1.1, fault tolerant techniques are not free. Mainstream low-cost systems have strict constraints on the overhead induced by the applied reliabilityimprovement techniques. In addition, to manage the overwhelming system complexity, the NoC properties, such as structural regularity, modularity and layering model, enable use of advanced error control methods to create fault-tolerant interconnections. In transient error management, powerful error control coding achieves higher error resilience than simple error control coding, at the cost of higher energy and area overhead. Permanent error management has a similar dilemma. Fault tolerant routing takes advantage of multiple routes to transmit multiple message copies or re-route the message around a faulty link. Links and router with permanent errors may be abandoned, wasting bandwidth, increasing latency [85] or increasing energy [84].

1.4

Book Organization

The challenges of reliable NoC design in deeply scaled technologies are summarized in the previous subchapter. In the reminder of this book, multi-layer transient and permanent error control design and simulation methods will be presented to address the reliability issues in nanoscale NoCs. The cooperation among three layers involved in our methods is shown in Fig. 1.10. In Chap. 2, previous datalink layer error recovery schemes and error control coding methods for transient errors are summarized. Existing physical layer techniques and network layer approaches for permanent errors are discussed, as well. In Chap. 3, we present an adaptive error control method for switch-to-switch links in nanoscale NoCs to manage reliability, throughput and energy. Unlike previous works, the proposed method adjusts both error detection and correction simultaneously at runtime. For a given application or predicted noise scenario, an appropriate error control scheme is selected for reliable message transmission. When link conditions degrade, more powerful error detection and correction are temporarily provided to recover the previous message. To achieve this adaptation, we implement a configurable M-error correction, 2M-error detection (MEC2MED) code, combined with a hybrid automatic repeat request (HARQ) retransmission policy. Based on the approach discussed in Chap. 3, we present a dual-layer (physical and datalink layer) transient and permanent error co-management method in Chap. 4. This co-management method uses the idle wires for configurable error control coding to replace permanently unusable wires, reducing the number of redundant wires. Furthermore, a packet re-organization algorithm that cooperates

Table 1.1 Different types of reliability-aware systems Type Issues Goal Long-life system Difficult or expensive Maximize mean time to to repair failure (MTTF) Reliable realErrors or delays can Fault masking capability time systems be catastrophic High-availability Downtime High availability systems very costly High-integrity Data corruption very High data integrity systems costly Mainstream lowReasonable level of Meet failure rate cost systems failures acceptable expectations at low cost Examples Satellites, spacecraft, implanted biomedical devices Aircraft, nuclear power plants, air bag electronics, radar Reservation systems, stock exchanges, telephone systems Banking, transaction processing, databases Consumer electronics, personal computers

No single point of failure; selfchecking pairs; fault isolation Check pointing, time redundancy, ECC; redundant disks None; memory ECC; bus parity

Triple modular redundancy (TMR)

Techniques Dynamic redundancy

12 1 Introduction

1.4 Book Organization

13

Fig. 1.10 Multi-layer cooperative error control

with a shortened error control coding method is proposed to support low-latency split transmission. Our co-management method provides the most energy efficient configuration for the current transient and permanent error condition, with minor performance degradation and area overhead. In Chap. 5, we address the transient error in datalink and network layers. We employ end-to-end error control in the network layer in low noise condition, and enhance the error control capability in high noise condition by adding hop-to-hop error control in datalink layer. One major contribution of this method is a protocol to switch between single-layer error control and dual-layer error control at runtime, based on the detected noise condition or system requirements. Simply combining end-to-end error control with hop-to-hop error control typically results in huge energy consumption. In our method, we employ the concept of product codes to perform dual-layer cooperative error control. Evaluation of residual error rate, latency and energy are provided. Traffic traces obtained from benchmark suit have been used to examine the dual-layer method, in terms of handling imbalance traffic load and asymmetric error distribution over the network. In Chap. 6, we introduce a flexible parallel simulator to evaluate the impact of different error control methods on NoC performance and energy consumption. Different error control schemes can be inserted to the simulator in a plug-andplay manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault

14

1 Introduction

injection rates, fault types, fault injection locations and faulty flit types. The flexible simulation environment provided by this simulator allows examination of the efficiency of different error control schemes under different fault scenarios and traffic injection rates, as well as investigation of NoC-based chip multi-processor (CMP) system. Conclusions and future directions are presented in Chap. 7.

References 1. Rusu S, Tam S, Muljono H, Stinson J, Ayers D, Chang J, Varada R, Ratta M, Kottapalli S (2009) A 45 nm 8-core enterprise Xeon® processor in. Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 56–57 2. Kurd NA et al (2010) Westmere: A family of 32 nm IA processors. in Proc IEEE Intl SolidState Circuits Conf-Digest of Technical Papers 96–97 3. Shin JL et al (2010) A 40 nm 16-core 128-thread CMT SPARC SoC processor. in Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 98–99 4. Wendel DF et al (2011) POWER7TM: A highly parallel, scalable multi-core high-end server processor. IEEE Journal of Solid-State Circuits 46:145–161 5. Anders MA et al (2010) A 41 Tb/s bisection-bandwidth 560 Gb/s/W streaming circuitswitched 8  8 mesh network-on-chip in 45 nm CMOS. in Proc IEEE Intl Solid-State Circuits Conf-Digest of Technical Papers 110–111 6. Dally WJ, Towles B (2001) Route Packets, Not Wires: On-Chip Interconnection Networks. in Proc 38th Design Automation Conference (DAC’01) 684–689 7. Sgroi M et al (2001) Addressing the system-on-a-chip interconnect woes through communicationbased design. in Proc 38th Design Automation Conference (DAC’01) 667–672 8. Benini L, De Micheli G (2002) Networks on Chips: A new SoC paradigm. Computer 35:70–78 9. Henkel J, Wolf W, Chakradhar S (2000) Network on chip: An architecture for billion transistor era. in Proc 18th IEEE NorChip Conf 166–173 10. Benini L, De Micheli G (2001) Powering Networks on chips. in Proc Intl Symp System Synthesis 33–38 11. Jantsch A, Tenhunen H (2003) Networks on Chip. Kluwer Academic Publishers 12. Kim J, Park D, Nicopoulos C, Vijaykrishnan N, Das CR (2005) Design and analysis of an NoC architecture from performance, reliability and energy perspective. in Proc ACM/IEEE Symp on Architectures for Networking and Communications Syst (ANCS’05) 173–182 13. Salminen E, Kulmala A, Hamalainen TD (2007) On network-on-chip comparison. in Proc 10th Euromicro Conf on Digital Syst Design Architectures, Methods and Tools (DSD 2007) 503–510 14. Salminen E, Kulmala A, Hamalainen TD (2008) Survey of network-on-chip proposals. White paper, OCP-IP, 1–13 15. Agarwal A, Iskander C, Shankar R (2009) Survey of Network on Chip (NoC) Architectures & Contributions. Engineering, Computing and Architecture 3:1–15 16. Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) Cost considerations in Network on Chip. Integration - the VLSI journal, 38:19–42 17. Wiklund D, Liu D (2003) Socbus: switched network on chip for hard real time embedded systems. in Proc Intl Parallel and Distributed Processing Symp 1–8 18. De Micheli G, Benini L (2007) Networks On Chips. Morgan Kaufmann, San Francisco 19. Nilsson E, Millberg M, Oberg J, Jantsch A (2003) Load distribution with the proximity congestion awareness in a network on chip. in Proc DATE’03 1126–1127

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20. Liu J, Zheng L-R, Tenhunen H (2003) A guaranteed-throughput switch for network-on-chip. in Proc Intl Symp System-on-chip 31–34 21. Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. in Proc DATE’04 8890–895 22. Khorsandi S, Leon-Garcia A (1996) Robust non-probabilistic bounds for delay and throughput in credit-based flow control. in INFOCOMM 677–584 23. Zeferino CA, Kreutz ME, Carro L, and Susin AA (2002) A study on communication issues for systems-on-chip. in Proc Symp Integr Circuits and Syst Design 121–126 24. Radulescu A et al (2005) An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans on Computer-Aided Design of Integr Circuits and Syst (TCAD) 24:4–17 25. Zeferino C A, Santo FGME, Susin AA (2004) Paris: a parameterizable interconnect switch for networks-on-chip. in Proc Symp On Integr Circuits and Syst Design, 204–209 26. Zeferino A, Susin AA (2003) SoCIN: a parametric and scalable network-on-chip. in Proc Symp On Integr Circuits and Syst Design 169–174 27. Chan J, Parameswaran S (2004) Nocgen: a template based reuse methodology for networks on chip architecture. in Proc Intl Conf on VLSI Design 717–720 28. Bertozzi D, Benini L (2004) Xpipes: a network on chip architecture for gigascale systems-onchip. IEEE Circuits and Syst Magazine 4:18–31 29. Tamhankar RR, Murali S, De Micheli G (2005) Performance driven reliable link design for networks on chips. in Proc Asia and South Pacific Design Automation Conf (ASP-DAC’05) 749–754 30. Pullini A, Angiolini F, Bertozzi D, Benini L (2005) Fault tolerance overhead in Network-onchip flow control schemes. in Proc Symp On Integr Circuits and Syst Design (SBCI’05) 4–7 31. ITRS (2003) http://www.itrs.net/Links/2003ITRS/Design2003.pdf 32. Ho R, Mai KW, Horowitz MA (2001) The future of wires. Proc IEEE, 89:490–504 33. Ho PS, Lee Ki-Don, Yoon S, Wang Guotao (2004) Reliability challenges and recent advance for Cu Interconnects. in Proc 5th Intl Conf on Thermal and Material Simulation and Experiments in Micro-electronics and Micro-Syst 15–16 34. Mondal M, Wu X, Aziz A, Massoud Y (2006) Reliability analysis for on-chip networks under RC interconnect delay variation. in Proc Nanonet 1–5 35. Ismail IY (2008) Interconnect design and limitations in nanoscale technologies. in Proc ISCAS’08 780–783 36. Singhal R, Choi Gwan, Mahapatra R (2006) Information theoretic approach to address delay and reliability in long on-chip interconnects. in Proc ICCAD’06 310–314 37. Abraham JA and Fuchs WK (1986) Fault and error models for VLSI. Proc IEEE 74:639–654 38. Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 23:14–19 39. Karnik T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans on Dependenable and Secure Computer 1:128–143 40. Maheshwari A, Koren I, Burleson W (2004) Accurate estimation of soft error rate (SER) in VLSI circuits. in Proc IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems (DFT’04) 377–385 41. Chandra V, Aitken R (2008) Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS. in Proc DFT’08 114–122 42. Calhoun BH et al (2008) Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proc IEEE 96:343–365 43. Owens JD et al (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27:96–108 44. Vittal A, Chen LH, Marek-Sadowska M, Wang K-P, Yang S (1999) Crosstalk in VLSI interconnections. IEEE Trans on Computer-Aided Design of Integr Circuits and Syst (TCAD) 18:1817–1824

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1 Introduction

45. Aingaran K et al (2000) Coupling noise analysis for VLSI and ULSI circuits. in Proc IEEE International Symposiums on Quality Electronic Design (ISQED’00) 485–489 46. Duan C, Calle VHC, Khatri SP (2009) Efficient on-chip crosstalk avoidance CODEC design. IEEE Trans Very Large Scale Integr (VLSI) Syst 17:551–560 47. Li L, Vijaykrishnan N, Kandemir M, Irwin MJ (2004) A crosstalk aware interconnect with variable cycle transmission. in Proc Design, Automation Test in Europe (DATE’04) 102–107 48. Patel KN, Markov I L (2004) Error-correction and crosstalk avoidance in DSM busses. IEEE Trans Very Large Scale Integr (VLSI) Syst 12:1076–1080 49. Rossi D, Metra C, Nieuwland AK, Katoch A (2005) Exploiting ECC redundancy to minimize crosstalk impact. IEEE Design & Test of Computers 22:59–70 50. Pande PP, Ganguly A, Feero B, Belzer B, Grecu C (2006) Design of low power & reliable networks on chip through joint crosstalk avoidance and forward error correction coding. in Proc IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems (DFT’06) 466–476 51. Ganguly A, Pande PP, Belzer B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Test 24:67–81 52. Duan C, Tirumala A, Khatri SP (2001) Analysis and avoidance of crosstalk in on-chip buses. in Proc Hot Interconnects 133–138 53. Fu B, Ampadu P (2010) Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction. IEEE Trans on Circuits and Systems–II: Express Briefs 57:399–403 54. Shanbhag N, Soumyanath K, Martin S (2000) Reliable low-power design in the presence of deep submicron noise. in Proc ISLPED’00 295–302 55. Frantz AP, Cassel M, Kastensmidt FL, Cota E, Carro L (2007) Crosstalk- and SEU-aware networks on chips. IEEE Design & Test Computers, 24(4):340–350 56. Hoyos SE, Evans HDR, Daly E (2004) From satellite Ion flux data to SEU rate estimation. IEEE Trans Nuclear Science, 51:2927–2935 57. Zhang M, Shanbhag NR (2006) Soft-error-rate-analysis (SERA) methodology. IEEE Trans Computer-Aided Design of Integr Circuits and Syst (TCAD) 25:2140–2155 58. Bidokhti N (2010) SEU Concept to Reality (Allocation, Prediction, Mitigation). in Proc Reliability and Maintainability Symp (RAMS) 1–5 59. Krishnamohan S, Mahapatra NR (2004) A highly-efficient technique for reducing soft errors in static CMOS circuits. in Proc ICCD’04 126–131 60. Mastipuram R, Edwin CW (2004) http://www.cs.columbia.edu/~cs4823/handouts/soft-errorspaper.pdf 61. Lantz L II (1996) Soft errors induced by alpha particles. IEEE Trans Reliability 45:174–179 62. Heidel DF et al (2008) Alpha-particle-induced upsets in advanced CMOS circuits and technology. IBM J Research and Development 52:225–232 63. Ziegler JF (1996) Terrestrial cosmic rays. IBM J Research and Development 40:19–40 64. Gordon MS et al (2004) Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground. IEEE Trans on Nuclear Science 51:3427–3434 65. Wilkinson JD, Bounds C, Brown T, Gerbi B, Peltier J (2005) Cancer radiotherapy equipment as a cause of soft errors in electronic equipment. IEEE Trans Device and Materials Reliability 5:449–451 66. Franco L et al (2005) SEUs on commercial SRAM induced by low energy neutrons produced at a clinical linac facility. in Proc RADECS’05 67. Khazaka R, Nakhla M (1998) Analysis of high-speed interconnects in the presence of electromagnetic interference. IEEE Trans Microwave Theory Tech 46:940–947 68. Hashimoto M, Yamaguchi J, Sato T, Onodera H (2005) Timing analysis considering temporal supply voltage fluctuation. in Proc ASP-DAC’05 1098–1101 69. Balasubramanian A et al (2008) Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Trans Nuclear Science 55:2079–2084

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Chapter 2

Existing Transient and Permanent Error Management in NoCs

Error control schemes combined with various error control codes are typically employed to handle the transient errors. Physical layer techniques, such as spare wire replace and split transmission, and network layer approaches, such as faulttolerant routing have been widely investigated for permanent error management. In this chapter, we will review the state-of-the-art techniques for transient and permanent error management in NoCs.

2.1

Error Control Schemes

Three typical error control schemes are used in on-chip communication: error detection combined with automatic repeat request (ARQ), hybrid ARQ (HARQ) and forward error correction (FEC). The generic diagram for transmitter and receiver is shown in Fig. 2.1. ARQ and HARQ use not acknowledge (NACK) signal to request transmitter resending message. FEC does not need acknowledgement signal to recover detected error; instead, it corrects error immediately if error is identified in receiver.

2.1.1

Automatic Repeat Request

In error detection plus automatic repeat request (ARQ) scheme, the decoder in the receiver performs error detection. If an error is detected, retransmission is requested. This scheme is proved as the most energy-efficient method for reliable on-chip communication, if the error rate is rarely small [1]. There are three types of ARQ – stop-and-wait (SW), go-back-N (GBN) and selective-repeat (SR) [2]. As shown in Fig. 2.2a, SW ARQ does not transmit new data until the positive acknowledgement is received. During the time waiting for Q. Yu and P. Ampadu, Transient and Permanent Error Control for Networks-on-Chip, DOI 10.1007/978-1-4614-0962-5_2, # Springer Science+Business Media, LLC 2012

19

Fig. 2.1 Generic diagram for error control scheme

Fig. 2.2 Types of ARQ scheme: (a) stop-and-wait, (b) go-back-N, (c) selective-repeat

2.1 Error Control Schemes

21

ACK/NACK, the transmitter is in idle mode; therefore, this scheme results in long latency and low throughput. Different with SW ARQ, GBN ARQ keeps transmitting data while the transmitter is waiting for the feedback. If an error is detected at the receiver, the data transmitted in the previous NR cycles will be retransmitted, shown in Fig. 2.2b. Here, NR is the round trip delay. GBN ARQ can achieve a high throughput in low error rate conditions, because limited data are retransmitted. As the error rate increases, SR ARQ becomes more efficient than SW ARQ and GBN ARQ. SR ARQ only retransmits the erroneous data to improve the throughput, but requires a large buffer to store previous date until the missing portion arrives, as shown in Fig. 2.2c.

2.1.2

Hybrid Automatic Repeat Request

Hybrid automatic repeat request (HARQ) attempts to correct the detected error; if the number of errors exceeds the codec error correction capability, retransmission is requested. This method achieves more throughput than ARQ, at the cost of more decoder area and redundant bits [2]. For example, extended Hamming code can detect and correct errors; thus, this code has been widely employed in HARQ error control scheme for on-chip interconnects. Depending on the amount of retransmission information, HARQ are divided into type-I HARQ and type-II HARQ [2, 3]. The former one transmits both the error detection and correction check bits. In contrast, the latter one transmits parity checks for error detection in the first transmission. The check bits for error correction are transmitted in the second transmission, if necessary. As a result, type-II HARQ consumes less power consumption than type-I HARQ [4].

2.1.3

Forward Error Correction

Forward error correction (FEC) is typically designed for the worst-case noise condition. Different with ARQ and HARQ, no retransmission is needed in FEC [4, 5]. The decoder always attempts to correct the detected errors. If the error is beyond the codec’s capability, decoder failure occurs. Block FEC codes achieves better throughput than ARQ and HARQ; however, this scheme designed for the worst-case condition wastes energy if the noise condition is favorable. Because of encoding/decoding with previous saved input and current input, convolutional code increases coding strength but yields significant codec latency [6]; thus, FEC with convolutional code is not suitable for on-chip interconnect network. In this chapter, we focus on the block codes.

22

2.2

2 Existing Transient and Permanent Error Management in NoCs

Error Control Coding

Error control coding is essential for the error control scheme mentioned in the previous subchapter. The discipline of error control coding is derived from information theory that is discovered by Claude Shannon in 1948 [7]. Shannon proved that there exist error control codes that facilitate achieving a virtual error-free communication channel as long as the transmission rate is less than the channel capacity C, bits per second. Shannon-Hartley theorem describes the channel capacity for an additive white Gaussian noise (AWGN) channel is expressed in (2.1). C ¼ B log2 ðS=N þ 1Þ

(2.1)

where S/N is signal-to-noise ratio and B is channel bandwidth. Thanks to the advanced integrated circuit design techniques and manufacturing process, error control coding can be applied not only to wireless communication and data storage applications [8], but also to on-chip interconnect [9–14]. With error control coding, we can reduce the supply voltage of the interconnect driver and receiver while still maintaining the original transmission throughput and ensuring the system reliability. We assume that a block of k bits is encoded to an n-bit codeword (n > k). For a binary code, there are 2k codewords in the codebook. If the received codeword does not belong to the codebook, an error must be injected on codeword during transmission. By searching in the codebook, the decoder is capable of detecting or correcting the error. Figure 2.3 shows the decoding spheres demonstrating the process of decoding. Each point represents a codeword. The parameter t is the radius for the sphere where a valid codeword locates; if the received vector is within the sphere, error can be detected. The smallest number of different bits between two valid codewords is Hamming distance dmin, which is a metric to judge a code’s error detection and correction capability. For a code with the Hamming distance dmin, all dmin  1 bit error patterns can be detected. Assume that the codeword C is transmitted. If the received codeword

Fig. 2.3 Decoding spheres

2.2 Error Control Coding

23

is Y (shown in Fig. 2.3), the decoder can detect the error injected during the transmission. This is because Y is an invalid codeword for the given codebook but within the sphere of the codeword C. If the received codeword is D, the error happened in transmission cannot be discovered because D is also a valid codeword in the codebook. To correct the detected error, the radius t must be no greater than
d 1 min . Resume the previous example. If the codeword Z is received, the decoder 2 might correct the codeword to D, because Z is within the sphere of the valid codeword D in the codebook. This is a decoding failure. Although it recognizes the error if X is received, the decoder is not able to correct the error because X is not belong to any valid codeword’s sphere. The simplest error detection code is single parity check code that has a Hamming distance of 2. Hamming code (n, k) has a dmin of 3 that can be used either error detection code (detecting 1- and 2-bit errors), or error correction code (correcting 1-bit errors). Extended Hamming code can detect 1- and 2-bit errors and correct 1-bit errors [6]. Cyclic redundancy codes are used to detect burst errors [6]. More complex codes, such as binary Bose-Chaudhuri-Hocquenghem (BCH) codes [15], are capable of correcting more error bits at the cost of large area, delay and power consumption. In this subchapter, we summarize popular codes that have been applied to NoC links.

2.2.1

Single Parity Check Code

Single parity check code is a simple block code, which appends an additional parity check bit after the original message bits. Depending on the way the additional check bit is calculated, single parity check code is divided into odd parity check code and even parity check code. If the total number of ‘1’ in the message is an odd number and party check bit is ‘1’, this is odd parity check code; otherwise, it is an even parity check code. Because of its linearity, even parity check code is more popular than odd parity check code. With one additional check bit, single parity check increases the minimum distance to 2 and achieves 1-bit error detection capability (but no error correction capability). This code combined with retransmission can be applied to on-chip interconnect operating in low noise region [1, 16].

2.2.2

Hamming Code

Hamming code is another simple linear block code. For a standard Hamming(n, k) code, codeword n and original message k are satisfied with (2.2) and (2.3) n ¼ 2r  1

(2.2)

k = 2r  1  r

(2.3)

24

2 Existing Transient and Permanent Error Management in NoCs

Table 2.1 Several Hamming codes and their variants Check bit Standard Hamming Shortened Hamming (r ¼ n  k) code (n, k) code (n, k) 3 (7, 4) – 4 (15, 11) (12, 8) 5 (31, 26) (21, 16) 6 (63, 57) (38, 32) 7 (127, 120) (71, 64) 8 (255, 247) (136, 128) 9 (511, 502) (265, 256) 10 (1,023, 1,013) (522, 512)

Ex-shortened Hamming code (n, k) – (13, 8) (22, 16) (39, 32) (72, 64) (137, 128) (266, 256) (523, 512)

in which, the positive integer r is the number of check bits. For a systematic Hamming code, the generator matrix is constructed below Gkn ¼ ½Ik jPkðnkÞ 

(2.4)

where Ik and PkðnkÞ are identity and parity matrices, respectively. Thus, the Hamming codeword C is obtained with equation C1n ¼ m1k  Gkn

(2.5)

in which, m1k is the input message. In the decoder, the received codeword is computed with the parity check matrix HðnkÞn to obtain the syndrome vector S1ðnkÞ . If the syndrome vector is not zero and matches to one of the H column, the error bit within the codeword is identified. HðnkÞn ¼ ½PTkðnkÞ jIðnkÞ 

(2.6)

S1ðnkÞ ¼ m1n  HTðnkÞn

(2.7)

The minimum distance of Hamming code is 3, so Hamming code can detect 2-bit errors or correct 1-bit errors. Adding one parity check bit on the top of Hamming codeword, we can extend the Hamming code and increase improves the minimum distance to 4. Consequently, the extended Hamming code is capable detect 3-bit errors, or, correct 1-bit errors and detect 2-bit errors (i.e. single-error correction double error detection, SECDED). Standard Hamming code has strict constraints on the original message width, which is not flexible for NoC link design. By truncating the generator matrix, the codeword for standard Hamming code can be modified as shown in Table 2.1. To obtain the shortened Hamming code, one can subtract the same amount of binary bits from codeword and original message. Consequently, the input width for the

2.2 Error Control Coding

25

shortened Hamming code can be modified to a power of 2, as shown in third column of Table 2.1. The shortened version of Hamming codewords can further be extended by adding an additional check bit, as shown in the fourth column of Table 2.1. The shortened Hamming code maintains the same minimum Hamming distance but has flexible input width, at the cost of reducing code rate. Now, let’s see how to create a shortened Hamming code. Given a Hamming (15, 11) with generator matrix G1115 below. 2

G1115

100000000001100

3

60 1 0 0 0 0 0 0 0 0 0 0 0 1 07 6 7 6 7 60 0 1 0 0 0 0 0 0 0 0 1 1 1 07 6 7 6 7 60 0 0 1 0 0 0 0 0 0 0 0 1 1 07 6 7 60 0 0 0 1 0 0 0 0 0 0 1 0 0 17 6 7 6 7 ¼ 60 0 0 0 0 1 0 0 0 0 0 0 1 0 17 6 7 60 0 0 0 0 0 1 0 0 0 0 1 1 0 17 6 7 6 7 60 0 0 0 0 0 0 1 0 0 0 0 0 1 17 6 7 60 0 0 0 0 0 0 0 1 0 0 1 0 1 17 6 7 6 7 40 0 0 0 0 0 0 0 0 1 0 0 1 1 15 000000000011111

(2.8)

To obtain the generator matrix for the shortened Hamming code, HM(12, 8), one can remove the first three rows and the first three columns in G1115. Consequently, G812 is composed of the bold elements in G1115. The extended version of HM(12, 8) has one more column ‘1’ vector in the generator matrix (i.e. G813) than G812. 2

G813

1000000001101

3

6 7 60 1 0 0 0 0 0 0 1 0 0 1 17 6 7 60 0 1 0 0 0 0 0 0 1 0 1 17 6 7 6 7 60 0 0 1 0 0 0 0 1 1 0 1 17 7 ¼6 60 0 0 0 1 0 0 0 0 0 1 1 17 6 7 6 7 60 0 0 0 0 1 0 0 1 0 1 1 17 6 7 60 0 0 0 0 0 1 0 0 1 1 1 17 4 5 0000000111111

(2.9)

Similar principle applies to the coded shorten and extended codes with larger inputs For low transient noise conditions, Hamming codes and their variants have been widely used to protect link errors [1, 14, 16–19]. Other SECDED code (e.g. Hsiao code in [20]) can also be used for on-chip interconnect.

26

2 Existing Transient and Permanent Error Management in NoCs

2.2.3

Cyclic Redundancy Check Code

A linear block code is a cyclic code C if any cycle shift of this code is another codeword in the code set C. Given the input polynomial m(x) and generator polynomial g(x), the non-systematic codeword C (n, k) is constructed with (2.12). mðxÞ ¼ m0 þ m1 x þ m2 x2 þ    mk xk

(2.10)

gðxÞ ¼ 1 þ g1 x þ g2 x2 þ    gr1 xr1 þ xr

(2.11)

cðxÞ ¼ mðxÞ  gðxÞ ¼ c0 þ c1 x þ c2 x2 þ    cn xn

(2.12)

The systematic codeword can be computed with (2.13). cðxÞ ¼ mðxÞ  xnk þ RgðxÞ ½mðxÞ  xnk 

(2.13)

where, Rg(x)[ ] represents the reminder of dividing the polynomial in the bracket by g(x). The reminder is the parity check bits for the systematic cyclic codeword [6]. A simple linear feedback shift register (LFSR) can realize the function expressed in (2.13), at the cost of large latency overhead. Cyclic redundancy check (CRC) code is a class of cyclic code, whose generator polynomial g(x) ¼ (x + 1)*p(x)  and p(x) is a primitive polynomial. m For GFðpm Þ ¼ 0; 1; a, a2 ; a3 ;::: ap 2 , the primitive polynomial is the minimal polynomial that has a root in GF(pm). To reduce the codec latency, parallel CRC implementations have been investigated [21–23]. In this book, we employ the tool [24] to generate the hardware description code for our experimental uses. Because of single-error and burst error detection capability, CRC has been applied to networks-on-chip links to detect multi-bit transient errors [1, 16, 25].

2.2.4

Bose-Chaudhuri-Hocquenghem Code

Bose-Chaudhuri-Hocquenghem (BCH) code is one subset of cyclic codes, and its minimum Hamming distance is greater than 2td + 1 (td, number of correctable error bits in codeword). For a binary BCH code (n, k, dmin), the generator polynomial   gðxÞ ¼ LCM fb ðxÞ; fbþ1 ðxÞ;    fbþ2td 1 ðxÞ

(2.14)

in which, LCM means least common multiple, fðxÞis the minimal polynomial, k and n is satisfied with k ¼ n  deg½gðxÞ

(2.15)

2.2 Error Control Coding

27

Table 2.2 Several binary BCH codes and their variants’ generator polynomials Standard binary Shorten binary Primitive BCH code BCH code polynomial f(x) Generator polynomial g(x) x28 + x27 + x26 + x23 + x20 BCH (127, 99) BCH(92, 64) x7 + x3 + 1 + x19 + x18 + x13 + x10 + x9 + x7 + x5 + x4 + x3 + 1 8 4 3 32 x + x31 + x30 + x29 + x27 BCH(225, 223) BCH(160, 128) x +x +x + x2 + 1 + x26 + x25 + x22 + x20 + x19 + x17 + x16 + x14 + x9 + x7 + x6 + x5 + x4 + x 3 + x2 + 1 9 4 27 BCH(511, 484) BCH(283, 256) x +x +1 x + x26 + x24 + x22 + x21 + x16 + x13 + x11 + x9 + x8 + x6 + x5 + x4 + x3 + 1 x40 + x39 + x33 + x31 + x30 + x29 BCH(1,023, 983) BCH(552, 512) x10 + x3 + 1 + x27 + x25 + x24 + x23 + x22 + x21 + x19 + x16 + x12 + x11 + x10 + x9 + x7 + x4 + x3 + x + 1

Fig. 2.4 Architecture of a BCH decoder with GF(2m) arithmetic

Given td ¼ 4, the binary BCH codes (including shorten codes) and their generator polynomials are shown in Table 2.2. The encoding computation for binary BCH is similar to (2.13). However, the decoding process of BCH is much more complex than that of other linear block codes. The architecture of a BCH decoder with GF(2m) is shown in Fig. 2.4 [15]. For a td-error correcting binary BCH (n, k), the syndrome S is calculated with the expression (2.16). S12td ¼ r1n  HT2td n where r1n is received codeword, and H is the parity check matrix.

(2.16)

28

2 Existing Transient and Permanent Error Management in NoCs

2

1

6 61 6 H¼6 6 .. 6. 4 1

ab abþ1 .. . abþ2td 1

3  b 2  b n1 a  a  bþ1 2  bþ1 n1 7 7 a  a 7 7 7 .. .. .. 7 . . . 5  bþ2t 1 2  bþ2t 1 n1 d d a  a

(2.17)

in which, ab, . . ., ab+2td1 are roots of the generator polynomial g(x). Different with previous linear block codes, the syndrome computation for BCH code is hardware-consuming because of large parity check matrix expressed in (2.17). Each element in the equation is represented with an m-bit vector. Suppose the error location polynomial is given by (2.18). sðxÞ ¼ s0 þ s1 x þ s2 x2 þ    þ std xtd

(2.18)

The coefficient for s(x) can be calculated based on the relationship between the syndromes S and s (x) shown in (2.19), which can be solved by PetersonGorenstein-Zieler algorithm, Euclid’s algorithm, Berlekamp-Massey algorithm (BMA) [15] and inversionless BMA [26]. Stþi ¼

td X

Stþij sj

ði; ¼ 1; 2; :::; tÞ

(2.19)

j¼1

The obtained s(x) is one row polynomial of the H matrix. The third step in the BCH decoding process is to compare s(x) with H matrix and identify which H column the error location polynomial s(x) matches to. In the Chien search algorithm, the error bit position is confirmed when we find the root for (2.20). sðaj Þ ¼ s0 þ s1 aj þ s2 a2j þ s3 a3j þ    þ std atd

(2.20)

The corresponding error bit position is (n-1-j). For binary BCH, XORing the (n-1-j) bit can correct the received codeword. The hardware overhead for binary BCH codes have been evaluated in Refs. [27, 28].

2.2.5

Product Code

Product code recently has been applied to on-chip interconnect, because of lower complexity (than BCH code) and higher error detection/correction capability for burst errors (than single parity check code, Hamming code and CRC) [27]. Product code is constructed with two simple component codes, one for row and one for column. Figure 2.5 shows the encoding process for product code Cp(n, k) using C1(n1, k1) and C2(n2, k2) for column and row encoding, respectively. The Cp code input k is the product of C1 code input k1 and C2 code input k2. Similarly,

2.3 Spare Wires

29

Fig. 2.5 Encoding process of product codes

n ¼ n1*n2. Consequently, the minimum Hamming distance for Cp is the product of the minimum Hamming distances of C1 and C2 [4]. Three stage decoding process is proposed in Ref. [27]. In the first stage, row decoding is performed to obtain row syndrome and row status vector, which indicates which row has error. If the detected error is correctable, error-free message is produced by flipping the erroneous bit; otherwise the consecutive decoding stages are needed. In the second stage, column decoders detect and correct errors in the codeword with the assistant of row status vector. To adjust the potential wrong row/column correction in the first two stages, another row decoding is executed in the last stage. This decoding process is shown in Fig. 2.6. In Ref. [27], product code has been employed to switch-to-switch links, showing the advantage on energy efficiency and error resilience. In this book, we propose to apply product code principle to dual-layer error control in networks-on-chip in Chapter 6.

2.3

Spare Wires

Permanent errors are usually caused by imperfect manufacturing process or devices aging. These errors do not vanish unless the faulty components are abandoned or replaced with new ones. Broken wires can be replaced with spare wire either in testing stage [29] or at run time [28, 30].

30

2 Existing Transient and Permanent Error Management in NoCs

Fig. 2.6 Decoding process of product codes

Fig. 2.7 Two approaches for permanent error management: (a) half splitting transmission, (b) phit size reduction

2.4

Split Transmission

Splitting transmission improves the utilization rate of broken links and reduces the needs of re-routing to reduce the network congestion and latency. If spare wires are run out or the router is nonfunctional, re-routing is needed. As shown in Fig. 2.7a, half splitting transmission [28] divides one flit into two fractions, transmitting one fraction each cycle. This approach is not efficient if the ratio of broken wires over all links is much smaller than 0.5. In Ref. [31], the user reduces the phit size (¼switch link width) to the maximum number of healthy wires per switch-to-switch link set (Fig. 2.7b).

2.5

Fault-Tolerant Routing

Other than spare wire and split transmission, fault tolerant routing algorithms are suitable to handle permanent link errors. The fault tolerance is achieved either by redundant packets or by redundant routing paths.

2.5 Fault-Tolerant Routing

2.5.1

31

Redundant-Packet-Based Routing

The essence of the redundant-packet-based fault tolerant routing algorithms is to send multiple copies of packets over network and choose one correct copy at the destination. The disadvantages of this routing category are follows: • • • •

Add more network congestion; Increase power consumption; Lose fault tolerance capability if the number of copies decreases; Boost the router design complexity.

Different efforts have been made to improve the efficiency of redundant-packetbased routing. Flooding routing algorithm requires the source router sending the packet to each possible direction and the intermediate routers forwarding the received packet to all possible directions as well [32]. Various flooding variants have been explored. In the probabilistic flooding approach, source router sends multiple packet copies to all of its neighbors; the middle routers forward the received packets to their neighbors with a pre-defined probability ( wrc. Besides replacing router and link energies with the ones using hop-to-hop ECC, the energy for the proposed method mode 2 (expressed in (5.15)) additionally includes the energy portion consumed by the hop-to-hop flit retransmission. Similarly, we use the go-back-n retransmission protocol. Avg: Energy per Packet Proposed mode 2 l m w ¼ ENI Encoder þ ENI Decoder I þ h wpf EProposedHop  l m  þ pend retrans ENI Decoder II þ h EProposedHop wwrcf þ 1

(5.15)

104

5 Dual-Layer Cooperative Error Control for Transient Error

where EProposedHop ¼ ELink 2 þ ERouter þ EHop Codec   þ phop retrans RN ELink 2 þ EHop Codec

(5.16)

As shown, Equation (5.15) adds hop-to-hop ECC overhead to Equation (5.14). But, the enhanced error control is capable of reducing the probability of retransmission pend_retrans, so that the average energy can be reduced. Although the proposed dual-layer adaptive ECC is more complex than other methods, modules for hop-to-hop ECC and step2 end-to-end decoder can be disabled. If the hop-tohop ECC function is inactive, the incoming flit is passed through the codec discarding the syndrome (in the decoder) and check bits (in the encoder) computation. One AND2 gate is needed to ensure the validity of the computed syndrome/ check bits. Moreover, the use of product codes prevents the execution of error detection/correction on the entire packet; instead, the column decoding is performed on each hop. In addition, the type-II hybrid ARQ scheme incorporated with the dual-layer ECC significantly reduces the energy consumption of transferring parity check bits. Consequently, our method can achieve better energy performance than other methods.

5.5.3.2

Statistical Comparison

The impact of noise deviation voltage on the average energy per useful packet is shown in Fig. 5.16. By examining the energy consumption over a wide range of noise deviation voltages, we can see that end-to-end ECC is not energy-efficient. In the end-to-end SECDED, ECC encoding and decoding is executed on the entire packet, which requires large XOR trees and consumes significant power. Similarly, the CRC encoder/decoder has long XOR trees, but consumes less decoder power because there is no error correction circuit. The end-to-end error detection scheme (end-to-end CRC) consumes slightly less energy than the end-to-end SECDED in low noise conditions (e.g. sN