Three Dimensional System Integration
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Antonis Papanikolaou Dimitrios Soudris Riko Radojcic ●
Editors
Three Dimensional System Integration IC Stacking Process and Design
Editors Antonis Papanikolaou Department of Electrical and Computer Engineering National Technical University of Athens 157 80 Athens Zographou Campus Greece
[email protected] Dimitrios Soudris Department of Electrical and Computer Engineering National Technical University of Athens 157 80 Athens Zographou Campus Greece
[email protected] Riko Radojcic Qualcomm Inc. San Diego, CA USA
[email protected] ISBN 978-1-4419-0961-9 e-ISBN 978-1-4419-0962-6 DOI 10.1007/978-1-4419-0962-6 Springer New York Dordrecht Heidelberg London © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Contents
1 Introduction to Three-Dimensional Integration................................... Antonis Papanikolaou, Dimitrios Soudris, and Riko Radojcic
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2 TSV-Based 3D Integration...................................................................... James Burns
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3 TSV Characterization and Modeling..................................................... Michele Stucchi, Guruprasad Katti, and Dimitrios Velenis
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4 Homogeneous 3D Integration................................................................. Robert Patti
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5 3D Physical Design................................................................................... Jason Cong and Guojie Luo
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6 Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs........................................................................... 103 Young-Joon Lee, Michael Healy, and Sung Kyu Lim 7 PathFinding and TechTuning.................................................................. 137 Dragomir Milojevic, Ravi Varadarajan, Dirk Seynhaeve, and Pol Marchal 8 3D Stacking of DRAM on Logic............................................................. 187 Trevor Carlson and Marco Facchini 9 Microprocessor Design Using 3D Integration Technology................... 211 Yuan Xie 10 3D Through-Silicon Via Technology Markets and Applications......... 237 E. Jan Vardaman Index.................................................................................................................. 243 v
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Contributors
James Burns Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA, USA Trevor Carlson Ghent University, Ghent, Belgium Jason Cong University of California, Los Angeles, CA, USA Marco Facchini IMEC vzw & Katholieke Universiteit Leuven, Leuven, Belgium Michael Healy Georgia Institute of Technology, Atlanta, Georgia, USA Guruprasad Katti IMEC vzw & Katholieke Universiteit Leuven, Leuven, Belgium Young-Joon Lee Georgia Institute of Technology, Atlanta, Georgia, USA Sung Kyu Lim Georgia Institute of Technology, Atlanta, Georgia, USA Guojie Luo University of California, Los Angeles, CA, USA Pol Marchal IMEC vzw, Leuven, Belgium Dragomir Milojevic Universite Libre de Bruxelles, Brussels, Belgium Antonis Papanikolaou Department of Electrical and Computer Engineering, National Technical University of Athens, 157 80 Athens, Zographou Campus, Greece Robert Patti Tezzaron Semiconductor, Naperville, IL, USA vii
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Riko Radojcic Qualcomm Inc., San Diego, California, USA Dirk Seynhaeve AutoESL, Cupertino, California, USA Dimitrios Soudris National Technical University of Athens, Athens, Greece Michele Stucchi IMEC vzw, Leuven, Belgium Ravi Varadarajan Atrenta Inc., San Jose, California, USA E. Jan Vardaman TechSearch International, Austin, TX, USA Dimitrios Velenis IMEC vzw, Leuven, Belgium Yuan Xie Penn State, University Park, Pennsylvania, USA
Contributors
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Chapter 1
Introduction to Three-Dimensional Integration Antonis Papanikolaou, Dimitrios Soudris, and Riko Radojcic
1.1 The Ever Increasing Need for Integration The semiconductor industry has been one of the main enablers for the boom of the information technology revolution that we have witnessed in the beginning of the twenty-first century. Each new generation of consumer electronics devices that hits the shelves boasts more features and functionality, better connection to other devices, lower cost, and better power efficiency per function. An excellent example of this trend is the evolution of the mobile phone since its proliferation in the end of the last century. Mobile phones started out by offering the minimal functionality of voice calling, then evolved to offering short messaging services and since then the features have kept piling up. State-of-the-art mobile phones in 2010 are in reality computing platforms offering extreme power efficiency, small form factor, and low cost for the offered functionality, which includes connectivity with virtually all known standards, high definition video decoding, social networking, office productivity suites, GPS plus any application the software community generates! Consumers have gotten used to these trends and expect a further improvement with every generation of products coming out, which puts pressure on the consumer electronics manufacturers to deliver on these expectations. This translates to a continuous pursuit for low-cost and low-power integration. More and more functionality needs to be integrated into fewer chips to reduce the component count and the real estate of printed circuit boards. Chips with increased functionality need to be shrunk in order to reduce their cost and power consumption. The key driver of this continuous improvement has been semiconductor process technology scaling that has shrunk the physical dimensions of transistors and interconnections to miniscule sizes, transistor channels measure a few tens of nanometers across. This miniaturization has increased the functionality per unit of area in chips by about a factor two every 3 years for the past five decades; the first integrated
A. Papanikolaou (*) National Technical University of Athens, Athens, Greece e-mail:
[email protected] A. Papanikolaou et al. (eds.), Three Dimensional System Integration: IC Stacking Process and Design, DOI 10.1007/978-1-4419-0962-6_1, © Springer Science+Business Media, LLC 2011
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circuits in the 1960s comprised a few transistors, state-of-the-art integrated circuits in 2010 measure more than a billion transistors on a single die. Shrinking transistor sizes has provided other benefits as well; smaller transistors have lower capacitances so they are faster and consume less power each. Note that even though power per transistor is reducing, the increased level of integration is packing more of them into smaller spaces, elaborate design solutions are required to keep the chip-level power consumption low. This has fueled the evolution of electronics for decades. This miniaturization by physical dimension scaling is slowing down as transistor channel lengths hit the range of 20–30 nm. Process technology is running into problems such as process variability, increased leakage currents, lithography limitations. Designers are forced to embed worst-case margins in the chips in order to work around these issues, which leads to an increase in power consumption. Furthermore, manufacturing ever larger chips has a negative impact on the production yield; fewer of them turn out to be fully functional. A lot of research effort is invested worldwide to overcome these problems and enable the technology scaling to continue unabated. But it is very doubtful whether technology scaling alone can keep delivering the rate of improvement it offered in the past decades. Another source of increased integration has been advances in chip packaging. In the early days, packages housed one chip each. Later on multiple chips were being integrated in one package in various configurations, either side to side or on top of each other, and were interconnected using small wires inside the package. State-ofthe-art packaging techniques include System-in-a-Package, which integrates multiple chips of heterogeneous functionality and process technology into a single package interconnected with wire bonds. The benefits offered by technology scaling and packaging advances are coming to an end. The desire for further integration and power efficiency is not however. Consumers still want more functionality at lower cost and higher power efficiency, probably more than ever before as electronic devices are slowly becoming ubiquitous in the environment.
1.2 Chip Stacking Keeping up the trend of integration and power consumption reduction in the era of slower scaling clearly requires a new set of solutions. Chip stacking is seen by many in the industry as the technology that will enable the necessary continuum in the trend for increased integration. It is a class of solutions that has emerged as a combination of technology scaling and packaging techniques. Various flavors of chip stacking technologies have been proposed and some of them have been in production for a number of years. Stacks of packaged die interconnected using wire-bonding, flip-chip bumps or ball grid arrays, wafer-level packaging of chip stacks, and other techniques to stack and interconnect chips have been used to create products in the past. All these techniques manage to integrate more functionality in a single package and they reduce the power consumed in communication between
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chips since they substitute Printed Circuit Board connection with wire-bonds or solder balls which have much better electrical characteristics. To push the boundary of integration and power consumption reduction, chip stacking has taken another step. 3D stacked integrated circuit (3D SIC) is a chip stacking technique where the vertical conductors are embedded in the substrate during the manufacturing of the wafers in the foundry. This enables a very high interconnection density between neighboring die in the stack with low-capacitance interconnects. Figure 1.1 illustrates how the aforementioned chip stacking techniques score on a number of axes. Technology integration refers to the capability of integrating die or chips built using different process technologies. Interconnection density refers to the number of vertical connections that can exist per unit of area. Integration density quantifies the capability of the technique to integrate a lot of functionality in a small volume. Performance refers to latency of vertical interconnections and form factor refers to the size of the final product per functionality embedded. Multi-chip-modules (MCMs) which incorporate many chips in a package side by side can integrate very heterogeneous chips at a good, i.e. low, cost but score rather low on the other axes, because it is still a solution that requires a lot of area and interconnections need to traverse large distances. Chip stacks interconnected with wire-bonds are relatively good along all axes but do not excel anywhere. They are better than MCMs in integration density and form factor as they can pack more functionality in smaller volume and faster since the resulting wire bonds have better electrical characteristics. But, wire-bonding suffers from scalability issues. Wire-bonds can only connect I/O pins on the periphery of chips and the available real-estate there is limited. Hence wire-bonding cannot offer a significant increase in interconnection density. MCM
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Ball grid array (BGA) stacks interconnect the different chips in the stack using arrays of solder balls. They improve on technology integration, but they are less cost-efficient compared to wire-bonded stacks. One of their main advantages includes the better electrical characteristics of the balls compared to the wire-bonds. This is especially useful in power delivery; for instance, solder balls enable better power delivery to power-hungry blocks with much supply voltage variations. Wafer-level packaging (WLP) goes a step further in form factor and integration density. It uses large vias through the silicon substrate to interconnect the different die. This increases the integration density and improves the form factor of the final stack compared to BGA implementations. 3D stacked integrated circuits (3D SIC) or 3D integrated circuits (3D IC) technology is the next generation in chip stacking technology. Bare die are stacked and are interconnected using vias through the substrate with very fine pitches. It is today the only practical solution that provides the capability to interconnect different die with tens of thousands of interconnects. Even though it is currently still an expensive process, it offers advantages in integration density as it results in the smallest volume, the highest performance, the smallest final form factor for the packaged stack and has by far the highest interconnection density between the die in the stack. For the remainder of this book we will focus on the 3D SIC technology.
1.3 Benefits and Challenges of 3D Integration Stacking ICs and densely interconnecting them vertically carries a lot of benefits for the end product. However, the technology to take multiple planar die and perform the actual stacking and operational interconnection has not been completely ironed out yet. Moreover, a number of business challenges remain before the supply chain for the production of 3D SICs is fixed. The next paragraphs outline these benefits and challenges and set the stage to understand why chip stacking is considered so important a step in integration as well as the remaining challenges that need to be addressed before this technology can become mainstream.
1.3.1 Benefits 1.3.1.1 Heterogeneous Integration Typical consumer devices include a number of heterogeneous functionalities, like processing, sensing, memory, data transmission, which cannot be incorporated in a single die, because the underlying process technologies need to be optimized for the individual purposes. Chip stacking offers an alternative to board-level connectivity and system-in-package solutions which suffer from reduced interconnection density between the functionalities and increased board footprint,
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hence cost. Dies can be manufactured in different process technologies, even in different foundry lines or by completely different vendors and can be bonded at a later stage by a third party. This enables, for example, to stack DRAM memory on logic processing or analog and RF functionalities with baseband processing on a single chip. The increased interconnection density opens up new opportunities for efficient system integration, as outlined in Chap. 8. 1.3.1.2 High Degree of Integration in a Small Form Factor A strong trend to miniaturize consumer electronics products is evident nowadays; thickness of devices has even become a selling proposition for new generations of smartphones and tablets. This trend puts significant pressure on chip providers to add the chip form factor as another design optimization criterion. In order to make devices ever thinner, with the screen and the printed circuit board taking up a significant amount of z-axis real estate, chips need to be less than a couple of millimeters thick. Moreover, consumer electronics manufacturers are pushing chip vendors to increase the functionality per chip in order to reduce the component count on the printed circuit board and cost as a result. Stacking of thinned chip is the only technology available currently that can densely pack more functionality than ever before into a very thin package. This may be the key to enable the next wave of consumer electronics miniaturization. 1.3.1.3 Improved Power Consumption Power consumption is the second most important design optimization criterion after cost nowadays. Chips that are embedded in portable devices need to consume power in a very frugal manner in order to maximize battery lifetime between recharges. Power consumption is becoming ever more important for other application as well. Compute farms and personal computers need to regulate their power consumption to control temperature and avoid catastrophic side-effects to the chips themselves. Manufacturers of set-top boxes and other similar devices need components that are power efficient to avoid installing cooling equipment which increases cost. One of the main sources of power dissipation on chips is the wires interconnecting the various functional blocks of the chip. As more and more functionality is integrated on a chip and physical dimensions increase, these wires tend to get longer and more power hungry as a result, since they need to transmit more information, faster, over larger distances. Continuing this trend using conventional planar chips leads to a bottleneck. Chip stacking offers an alternative solution. Partitioning the functionality of the chip in multiple die and vertically stacking them increases the locality between the different functional blocks. Blocks that previously were on opposite sides of a planar die can now be placed on top of each other. This enables a severe reduction of interconnect lengths which directly translates to reduced power consumption or even faster data transmission if necessary.
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1.3.1.4 Cost Benefits Cost is the single most important driver and optimization target in the design of integrated circuits for most applications. Traditional semiconductor scaling techniques that have enabled the increased system integration up to now are becoming more difficult and more expensive with each new technology node. The cost of developing the process technology and building a foundry for the next node is becoming so expensive that only very few companies can afford it worldwide. Apart from sheer capital expenditures, yield is also becoming a bottleneck for chip production. Defects that reduce yield in the production process are not scaling in size together with the feature dimensions of chips and cleanrooms cannot become any cleaner, the defect density has saturated. Dies become bigger to accommodate more functionality and as a consequence yield is dropping. This further increases the cost of producing chips in each next technology node, since fewer of them will be functional. Chip stacking offers an alternative route to integration which may prove to be more cost-efficient. First, it enables the stacking of multiple die which means that large, low-yielding die can be split into smaller ones which will then be bonded together. Second, if some part of the system has more relaxed requirements than the critical one, it can be manufactured in an older, cheaper technology node to further reduce the overall cost. Hence there is great potential for cost optimization as long as the additional process steps added in the process for bonding the multiple die together are cheap enough! This is one of the major challenges that must be overcome in order for chip stacking to become a mainstream technology which will complement traditional CMOS to enable the next steps of scaling for the semiconductor industry.
1.3.2 Technical Challenges The potential benefits of chip stacking are too lucrative to ignore. Semiconductor companies, research centers and universities are spending significant time in an effort to address the following remaining technical challenges and make chip stacking a reality. 1.3.2.1 Process Steps Stacking multiple chips obviously requires additional process steps. These steps can be clustered into three main functions, namely through silicon via (TSV) etching and filling, thinning and bonding. TSVs are the vertical interconnections between the different die, they connect an interconnect of the die where they are created to an interconnect on the die just below in order to establish an electrical connection. Creating them requires to etch holes through the silicon substrate in the appropriate die during its manufacturing and to later fill these holes up with conductive material. Thinning refers to a process step that thins the wafer with the TSVs to a thickness ranging from few tens of micrometers to a few hundred micrometers.
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This is an essential step in order to create a 3D SIC with a small thickness. The third important step is bonding were die are bonded together in pairs. This requires the careful alignment of the two die and their bonding such that the TSVs will land at the correct places to establish electrical connections with the lower die. Chapter 2 explains these steps in much more detail.
1.3.2.2 Operating Temperature The operating temperature of chips is mainly determined by three factors, the ambient temperature, the density of their power consumption, and how well they can transfer heat out of the package. Power consumption creates heat and if it cannot be dissipated fast enough the temperature of the die increases leading to problems such as increased leakage currents in the transistors and reliability degradation. Stacking of multiple die affects the power consumption density and the capability of the chips to dissipate heat. The power density increases because multiple die are thinned and bonded together in a small volume, the power consumed over a large area in conventional planar die is now consumed in a small volume. As a result, a large amount of heat is generated in a small volume. The capability to dissipate this heat depends on the materials used in the chips and the package. In a conventional chip, a spreader is used to distribute the heat along the surface of the die from where it is subsequently dissipated through the package. In a stacked IC, the heat has to be potentially dissipated through another die. The difference in heat conductivity needs to be understood and evaluated. The fact that the die in the stack is thinned before bonding adds another level of complication; thicker die can spread heat much better than thin ones along their horizontal plane. One school of thought believes that this increase in power density can lead to a temperature increase in the overall die stack. Another school believes that even in conventional planar chips the temperature problems are encountered in small hotspots; hence, the problem is essentially similar. It is clear that some research is needed to compare the heat dissipation capabilities of conventional vs. stacked integrated circuits in the context of their packages and to assess the impact of how and where heat is generated on the operating temperature of the die. 1.3.2.3 Mechanical Stability Three-dimensional chip stacks will comprise a number of die of different sizes, thinned to a few tens of micrometers, made of different materials stacked and bonded on top of each other so as to retain electrical connections. This system presents a nightmare in terms of mechanical stability when temperature changes. Different materials, and as a result different die, have different thermal expansion coefficients and are affected in a different manner by temperature gradients. This creates a potential threat that the stack might be partially de-bonded if temperature changes fast, which might
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be a catastrophic failure because electrical connections may be jeopardized. Mechanical stress that builds up due to these sources can have subtler effects as well. Stress engineering has been widely used in deep sub-micron technology nodes to improve the electrical properties of transistors. Mechanical stress due to thermal expansion can interfere with the stress carefully engineered in the transistor channel to destroy the on-currents of transistors. Another major source of problems is the handling of the thinned wafers. After thinning, wafers are so thin that they actually become flexible. Extreme care needs to be taken to make sure they are transferred from one process step to the other without damaging them. The current solution for handling such wafers is to attach them to supporting carrier wafers, but even the operations of bonding and de-bonding them to and from the carrier wafers may create mechanical issues. 1.3.2.4 Testing Testing is a very important, albeit often underestimated, step in the chip manufacturing process. Any manufacturing plant wants to ship only operational products; hence, testing is critical. Testing the functionality and performance specifications of a 3D chip stack is similar to testing a conventional chip. Chip stacking, however, offers opportunities to test individual die before they are bonded together. In order to avoid bonding functional with nonfunctional die together, which leads to wasting functional die, each die should be tested separately. This adds another level of complication to the testing process. Moreover, testing individual thinned die is a tricky process as their mechanical probing is extremely difficult process. Research is needed to establish a proper testing protocol for chip stacks and a way to test the individual die before bonding to increase yield and minimize cost. Design-for-testability is another area of testing that may be affected by three-dimensional integration. It comprises techniques to embed testing functionality, scan-chains for instance, in the chip so as to efficiently test it. Partitioning the system functionality in multiple separate die can increase the complexity of such techniques, this impact needs to be better understood. 1.3.2.5 Bonding Strategies Three ways exist to perform the bonding that creates chip stacks; wafer to wafer, die to wafer, and die to die. Each of these alternatives has clear advantages and disadvantages. Wafer to wafer bonding is the fastest, since multiple stacks are created at once, but the different die in the stack have to be exactly the same shape and size. Die to wafer bonding is an intermediate solution where one wafer has been diced and individual die are bonded on the second wafer. This makes alignment more difficult, but it enables stacking of die with different physical dimensions and allows to pretest the die and to create stacks of functional die. Die to die bonding offers the most freedom to the foundry to mix and match operating die to create chip stacks. It is the least preferred approach, however, since it increases production time and cost significantly. Depending on the type of product any of the aforementioned approaches may be useful. Even wafer to wafer bonding which may result
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in bonding functional with nonfunctional die is good for production of DRAMs where the cost of individual chips is very small and it is much more important to increase the production speed and throughput.
1.3.3 Business Challenges There are clearly strong interactions between the technical solutions that need to be developed and the target products as outlined above. Another level of complication involves the interaction between the different vendors that are part of the chip stacking value chain. Successful and efficient production of 3D SICs requires the streamlining and standardization of a number of processes. The challenges that need to be addressed include the following. 1.3.3.1 Liability In the world of conventional planar chips and simple packaging options, it is relatively easy to find out whether it is the die that has stopped working or the package when the entire system brakes down. This interface enables companies to cooperate and each to take responsibility for its products. Chip stacking complicates this interface. When multiple bare die are stacked on top of each other and the chip stack stops working it is very difficult to establish what went wrong and who is to blame. Was each die operational before stacking? Did the bonding process destroy the functionality of some die? Were the die designed according to the bonding specs? What happens in case thermal expansion creates reliability problems? Will companies be willing to provide warrantees for the proper operation of their products in this context? Chip stacking introduces many interactions between products of different vendors and sorting out where the liabilities lie is increasingly difficult. It is necessary, however, in order to commercialize this technology on a wide scale. 1.3.3.2 Cost Reduction Chip stacking has the potential to become an integral part of the global semiconductor production process if it can resolve the problems faced by scaling into the very deep submicron technology nodes, such as yield degradation. But this is only realistically achievable if the additional process steps related to chip stacking become very cost efficient and yielding. 1.3.3.3 Vendor Interfaces Traditional chip manufacturing has established interfaces between vendors in the supply chain which have served the industry well for a number of years. In a simple case design houses design the ICs and hand-off the layout to the foundries, the
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foundries manufacture the dies and hand them over to houses that perform packaging, assembly, and test. These three entities are distinct and one can hand off to another based on well-defined interfaces. Chip stacking complicates this process. It is not clear which steps need to be undertaken in a foundry and which can be performed by a packaging house. In the case of densely interconnected chip stacks the etching and filling of through silicon vias must be performed in the foundry because they sit in the middle of the manufacturing process. But thinning and bonding can be performed by either a foundry or a packaging house. In the case of stacking of heterogeneous die from multiple vendors or foundries things can become even more complex. The industry players need to come up with a new set of, potentially flexible, interfaces in order to establish a viable supply chain for the production of 3D SICs.
1.3.3.4 Standardization The hand-off between different vendors discussed above will be enabled by the standardization of key technology and design parameters and processes. The interfaces between chip stacking related process technology steps need to be standardized so that they can be executed by different vendors. For example, the physical dimensions of the TSVs fabricated by a foundry pose strict requirements on the alignment accuracy of the bonding process which may be performed by a packaging house. There are a large number of such parameters and interactions that need to be standardized to streamline the process and ensure full compatibility between vendors.
1.3.3.5 Design Kits The process of designing chip stacks should be independent of the supply chain that will produce the actual product with design kits acting as the interfaces to the manufacturing vendors, as is the case nowadays with conventional ICs. This implies the creation of the necessary integrated design kits and additional information and tools for designers that will span the responsibility of multiple vendors.
1.4 Purpose of this Book A large body of literature already exists on individual topics of chip stacking and three-dimensional integration, ranging from the issues revolving around the process and packaging technologies (process modules and steps, materials, issues with characterization and metrology, yield, etc.) to issues related to design of systems
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using this novel integration approach (building circuits, architectures, and systems using stacks of homogeneous or heterogeneous chips). Since this is still an integration technology in development, the process side has been explored in much more detail and consolidated information can be found in various publications [1–4]. The design of three-dimensionally integrated circuits [5] and especially entire systems has received much less attention up to now. The purpose of this book is to provide an overview of the entire trajectory from basic process technology issues to the design at the system level of three-dimensionally integrated nano-electronic systems. The emphasis has been put on the design side, physical design and design at the architecture and system level, because the technology is entering the maturity stage and these issues are starting to become very important. The book is intended for an audience with a basic grasp of electrical engineering concepts including some familiarity with fabrication of semiconductor devices, very large scale integration (VLSI) and computer architecture.
1.5 Book Contents The book can be roughly divided in three main sections. The first section, which includes Chaps. 2–4, explains the issues related to the process technology itself as well as some issues revolving around electrical modeling of the vertical through silicon vias. Chapter 2 provides a historical perspective of three-dimensional integration and dives deeper into the details of the process technology required to stack multiple die together and interconnect them with through silicon vias. Chapter 3 discusses in detail how to model the electrical characteristics of these vias in order to create the necessary design kits. Chapter 4 starts with a high-level outline of the basic considerations involved in three-dimensional integration and goes on to illustrate an industrial example of integration of homogeneous die. The second section, Chaps. 5–7, discusses issues in the context of physical design of three-dimensionally integrated ICs. Chapter 5 provides an overview of the entire trajectory of the physical design process for three dimensionally integrated systems from a chip designer point of view. Chapter 6 goes into more detail in the routing strategies required for optimal interconnection of the different die. Chapter 7 discusses why and how the process technology and the design of 3D SICs need to interact with each other in order to result in an optimal system implementation that takes full advantage of the technology offerings. The third and final section, Chaps. 8 and 9, outlines the architecture and system design aspects that come with three-dimensional integration. Chapter 8 goes in detail about the design of a system with a DRAM stacked on top of a microprocessor to exploit the additional interconnection density between the two. Chapter 9 discusses how to optimize microprocessor design given the additional degrees of freedom provided by three-dimensional integration.
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Finally, Chap. 10 provides an outlook on the markets and applications that are expected to drive the development of both the process technology and the design environment and tools in the future.
References 1. Garrou P, Bower C, Ramm P (2008) Handbook of 3D integration: technology and applications of 3D integrated circuits. Wiley-VCH, Weinheim 2. Bakir M, Meindl J (2008) Integrated interconnect technologies for 3D nanoelectronic systems. Artech House, Norwood 3. Tan C-S, Gutmann R, Reif L (2008) Wafer level 3-D ICs process technology. Springer, New York 4. Deng Y, Maly W (2010) 3-Dimensional VLSI: a 2.5-dimensional integration scheme. Springer, New York 5. Pavlidis V, Friedman E (2008) Three-dimensional integrated circuit design. Morgan Kaufmann, San Franscisco
Chapter 2
TSV-Based 3D Integration James Burns
2.1 Introduction 2.1.1 Initial Studies and Experiments Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Fig. 2.1 in a symbolic drawing along with a cross-section of an actual 3D IC. The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. A TSV drawing and a cross-section of a TSV are shown in Fig. 2.2. A 3D IC technology was viewed as necessary to maintain integrated circuit performance on the path described by Moore’s law. One issue was the projected increase in chip-operating frequencies that would lead to different clock rise and
J. Burns (*) Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA, USA e-mail:
[email protected] A. Papanikolaou et al. (eds.), Three Dimensional System Integration: IC Stacking Process and Design, DOI 10.1007/978-1-4419-0962-6_2, © Springer Science+Business Media, LLC 2011
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Fig. 2.1 (a) An expanded view that illustrates that a 3D IC consists of 2D ICs that are thinned, bonded together, and interconnected with TSVs distributed within the planes of the 2D ICs. (b) A cross-section of a 3D ring oscillator built with a fully depleted SOI (FDSOI) technology
fall times within a chip as shown in Fig. 2.3. Numerous theoretical studies examined the performance of 3D ICs as a function of the number of active tiers and the placement of memory, logic, and other functions among and within the active tiers, but early attempts to build even rudimentary 3D ICs were unsuccessful. Those 3D ICs were constructed using epitaxial overgrowth or polysilicon deposition [3] to stack silicon layers, but the transistor characteristics or transistor densities were unsatisfactory. Attempts to create vertical connections through silicon chips were frustrated by the inability to uniformly thin the chips to less than 50 mm and to insulate deep cuts etched through the thinned chips. At the same time IC technology developments led to tighter design rules and improved transistor performance so that IC progress continued to satisfy Moore’s Law. Within the last 10 years it became clear that Moore’s law could not be met solely by transistor design and fabrication innovations. Therefore, the development of an alternate technology to design and construct microelectronic systems as 3D devices became essential.
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Fig. 2.2 (a) A drawing of a TSV and (b) a SEM of two parallel TSVs that are ~100 mm deep with an aspect ratio of 20, courtesy of IBM
2.1.2 Advanced 3D Packaging Many of the gains projected for a 3D IC technology were achieved by advancements in packaging that reduced the interconnect length among chips [4]. Multichip modules, stacked-edge connected chips, and ball-bonded chips are examples of past packaging innovations. Further innovation included dual inline packages (DIP) configured to stack two DIPs with pins inserted into pins and stacked ceramic modules with chips bump-bonded face down to increase the functional density of the
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Process Technology (nm)
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From 2003 ITRS Roadmap
700 MHz
1.25 GHz 2.1 GHz
150
6 GHz 100 50 0 1995
10 GHz
13.5 GHz
(20 mm x 20 mm Die) 2000
2005 Year
2010
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Fig. 2.3 Technology improvements have produced increased chip clock frequencies. The radius of the circle shows the distance a data signal can propagate within a single-clock-cycle as a function of clock frequency and indicates that above ~4 GHz data cannot be reliably clocked across a 20 mm × 20 mm die
package. Products that contain these advanced packages are in today’s market place with cell phones being the consumer product that illustrates advanced packaging used to maximize performance, ease of use, and at a minimum size, particularly its thickness. However, the interconnect density in the direction perpendicular to the plane of the cell phone’s circuit boards is still a small fraction of the multilevel metallization vias in any of its ICs. This suggests that future cell phones could be more compact and functional if constructed with 3D ICs. Recent innovations in 3D packaging include a 3D IC system developed by ChipPac as shown in Fig. 2.4 where chips are stacked, bonded, and interconnected at the chips’ edges and the stack assembly is attached and connected to a chip carrier. Another 3D packaging approach developed by Irvine Sensors is shown in Fig. 2.5. In this concept the interconnect is designed to extend to the edge of each chip so that when several chips were stacked and bonded together the edge of the assembly could be polished to expose the interconnect at the chips’ edges. The compact 3D system was completed by depositing and patterning interconnect metal on the stack’s edges. In a more recent approach to building 3D chips, 2D chips are stacked and either bump- or adhesively bonded to a base wafer. In this design vertical connections are achieved within but not through the chips. The sizes of the chips can be different which permits the integration of chips from different sources and different technologies, but the alignment of the pads on the base wafer and the chips to be attached must be compatible. A Geiger counting imager [5], shown in Fig. 2.6, is an example of such a technology. The base wafer is a CMOS readout to which an avalanche photo diode array is adhesively attached and connections between the imager and the CMOS readout are made by deposited aluminum. The interconnect design limits
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Fig. 2.4 A 3D package by ChipPac consists of four chips that are stacked and bonded. The chips are electrically connected to each other and to the chip carrier by wire bonds
Fig. 2.5 Irvine Sensor’s Neo-StackTM technology accommodates a variety of different sized chips that are stacked and edge connected to make a module of 4–50 layers that is less than 13 mm thick
the vertical connection density and image fill factor of the 3D chip. Similar 3D chips have been made using bump bonding techniques, but the density is limited by the size of the bond pads which are a function of the chip–wafer alignment budget and the bond pad size. Note that any of the preceding approaches to 3D construction can be embedded into a multichip module to further increase the packing density of the
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APD diode
Light shield
Diode-CMOS connection
CMOS readout ( beneath the diode tier)
Fig. 2.6 A 32 × 32 Avalanche photo diode array bump-bonded to a CMOS readout with a 100-mm pitch and a 5% fill factor
system. However, none of these approaches has the ability to achieve vertical connections that are distributed within the chip’s area with vertical interconnect densities that approach the density of back-end-of-the-line (BEOL) vias.
2.1.3 Recent Progress in 3D IC Technology Within the last 10 years significant progress has been made in solving a fundamental set of 3D fabrication challenges. • High strength and void-free chip and wafer-bonding processes [6] evolved from CMP techniques used to fabricate SOI wafers. Further refinements of those CMP processes made it possible to thin wafers to less than 50 mm with a total thickness variation less than 1 mm and without altering transistor parameters. • The migration of SOI device technology into commercial production presented an alternate path to thin wafers by using the buried oxide as an etch stop to set the final tier thickness to be the sum of the BOX, the SOI layer, and the interconnect layers [7]. • Deep oxide and silicon-etching equipment and processes were developed to etch 50-um deep cavities with near vertical sidewalls. • Similar improvements in dielectric and metal deposition techniques made it possible to reliably coat the cavities with a dielectric and fill them with conductors such as polysilicon or tungsten to form TSVs [8]. • Thermal compression bonding of copper TSVs became another chip–wafer or wafer–wafer bonding option [9].
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• Alignment equipment originally developed for thick film processes was modified to permit improved wafer–wafer alignment with overlays less than 2 mm. • More recently, the development of a wafer–wafer alignment system that incorporates wafer–stepper alignment principles has demonstrated wafer–wafer overlays less than 500 nm [10]. Numerous institutions are developing 3D IC technologies based on either wafer–wafer or chip–wafer bonding [11–15] and it is conceivable that the topology of advanced 3D ICs will be tailored to the application such as a lens-shaped chip for imaging system or even an irregular surface to mimic the human brain surface. No consensus has emerged as to the optimum path to achieve a 3D IC capability, but current progress has shown that a 3D IC technology is essential and probable rather than desirable and possible.
2.1.4 3D IC Technology in the ITRS Roadmap The 2007-ITRS roadmap identified the interconnection problem as one of the nearterm (through 2015) “grand challenges” since additional device and interconnect scaling alone could not deliver the required increase in IC performance. A 3D technology with TSVs aligned on a tight pitch was one of the new technologies identified to meet that challenge. The 2008 update [16] of the roadmap included increased emphasis on 3D IC technology development and specified a set of TSV-critical dimensions based on a stacked wafer model with wafers thinned to 10 mm. The TSV parameters analyzed are illustrated in Fig. 2.7 and a summary of the update is contained in Table 2.1. The wafer–wafer or chip–wafer alignment problem was defined as a major obstacle to scale the vertical interconnects and new approaches to the alignment problem were seen as necessary. Additional issues such as 3D IC design and thermal–mechanical modeling tools were identified as future challenges.
TSV-2 Tier 2
TSV-1
Bond line
L Tier 1
Θ D S P
PD
Fig. 2.7 The TSV parameters of Table 2.1 included in the 2008 ITRS update
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Table 2.1 High-density through silicon via projections in 2008 ITRS update Year Principle parameters 2008 2009 2010 2011 2012 2013 1.6 1.5 1.4 1.3 1.3 1.2 TSV diameter, D (mm) TSV pitch, P (mm) 5.6 5.5 4.4 3.8 3.8 2.7 Pad spacing, S (mm) 1 1 1 0.5 0.5 0.5 Pad diameter, PD (mm) 4.6 4.5 3.4 3.3 3.3 2.2 Bonding accuracy, 1.5 1.5 1 1 1 0.5 D (mm), 3sigma
2014 1.2 2.6 0.5 2.1 0.5
2015 1 2.5 0.5 2 0.5
2.2 TSV-3D Integration Technologies 2.2.1 Introduction The TSV is the structure that has the greatest potential for widespread use in advanced 3D ICs because it can be scaled to achieve a vertical connection density that approaches the density of 2D vias and its electrical properties of low electrical resistance, parasitic capacitance, and parasitic inductance are compatible with the requirements of advanced microelectronic systems. Equally important, TSV fabrication uses thin film processes typical of BEOL technologies unlike ball bonds, wire bonds, tape bonds, or solder bonds that are thick film technologies with limited potential to scale the connections. All 3D IC fabrication process comprise three basic steps, namely wafer thinning, TSV etching and filling, and tier bonding (Fig. 2.1). Depending on the sequence of these steps we can distinguish between different approaches. A process is described as “TSV first” or “TSV last” if the TSVs are fabricated before or after tier bonding, respectively, and the order in which TSVs are fabricated within a 3D IC process is an important process decision to be made before developing a 3D IC technology. The process flows for TSV first, TSV last, and TSV middle – an intermediate flow – are contained in Table 2.2 [17] and 3D IC process flows for TSV-first and TSV-last technologies are illustrated in Figs. 2.8 and 2.9, respectively.
2.2.2 TSV Design The goal of TSV design is to minimize the size and maximize the TSV pitch without exceeding the maximum resistance permitted by an application. This combination results in a TSV whose low capacitance and resistance leads to a power-efficient design that meets the system’s performance requirements. The resistance, R, of a TSV can be calculated as a function of the features illustrated in Fig. 2.6:
R = rL / ( D − d ) (( D − d ) + 2 tan ΘL )
(2.1)
2 TSV-Based 3D Integration Table 2.2 TSV process flows TSV first Etch deep silicon cavities Insulate cavities Fill cavities with a conductor Fabricate BEOL interconnect Bond wafer pair Thin backside of upper wafer Fabricate BEOL interconnect on upper wafer
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TSV middle Etch deep silicon cavities Insulate cavities Fabricate transistors Fill cavities with a conductor Fabricate BEOL interconnect Bond wafer pair Thin backside of upper wafer
a
TSV last Fabricate transistors Fabricate BEOL interconnect Bond wafer pair Thin backside of upper wafer Backside etch deep silicon cavities Insulate cavities Fill cavities with conductor
b
Start 1
3
Glass 2 3 Glass 2
Glass 3
Glass
Tier 2-1 bond
2
Tier 3-2 bond
2 1
1 3
TSV-bond pad connection
2
2 1
1
2 Tier 3D IC
Finish: 3 Tier 3D IC
Fig. 2.8 The TSV-first process flow for a three-tier 3D IC. With the exception of the base chip, #1, all wafers have TSVs formed before first metallization. The assembly of a two-tier 3D device from wafers 1 and 2 is shown in column (a). The glass layer is bonded to wafer #2 to provide support during substrate thinning to expose the tips of the TSVs. Wafer #2 is aligned to bond pads on the lower tier and bonds are formed through contact with metal pads on the lower tier. After bonding the glass layer is removed. (b) Wafer 3 is added to the two-tier assembly to form a three tier 3D device
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a
b
Start 1
3
3 2 e
2
Tier 3-2 bond
2
Tier 2-1 bond
1 3
1
2 2 1 1 3
2
2
Tier 2-1 connection 1
2 tier 3D IC
1
Finish: 3 tier 3D IC
Fig. 2.9 The TSV-last process flow for a two-tier 3D IC is shown in column (a). After bonding wafer 2 to wafer 1, the substrate of wafer 2 is thinned then TSVs are formed between the wafers. A continuation of the TSV-last flow is shown in column (b) in which wafer 3 is bonded to the twotier 3D assembly. Substrate thinning of wafer 3 and TSV formation complete the 3D process flow
where r is the resistivity of the metal plug, L is the length the TSV, D is the size of the TSV, which is assumed to be square at the bottom contact, d is the thickness of the dielectric on the TSV sidewalls, and Q is the taper of the TSV cavity. Equation (2.1) indicates that it is desirable to reduce the dielectric thickness on the sidewalls in order to minimize the TSV resistance. From (2.1) we obtain the required size of the bottom contact, D as follows:
D = 2 d – L tan Θ + (( L tan Θ)2 + ( rL / R))
(2.2)
We require that the TSV plug be fully landed; that is the plug must not extend beyond the lower metal pad. From this we determine the TSV pitch to be:
P = 2WA + D + S + 2 L tan Θ
(2.3)
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where WA is the wafer–wafer alignment overlay and S is the minimum metal–metal spacing permitted in the 2D design rules. The final expression is as follows:
P = 2WA + 2 d + S + L tan Θ + (( L tan Θ)2 + ( rL / R))
(2.4)
Equation (2.4) indicates that a minimum TSV pitch requires that the TSV etch process produce vertical sidewalls, the dielectric deposition process produce thinpinhole free dielectrics, and, most importantly, the alignment tool be capable of sub-micron wafer–wafer alignment.
2.2.3 SOI-Based TSV Technology TSVs used in the fabrication of SOI-based 3D ICs [14] do not require deposition of a dielectric layer since the TSVs are placed in the field oxide regions of the ICs. As a result, the TSV process is simpler and, for the same pitch, the connection resistance is lower than that for a TSV through bulk silicon since the entire TSV cut is filled with a conductor. Because the TSVs are embedded in the field oxide, the parasitic capacitance and inductance between adjacent connections is reduced. A TSV design used in a SOI-based 3D IC technology is shown in Fig. 2.10. An SOI-based 3D IC technology is not the impediment it had been in the past since SOI wafer fabrication has emerged as a main line technology for high performance ICs and has also transitioned to a foundry.
Fig. 2.10 (a) Cross-sectional and (b) isometric drawing of a TSV used in a SOI-based 3D IC technology. The tungsten plug connects the metal annulus in the upper tier to the metal pad (3D land) in the lower tier. The top of the plug is defined by a resist mask; the metal annulus defines the size of the plug at the 3D land
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2.3 TSV Process Integration 2.3.1 Stack Alignment The TSV pitch is a critical factor in the viability of the 3D technology since for optimal circuit density the minimum pitch of the TSVs should be comparable to that of the 2D vias that connect multilevel metal layers. The principle limit for the TSV pitch has been wafer–wafer alignment as described in the 2008 ITRS roadmap and as seen in (2.4). As an example, consider the layout of the 3D ring oscillator in Fig. 2.1b. The device was successfully fabricated using an SOI-based 3D technology with inverters in two tiers that were connected with TSVs so that the oscillator’s signal cycled between tiers as shown in the figure. In the design shown in Fig. 2.10 the bottom metal contact of the TSV is the 3D Land and the TSV cut is the size of the resist mask used to etch the TSV cavity. The 3D Land is:
3D Land = 2 WA + D.
(2.5)
In the initial set of 3D design rules the 3D Land was 5.5 mm since the wafer–wafer alignment overlay was 2 mm and D was 1.5 mm. An improved alignment system [10] with an overlay of 0.5 mm and an improved TSV etch process with D = 0.5 mm permitted scaling the 3D Land to 1.5 mm and a reduction in pitch from 9 to 4.5 mm. This example illustrates that alignment overlay is a fundamental impediment to decreasing the size of TSVs.
2.3.2 Stack Bonding Two issues are dominant in the development of a proper bonding technique. The first is establishing the bonding process itself together with the appropriate materials. The second involves maintaining the mechanical stability of the individual tiers and the complete stack during and after the bonding process is complete. Early attempts to build 3D ICs used adhesives as the bonding technology [18]. Experiments indicated that the TSV pitch could not be scaled to less than 6 mm with an adhesive bond due to outgassing from the adhesive. In addition, the adhesive was not sufficiently stable to develop 3D ICs with three or more tiers. That led to the development of alternate technologies such as low temperature oxide–oxide bond [6] and metal–metal thermal compression bond processes [9]. Any bond process must be compatible with the alignment technique used so that the alignment is not degraded during bonding and the process must also be consistent with stacking more than two tiers for those cases where a 3D IC composed of three or more tiers is required. These requirements mean that the thermal processes of layer bonding must not weaken any bonds and TSV connections previously established.
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Metal–metal and metal–oxide bonding techniques have been used for years in lead attachments and glass–metal seals and that technology has been extended to 3D integration. Copper–copper bonding is an attractive candidate for TSV-first processes since it creates a strong bond and an electrical connection simultaneously and the copper layers can aid heat extraction. However, the TSV conductor cannot be a part of the wafer-bonding process for TSV-last processes. In any bonding process, cleanliness is essential to eliminate voids created by particles. An additional void creation mechanism is gaseous reaction products created during silicon and oxide bonding that cause bubbles that create bond voids. The bond is initially formed at room temperatures immediately following alignment and additional processes are required to increase the bond’s strength. When successfully implemented, the bond process leads to a very thin bond with no voids and has the strength to maintain wafer–wafer alignment during the addition of one or more tiers to the system. Wafer distortion during fabrication must be controlled since excess deformation will decrease the wafer bond strength particularly for oxide-fusion processes where intimate contact between surfaces is required to initiate and establish a strong bond. Wafer deformation is reduced by using compensating films on the backside of wafers to decrease the deformation to less than 50 mm for a 150-mm diameter wafer, a value that will not compromise the bond process. In addition, wafer distortion, some times called continental drift, can lead to misalignment between critical features of the TSV. In principle it could be possible to compensate for distortion by measuring wafer distortion and offsetting the distortion with a wafer chuck having the ability to maintain temperature gradients. Ultimately, a process must be characterized to determine the amount of distortion that occurs so that the value can be added to the design of the TSV since distortion is an additive factor in misalignment.
2.3.3 TSV Etching and Filling In order to minimize the TSV pitch, an etch chemistry is required that maximizes the aspect ratio of the TSV cavity defined as the ratio of the depth to the width of the cavity. In addition the etch process must be selected to avoid resist erosion which can lead to an increase in the lateral size of the cavity at the surface. A mask, such as aluminum, that is not attacked by the etch process can be used to maintain the dimensional integrity of the mask but removal can be a challenge. In all cases mask removal must be compatible with the TSV metals used, particularly for TSVlast processes. Etch reaction products must be monitored and controlled since they can alter or block the deep cavity etch [19]. In the case of a TSV cavity formed through silicon, a pin-hole free insulator must be deposited on the sidewalls, the bottom corners, and the top edges to provide a reliable insulated coating for yield and reliability considerations. Another etch process is required to remove the insulator from the bottom of the cavity to expose the metal pad without attacking the
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insulator on the sidewalls or the metal pad. This challenge does not exist for SOI-based 3D IC technologies, since the TSVs are formed in the field oxide. Metal deposition processes must have thermal cycles that do not degrade the 3D bonding and TSV structures previously established. A lesser problem for a TSV design but one that requires some thought is the possibility of field-induced leakage due to a lightly doped substrate so sidewall doping may be required. A TSV-last process that includes SOI and bulk wafer fabrication, oxide fusion bonding, oxide etching to form 8-mm TSV cuts with tungsten connections was used to fabricated three layer 3D ICs [14]. The bond temperature never exceeded 275ºC while the oxide and tungsten deposition temperatures were 450º and 475ºC, respectively. Finally a thermal analysis of the entire 3D IC fabrication process is required to insure that the 3D IC is thermally stable and the electronic properties of the devices have not been degraded at the completion of the 3D IC process.
2.4 Characterization of TSV Processes 2.4.1 Physical Characterization Stack bond strength is evaluated by the crack insertion test [20] using a pair of witness wafers. The percentage of bond voids is measured with infrared microscopy using a pair of witness wafers or with an acoustic imaging system using a bonded pair. Experience has shown that the extensive use of witness wafers is essential to maintain control of the bond process since the bond strength measurement is a destructive measurement and a defective bond can lead to the loss of the entire 3D assembly. Wafer–wafer alignment after bonding and substrate thinning is measured using standard lithographic metrology tools but the optical path between alignment structures in both tiers must be free of opaque layers which places restrictions on the design of alignment targets.
2.4.2 Electrical Characterization Active and passive test devices are required for in-process and completed assembly analysis. Electrical test structures can also be used to measure stack alignment after 3D fabrication either by measuring the via resistance or by measuring the yield of TSV structures designed with varying degrees of misalignment between the TSV cut and pad. The TSV design can be optimized and the process margins determined by measuring the yield of TSV chains designed with a set of TSV sizes and misalignment values. Test transistors are required for testing during the 3D assembly process and at the completion of 3D assembly in order to determine if the 3D process has degraded the devices. Witness wafers with TSV chains and test transistors are valuable tools to
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aid the development and control of the 3D IC process. TSVs are required to reach transistors in each of the tiers to determine whether heat dissipation, oxide charge within the 3D assembly, or processing problems have altered transistor performance. In all cases it is essential that those same transistors be measured before the initiation of 3D process to accurately measure device changes due to the 3D process. TSV structures are also required for the extraction of resistance, capacitance and inductance and to optimize CAD software for the analysis of circuit performance. It is important to place standard circuits such as ring oscillators, SRAMs and counters in each of the tiers to assess fabrication effects on circuit yield and at least one of the circuit types should have components distributed in each level since it is difficult to diagnose circuit failure of large 3D circuits. A ring oscillator is a good candidate for this activity.
2.4.3 3D vs. 2D Chip Yield The major yield detractors for a 3D IC technology are bond defects from stacking, TSV opens, TSV shorts to polysilicon or to the metal interconnect due to stack misalignment, and changes of device parameters due to 3D processing. The latter yield detractor can sometimes be minimized by a post-processing sinter. Singulation, the dicing of a 3D wafer stack into individual 3D chips, can be a loss mechanism due to the 3D assembly delaminating in the dicing streets since the thinned tiers are susceptible to fracture from dicing debris. This failure mechanism can be minimized by layout practices that keep the streets free of metals and polysilicon. Heat buildup within the stack is a unique 3D failure mechanism that can cause parametric drift and circuit failure [21–22] and the removal of heat from a 3D IC chip is a major challenge confronting 3D technology development.
2.5 TSV-Based Chips 2.5.1 3D Design Challenges Within the last 5 years, 2D circuit design, layout, and circuit extraction tools have been adapted to design 3D circuits and work continues to improve the tools [23–24]. One challenge is to design the CAD tools to be compatible with the different 3D technologies such as TSV-first and TSV-last as well as a bulk wafer vs. a SOI-based 3D technology. 3D IC is an evolving technology and CAD tool development, to be effective, must take place in step with the 3D technology which includes the development of improved models of TSVs so the tools can better simulate 3D IC circuit performance. Visualization of 3D chips from the design data both in cross section as well as in an exploded view is essential both for the chip designer and for the technologist to support yield studies and failure analysis as part of the fabrication and development effort (Fig. 2.11).
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a
b
3D via 2.0 mm 3D via landing pad 1.5 mm 3D via landing pad 5.5 mm
3D via ~1.0 mm
Inter-metal via 0.4 mm
c Tier 2 Tier 1 Fig. 2.11 (a) The landing pad of a SOI- based 3D inverter fabricated with the TSV of Fig. 2.9 is reduced from 5.5 mm (b) to 1.5 mm by a reduction of alignment overlay error and TSV size. (c) The inverters are located in two tiers and connected by TSVs to from the 3D ring oscillator in Fig. 2.1
2.5.2 Functional 3D Chips with TSV A 3D imager is an obvious application of 3D due to the possibility of achieving a 100% fill factor which is an imaging plane unobstructed by interconnections and other opaque features. This is a result that cannot be achieved by scaling a 2D technology. A 3D imager [25] that was reported by Lincoln Laboratory is shown in Fig. 2.12. 3D IC chips with memory attached to a processor chip is another important application since dense TSVs will minimize routing delays as well as delays in obtaining information from the memory and numerous institutions have reported such 3D chips. 3D has been touted as a natural application for ICs with mixed materials and or mixed technologies. The mixed material 3D ICs are of particular interest for building imagers that operate in the ultraviolet and infrared spectrums but utilize silicon readouts and the integration of Indium phosphide with silicon CMOS has already been demonstrated [26]. 3D ICs constructed with different processes are of particular interest and a mixed silicon technology chip has been demonstrated that was composed of three tiers: a photo diode layer, a 3.3-volt CMOS layer, and 1.2 and 1.5-V CMOS layers to form an avalanche photodiode imager [27].
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Fig. 2.12 (a) Captured raw image from digital tile at 10 fps, with digital data read out in 1 ms and (b) cross-sectional SEM micrograph through functional 3D-integrated active-pixel imager
2.6 Future Challenges The lack of access to 3D fabrication by circuit designers has been an impediment for 3D design and has limited a full exploration of 3D opportunities. However, several institutions have opened their technology to external designers who can
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b 3D Circuits FPGA, stacked memory (SRAM & CAM), asynchronous microprocessor, FFT with on-chip memory, multi-processor chip with high-speed RF interconnect, ASIC with DC-DC converter, reconfigurable ∆Σ modulator, decoder with 3cube torus network, self-powered and mixedsignal RF chips 3D Imaging Applications ILC pixel readout, high-speed imaging FPA, 3D adaptive image processor, artificial bio-optical sensor array, 3D retina, 3D-integrated MEMS biosensor, sensor lock-in-amplifier 3D Technology Characterization 3D signal distribution, 3D interconnect methods, parasitic RF & 3D radiation test structures
Fig. 2.13 (a) Photograph of a 22 ´ 22 mm 3D multiproject chip fabricated with a SOI-based 3D technology and (b) a list of 3D circuits designed by members of the 3D community. Multiproject programs will be the key to future 3D IC design
submit their IC designs for 3D fabrication. Lincoln Laboratory has published 3D design rules and completed three 3D multiproject fabrication runs based on a threetier technology with TSVs. A photograph of the 3D chip and a list of 3D circuits contained in the chip are shown in Fig. 2.13. Tezzaron has acquired funding to support a 3D multiproject program and IMEC has also established a multiproject capability. However, continued financial support from the microelectronic industry or governments will be required to sustain access to 3D technologies until IC houses commit to establishing a 3D capability. An encouraging development that will aid 3D IC fabrication efforts is the formation of a consortium by equipment suppliers to accelerate the development of 3D IC-specific equipment. The TSV design must continue to be scaled if 3D is to satisfy new applications. Fabrication advancements and improved wafer–wafer alignment tooling will scale future TSVs. However, each TSV requires a zone about it from which there can be no silicon, polysilicon, or metal interconnect thus decreasing the effective density of the chip. As a result the TSV scaling limit may not be based on feature sizes but on the exclusion zones required by the TSV and work will be required to minimize the impact of those exclusion zones. Layout tools will be required to better partition circuits among tiers to optimize TSV placement and minimize the impact of TSVs on circuit density. The greatest technological challenge is heat control and removal from within a 3D IC, particularly the embedded layers, and improved CAD tools will be essential for the optimal placement of heat-generating circuits to minimize heat effects on 3D IC performance. There are also challenges in the factory connected with yield. A wafer-scale 3D technology represents the greatest yield risk since a bond failure could doom at least two wafers if not more. For that reason chip–wafer circuits will continue to receive
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careful attention to work around the yield problem. Yield can also be a problem due to the coincidence of defective transistors that would cause 3D circuit failure. Redundancy techniques can be used initially to work around defective regions but eventually test techniques will be required to map the good regions of each wafer in order to match wafers of varying quality prior to 3D assembly. Technology development will be required to introduce conductive features such as heat pipes or cooling channels between or within the tiers to further minimize heat effects on circuits. In spite of these challenges, the demonstrations of functional 3D imagers, 3D processors with stacked memory, 3D CMOS with stacked MEMS, and 3D ICs with mixed technologies and materials are proofs of concept that a 3D IC technology in the marketplace is within sight. Acknowledgments The work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.
References 1. Reber M, Tielert R (1996) Benefits of vertically stacked integrated circuits for sequential logic. In: Proceedings of the IEEE international symposium on circuits and systems, vol 4, pp 121–124 2. Akasaka Y (1986) Three-dimensional IC trends. Proc IEEE 74(12):1703–1714 3. Chan VWC, Chan PCH, Chan M (2000) Three dimensional CMOS integrated circuits on large grain polysilicon films. In: Technical digest - IEEE international electron devices meeting, pp. 161–164 4. Lea R, Jalowiecki I, Boughton D, Yamaguchi J, Pepe A, Ozguz V, Carson J (1999) A 3-D stacked chip packaging solution for miniaturized massively parallel processing. IEEE Trans Adv Packag 22(6):424–432 5. Aull BF, Loomis AH, Gregory J, Young D (1998) Geiger-mode avalanche photodiode arrays integrated with CMOS timing circuits. In: IEEE annual device research conference digest, pp 58–59 6. Warner K, Burns J, Keast C, Kunz R, Lennon D, Loomis A, Mowers W, Yost D (2002) Lowtemperature oxide-bonded three-dimensional integrated circuits. In: IEEE international SOI conference proceedings, pp 123–124 7. Burns J, McIlrath L, Hopwood J, Keast C, Vu DP, Warner K, Wyatt P (2000) An SOI-based three-dimensional integrated circuit technology. In: IEEE international SOI conference proceedings, pp 20–21 8. Topol A, Tulipe D, Shi S, Alam S, Frank D, Steen S, Vichiconti J, Posillico D, Cobb M, Medd S, Patel J, Goma S, DiMilia D, Farinelli M, Wang C, Conti R, Canaperi D, Deligianni L, Kumar A, Kwietniak T, D’Emic C, Ott J, Young A, Ieong M (2005) Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). In Technical Digest - IEEE International Electron Devices Meeting, pp. 363–366 9. Reif R et al (2002) 3-D interconnects using Cu wafer bonding: technology and applications. In: Advanced metallization conference (AMC) 10. Warner K, Chen C, D’Onofrio R, Keast C, Poesse S (2004) An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication. In IEEE international SOI conference proceedings, pp 71–72
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11. Fukushima T, Yamada Y, Kikuchi H, Koyanagi M (2005) New three-dimensional integration technology using self-assembly technique. In: Technical digest – IEEE international electron devices meeting, pp. 359–362 12. Tropol AW, La Tulipe DC Jr, Shi L, Frank DJ, Bernstein K, Sheen SE, Kumar A et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5):491–506 13. Tezzaron Semiconductor, Naperville, IL 60563, http://www.tezzaron.com/technology/ FaStack.htm 14. Burns JA, Aull BF, Chen CK, Chen C-L, Keast CL, Knecht JM, Suntharalingam V, Warner K, Wyatt PW, Yost D-RW (2006) A wafer-scale 3-D circuit integration technology. IEEE Trans Electron Devices 53(10):2507–2516 15. Van Olmen J, Mercha A, Katti G, Huyghebaert C, Van Aelst J, Seppala E et al (), “3D stacked IC demonstration using a through silicon via first approach. IMEC. http://www.imec.be/ ScientificReport/SR2008/HTML/1224951.html 16. (2008) International Technology Roadmap for Semiconductors: ITRS. Semiconductor Industry Association, San Jose, CA http://www.itrs.net/Links/2008ITRS/Home2008.htm 17. Knickerebocker JU, Andry PS, Dang B, Horton RR, Interrante MJ, Patel CS et al (2006) Three-dimensional silicon integration. IBM J Res Dev 50(4/5):553–567 18. Burns J, McIlrath L, Keast C, Lewis C, Loomis A, Warner K, Wyatt P (2001) Threedimensional integrated circuits for low-power, high-bandwidth systems on a chip. In: Digest of technical papers. IEEE international solid-state circuits conference, pp 268–269, 453 19. Knecht J, Yost D, Burns J, Chen C, Keast C, Warner K (2005) 3D via etch development for 3D circuit integration in FDSOI. In IEEE Int. SOI Conf. Proc., pp 104–105 20. Maszara WP, Goetz G, Caviglia A, McKitterick JB (1988) Bonding of silicon wafers for silicon-on-insulator. J Appl Phys 64(10):4943–4950 21. Chen CL, Chen CK, Burns JA, Yost D-R, Warner K, Knecht JM, Wyatt PW, Shibles DA, Keast CL (2007) Thermal effects of three dimensional integrated circuits stacks. In: IEEE international SOI conference proceedings, pp 91–92 22. Sri-Jayantha SM, McVicker G, Bernstein K, Knickerbocker JU (2006) Thermalmechanical modeling of 3D electronic packages. IBM J Res Dev 50(4/5):553–567, 623–634 23. Mentor Graphics, IC Nanometer Design Tool Suite 24. Cadence Virtuoso Design Tool 25. Suntharalingam V, Berger R, Clark S, Knecht J, Messier A, Newcomb K, Rathman D, Slattery R, Soares A, Stevenson C, Warner K, Young D, Ang LP, Mansoorian B, Shaver D (2009) A fourside tileable, back illuminated, three-dimensionally integrated megapixel CMOS image sensor. In: Digest of technical papers. IEEE international solid-state circuits conference, pp 38–39 26. Warner K, Oakley DC, Donnelly JP, Keast CL, Shaver DC (2006) Layer transfer of FDSOI CMOS to 150 mm InP substrates for mixed-material integration. In: International conference on indium phosphide related materials, pp 226–228 27. Aull B, Burns J, Chen C, Felton B, Hanson H, Keast C, Knecht J, Loomis A, Renzi M, Soares A, Suntharalingam V, Warner K, Wolfson D, Yost D, Young D (2006) Laser radar imager based on three-dimensional integration of Geiger-mode avalance photodiodes with two SOI timing-circuit layers. In Digest of technical Papers. IEEE international solid-state circuits conference, pp 304–305
Chapter 3
TSV Characterization and Modeling Michele Stucchi, Guruprasad Katti, and Dimitrios Velenis
3.1 Definition and Structure of a TSV The through-silicon via (TSV) is composed of a conductor, also named “nail” or “plug,” crossing the Si substrate of the stacked dies [1, 2], as shown in Fig. 3.1. The conductor [common material choices include copper (Cu), tungsten (W), and polysilicon] is electrically insulated from the substrate by a dielectric layer (usually SiO2) and interconnects the metal wires of the stacked dies. The geometry of the TSV conductor may vary depending on the 3D stacking technology. The area crossed by current may have different shapes (squared, rectangular, circular, elliptical, and polygonal) [3]. Also, the lateral surface of the conductor can be cylindrical or conical. The TSV interconnection of metal wires in adjacent dies within a 3D stack can follow different schemes [2]. For example, TSVs can connect a Metal 1 (M1) wire of the top die with the topmost MN wire of the bottom die [4] when the latter features N-level wire hierarchy, as shown in Fig. 3.2. Another scheme may foresee the connection of both the topmost MN layers of two adjacent stacked dies. The electrical link established by a TSV between dies can be utilized for any of the typical functions supported by standard 2D interconnects: signal (analog and/or digital), clock, and power supply/ground links. In general, the geometry and the materials used in all the TSVs crossing a die are the same and this simplifies the optimization of the 3D technology process. Once the TSV technology is fixed, the only degree of freedom in achieving different design requirements in the electrical characteristics of TSV links is to employ more TSVs in parallel in the same link. For example, this can be utilized in power supply distribution networks, where high DC current capability is required and low-resistance interconnects are desirable. Connecting multiple TSVs in parallel can decrease the resistance of power/ground links among the
M. Stucchi () IMEC vzw, Leuven, Belgium e-mail:
[email protected] A. Papanikolaou et al. (eds.), Three Dimensional System Integration: IC Stacking Process and Design, DOI 10.1007/978-1-4419-0962-6_3, © Springer Science+Business Media, LLC 2011
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Fig. 3.1 Through-silicon via providing electrical links among multiple vertically stacked die
Fig. 3.2 Cross-section of a TSV
stacked dies. In addition, an increase in the parasitic TSV capacitance due to multiple parallel TSVs can also contribute to compensating dI/dt effects, similar to the effect of inserting large decoupling capacitors. The electrical parameters of a TSV, namely, RTSV , LTSV , and CTSV would strongly depend on the TSV structure (both geometry and materials). This dependence is discussed in Sect. 3.2.
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3.2 Electrical Characteristics of a TSV: RTSV , CTSV , LTSV In this section, the resistance, inductance, and capacitance of a TSV are modeled and analyzed. The analysis is limited to low-frequency regime. The parameters are evaluated with static solvers and analytical formulas, and the obtained results are compared with electrical measurements where applicable. The TSV electrical parameter values can be used in basic circuit analysis of 3D interconnect links in digital applications with clock frequency of a few hundreds of megahertz. High-frequency analysis and modeling require the use of Maxwell equation solvers [5] and they are not considered here. In the discussion that follows, the geometry of the TSV is assumed to be cylindrical; other geometries require the use of the appropriate geometrical models and formulas.
3.2.1 TSV Resistance The electrical dc resistance of a uniform conductor is given by the known formula:
R=
rL , A
(3.1)
where L is the conductor length, A is the conductor section crossed by the electrical current and assumed constant along L, and r is the resistivity of the conductor material. For a cylindrical TSV, as shown in Fig. 3.3, A = p (d/2)2 where d is the diameter of the conducting plug, given by d = D – 2t, where D is the diameter of the TSV and t is the thickness of the insulator between the conducting plug and the substrate. The thickness T of the substrate after thinning determines the length of the plug; since L = T, for a TSV the formula (3.1) becomes
RTSV =
rT
p (d / 2 )
2
.
(3.2)
Equation (3.2) is the resistance introduced by a TSV assuming that the contact resistances with the metal layers above and below the TSV are negligible. Several values of TSV resistance are calculated using (3.2) and are listed in Table 3.1 for a reasonable set of geometrical parameters. Copper (Cu) with a resistivity of 1.7 mW cm is assumed as the conducting plug for calculating RTSV in Table 3.1. RTSV simulations by a static solver (Raphael™ by Synopsis [6]) assuming the same TSV geometries are also included in Table 3.1. The simulations are based on a realistic current distribution inside the TSV from the metal connection on the top to the landing pad on the bottom. The results in terms of resistance are consistent with those obtained by using the simple analytical formula (3.2).
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Fig. 3.3 Geometrical parameters of a cylindrical TSV used to calculate the TSV resistance RTSV Table 3.1 Analytical model and Raphael simulations results for RTSV D (mm) 2 2 5 5 10 10
t (nm) 50 100 50 100 1,000 2,000
T (mm) 20 20 20 20 50 50
RTSV (mW) (analytical) 118.5 132.0 17.8 18.6 16.7 29.7
Table 3.2 Comparison of RTSV values obtained by simulations TSV chain Single TSV link Number of resistance (W) resistance (mW) TSVs in chain (measured) (measured) 8 0.704 175.9 98 10.292 210.1 998 106.222 212.9
RTSV (mW) (simulated) 119.3 132.8 17.9 18.7 16.9 30.0
Deviation (%) 0.6 0.6 0.6 0.6 0.9 0.9
measurements on TSV chains and Single TSV link resistance (mW) (simulated) 183.6 183.6 183.6
Deviation (%) 4.382 12.599 13.756
For all the TSV dimensions considered for the Cu plug, RTSV is always estimated to be below 200 mW. For a mature and optimized 3D bonding process with micrometer scale TSV geometries, the TSV contact resistance value is very small, therefore maintaining the total RTSV in the milliohm range. Electrical measurements on a typical TSV chain, which is illustrated in Figs. 3.4a, b, are listed in Table 3.2 and show values of resistance of ~200 mW per link, which includes two TSVs plus the metal connections between them and to the next link. Raphael™ simulation results for a single TSV link are illustrated in Fig. 3.4c and show good agreement between measurement and simulations. It is also shown in Table 3.2 that the percent deviation increases with the number
3 TSV Characterization and Modeling
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Fig. 3.4 (a) Schematic representation of a TSV chain. (b) SEM picture of a TSV chain after etching away the substrate of the top die. (c) Single TSV chain link simulated in Raphael™
of TSVs in the chain; this can be attributed to a larger spread of the higher values of TSV resistance for longer TSV chains. Specific test structures for measuring TSV resistance can be found in [7].
3.2.2 TSV Capacitance An individual TSV structure is shown in Figs. 3.5 and 3.6 and it can be viewed as a cylindrical MOS capacitor structure considering the conducting plug as the gate and substrate contact as ground. Therefore, the TSV capacitance behavior is similar to the MOS behavior [7]. C–V characteristics of the TSV with p-Si substrate will follow a similar pattern as planar MOS C–V characteristics with p-Si substrate. Based on the TSV bias (VTSV), there are three distinct regions of operations, namely, accumulation, depletion, and inversion as illustrated in Fig. 3.7. Accumulation region: Accumulation occurs for large negative bias of the TSV plug with respect to the p-Si substrate. At this bias, majority charges accumulate at the Si-SiO2 interface and act as a conductive plate, thus making the total TSV capacitance equal to the insulator capacitance. For a cylindrical TSV structure, as shown in Fig. 3.6, the insulator capacitance is given by the following formula (3.3):
C=
2p e i L ln [b / a ]
(3.3)
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Fig. 3.5 Components of TSV capacitance: the insulator capacitance CINS and the depletion capacitance CDEP
Fig. 3.6 Illustration of capacitance for a cylindrical structure in Si substrate
where L is the TSV length, which is equal to the substrate thickness T, ei is the dielectric constant of the insulator, d = 2a is the diameter of the Cu conductive plug, and D = 2b is the TSV diameter. Therefore, the thickness of the insulator oxide is: t = (b − a) = (D − d )/2. Substituting these parameters of the TSV, equation (3.3) becomes CINS =
2p e iT . ln [D/d ]
(3.4)
3 TSV Characterization and Modeling
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Fig. 3.7 Accumulation, depletion and maximum depletion regions on a C–V curve for a TSV characterized as a metal–insulator–semiconductor capacitor
Depletion region: In a p-type substrate, if a positive enough voltage VTSV is applied to the TSV with respect to the substrate, a depletion region and consequently a depletion region capacitance will be formed. In the depletion region, majority carriers in the substrate are pushed away from the substrate–insulator interface and form a depletion capacitance in series with the insulator capacitance as shown in Fig. 3.5. As a result, the total MOS capacitance is reduced. The width of the depletion region determines the reduction of the TSV capacitance and it depends upon several factors, such as the TSV diameter, the oxide thickness of the insulator layer, the work function of the metal and oxide charges, the doping of the substrate, etc. [8]. The detailed analytical model [9–10] is obtained by solving the 1-D Poisson’s equation in cylindrical co-ordinate system with adequate boundary conditions and the depletion TSV capacitance is given by the following analytical expression: CDEP =
2πTε Si , ln [DDEP /D ]
(3.5)
where DDEP is the diameter of the boundary of the depletion region in the substrate surrounding the TSV, as shown in Fig. 3.6; eSi is the dielectric constant of the Si substrate. DDEP depends on the voltage VTSV applied to the TSV with respect to the Si substrate. When a depletion region is formed, the total TSV capacitance is given by the series of CINS and CDEP:
CTSV =
CINS CDEP . CINS + CDEP
(3.6)
By substituting (3.4) and (3.5) into (3.6), it is possible to calculate analytically the total capacitance of the TSV in the depletion region.
40 Table 3.3 Analytical model and Sdevice™ simulation results inversion regions CINS (fF) CINS (fF) accumulation accumulation (simulation) D (mm) T (nm) Na (cm−3) (analytical) 5 120 2E15 88.23 88.4 5 120 1E17 88.23 88.4 2 50 2E15 84.61 84.77 2 50 1E17 84.61 84.77
M. Stucchi et al. for CTSV in accumulation and
Deviation (%) 0.199 0.199 0.185 0.185
CTSVmin (fF) (simulation) 37.20 69.98 21.65 52.37
Inversion-minimum depletion capacitance region: For low-frequency signals, the holes and electrons in the p-Si substrate respond to the signals on the gate and electrons get accumulated at the silicon–insulator interface, thus inverting the substrate type. As a result, the substrate gets isolated from the gate and the inversion TSV capacitance value increases to CINS as shown in Fig. 3.7. Alternatively for high-frequency signals, holes and electrons in the p-Si substrate do not get sufficient time to respond to the changes on the gate and the depletion width stays pinned to its maximum value offering minimum depletion capacitance CTSV = CTSVmin. Comparison between Sdevice™ [11] simulations and the analytical model for the TSV capacitance in accumulation (3.4) is presented in Table 3.3 for various TSV parameters. The analytical model is able to accurately predict CINS in accumulation for different values of TSV diameter and oxide liner thickness. Minimum depletion capacitance CTSVmin can also be calculated by simulation by specifying the value of the following parameters: The work function difference between metal conductor and Si substrate: fms = fm − fs, and the doping density of the p-substrate: Na. Simulated values for CTSVmin using Sdevice™ are also listed in Table 3.3. 3.2.2.1 TSV Capacitance vs. Supply Voltage TSV C–V behavior suggests that the TSV capacitance is voltage dependent and would depend upon the operating region of the TSV. Furthermore, TSV capacitance in the accumulation and maximum depletion regions could differ by a factor of 2 or more, according to simulation results performed on TSVs with 5 mm diameter, 20 mm length, and oxide insulator thickness of ~120 nm. Such C–V behavior of TSVs might represent a problem and an opportunity at the same time. If the depletion region corresponds to zero or negative TSV voltages, as shown in Fig. 3.8a, the capacitance seen by the signals propagating along TSVs is lower than the insulator capacitance, thus allowing faster signal propagation (lower RC delay) and lower dynamic energy consumption (E = aCV2, where a is the signal activity factor). The problem arises if the depletion region occurs at the range of the supply and signal voltages, as illustrated in Fig. 3.8b; this would create a voltage-dependent TSV capacitance, thus forcing the design of 3D circuits to be conservative and consequently more energy consuming. Option (c) in Fig. 3.8 would offer a maximumTSV capacitance which is ideally not desired. Therefore, an upfront C–V characterization
3 TSV Characterization and Modeling
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Fig. 3.8 Possible occurrences of the depletion region for TSV capacitance. (a) At negative or zero voltages, (b) at the VDD range, (c) at voltages higher than the TSV operating voltage range
of the TSV capacitance for a given 3D technology, prior to the circuit design phase, is very important. Various techniques that reduce the TSV capacitance to improve the 3-D IC performance are detailed in [12]. Test structures for TSV capacitance characterization are proposed and described in [7]. 3.2.2.2 TSV Crosstalk The coupling between adjacent TSVs cannot be trivially treated in an analytical way as a parallel plate capacitor with fringing capacitance, which is the standard approach for 2D interconnects. Both the geometry and the equivalent circuit of the coupled TSVs are rather complex due to the cylindrical shape of TSVs and the semiconductor nature of the substrate between them, as shown in Fig. 3.9. The silicon substrate among the TSVs is connected to the ground; therefore, a few electric field lines would be originating from one TSV and terminating on the other, providing a minimal mutual capacitance between neighboring TSVs. This mutual capacitance can be reduced further with increasing the distance between the TSVs (i.e., the TSV pitch). The crosstalk between two TSVs in the presence of a substrate contact, as shown in Fig. 3.10, has been simulated in Sdevice™. For the simulation, a voltage pulse of 1.2 V, 100 ps duration, and 5 ps rise/fall time is applied on one TSV (i.e., the aggressor TSV), and the resulting voltage on the other TSV (i.e., the victim TSV) is measured. For the simulation experiment, different insulator oxide thicknesses and different TSV pitches are considered, together with different positions of the substrate contact. The simulation results are listed in Table 3.4. The crosstalk voltage among TSVs is reduced with increasing pitch. In addition, by increasing the thickness of the insulator oxide, the crosstalk is also reduced since the capacitive coupling between the TSVs and the substrate is lower. Finally, the distance of the ground substrate contact from the TSVs (DGND) is considered. As the distance of the ground contact from the TSVs increases, the resistance of the substrate to the ground increases and more electric field lines are likely to originate and terminate on neighboring TSVs, thus increasing coupling. Therefore, the amount of crosstalk between TSVs increases as the ground contact is placed farther away from the TSV pair. According to the parameters considered in Table 3.4, a ground contact can be placed up to
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Fig. 3.9 Equivalent circuit describing capacitive crosstalk interaction among TSVs
Fig. 3.10 Setup for crosstalk simulation among two neighboring TSVs, considering the effect of a substrate ground contact Table 3.4 Simulation of crosstalk between pair of TSV for different pitch length, insulator oxide thickness, and distance of the substrate ground contact Ground contact Induced voltage D (mm) t (nm) TSV pitch (mm) distance (mm) (% of VDD) 5 5 5 5 5 5 5 5 5
50 50 50 50 50 50 100 100 100
10 10 10 20 20 20 10 10 10
0 100 1,000 0 100 1,000 0 100 1,000
0.00625 0.00627 7.62 1.43E-06 1.42E-06 0.95 0.00730 0.00755 0.00852
3 TSV Characterization and Modeling
43
500 mm away from the TSV pair without significant effects on the amount of crosstalk between the two TSVs. The amount of coupling is expected to increase in the presence of additional TSV aggressors surrounding a victim TSV. However, placing contacts to the ground in smaller distances among TSVs is expected to keep crosstalk at a negligible level, even in this case. 3.2.2.3 TSV Leakage Current and Breakdown Voltage The leakage current and breakdown voltage of a TSV are as important as the TSV resistance and capacitance. In fact, a leaky TSV represents a waste of static energy toward the substrate, and a consequent potential voltage drop on interconnects that could violate the noise margins of the digital signals. The TSV should also withstand potential overstresses caused by ESD-EMI events without being damaged and becoming leaky. One of the potential contributing factors to the TSV leakage and breakdown is the lack of uniformity of the insulator layer thickness: local reduction of oxide thickness increases locally the electric field between the plug and the substrate, thus increasing the possibility of leakage and breakdown. The quality of the insulator layer is therefore of capital importance, however, limited data is available on these reliability aspects [13]. In ideal conditions, by considering an oxide insulator thickness of ~100 nm, and assuming the ideal oxide breakdown strength at ~8 MV/cm, the TSV breakdown should occur at ~80 V. In reality, this value could be much lower, since the oxide breakdown strength is weakened during processing due to undesired effects such as plasma damage and moisture uptake. Furthermore, the roughness of the TSV sidewall at the substrate side could also create protrusions that increase the electric field. Various test structures to evaluate the TSV leakage and breakdown along with measurements are detailed in [7].
3.2.3 TSV Inductance The inductance contribution of a TSV in a current loop – or partial inductance – depends on both the self- and mutual-inductive components of a TSV. However, specifying these components requires that the current loop of the TSV and any other neighboring current loops linked with that one are precisely defined. Since this information is not available a priori, the only possible evaluation of the TSV partial inductance is by considering a current return path at infinity. This quantity can be determined by an analytical formula [14]. For the cylindrical-shaped TSV assumed in this chapter, the partial self-inductance depends upon the TSV diameter and length, and is given by the following expression [14]: LTSV =
2T + r 2 + 2T )2 ( mo 2 TSV 2 + rTSV − rTSV + (2T ) 2T ln 4p r TSV
(
,
)
(3.7)
44
M. Stucchi et al. Table 3.5 Analytical model results for LTSV D (mm)
t (nm)
T (mm)
L TSV (pH)
2 2 5 5 5 5 10 10
50 100 50 100 50 100 1,000 2,000
20 20 20 20 50 50 50 50
13.83 14.04 10.19 10.26 34.27 34.47 29.52 32.29
where mo is the permeability of free space given by 4p × 10−7 H/m, rTSV = d / 2, and T = TSV length. In Table 3.5, the partial self-inductance values obtained with (3.7) for different dimensions of the TSV are listed. By considering the frequency at which the reactive part of the TSV impedance becomes comparable with the resistive part, RTSV £ w LTSV, the TSV partial self-inductance can be considered negligible in first approximation for frequencies up to ~3 GHz. Signal rise times containing such frequency components correspond to clock signals with a frequency in the order of 10% of this value, namely, ~300 MHz [15].
3.3 Impact of TSV Geometry and Material Parameters on RTSV and CTSV The simulations and analytical formulas presented so far can be used to determine the impact of geometry and material parameters on the resistance, capacitance, and inductance of a TSV. It is then possible (1) to predict the electrical characteristics of a TSV given the technology parameters such as diameter, insulator layer thickness, dielectric constant of the insulator, and resistivity of the plug conductor; (2) to find the technology parameters which provide the desired values of RTSV, CTSV, and LTSV by exploring the technology parameter space within a specific range of dimensions and/or material parameters. Both (1) and (2) are very important analyses for circuit design and process tuning, respectively. In Figs. 3.11a–e, examples of exploration of the impact of technology parameters on R TSV , C TSV , and L TSV are demonstrated. In Fig. 3.11a, the effect of TSV diameter and dielectric oxide thickness on the resistance of a TSV is illustrated. It is shown that varying the value of the dielectric oxide thickness can affect the resistance of a TSV only for diameter lengths shorter than 2 µm. The impact of the same geometrical parameters on the TSV capacitance at accumulation and inversion regions is illustrated in Figs. 3.11b, c, respectively. As shown in Fig. 3.11b, the capacitance of a TSV in accumulation is affected by the value of the dielectric oxide thickness predominantly at long diameter lengths. Also, the TSV capacitance in maximum depletion region depends on both the TSV diameter and the oxide thickness as shown in Fig. 3.11c. Notice, however, that the TSV capacitance values
3 TSV Characterization and Modeling
Fig. 3.11 Impact of TSV geometry and materials on electrical characteristics
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in maximum depletion region that are shown in Fig. 3.11c are significantly lower than the corresponding values in accumulation shown in Fig. 3.11b for the same values of TSV diameter and dielectric oxide thickness. Furthermore, the effect of the TSV diameter D and length T on the self-inductance of a TSV is illustrated in Fig. 3.11d. As shown in Fig. 3.11d, changing the TSV diameter has a small effect on the inductance of a TSV for short TSV lengths. However, this effect becomes more prominent when the TSV length is within the range of 20–25 µm. In this case, increasing the diameter of the TSV results in a reduction in the partial self- inductance of the TSV. Finally, the effect of substrate doping on the capacitance of a TSV in maximum depletion region is illustrated in Fig. 3.11e. It is shown in this figure that increased doping of the substrate increases the TSV capacitance, especially for low dielectric thickness values. A complete example of using this information for designing an optimal 3D system is reported in [16].
3.4 Electrical Modeling of a TSV The basic electrical model of the TSV consists of a lumped RLC network, as shown in Fig. 3.12a. RTSV and L TSV cause the voltage drop along the interconnected nodes between Metal 1 of the top die and the top metal of the bottom die. Shunt path for the current is provided by CTSV connected between TSV and ground. As suggested in Sect. 3.2, for contemporary TSV dimensions, L TSV is predominant only for frequencies above 3 GHz when RTSV £ w L TSV . By ignoring the inductance, the approximate model is a simplified RC model as shown in Fig. 3.12b. The model has been successfully validated using the 2D/3D Ring Oscillator power-delay measurements and simulations [17]. At high frequencies, the electrical model of a TSV becomes more complicated.
Fig. 3.12 Lumped models for TSV impedance
3 TSV Characterization and Modeling
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3.4.1 Impact of TSV on Interconnect Links By considering the RC model of a TSV in a typical transmitter–interconnect– receiver link, it is possible to estimate its impact on speed and energy consumption of such a link. The impact of R TSV and CTSV on circuit delay can be analyzed with the help of the schematic shown in Fig. 3.13. In this schematic, an inverter is placed on the bottom die driving an inverter on the top die through TSV and wire RC loads. The entire network in the signal path is shown in Fig. 3.13. Cext and Cint indicate the output and input capacitances of an inverter, respectively. Rw_B and Cw_B denote the lumped interconnect wire load on the bottom die, while Rw_T and Cw_T represent the lumped wire load on the top die. The Elmore delay of the link can be expressed as:
tp = 0.69Rdr Cext
( + 0.69 (R + 0.69 (R
)
+ 0.69 Rdr + nRw _ B Cw _ B
)
dr
+ Rw _ B + 0.5RTSV CTSV
dr
+ Rw _ B + RTSV + Rw _ T Cw _ T + Cint ,
)(
(3.8)
)
where Rdr is the driving resistance of the inverter. First-order calculations [18] indicate that Cint and Cext are in the order of ~3 fF while the driving resistance of inverter is in the order of kilo ohms for 0.25 mm technology. Since CTSV = 35 fF, the TSV capacitance is much larger than the Cint and Cext values, and the term (Rdr + Rw_B + 0.5RTSV)CTSV would have a dominant effect in the signal delay described by (3.8). It can also be seen in (3.8) that the term RTSV is always added to the driving resistance of the inverter Rdr and to the BEOL resistances Rw_B and Rw_T . Since, smaller wire cross-sections and longer interconnect lengths produce larger BEOL resistances, RTSV values of ~20 mW in contemporary TSV architectures would have a minimal impact on the delay. The predominant impact of CTSV and the reduced impact of RTSV approximate the lumped TSV impedance model with a single capacitor, as shown in Fig. 3.12c.
Fig. 3.13 Equivalent circuit model for a pair of inverters on stacked die, connected through a TSV
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3.5 Conclusions In this chapter, an electrical model of the TSV has been presented. Since the TSV provides an electrical link between interconnects of 3D stacked dies, it is important to know how the basic electrical parameters such as resistance R TSV , capacitance CTSV , and inductance L TSV are related to geometry and physical parameters of the materials used in TSV architectures. From a circuit design perspective, it is also important to have an electrical model of the TSV that describes the most relevant effects and allows for first-order approximations of signal speed and energy in 3D interconnect links. This chapter has provided a basic investigation of these aspects. In addition, aspects related to reliability of TSVs such as leakage mechanisms and breakdown voltages have also been discussed. The validity of the proposed models can be extended to high-frequency regime by using proper simulation tools, test structures, and electrical measurements.
References 1. Topol AW et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5):491–506 2. Beyne E (2006) The rise of the 3rd dimension for system integration. In: Proceedings of international interconnect technology conference, Burlingame, CA, 5–7 June, pp 1–5 3. Pak JS, Ryu C, Kim J (2007) Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation. In: Proceedings of international conference on electronic materials and packaging, Daejeon, 19–22 November, pp 19–22 4. Van Olmen J et al (2008) 3D stacked IC demonstration using a through silicon via first approach. IEDM Technical Digest pp 603–606 5. Kamon M, Silveira L et al (1996) FastHenry USER’S GUIDE: version 3.0, Massachusetts Institute of Technology, November, ftp://rle-vlsi.mit.edu/pub/fasthenry 6. Raphael Interconnect Analysis Program Reference Manual (2007) Version A-2007.09, Synopsis Inc., Mountain View, CA 7. Stucchi M, Perry D. Katti G. Dehaene W (2010) Test structures for characterization of through silicon vias, IEEE International Conference on Microelectronic Test Structures (ICMTS) 8. Sze SM (1981) Physics of semiconductor devices. John Wiley & Sons, New York 9. Katti G et al (2010) Electrical Characterization & Modeling of Through Silicon Via (TSV) for 3D ICs, IEEE Transactions on Electron Devices, Volume 57, Issue 1; Jan, pp 256–262 10. Bandyopadhyay T, Chatterjee R, Chung D, Swaminanithan M, and Tummala R (2009) Electrical modeling of through silicon and package vias, IEEE Inter. Conf. 3D System Integration, Sep, pp 28–30 11. Sentaurus Device User Guide (2008) Version A-2008.09, Synopsis Inc., Mountain View, CA 12. Katti G, Stucchi M, Olmen JV, Meyer KD, and Dehaene W (2010) Through-silicon-via capacitance reduction technique to benefit 3-D IC performance, IEEE Electron Device Lett., vol. 31, no. 4, Jun, pp 549–551 13. Kikuchi H et al (2008) Tungsten through-silicon via technology for three-dimensional LSIs. Jpn J Appl Phys 47(4):2801–2806 14. Pucel R (1985) Gallium arsenide technology, Technology and Design Considerations of Monolithic Microwave Integrated Circuits. In: Ferry D (ed) Howard W. Sams and Co., Indianapolis, IN, chapter 6, pp 216
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1 5. Young B (2001) Digital signal integrity. Prentice Hall, New York, pp 45 16. Marchal P et al (2009) 3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot, Proceedings of the IEEE, Volume: 97, Issue: 1, pp 96–107 17. Katti G et al (2009) 3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective Bonding, in IEDM Tech. Dig., pp 357–360 18. Rabaey J et al (2003) Digital integrated circuits, Upper Saddle River, New Jersey 07458, 2nd edn. Prentice Hall Electronics and VLSI Series
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Chapter 4
Homogeneous 3D Integration Robert Patti
4.1 Introduction This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like materials or components – but also provides information about homogeneous 3D assemblies in combination with other 2D or 3D devices. One example of homogeneous integration is the stacking of memory layers to create a 3D memory device. In such a device, the component layers are usually made of the same material and are often virtually identical in design. This chapter uses 3D DRAM as a reference application.
4.2 3D Assembly Options There are three basic ways to assemble 3D devices: wafer-to-wafer (W2W), dieto-wafer (D2W), and die-to-die (D2D). Each method has its advantages; each application must be examined to determine the best way to realize the cost benefits of 3D. W2W assembly is potentially the most cost effective because wafer-level handling and processing allows hundreds or thousands of devices to be created at once. On the other hand, D2W and D2D work well for dissimilar materials where the mismatch in thermal coefficient of expansion (TCE) might make W2W impractical. Almost all 3D assembly processes require processing at temperatures of 300°C or higher. Higher temperatures and higher TCE mismatch cause problems with alignment and increase the induced stress within the part. However, 3D assembly with homogeneous material suffers minimal TCE mismatch and is therefore ideal for W2W bonding.
R. Patti (*) Tezzaron Semiconductor, Naperville, IL, USA e-mail:
[email protected] A. Papanikolaou et al. (eds.), Three Dimensional System Integration: IC Stacking Process and Design, DOI 10.1007/978-1-4419-0962-6_4, © Springer Science+Business Media, LLC 2011
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A critical factor in 3D processing is ultimate device yield. A 3D assembly has approximately the same yield as the equivalent 2D device – for example, a four-layer stack of size 5 × 5 mm will have yield equivalent to a single-layer die measuring 10 × 10 mm. Unless extraordinary techniques are used to address yield, 3D will have limited appeal. D2W and D2D assembly techniques allow the use of a known good die (KGD) protocol that can produce yields superior to the equivalent 2D die, but this is at the cost of additional handing. Another effective way to address yield is with built-in repair and redundancy. The underlying repetitive design of memories, FPGAs, and image sensors make these devices readily capable of built-in repair and redundancy schemes; indeed, most of them already use such schemes. As a result, these applications are excellent candidates for wafer-bonded 3D devices. They can be made into the equivalent of huge 2D dies yet maintain reasonable yield by repair and redundancy without any KGD techniques. Our reference application, 3D DRAM, uses homogeneous materials and repair-and-redundancy schemes, so it is ideally suited for cost-effective W2W assembly. Many other high-volume lower-margin devices fall into the realm of W2W bonding for the same reasons.
4.2.1 W2W Alignment Wafer-to-wafer alignment in 3D-assembled circuits, measured post bonding, is ~1 mm three sigma for 300 mm wafers using a copper-to-copper bonding process. Oxide bonding, such as that used in the Ziptronix DBI® (direct bond interconnect) process, can achieve a more precise alignment of ~0.5 mm because the initial bond is performed at room temperature. Frequent topics of debate in 3D discussions are what the alignment needs to be, and what the road map should look like. There may or may not be a need to improve significantly beyond the current equipment. Unlike the shrinking 2D design rules, 3D must contend with the metal interconnect layers and a finite substrate thickness. If the vertical direction is 10 mm (today, 10–12 mm is the norm for Tezzaron), then staying in the 2D plane still makes sense a lot of the time. One would not choose to go vertically 10 mm if one can instead go horizontally 1 mm. Thus, 3D wafer alignment is already in the correct range for most, if not all, applications. Certainly there will be improvements in the equipment and there will be applications that can drive the vertical pitch requirement lower, but today’s capabilities probably exceed requirements. The tightest pitch requirement presented to Tezzaron to date was for a frontside-to-frontside bond at 1.4 mm. The pitch was necessary for pixel pitch interfacing of a CMOS image sensor. Because it was a face-to-face bond, through-silicon via (TSV) pitch was not involved; the only requirement was tight wafer-to-wafer alignment.
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4.3 3D Bonding Options 3D integration has drastically improved in the last 10 years. Numerous entities have demonstrated void-free bonding of wafers and thinning wafers to only a handful of microns. The most promising 3D assembly technologies seem to be those that can accomplish both the mechanical interconnect and the electrical interconnect at the same time. There are at least three bonding processes that offer this one-step interconnection: copper-to-copper, copper-tin eutectic, and direct oxide. The market will likely find more than one effective process, but the one that offers the best price performance is most likely to succeed in the market. Copper-to-copper metal bonding seems to have the edge. Wafers can literally be taken right from the fab with no special surface processing and no additional deposition steps, cleaned (a slight oxide etch), and bonded. The other bonding process options require more work up front. The copper-to-copper bonding seems to produce the required bond quality and at the lowest price point, but the other flows may have advantages that stem from lower temperatures and higher throughput. Market forces will ultimately pick the best techniques.
4.4 Wafer-to-Wafer Assembly This section offers an example of 3D W2W assembly using Tezzaron’s SuperContact™ enabled wafers and copper-to-copper thermal diffusion bonding. Tezzaron’s stacking method uses a “vias-middle” approach to integrate two or more wafers into a fully interconnected wafer stack. Hundreds of thousands of TSVs are built into the circuitry of the wafers. The base wafer may be built with or without TSVs, as desired. Tezzaron’s “SuperContact™” TSVs may be either copper or tungsten, and may be laid down before the first metal contact layer or created at a later processing stage. In all cases, creating the TSVs requires a new process module at the vendor fab. The module has proven relatively easy to add and does not introduce any new materials at the stage where the TSVs are added. To lay down TSVs after transistors have been created, but before any contact metal, the TSVs are etched through the oxide and into the silicon substrate approximately 6 mm. The walls are lined with SiO2/SiN. The TSVs are filled with tungsten or copper and finished with chemical-mechanical polishing (CMP). This completes the unique processing requirements at the wafer level. The wafer is then finished with its normal processing, which can include a combination of aluminum and copper wiring layers. The top layer must be copper. The top is metallized with a 0.5-mm SiO2 insulating glass layer followed by a 1.0-mm Cu metal bonding layer. The bonding layer, formed by a copper single- or dual-damascene process, is laid out in a proprietary design of bondpoints (Fig. 4.1). All wafers, including the base wafer, are metallized in this manner. The oxide surface is then slightly recessed, leaving the bondpoints elevated above the oxide.
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Dielectric (SiO2/SiN) Gate poly STI (Shallow trench isolation)
Silicon (full depth not shown)
TSV
W (Tungsten TSV & vias) Al or Cu interconnect (M1–M5) Cu bondpoints (M6, top metal)
Fig. 4.1 A tungsten TSV in a six-metal process with Metal 6 as the copper bonding layer
TSV
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Dielectric(SiO2/SiN) Gate poly STI (Shallow trench isolation) W (Tungsten TSV & vias) Al or Cu interconnect (M1 - M5)
Silicon (full depth not shown)
Cu bondpoints (M6, top metal)
Fig. 4.2 Face-to-face bonding
One TSV-enabled wafer is inverted onto the base wafer, frontside-to-frontside, see Figs. 4.2 and 4.3. The wafers are aligned and then bonded, using a thermal diffusion bonding process at
