Solid State Technology Magazine - AUGUST-SEPTEMBER 2011

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AUGUST/SEPTEMBER 2011

Scatterometry Measurement of 28nm Metal Gates Advances in Double-patterning EUV OPC Flow Optimization

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p. 14

p. 18

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D FA B R I C AT I O N E Q U I P M E N T F O R T H E I N T E G R AT E D C I R C U I T I N D U S T R Y

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Solid State Equipment Corporation SINGLE WAFER WET PROCESSING AND CLEANING

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©2010 Solid State Corporation

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A U G / S E P T 2 0 11

Vol. 54 • No. 8

CO N T E N T S The interior of KLA-Tencor’s SpectraShape tool, which includes a multi-azimuth spectroscopic ellipsometer with broadband light extending into the deep UV portion of the spectrum and a polarized, enhanced UV reflectometer.

C OV E R A R T I C L E

F E AT U R E S CDS

11 Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates Measuring CD Data show that a new generation SCD tool has good sensitivity and measurement repeatability for the 28nm HKMG ADI process. Y. H. Huang, et al., United Microelectronics Corporation,Tainan Science Park, Taiwan, C. H. Lin, KLA-Tencor Corp., Milpitas, CA.

14 Double-patterning, topcoat-less RESISTS

photoresists and silicon hard masks Double-patterning, spin-on silicon hard masks, and topcoat-less resists are enabling immersion lithography

D E PA R T M E N T S World News 6 Tech News 8 ■

Is 3D packaging where it needs to be?

Mark Slezak, Brian Osborn, JSR Micro, Inc.,

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AMAT’s DRAM fab tools for denser transistors

Sunnyvale, CA.

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Samsung-Grandis spotlights MRAM potential— and uphill climb

to meet today’s advanced technology node requirements.

Web Exclusives 2

18 EUV OPC flow optimization EUV MASKS

Ad Index 23

for volume manufacturing EUV OPC flows can be optimized to meet stringent production turn-around-time and accuracy requirements of future nodes. Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc.,

COLUMNS

Mountain View, CA, USA

Editorial 4 RESISTS

The 450mm transition: many unanswered questions

by using EUV assist layers

Peter Singer, Editor-in-Chief

Because no single method is delivering the needed

Industry forum 24

reduction in LER, combining the benefits of an assist layer material during EUV lithography and a smoothing

Leveraging collaborations to drive down the LED cost curve

process after lithography might be the dual-prong

Jeff Desroches, ATMI, Inc., Tempe, AZ USA

21 Improving line roughness

solution that is needed. Carlton Washburn, Brewer Science, Inc., Rolla, MO USA

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Solid State Technology

ONLINE Diane Lieberman, Group Publisher Ph: 603/891-9441, [email protected]

Web Exclusives

Peter Singer, Editor-in-Chief Ph: 603/891-9217, [email protected] Meredith Courtemanche, Editor, Digital Media Ph: 603/891-9176, [email protected]

ONLINE AT WWW.SOLID-STATE.COM ___________________

Robert C. Haavind, Editor-at-Large Ph: 603/891-9453, [email protected] Debra Vogler, Senior Technical Editor, Ph: 408/774-9283, [email protected]

SEMICON WEST 2011 This year’s flagship show felt a lot more optimistic all around this year, judging by observations and comments from visitors and exhibitors and even SEMI itself. And SST was busier than ever: More than two dozen video and podcast interviews with industry execs, researchers, and analysts. Half a dozen bloggers—in addition to our own editors—reporting from all areas of the show floor and conference sessions, from 3D integration to FinFETs to EUV, and high-growth markets including LEDs and solar PV. We also rounded up of dozens of new products launched at this year’s show, from front-end processes to backend testing to components in between. Everything is online at electroiq.com/semicon_west_2011.

450mm transition: Must-know changes, cost hurdles Bill Shaner from Entegris discusses key changes in the semiconductor manufacturing industry’s move from 300mm to 450mm wafers: wafer fragility and sag, increased weight, and more capital investment. And Crossing Automation’s Bob MacKnight highlights the industry’s top three cost-related hurdles when it comes to the 450mm wafer size transition—particularly how automation will mesh with new tools.

Renesas post-quake: Rebuilt and revitalized

James Montgomery, News Editor Ph: 603/891-9109, [email protected] Laura Peters, Contributing Editor Phil Garrou, Contributing Editor Rachael Caron, Marketing Manager Cindy Chamberlin, Presentation Editor Katie Noftsger, Production Manager Dan Rodd, Illustrator Debbie Bouley, Audience Development Manager Marcella Hanson, Ad Traffic Manager EDITORIAL ADVISORY BOARD John O. Borland, J.O.B. Technologies Jeffrey C. Demmin, Tessera Technologies Inc. Michael A. Fury, The Techcet Group, LLC Rajarao Jammy, SEMATECH William Kroll, Matheson Tri-Gas Ernest Levine, Albany NanoTech Lars Liebmann, IBM Corp. Dipu Pramanik, Cadence Design Systems Inc. Griff Resor, Resor Associates Linton Salmon, TI A.C. Tobey, ACT International

EDITORIAL OFFICES

Renesas’ rebuilding efforts following the March 11 disaster are the epitome of courage, teamwork, dedication, and learning from adversity—sometimes with unexpected benefits.

PennWell Corporation, Solid State Technology 98 Spit Brook Road LL-1, Nashua, NH 03062-5737; Tel: 603/891-0123; Fax: 603/891-0597; www.solid-state.com CORPORATE OFFICERS 1421 SOUTH SHERIDAN RD., TULSA, OK 74112 TEL: 918/835-3161

CEA LETI Review CEA-LETI gave SST an exclusive look at this summer’s Annual Review, with discussions on a variety of hot topics: sustaining Europe’s semiconductor industry, IDM’s top challenges, III-V/Si integration, and maskless lithography progress.

Frank T. Lauinger, Chairman Robert F. Biolchini, President and CEO Mark Wilmoth, Chief Financial Officer TECHNOLOGY GROUP

When to outsource: Ask the right questions and avoid pitfalls

Christine A. Shaw, Senior Vice President and Publishing Director Gloria Adams, Senior VP, Audience Development

Mark Danna from Owens Design shares a critical list of questions for companies considering outsourcing a project. While outsourcing can benefit mature (semiconductor) and emerging (photovoltaics) markets, the wrong decisions or strategies can destroy all of outsourcing’s proposed benefits.

Lithography CoO, and extending with complimentary e-beam David K. Lam from Multibeam addresses lithography cost-of-ownership, and how the industry does not have to “throw out” optical lithography as it proceeds to more advanced nodes—complementary e-beam lithography (CEBL) is a strong option.

2 Solid State Technology

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EDITORIAL

The 450mm transition: Many unanswered questions

T 

he move to a larger wafer size -- from 300mm to 450mm that process engineers do to keep – has been the focus of an interesting debate for the last driving things forward,” he said. five years. The largest semiconductor manufacturing Presently, although some tools have already been introcompanies in the world – Intel, TSMC and Samsung – have duced, 450mm is still at the feasibility stage. “We don’t really been strongly advocating the move, urging equipment know if we can do it or not,” Johnson said. “Once we start suppliers to start development (which has started) and putting pilot tools in, the costs start going through the roof. SEMI to create the necessary standards (which is done). This is fairly standard. Feasibility is relatively cheap. Hopefully, Equipment suppliers have been understandably slow to we can decide one way or the other whether this will be worth embrace the change, given the long time for them to see it before we start spending cubic gigabucks on R&D.” the return on their investment during the last wafer size Another unanswered question is how many technology transition (200mm to 300mm). nodes will be left by the time 450mm wafers The move to 450mm took on are in production. Intel is starting “If 450mm is really some new urgency at this year’s 22nm in production at the end of Semicon West. Applied Materials this year or early 2012. That means going to end up being announced that it would spend that they’ll be at 7nm right after a single node product, $100 million on developing the first 450mm production fab it ain’t worth it.” 450mm tools (which some say is is slated to be in operation. “We just the cost of doing feasibility studies), hear people talking, ‘We can do 32nm, companies such as EVG and KLA-Tencor we can do 22nm with some of these tools.’ So introduced new 450mm products, and several panel sessions what? When 450mm comes into production, we’re going to were devoted to the topic. be at 14nm or 10nm or below technologies. That means we Many questions remain unanswered. Although most need EUV, immersion for mix-and-match, and probably dry people seem to agree that it’s no longer a question of “if” litho all to be economically viable,” Johnson said. “The next but only “when,” there’s still a long way to go. question we have is how many nodes do we have? How long is Speaking on one of the panels was Gartner’s Bob Johnson, conventional silicon going to keep going after we pass 10nm research vice president, semiconductor manufacturing, who level, and I don’t think anybody knows the answer to that.” noted that the move is purely a cost play, with a target goal Johnson provided an interesting look at ROI considof a 30% reduction in production costs. The problem, said erations, comparing the market and thinking during the Johnson, is that there is a fundamental conflict of interest transition to 300mm in 1997, to the way it is today. “In 1997, between semiconductor and equipment manufacturers. we were convinced, looking in our rearview mirror, that “The way it looks right now is we’ve got the opportunity to the industry growth that was going on at 17% per year was spend billions of dollars on R&D that could go for other going to continue forever. We didn’t realize that we already projects, and end up cutting the market (for equipment) passed the inflection point two years earlier, and we weren’t by about 30% going forward. This is not a heck of a lot of going to realize that for another for our five years. Now we incentive to put a lot of the R&D money out there.” know that the long term growth trend in the industry is Johnson also questioned the real cost savings that have mid single digits, somewhere around 6%/year. If you look at been gained by previous wafer size transitions. “If you look the ability of the industry to generate funding for fabs and at the 30 year period from 1980 to 2010, we had 14 major everything else, it’s much less than it was back in 300mm technology node changes, each one generating, over roughly days.” We could reasonably look at about ten nodes over a two-year period, about a 50% reduction in cost. That’s the product life of 300 mm tools. Now if we look forward, 30% per year,” he said. During that time, there were three maybe 3? Maybe one? I submit if 450mm is really going to major wafer size transitions. “Each wafer transition was end up being a single node product, it ain’t worth it.” Truer ■ about the equivalent of one year’s worth of scaling. Wafer words have never been spoken. size changes really didn’t have a lot with reduction of costs. Pete Singer What happened instead was shrinks, scaling, cleverness Editor-in-Chief in making smaller cell sizes and a lot of the other things 4 Solid State Technology

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𰁌𰁁𰁓𰁅𰁒𰀠𰁍𰁁𰁒𰁋𰁉𰁎𰁇𰀠𰁓𰁙𰁓𰁔𰁅𰁍𰁓𰀠 𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰁆𰁏𰁒𰀠𰁔𰁈𰁅𰀠𰁓𰁅𰁍𰁉𰁃𰁏𰁎𰁄𰁕𰁃𰁔𰁏𰁒𰀠𰁉𰁎𰁄𰁕𰁓𰁔𰁒𰁙

𰁑𰁕𰁁𰁌𰁉𰁔𰁙 𰁓𰁐𰁅𰁅𰁄 𰁒𰁅𰁌𰁉𰁁𰁂𰁉𰁌𰁉𰁔𰁙

𰁉𰁃𰀠𰁍𰁡𰁲𰁫𰁩𰁮𰁧𰀺𰀠𰀠𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰁐𰁯𰁷𰁥𰁲𰁌𰁩𰁮𰁥𰀠𰁉𰁃𰀠𰁬𰁡𰁳𰁥𰁲𰁳𰀠𰁰𰁥𰁲𰁭𰁡𰁮𰁥𰁮𰁴𰁬𰁹𰀠𰁭𰁡𰁲𰁫𰀠𰁨𰁵𰁭𰁡𰁮𰀠𰁲𰁥𰁡𰁤𰁡𰁢𰁬𰁥𰀠𰁴𰁥𰁸𰁴𰀬𰀠𰀲𰁄𰀠𰁣𰁯𰁤𰁥𰁳𰀠𰁡𰁮𰁤𰀠𰁇𰁲𰁡𰁰𰁨𰁩𰁣𰁳𰀮 𰁗𰁡𰁦𰁥𰁲𰀠𰁍𰁡𰁲𰁫𰁩𰁮𰁧𰀺𰀠𰀠𰁏𰁵𰁲𰀠𰁗𰁡𰁦𰁥𰁲𰁬𰁡𰁳𰁥𰂮𰀠𰁳𰁹𰁳𰁴𰁥𰁭𰁳𰀠𰁭𰁡𰁲𰁫𰀠𰁳𰁩𰁬𰁩𰁣𰁯𰁮𰀬𰀠𰁣𰁥𰁲𰁡𰁭𰁩𰁣𰀬𰀠𰁡𰁮𰁤𰀠𰁯𰁴𰁨𰁥𰁲𰀠𰁷𰁡𰁦𰁥𰁲𰀠𰁭𰁡𰁴𰁥𰁲𰁩𰁡𰁬𰀠𰁵𰁰𰀠𰁴𰁯𰀠𰀲𰀰𰀰𰁭𰁭𰀮 𰁗𰁡𰁦𰁥𰁲𰁬𰁡𰁳𰁥𰀠𰁌𰁅𰁄𰀺𰀠𰀠𰁆𰁯𰁲𰀠𰁴𰁲𰁡𰁮𰁳𰁰𰁡𰁲𰁥𰁮𰁴𰀬𰀠𰁳𰁥𰁭𰁩𰀭𰁴𰁲𰁡𰁮𰁳𰁰𰁡𰁲𰁥𰁮𰁴𰀠𰁡𰁮𰁤𰀠𰁯𰁰𰁡𰁱𰁵𰁥𰀠𰁉𰁉𰁉𰀭𰁉𰁖𰀠𰁷𰁡𰁦𰁥𰁲𰀠𰁉𰁄𰀠𰁭𰁡𰁲𰁫𰁩𰁮𰁧𰀮 𰁑𰁵𰁡𰁬𰁩𰁴𰁹𲀔𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰀳𰀰𰀫𰀠𰁹𰁥𰁡𰁲𰁳𰀠𰁯𰁦𰀠𰁥𰁸𰁰𰁥𰁲𰁩𰁥𰁮𰁣𰁥𰀠𰁰𰁲𰁯𰁶𰁩𰁤𰁩𰁮𰁧𰀠𰁳𰁰𰁥𰁣𰁩𰁡𰁬𰁩𰁺𰁥𰁤𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁡𰁮𰁤𰀠𰁣𰁯𰁭𰁰𰁬𰁥𰁴𰁥𰀠𰁭𰁡𰁲𰁫𰁩𰁮𰁧𰀠𰁳𰁯𰁬𰁵𰁴𰁩𰁯𰁮𰁳𰀮 𰁓𰁰𰁥𰁥𰁤𲀔𰁐𰁯𰁷𰁥𰁲𰁌𰁩𰁮𰁥𰀠𰁅𰀠𰀴𰀰𰀠𰁉𰁃𰀻𰀠𰁴𰁨𰁥𰀠𰁦𰁡𰁳𰁴𰁥𰁳𰁴𰀠𰁤𰁯𰁵𰁢𰁬𰁥𰀭𰁨𰁥𰁡𰁤𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁭𰁡𰁲𰁫𰁥𰁲𰀠𰁡𰁶𰁡𰁩𰁬𰁡𰁢𰁬𰁥𰀠𰁷𰁩𰁴𰁨𰀠𰁯𰁶𰁥𰁲𰀠𰀱𰀶𰀰𰀰𰀠𰁃𰁐𰁓𰀮 𰁒𰁥𰁬𰁩𰁡𰁢𰁩𰁬𰁩𰁴𰁹𲀔𰁒𰁏𰁆𰁉𰁎𲀙𰁳𰀠𰁯𰁷𰁮𰀠𰁬𰁡𰁳𰁥𰁲𰀠𰁴𰁥𰁣𰁨𰁮𰁯𰁬𰁯𰁧𰁹𰀮𰀠𰁗𰁯𰁲𰁬𰁤𰁷𰁩𰁤𰁥𰀬𰀠𰁡𰁷𰁡𰁲𰁤𰀭𰁷𰁩𰁮𰁮𰁩𰁮𰁧𰀠𰁣𰁵𰁳𰁴𰁯𰁭𰁥𰁲𰀠𰁳𰁥𰁲𰁶𰁩𰁣𰁥𰀠𰁡𰁮𰁤𰀠𰀲𰀴𰀯𰀷𰀠𰁳𰁵𰁰𰁰𰁯𰁲𰁴𰀮

𰁗 𰁅 𰁔 𰁈 𰁉 𰁎 𰁋𰀠𰁌 𰁁 𰁓 𰁅 𰁒

𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰀠𰁗𰁗𰁗𰀮𰁒𰁏𰁆𰁉𰁎𰀮𰁃𰁏𰁍 _______________

𰁒𰁏𰁆𰁉𰁎𰀭𰁂𰁁𰁁𰁓𰁅𰁌𰀠𰁉𰁎𰁃𰀮𰀠𰀶𰀸𰀠𰁂𰁡𰁲𰁮𰁵𰁭𰀠𰁒𰁤𰀮𰀬𰀠𰁄𰁥𰁶𰁥𰁮𰁳𰀬𰀠𰁍𰁁𰀠𰀰𰀱𰀴𰀳𰀴𰀠𰀠𰀹𰀷𰀸𰀮𰀶𰀳𰀵𰀮𰀹𰀱𰀰𰀰𰀠𰁩𰁮𰁦𰁯𰁀𰁲𰁯𰁦𰁩𰁮𰀭𰁢𰁡𰁡𰁳𰁥𰁬𰀮𰁣𰁯𰁭

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WORLD NEWS ■ BUSINESS TRENDS Americas

Semi growth outlooks less rosy for 2011

Japan

Asia Pacific

Americas Japan

Europe

Asia Pacific Europe

15% Monthly change 80% Yearly change Outlooks for 2011 semiconductor growth aren’t quite as optimistic as they were just a few months ago. IC Insights 10% 60% has halved its projection to 5% (vs. 10%), with only the OSD segment (optoelectronics, sensors, and discretes) remaining 5% 40% flat. IDC also has lowered its 2011 forecast, to the floor of its previously projected 6%-8% range, and tweaked down 0% 20% its outlook for global MPUs (9.3% vs. 10.3%) after seeing -5% 0% shipments and revenues decline -4% in 2Q11. Those overall forecast adjustments are more in line with the 5.4% the -10% -20% WSTS and SIA have been predicting, even with a -2% decline J J A S O N D J F M A M J J J A S O N D J F M A M J in 2Q11 chip sales. (Back in June iSuppli slightly raised its 2010 2011 2010 2011 outlook to 7%.) WaferNews sources: SIA, WSTS *Based on a three-month moving average What’s putting a damper on 2011 outlooks? Macroeconomic headwinds, ranging from the Japanese March 11 Worldwide semiconductor sales by region, based on a 3-mo. moving average. (Source: SIA, WSTS) disaster to Middle East unrest to continued economic uncertainty in the US and Europe. GDP growth has been slowing for about a year, notes IC Insights, though 2H11 should be “moderately rating, nor similar action looming against some EU nations. IC better” thanks to Japan’s rebound and rebuild from the March 11 Insights’ end-of-July update predicted US and EU debt crises would disaster, lower gas prices, and tax breaks. “lessen” in 2H11 to help its outlook—but that was before the S&P’s Note that these forecasts, as of press time, do not include any move, which spawned a subsequent week of multi-hundred-point long-term impact from the S&P’s Aug.5 downgrade of US credit volatility in major financial markets worldwide. ■

WORLDWIDE HIGHLIGHTS Photoresist revenues will grow at about 5% for the next several years, says Techcet Group, which says consolidation is long overdue among resist suppliers, and EUV may be the last straw. Intermolecular has inked a deal with GlobalFoundries to use its combinatorial technology on R&D for semiconductor manufacturing lines covering 45nm down to 14nm. Avantor and SACHEM have developed a new selective etch chemistry that doubles as wafer cleaner. Ajit Manocha has been appointed interim CEO at GlobalFoundries; both CEO Doug Grose and COO Chia Song Hwee are stepping aside. Surging gold prices—especially given

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recent US and EU economic turmoil— are accelerating an increase in Cu wire shipments, says Techcet. A trio of companies dominates the $3.3B set-top box IC market, which is expected to flatten out over the next few years, says ABI Research. Silicon semiconductor wafer growth was nearly flat year-over-year in 2Q11 says SEMI, noting the “impressive” unbroken supply chain in the aftermath of the Japan earthquake,. Cypress Semiconductor and UMC say they have produced working silicon on 65nm SONOS flash.

AMERICAS A temporary stand-in process used in solvent cleaning being started up for

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the first time was behind a June fire at Intel’s Fab 22 facilities in Chandler, AZ. Brazil has given CEITEC the green light for the nation’s first chip fab. KLA-Tencor has joined SEMATECH’s lithography defect reduction program, housed at the U. of Albany’s College of Nanoscale Science and Engineering (CNSE), to collaborate on several areas of EUV lithography. Veeco has dropped its CIGS tool business, saying it hasn’t generated returns soon enough. Georgia Tech researchers have used zinc oxide nanowires to create a new type of piezoelectric resistive switching device, which can be used to build self-powered nanoelectromechanical systems.

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Two execs with Varian ties have new gigs: former CEO Garry Rogerson is the new CEO at Advanced Energy, while current VSEA exec Stan Yarbro is now a FSII board member.

ASIAFOCUS SMIC has appointed Tzu-Tin Chiu as its new CEO, replacing David Wang who resigned in July. Chiu most recently was president/CEO of Hua Hong NEC.

Tokyo Electron Device and Powercast have jointly developed a cell phone chip that converts RF energy to electricity.

SPTS management has completed a buyout (enterprise value ~$200M) with backing from EU private equity firm Bridgepoint.

EUROFOCUS

EV Group is adding floorspace, equipment, and recruiting 100 workers in an expansion of its Austrian headquarters.

EV Group has released a wafer bonding system for 450mm SOI wafers; Soitec will qualify the first one this fall.

Samsung has widened its lead on in the NAND flash market to 40% market share, vs. 28% for Toshiba and 13% for Hynix, says DRAMeXchange. Samsung and Hynix also are reportedly speeding development of 2Xnm DRAM modules to ramp production by year’s end. Undeterred by two unsuccessful bids over the past decade to kick-start domestic chip manufacturing, the Indian government has launched yet another bid to attract investors for domestic chip fabs. Hitachi has rolled out enterprise-class MLC SSDs built with Intel’s 25nm NAND flash technology. A Samsung study finds no link between its chip plants and cancer, though labor advocates are challenging the study’s transparency and independence. Gigaphoton says its EUV (LPP source) debris mitigation technology now achieves 93% Sn removal. Nomura has sold all its shares in semiconductor packaging substrate maker Eastern Co. to the firm’s parent company. Renesas has divested its audio processing chip business to Murata Manufacturing. Researchers in China report a “breakthrough” in densely doping indium to give coral-like SnO2 nanostructures, for use in gas sensors. Dongbu HiTek has ramped volumes of Chinese firm BYD’s CMOS image sensors.

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TECHNOLOGY NEWS Is 3D packaging where it needs to be?

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ore than a hundred attendees gathered at a Suss Eric Strid of Cascade Microtech revealed that the company MicroTec workshop at this year’s SEMICON West (“3D is producing lithographically printed probe cards by MEMS Integration: Are we there yet?”) to hear technical experts techniques capable of 6μm sq. x 20μm high probe tips on 40μm from around the globe to present updates on the status pitch for testing dense 3D IC pads. “Such technology allows of 3D IC packaging. scalability to lower cost and finer pitches,” he said, adding that Eric Beyne of IMEC addressed the technical issues of carrier these probe cards “are being sold in research quantities.” Standard systems for 3D through-silicon via (TSV) thinning and backside pad locations are required for vendor interchangeability, and processing, pointing out that right now silicon carriers are favored “standard materials specs for pads are needed in terms of materials, over glass because: (1) the glass must be CTE matched to silicon thickness and flatness,” he reported. over a large temperature range, (2) the high cost of ground to tight TTV speciDevice Adhesive on device fication, and (3) a negative effect on 1 Device plasma-based post-grinding backside Polymer adhesive 3 Carrier processes due to its low thermal conducCarrier ZoneBONDTM carrier 2 tivity. After alignment and temporary 4 Release zone bonding, Beyne recommends the use Thin device of use of in-line metrology to insure Stiction zone bonding integrity before grinding occurs. Basic Process Flow: Rama Puligadda, division manager 5 and 6 1. Coat polymer adhesive on device for advanced materials R&D for Brewer 2. Create carrier: Release zone and stiction zone Science, indicated that their Zonebond 3. Bond face to face room-temperature debonding process is 4. User processes: Thin, pattern, etc. 7 meeting all customer requirements and 5. Remove stiction zone adhesive is moving toward full commercial intro- 6. Mount device side on film frame duction. The Zonebond process basically 8 7. Separate carrier from adhesive uses a 2.5mm ring of adhesive to hold the 8. Clean adhesive from device wafer in place for grinding and backside processing. This allows for easier subsequent debonding. The thin wafers are released from the carrier at Stefan Lutter, bonder project manager for Suss MicroTec, room temperature after mounting on a film frame. discussed the company’s open platform approach, which is capable Stephen Pateras, product marketing director at Mentor of using any of the following bond/debond technologies. They see Graphics, pointed out that TSVs can be used to create test access temporary bonding trending toward the newer room-temperature paths so that all BIST resources can be accessed on any device. (RT) release processes. Pateras also concludes that all EDA players need to support Suss’ new product introduction is a HVM debonder/cleaner line common test access infrastructures since this will be required for the new RT release processes. — Dr. Phil Garrou, contributing to stack die from difference sources. editor

AMAT’s DRAM fab tools for denser transistors

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pplied Materials debuted three systems at SEMICON West for next-generation DRAM chip manufacturing: the Centura DPN HDTM system to improve the gate insulator scaling, the Endura HAR Cobalt PVD system for high-aspect-ratio (HAR) contact structures, and the Endura Versa XLR W PVD system for reduced gate stack resistance. (Also at SEMICON West, Applied decloaked a new Vantage Vulcan RTP tool for 2Xnm with backside wafer heating, and a new deposition and UV curing toolset for 22nm interconnects.)

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Key transistor technologies, borrowed from logic devices, are helping DRAM chips achieve better performance and speed, overcoming a “memory wall:” the speed of the control circuitry that transfers data between the memory cell array and external data bus. These transistors are denser and more advanced, requiring new toolsets, Applied asserts. The Applied Centura DPN HD system incorporates nitrogen atoms into the gate insulator to improve its electrical characteristics. The high-dose gate stack system for oxynitride gate scaling is said

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products, emphasized the impetus behind the HAR Cobalt PVD chamber (Fig. 2) and the need to transition from TiSi2 to cobalt. (Listen to the interview at electroiq.com/podcasts). Cobalt replaces titanium for transistor contact metallization on the Endura Cobalt system, depositing uniform films in high-aspect-ratio contact structures with 50% lower contact resistance than titanium. DRAM devices fabbed with the lower-resisitivity element can have faster switching speed and lower power consumption, he explained. Meanwhile, the Applied Endura Versa XLR W PVD system is a tungsten-based tool that is said to offer a 20% reduction in gate stack resistivity (Fig. 3). The optimized reactor design improves consumable component lifetimes as well. Together these two products (PVD Co) replace the much cheaper TiCl4 process, which has been used for many years but has shortcomings. An interesting sidenote to the introduction of these products is that using PVD instead of CVD runs counter to industry expectations. — D.V.

Provides control for on/off state

Polysilicon gate

Insulates gate electrode from channel

Oxynitride Silicon

Drain

Source Channel

Nitrogen content

Carriers

Figure 1. The gate dielectric/oxide. Decoupled plasma nitridation enables high surface nitrogen content. (Source: Applied DRAM HAR cobalt PVD High aspect ratio PVD for 2x DRAM

Aspect ratio ALPS step coverage Co → 65nm Step coverage requirement 50nm

35nm

120nm

1:1

≥7:1

≤3:1 Aspect ratio

AN EXCITING NEW CONCEPT IN PLASMA TECHNOLOGY

PLASMA-PREEN“

Figure 2. Logic-derived expertise for fast DRAM implementation.(Source: AMAT)

to increase DRAM periphery speeds, which enhance DRAM output. The HD technique builds on Applied’s decoupled plasma nitridation (DPN) technology for advanced logic and memory fab. Decoupled plasma nitridation enables high surface nitrogen content (Fig. 1). Higher nitrogen content leads to higher capacitance, thus enabling equivalent oxide thickness (EOT) scaling, explained David Chu, global products management at Applied Materials. The ot her members of the Normalized resistivity product t rio addressing 2Xnm Versa PVD DRAM scaling challenges are the Endura HAR Versa XLR PVD Cobalt PVD tool 20% reduction for periphery contacts, and the Endura Versa XLR W PVD tool for memory 1000 1250 0 250 500 750 gate electrodes. Thickness (Å) Kevin Moraes, director of product Figure 3. The Versa XLR W PVD chamber enables lower gate resistance required for 2Xnm. management for (Source: Applied Materials) metal deposition

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Manufactured from a Microwave Oven Hybrid Cleaning-Ceramic Cleaning Wire Bond Pad Cleaning Die Attach Pad Cleaning Epoxy Bleed Removal Flux Residue Removal Photo Resist Removal Surface Preparation for Welding, Soldering and Inking

Plasmatic Systems, Inc. 1327 Aaron Road North Brunswick, NJ 08902 TEL: (732)-297-9107 FAX: (732)-297-3306 Email: [email protected] www.plasmapreen.com

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TECHNOLOGY NEWS

c o ntin ue d fr o m p a g e 10

Samsung-Grandis spotlights MRAM potential—and uphill climb Korean semiconductor giant Samsung Electronics has acquired Grandis, a maker of spin-transfer torque random access memory (STT-RAM), a flavor of magnetic random-access memory (MRAM). The only details disclosed were that it closed in July, covering “the full scope” of Grandis technology, assets, and HR, and will be folded into Samsung’s memory chip R&D operations. MRAM’s promise is for its nonvolatility, power efficiency, and operation at ultrahigh speeds, for applications requiring highdensity memory or lower power consumption (e.g. smart phones). It’s also touted for its scalability, beyond 32nm or whenever current memory technologies finally lose steam. However, current memory technologies have continued to scale well enough to keep such next-gen memory technologies at bay—Intel famously said back in 2003 that NAND flash wouldn’t be able to scale past the 60nm node, and now it’s at 20nm and counting, notes Jim Handy from Objective Analysis, and Toshiba/Sandisk reportedly have a 19nm device dubbed “1X” and another called “1Y” in the works suggesting another node in the hopper. Perhaps this Samsung-Grandis deal is no more than IP positioning, “a preemptive move by Samsung to secure potential IP and technology in the MRAM arena, and not necessary representing a significant

move forward in bringing the technology to mass production,” says Michael Yang, principal analyst for memory and storage at IHS iSuppli. Note that Toshiba and Hynix recently announced their own MRAM partnership, aiming to eventually create a production JV and cross-license patents, joining forces to minimize risk and accelerate MRAM’s pace toward commercialization. Hynix CEO Oh Chul Kwon called MRAM “our next growth platform,” while Toshiba’s Kiyoshi Kobayashi pledged to “strongly promote initiatives” integrating products from MRAM to NAND to HDD. Keep in mind that Samsung already has put its bet down on phasechange memory (which it calls PRAM), and claims to be shipping actual devices. (Others touting improvements in PCM over the past few months: an IBM/industry/academia consortia, Numonyx/Micron, Samsung, and KAIST.) Buying Grandis suggests Samsung is at least covering its IP bases in next-gen memory tech—or maybe it’s even an outright change of strategic direction, Handy speculates. In the end, it all comes back to scalability. As long as memory makers continue to extend existing memory technologies’ limits—and at higher volumes and lower costs—next-gen memory technologies won’t get the hard push they need to prove manufacturing costcompetitiveness and achieve commercialization. — J.M.

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MEASURING CDs

Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates E XECUTIVE OVERVIEW

enhanced ultra-violet reflectometer (eUVR). The multi-AZ and multi-channel capabilities of this new tool promised enhanced critical parameter sensitivity and reduced correlation between parameters. We planned to gather data from process of record (POR), focus-exposure matrix (FEM) and design of experiment (DOE) wafers to characterize the performance of this new SCD tool on metal gate ADI and AEI structures. We also planned to compare metal gate AEI scatterometry measurement results to transmission electron microscopy (TEM) reference measurements. This evaluation process was designed to demonstrate the ability of this new-generation scatterometer to serve as a production process monitor for complex metal gate structures at the 28nm node and beyond.

For reduced gate leakage and enhanced device performance, many IC manufacturers utilize novel metal gate technologies instead of traditional poly silicon gates. The new materials and geometries required to form metal gates mean that new parameters control the optimization of device performance [1]. Traditional gate process control has relied heavily on scatterometry for ensuring that variation in structural dimensions remain in control, as some dimensional deviations can strongly affect device performance. A new-generation scatterometry tool with multiple extensions to traditional scatterometry technology is evaluated as a production process monitor for complex metal gate structures at the 28nm device node and beyond.

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nline control and monitoring of the dimensions of the high-k metal gate (HKMG) structure are critical for device performance [2]. This paper focuses on dimensional measurement and control of a 28nm high-k metal gate for two layers: after-develop inspection (ADI) and after-etch inspection (AEI). For ADI, critical measurement parameters include side wall angle (SWA) and critical PR dimension (CD). The ADI structure is very challenging for traditional HM_HT BARC2 scatterometry measurements because the six different films under the photoresist (Fig. 1a) result in high correlation among measurement HM_recess BARC1 parameters. For the AEI process, nanometer-sized variations in the Poly_TCD high-k and metal gate recess relative to poly Si width (Fig. 1b) affect Poly_HT device performance [3]. This recess represents another challenge Poly_WA HM for traditional scatterometry tools because nanometer-sized variations are difficult to detect. To qualify for production process control Poly MG_recess of these structures, the metrology tool must not only be sensitive MG to variations in all key structural parameters, but also be precise, Si HK_recess HK non-destructive, and capable of production-worthy throughput. Critical dimension scanning electron microscopy (CD-SEM) Figure 1. a) ADI model and stack information; and b) AEI model and parametric description nearly qualifies—except that not just CD but also shape metrology for HKMG. is required. Scatterometry emerges as the only near-term option. We decided to evaluate a new-generation spectroscopic critical Experiment and results dimension (SCD) metrology tool, KLA-Tencor’s SpectraShape High-k metal gate ADI. The first study was designed to determine 8810, to determine if it had the sensitivity and precision required the sensitivity and precision of scatterometry measurement for a for measurement of critical parameters on metal gate structures. 28nm high-k metal gate ADI layer. Two wafers were used in the study. The new tool’s core technologies include a multi-azimuth (“multi- The first was exposed with a focus-exposure matrix (FEM), while AZ”) spectroscopic ellipsometer with broadband light extending the second was exposed with constant, standard (POR) lithography into the deep UV portion of the spectrum [4] and a polarized, conditions. For the same DOE conditions, there were two targets in one field: one for an NMOS structure and a second for a PMOS structure. AcuShape2 advanced modeling software was used to Y. H. Huang, C. H. Chen, K. Shen, H. H. Chen, C. C. Yu, J. H. Liao, United Microelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C. C. H. Lin, break the parameter correlation. The floating parameters used in KLA-Tencor Corporation, One Technology Drive, Milpitas, CA, USA the model (the measurement parameters) include the critical param-

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Measured CDs continued from page 12

SCD NMOS PR MCD Bossung curve E+1

MCD (nm)

NMOS

PMOS

E+2

53.00

E+3 E+4 E+5

48.00

E+6

43.00

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E+7 38.00 33.00

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SCD NMOS PR MCD Bossung curve E+1

MCD (nm)

PR SWA

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PR MCD E+2

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43.00

E+7 38.00 33.00

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F+3

F+4 F+5 Focus

E+8 E+9 E+10 F+7 F+8

F+6

Figure 2. MCD as function of focus and exposure for NMOS target (top) and PMOS target (bottom).

eters photoresist height (PR_HT), middle CD (MCD) and sidewall angle (SWA); plus the heights of BARC1, BARC2, hardmask and poly. The scatterometry measurement requirements included: 1) dynamic precision