Offset Reduction Techniques in High-Speed Analog-To-Digital Converters Analysis Design and Tradeoff

OFFSET REDUCTION TECHNIQUES IN HIGHSPEED ANALOG-TO-DIGITAL CONVERTERS Analysis, Design and Tradeoffs ANALOG CIRCUITS ...

Author: Pedro M. Figueiredo | João C. Vital

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OFFSET REDUCTION TECHNIQUES IN HIGHSPEED ANALOG-TO-DIGITAL CONVERTERS Analysis, Design and Tradeoffs

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University

For other titles published in this series, go to www.springer.com/series/7381

OFFSET REDUCTION TECHNIQUES IN HIGHSPEED ANALOG-TO-DIGITAL CONVERTERS Analysis, Design and Tradeoffs

PEDRO M. FIGUEIREDO MIPSABG Chipidea JOÃO C. VITAL MIPSABG Chipidea

Pedro M. Figueiredo Chipidea Microeletrónica Av. Dr. Mário Soares 33 2740-119 Porto-Salvo Taguspark, Portugal [email protected]

ISBN: 978-1-4020-9715-7

João C. Vital Chipidea Microeletrónica Av. Dr. Mário Soares 33 2740-119 Porto-Salvo Taguspark, Portugal [email protected]

e-ISBN: 978-1-4020-9716-4

Library of Congress Control Number: 2008942088 © Springer Science + Business Media B.V. 2009 No part of the work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by purchaser of the work. Printed on acid-free paper. 987654321 springer.com

To Patrícia and Gonçalo

Contents

Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . xv 1.

HIGH-SPEED ADC ARCHITECTURES . . . . . . . . . . . . . . . . 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 The Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.2.1 1.2.2 1.2.3

Basic Operations and Transfer Function . . . . . . . . . . . . . . . . . . . . . 2 Static Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.1 1.3.2 1.3.3

Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 10 The Interpolation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4 Two-Step Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.1 1.4.2

Two-Step Flash ADC with DAC and Subtractor . . . . . . . . . . . . . . 17 Two-Step Subranging Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5 Folding and Interpolation ADCs . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 1.5.2 1.5.3

Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cascaded Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 33

1.6 Building Blocks of CMOS High-Speed ADCs . . . . . . . . . . . . . . . . 38 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5

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The MOS Differential Pair . . . . Effect of Mismatches . . . . . . . . CMOS Folding Circuit . . . . . . . Latched Comparators . . . . . . . Considerations About the Yield

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AVERAGING TECHNIQUE – DC ANALYSIS AND TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 vii

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2.2 Published Studies on the Averaging Technique. . . . . . . . . . . . . . . 73 2.3 Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.1 2.3.2 2.3.3 2.3.4

Equivalent Resistance of an Infinite Resistive Network Calculation of the Output Voltage . . . . . . . . . . . . . . Calculation of the Gain . . . . . . . . . . . . . . . . . . . . . . Application to MOS Differential Pairs . . . . . . . . . . . .

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2.4 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . . . 86 2.4.1 2.4.2 2.4.3 2.4.4

INL due to Mismatches in the Transistors and Current Sources DNL due to Mismatches in the Transistors and Current Sources Mismatches in the Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . Application to MOS Differential Pairs . . . . . . . . . . . . . . . . . . .

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87 89 90 90

2.5 Averaging in Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.5.1 2.5.2

Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . . . 111

2.6 Considerations About the Yield . . . . . . . . . . . . . . . . . . . . . . . . 116 2.7 Termination of the Averaging Network . . . . . . . . . . . . . . . . . . . 118 2.7.1 2.7.2 2.7.3 2.7.4

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Existing Terminating Strategies . . . . . . . Improved Terminating Strategy . . . . . . . Comparison of the Terminating Solutions Folding Circuits . . . . . . . . . . . . . . . . . .

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120 126 132 134

AVERAGING TECHNIQUE – TRANSIENT ANALYSIS AND AUTOMATED DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.2 Flash ADC Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.3 Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.3.1 3.3.2

Exact Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Approximated Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

3.4 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 3.4.1 3.4.2

Simulation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Time Dependence of the Offset Voltage . . . . . . . . . . . . . . . . . . . . 160

3.5 Design of Averaged Pre-amplifier Stages in Flash ADCs . . . . . . . 169 3.5.1 3.5.2

Interface with HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Properties of Differential Pairs with the Same Saturation Voltage (VSAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 3.5.3 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 3.5.4 Application Example: Pre-amplifier Stage for a 7-bit 200 MS/s Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.5.5 Application Example: Variation of G0 . . . . . . . . . . . . . . . . . . . . . 181 3.5.6 Application Example: Variation of α . . . . . . . . . . . . . . . . . . . . . . 185 3.5.7 Application Example: Variation of N . . . . . . . . . . . . . . . . . . . . . 187 3.5.8 Application Example: Variation of R0/R1 . . . . . . . . . . . . . . . . . . 191 3.5.9 Application Example: Variation of fs . . . . . . . . . . . . . . . . . . . . . . 193 3.5.10 Application Example: Specifying the ISSR0 Product . . . . . . . . . . . 196 3.5.11 Application Example: Interpolation in Averaged Pre-amplifiers . . . 200

Contents 4.

ix

INTEGRATED PROTOTYPES USING AVERAGING . . . 205 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.2 7-bit 120 MS/s I/Q Flash ADC. . . . . . . . . . . . . . . . . . . . . . . . . 206 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8

Specifications . . . . . . . . . . . . . . Bias Current Generation . . . . . . Pre-amplifier Stage . . . . . . . . . . Resistive Ladder . . . . . . . . . . . . Reference Voltage Generator . . . Latched Comparators . . . . . . . . Digital Encoder . . . . . . . . . . . . . Layout and Measurement Results

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206 207 209 215 216 218 220 222

4.3 10-bit 100 MS/s Folding and Interpolation ADC . . . . . . . . . . . . 227 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5

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Specifications and Architecture . . Sample-and-Hold . . . . . . . . . . . . Folding Stages . . . . . . . . . . . . . Latched Comparators . . . . . . . . Layout and Measurement Results

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227 229 234 245 246

OFFSET CANCELLATION METHODS . . . . . . . . . . . . . . 261 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 5.2 Offset Cancellation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 262 5.2.1 5.2.2 5.2.3 5.2.4

Input Offset Storage (IOS) . . . . . . . . . . . Output Offset Storage (OOS) . . . . . . . . . Multi-stage Offset Storage . . . . . . . . . . . Utilization of Auxiliary Differential Pairs

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5.3 New Offset Cancellation Technique . . . . . . . . . . . . . . . . . . . . . . 273 5.3.1 5.3.2

Offset Calibration in the Pre-amplifier and Latched Comparator . . 274 Elimination of Charge Injection Differences . . . . . . . . . . . . . . . . . 281

5.4 6-bit 1 GHz Two-Step Subranging ADC . . . . . . . . . . . . . . . . . . 285 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6

6.

Specifications and Architecture . . . Fine Flash ADCs . . . . . . . . . . . . Coarse Flash ADC . . . . . . . . . . . Redundancy . . . . . . . . . . . . . . . . Selection of the Reference Voltages Layout and Measurement Results .

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CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 6.1 Overview of the Research Work . . . . . . . . . . . . . . . . . . . . . . . . 305

Appendix A. AVERAGING WITH PIECEWISE LINEAR DIFFERENTIAL PAIRS . . . . . . . . . . . . . . . . . . . . . . . . . 313 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 A.2 Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 A.3 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . . 318


x A.3.1 A.3.2 A.3.3 A.3.4

Mismatches Mismatches Mismatches Mismatches

in in in in

the Transistors of the Differential Pair the Tail Current Sources . . . . . . . . . . Resistors R0 . . . . . . . . . . . . . . . . . . . Resistors R1 . . . . . . . . . . . . . . . . . . .

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Appendix B. MISMATCHES IN THE RESISTORS OF THE AVERAGING NETWORK . . . . . . . . . . . . . . . . . . . . . . . . 333 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 B.2 Mismatches in Resistors R0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 B.3 Mismatches in Resistors R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

B.3.1 Common-Mode Mismatch Component (δR1[k]) . . . . . . . . . . . . . . . 336 B.3.2 Differential-Mode Mismatch Component (ΔR1[k]) . . . . . . . . . . . . 339

Appendix C. AVERAGING IN FOLDING STAGES . . . . . . . . . . 341 C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 C.2 Equivalence Between Circular and Infinite Networks . . . . . . . . . 345 C.3 Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 C.3.1 Calculation of the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . 348 C.3.2 Calculation of the Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

C.4 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 C.4.1 INL due to Mismatches in the Transistors and Current Sources . . 355 C.4.2 DNL due to Mismatches in the Transistors and Current Sources . . 357 C.4.3 INL and DNL due to Mismatches in the Resistors . . . . . . . . . . . . 359

REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Preface

The advent of CMOS technologies with lower feature sizes enables a sustained increase in the available memorization and processing capabilities, favoring the signal processing operations performed in digital domain. Quite often the signals to be processed are analog and, in some cases, must become analog after the digital processing. This requires the utilization of components that make the translation between the two domains: the Analog-to-Digital Converter (ADC) receives an analog signal and produces its binary coded representation; the Digital-toAnalog Converter (DAC) performs the opposite operation. Presently there are data converters in virtually all electronic systems: audio, video and imaging, communications, control, radar, etc. The two most fundamental parameters of data converters are the sampling frequency (rate at which the input is examined and the corresponding output is produced), and the resolution (which determines the minimum analog signal amplitude that can be processed). Practical implementations indicate a primary tradeoff between these two parameters: data converters with higher sampling frequency have a smaller resolution. There are several ADC architectures, each suited to a certain resolution/sampling frequency range. This book focus on CMOS high-speed ADCs: the flash, two-step flash and folding and interpolation converters. These architectures (which currently achieve resolutions ranging from 6 to 10 bit, and sampling frequencies extending from 100 MHz to several GHz) and the tradeoffs in their constituting blocks are addressed in detail; furthermore, silicon implementations using all three architectures are presented.

xi

xii


These converters have the common characteristic of possessing subblocks that have no special linearity requirements, but whose offset voltages are of the upmost importance because they determine the overall ADC linearity. Offsets can be reduced by enlarging the components, but this increases the parasitic capacitances, leading to a larger power dissipation or to the reduction of the maximum operating frequency. The offset voltage is, in this way, the fundamental design parameter in high-speed CMOS analog-to-digital converters. The utilization of offset reduction techniques is mandatory to achieve high frequency operation with low power dissipation and layout area. Averaging and offset sampling are the two most widely used and both are thoroughly examined and characterized. The most exhaustive study ever performed about averaging is, to the best knowledge of the authors, presented in this book. Also, previously proposed offset sampling methods are carefully reviewed to understand their limitations. Then two new techniques are proposed that, when combined, yield a nearly offset free comparator. The research work published by the authors in leading IEEE transactions and conferences [1–6] is detailedly presented and extended, resulting in a book that covers both the main high speed ADC architectures as well as the most widely used linearity improvement (offset reduction) techniques. This book is organized as follows. The first chapter starts with an overview of the basic operations realized inside an analog-to-digital converter, as well as the parameters used to characterize it. The main high-speed ADC architectures are then described. The advantages and limitations of each one are reviewed, and the techniques usually employed to improve their performance are presented. This chapter ends with a discussion on the operation and performance limitations of the basic building blocks used on these high-speed ADCs. The second chapter presents the DC characterization of the averaging networks employed in pre-amplifier and folding stages, by deriving general and exact expressions for the output voltages, gain and the standard deviation of the integral non-linearity (INL) and differential non-linearity (DNL) arising from any type of mismatch. These expressions are then particularized to the case of MOS differential pairs, and a good agreement with SPICE simulation results is found. The last section of this chapter examines existing solutions to terminate the

Preface

xiii

averaging network, and proposes a new one that outperforms all the others. The s-domain expression for the output voltage of an averaged preamplifier stage is derived in the beginning of the third chapter. This allows to evaluate the time response using a numerical Laplace Transform Inversion algorithm. An approximation that provides further insight into the behavior of the circuit, while avoiding the utilization of that numerical algorithm, is then proposed. A curious phenomenon which occurs in averaging networks is also identified and studied in this chapter: the offset voltage is a time dependent parameter. This happens because the contributions of the differential pairs take time to propagate through the network. Still in the third chapter, an automatic design procedure is presented, which is implemented as a computer program and has an interface with a SPICE simulator. It yields the final dimensions of the components that achieve a set of design specifications, in just a few seconds. This is the final goal and main motivation for the detailed theoretical characterization of averaging networks presented in this book. Another application is the high-level modeling of ADCs, where the impact of sub-blocks’ non-idealities in the global performance of the converter (or even on the system where it will be used) is assessed. The fourth chapter presents the design and test results of two integrated prototypes using averaging: a 7-bit 120 MHz flash IQADC and a 10-bit 100 MHz folding and interpolation converter. It is shown how to use the automatic design procedure mentioned above to guarantee a set of specifications across process and temperature corners; furthermore, the application of this procedure to the design of cascaded stages is also illustrated. A technique that compensates the IR drops in the ground line of the pre-amplifiers and folding circuits, and guarantees an equal tail current value for all the differential pairs is also disclosed. This is important because, when averaging is utilized, differences in the tail currents cause systematic deviations in the code transition levels of the ADC. The fifth chapter addresses offset sampling techniques. Their operation is examined thoroughly, to understand the limitations to the amount of offset reduction that can be achieved. A new offset calibration technique and a simple method to eliminate the effect of charge injection mismatches are disclosed. The combination of these two techniques overcomes the limitations found in existing offset sampling

xiv


methods, yielding practically no residual offset. This chapter ends with the circuit description and tests results of a 6-bit 1 GHz two-step subranging converter employing those techniques. Furthermore, a new reference voltage selection scheme is used in this ADC, which guarantees the fast selection of the important reference voltages, and halves the number of switches connected to the resistive ladder. Finally, chapter 6 provides an overview of the research work presented in each chapter, and draws the conclusions. This book has a number of appendixes which present accessory but relevant information. The general expressions derived in chapter 2 are evaluated in Appendix A, modeling the transfer function of the differential pair with a piecewise linear function – all previously published studies on the averaging technique made this simplification (among others), which yields the simplest but most inaccurate results. The approximations and limitations of those previous research works are, then, analyzed. Appendix B addresses the effect of resistor mismatches in averaging networks. As mentioned above, the DC characterization of averaged preamplifier and folding stages is made in chapter 2. However, since the analysis of folding stages is somewhat complex that chapter only presents the main results. The detailed derivation of the expressions that characterize the averaging network of folding stages is presented at Appendix C. PEDRO M. FIGUEIREDO JOÃO C. VITAL

List of Symbols and Abbreviations

⎣a ⎦

α β

γ μ τ τ[k] σ(VOS) σ(VOS)Δψ σ(VOS[t])Δψ Δψ[k] ΔP Δhi Δq Δq[k] ΔVCAL ΔVF

Integer immediately below the real number a. Amount of settling, defined by (3.1). Constant that determines the drain current of a MOS transistor (equal to μCoxW/L). Ratio between VR and VSAT. Carrier mobility. Time constant. Time constant associated to the propagation of the contribution of differential pair k. Total standard deviation of the offset voltage. (DC) Standard deviation of the offset voltage, due to a mismatch in parameter ψ. Standard deviation of the offset voltage, due to a mismatch in parameter ψ, at time instant t. Mismatch between the parameter ψ of two similar circuit elements of the differential pair k. Difference of the electrical parameter P in two identical devices (resistance, capacitance, threshold voltage, etc.). Difference of the process parameter hi in two identical devices (mobility, oxide thickness, concentration of implanted ions, etc.). Difference of charge injection. Difference of charge injection in stage k. Calibration voltage range. Voltage difference between consecutive zero crossings of the same folding circuit.

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Offset Reduction Techniques in High-Speed ADCs ΔVB

L−1 {G [s ]} ADC An .fi AP AC AR AVt Aβ bi B B[s] BJT C C[s] CMOS CDB CGS CGD CL Cox CP CP[k] CS CS[k] CMFB DAC DNL DNL[k] Dx eq ENOB fΔψ[k,vI] fi fs

Voltage difference between the zero crossings of consecutive folding circuits. Inverse Laplace Transform of G[s]. Analog-to-Digital Converter. Amplitude of the spectral component at nfi (n ∈ ` ). Matching constant associated to electrical parameter P. Matching parameter for capacitors. Matching parameter for resistors. Matching parameter for the Vt of MOS transistors. Matching parameter for the β of MOS transistors. ith output bit of the ADC. Constant dependent on the absolute values of R0 and R1, given by (2.11). Extension of B to s-domain, given by (3.2). Bipolar Junction Transistor. Constant dependent of R0/R1, given by (2.12). Extension of C to s-domain, given by (3.3). Complementary Metal Oxide Semiconductor. Drain-to-Bulk capacitance of the MOS transistor. Gate-to-Source capacitance of the MOS transistor. Gate-to-Drain capacitance of the MOS transistor. Load capacitance. MOS transistor gate oxide capacitance per unit of area. Parasitic capacitance. Parasitic capacitance in pre-amplifier stage k. Offset storage capacitor. Offset storage capacitor in pre-amplifier stage k. Common-mode feedback network. Digital-to-Analog Converter. Differential Non-Linearity. Differential Non-Linearity of code k. Distance between two matched devices. Quantization error of the ADC. Effective Number of Bits. Function that determines the deviation in the output current of differential pair k, caused by the Δψ mismatch. Input frequency. Sampling frequency.


FB FB[k] FF FF[k] FFT FTOT gm0 gm[k,vI] g’m[k,vI] G0 G0[k] G[t] GND hi HDTV iD iD[k,vI]

iDIFF iDIFF[k,vI] iDIFF0 iDIFF0[k,vI] Idiff[k,vI,s] IF IF[k] INL INL[k] IOS ISS

xvii

Number of folding circuits (used when there is only one stage). Number of folding circuits in the kth stage. Folding Factor (used when there is only one stage). Folding Factor of the circuits in the kth stage. Fast Fourier Transform. Overall Folding Factor in a cascaded folding architecture. Transconductance of a differential pair, for zero differential input voltage. Transconductance of the kth differential pair, when the input voltage is vI. Normalized transconductance, gm[k,vI]/gm[0,0]. DC Gain. DC Gain at stage k. Dynamic Gain, at time instant t. Ground. Process parameter (mobility, oxide thickness, concentration of implanted ions, etc.). High Definition Television. Drain current of the MOS transistor. Drain current of a transistor in the kth differential pair, when the input voltage is vI. Differential output current of a differential pair. Differential output current of the kth differential pair, when the input voltage is vI. Differential output current of a differential pair in the absence of mismatches. Differential output current of the kth differential pair, when the input voltage is vI, in the absence of mismatches. Laplace Transform of the differential output current of the kth differential pair, when the input voltage is vI. Interpolation factor (used when there is only one stage). Interpolation factor of the kth stage. Integral Non-Linearity. Integral Non-Linearity of code k. Input Offset Storage. Tail current of a differential pair.

xviii

ITERM


Value of the current source used in the proposed termination circuit. L Channel length of the MOS transistor. LC Length of a capacitor. Lmin Minimum length permitted by the technology. LR Length of a resistor. M[a,b] Remainder of the division of a by b. MOS Metal Oxide Semiconductor. N Linear network. N Number of non-saturated differential pairs in each side of the one being considered. Nb Resolution of the ADC. NbMSB Resolution of the coarse ADC in a two-step architecture. NbLSB Resolution of the fine ADC in a two-step architecture. NCOMP Total number of comparators connected to the folding circuits. NDP[k] Number of differential pairs in the kth stage. NH Number harmonics considered in the calculation of the THD. NFstg Number of stages in a cascaded folding architecture. NPstg Number of offset compensated cascaded pre-amplifier stages. NTOT Total number of zero crossings in a folding and interpolation ADC. NMOS N-Channel MOS transistor. OOS Output Offset Storage. P Electrical parameter of a component (resistance, capacitance, threshold voltage, etc.). phx Phase x. PMOS P-Channel MOS transistor. P(INL < ξ) Probability of having the |INL| of a certain code below ξ LSB. P(DNL < ξ) Probability of having the |DNL| of a certain code below ξ LSB. Q[a,b] Integer division of a by b. rDS MOS transistor drain–source incremental resistance. rONx ON resistance of switch Sx. R0 Load resistor of a differential pair. R1 Averaging resistor.


Req RTERM R, s sgn(x) SP Sx SINAD SNR SPICE S/H t td[k]

tr THD T/H TS UWB VBG vDS vGS vCAL vI vIP/vIN vOP/vON vO[k,vI]|j vO[k,vI] vO[k,vI,t] Vo[k,vI,s] VCALopt

xix

Equivalent resistance “seen” to the left and to the right of each output node in the averaging network – given by (2.4). Resistance used in the proposed termination circuit. Resistance resistance per square of polysilicon. Complex frequency. Sign function. Constant that indicates the matching of parameter P, as a function of the distance between the two devices. Switch x. Signal-to-Noise-and-Distortion Ratio. Signal-to-Noise Ratio. Simulation Program with Integrated Circuit Emphasis. Sample-and-Hold. Time. Time delay associated to the propagation of the contribution of differential pair k. Rise/fall time of the clock signal. Total Harmonic Distortion. Track-and-Hold. Sampling period. Ultra WideBand. Bandgap reference voltage. Drain-to-Source voltage of a MOS transistor. Gate-to-Source voltage of a MOS transistor. Calibration voltage. Input voltage. Positive/negative input voltage. Positive/negative output voltage. Voltage at node k due to the current source connected to node j, when the input voltage is vI. Output voltage of the kth differential pair, when the input voltage is vI. Output voltage of the kth differential pair, when the input voltage is vI, for time instant t. Laplace Transform of the output voltage of the kth differential pair, when the input voltage is vI. Calibration voltage at which perfect offset cancellation occurs.

xx


VCALrange VCM VDD VFS VLSB VOS VOS[k]Δψ

Calibration Range. Common-mode voltage. Supply voltage. Input range of the ADC. Quantization step of the ADC. Offset voltage. DC offset voltage in the zero crossing of the kth differential pair, due to mismatches in the parameter ψ. VOS[k,t]Δψ Offset voltage in the zero crossing of the kth differential pair, at time instant t, due to mismatches in the parameter ψ. VOVD Overdrive voltage of a MOS transistor, VGS−Vt. VR Difference of consecutive reference voltages in a resistive ladder. VREFP Upper extremity reference voltage. VREFN Lower extremity reference voltage. VRP Positive reference voltage applied to a pre-amplifier. VRN Negative reference voltage applied to a pre-amplifier. VSAT Differential input voltage at which a differential pair becomes completely unbalanced. Vt Threshold voltage of a MOS transistor. VT[k] Input voltage where the transition from code k – 1 to code k occurs. W Channel width of a MOS transistor. WC Width of a capacitor. WR Width of a resistor. Y(INL < ξ) Probability of having the overall INL of the ADC below ξ LSB. Y(DNL < ξ) Probability of having the overall DNL of the ADC below ξ LSB.

Chapter 1 High-Speed ADC Architectures 1.1

INTRODUCTION

The rapid technological evolution leads to CMOS technologies with lower feature sizes, allowing the integration of more complex systems in an single integrated circuit. The digital circuits, which are designed at a high level of abstraction, benefit directly from those advanced technologies, leading to a sustained increase in the available memorization and processing capabilities. In this way, there is a tendency to make all the signal processing in the digital domain. Quite often the signals to be processed are analog and, in some cases, must become analog after the digital processing. This requires the utilization of components that make the translation between the two domains: the Analog-to-Digital Converter (ADC) receives an analog signal and produces its binary coded representation; the Digital-to-Analog Converter (DAC) performs the opposite operation. The complete integration of a system – which may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. – in the same CMOS die is of the upmost importance, to reduce costs. This book focus on CMOS high-speed ADC architectures – flash, two-step flash and folding and interpolation – which have the common characteristic of possessing sub-blocks with no special linearity requirements, but whose offset voltages are of the upmost importance because they determine the overall ADC linearity. Those architectures are described in detail in the present chapter. The techniques used to improve the linearity of these converters – averaging and offset sampling – are addressed in subsequent chapters. This chapter starts with an introduction to the ADC as an electrical component: the basic operations it performs are presented, and its main characterization metrics are discussed. The various high-speed analog-to-digital conversion architectures are then described: the flash ADC in section 1.3, the two-step ADC in section 1.4 and, finally, the folding and interpolation ADC in section 1.5. For each architecture, the advantages and the main limitations as well as the techniques usually employed to improve their performance, are reviewed. P.M. Figueiredo and J.C. Vital, Offset Reduction Techniques in High-Speed Analog-to-Digital Converters, © Springer Science+Business Media B.V. 2009

1


2

This chapter ends with a discussion on the operation and performance limitations of the building blocks used in the high-speed ADCs (section 1.6).

1.2

THE ANALOG-TO-DIGITAL CONVERTER

1.2.1

Basic Operations and Transfer Function

The basic operations realized inside an ADC are represented in Fig. 1.1. The sampling operation transforms the continuous-time input into a discrete-time signal. This operation is controlled by the clock signal: in all high-speed ADC architectures the input is sampled once in every clock period. In this way the frequency of the clock corresponds to the sampling frequency, fs. The input signal can be a voltage or a current but, hereafter, it will be considered that it is a voltage which is, by far, the most common situation.

vIS vI

TS = 1/fs

Quantization Step (VLSB)

vIQ

t

t

t

vI

Sampling

Quantization

Encoding

011011 101010 010101 111000 010000 000000

Clock Signal (fs)

Figure 1.1. The basic operations performed in an ADC.

The sampling operation performs a time discretization of the input voltage, but the amplitude of the resultant sampled signal can still take any value – it is a continuous-amplitude signal. According to the Nyquist theorem, as long as the bandwidth of the input signal remains below fs/2 no information is lost, and the original signal can be reconstructed exactly. The next operation performed inside the ADC is the quantization of the sampled signal. The quantizer divides the input range of the ADC,

Chapter 1: High-Speed ADC Architectures

3

VFS, in several small regions called quantization steps, which have the width VLSB. The output voltage of the sampling circuit is approximated by one of the quantization levels, as shown in Fig. 1.1. An irreversible error is introduced – quantization error – which prevents the exact reconstruction of the input signal. The maximum quantization error is V eq max = ± LSB . 2 The last operation performed in a ADC is the assignment of a binary number, the output code, to each quantization level – encoding. The output of the ADC is, therefore, a binary coded representation of the quantized signal. The transfer function of an ADC is shown in Fig. 1.2. Output Code 11…111 11…110 11…101

00…010 00…001 00…000 0

VLSB

VFS

Input Voltage

Quantization Error (eq) +VLSB/2

Input Voltage Figure 1.2. Transfer function and quantization error of an ideal ADC. −V LSB/2

There are 2Nb quantization steps, where Nb is the resolution of the ADC which corresponds to the number of bits in the output code. Since V , (1.1) VLSB = FS 2Nb


4

increasing the resolution decreases VLSB and, therefore, the quantization errors. As will be made clear throughout this book, there is a fundamental tradeoff between the resolution and sampling frequency: faster ADCs tend to have a smaller resolution. The effect of the quantization errors can be viewed as an additive noise (called quantization noise), where V (1.2) eq (t ) ≤ LSB . 2 Considering that eq(t) is a random variable independent of the input VLSB , it can be demon2 strated [10, 11] that the maximum achievable signal-to-noise ratio (SNR) of an ADC is SNR[dB] = 6.02Nb+1.76. (1.3) In this way, even the ideal ADC has a limited SNR due to the quantization process. There are ADCs with nonuniform quantization steps [8, 9], or which use oversampling and noise-shaping to improve the performance [10]. None of those ADCs are considered in this book. High-speed conversion can also be achieved by using several ADCs working in time interleaving [12–14]. This matter is also not address in this book, which focus on the speed maximization of individual ADCs. Note, though, that when employing time interleaving it is fundamental to start by maximizing the speed of the unit ADC. signal1 and uniformly distributed between ±

1.2.2

Static Characterization of ADCs

The transfer function of real ADCs deviates from the ideal one, depicted in Fig. 1.2. These deviations can be divided into a linear and a nonlinear part. The linear part is caused by offset and gain errors, both represented in Fig. 1.3, which do not originate distortion and, therefore, are often unimportant. These errors are calculated by comparing the straight line that best fits, in the mean-square sense, the measured transfer function with the one of the ideal converter.

1

This approximation greatly simplifies the SNR calculation. Reference [10] shows that (1.3) has an error below 0.5 dB for Nb ≥ 2 bit. For example, the error of (1.3) for an 8-bit converter is only 0.1 dB.


5

VOS Ideal Transfer Function

Gain Error

Ideal Transfer Function

Real Transfer Function

Real Transfer Function

(a)

(b)

Figure 1.3. ADC transfer function with (a) offset error; (b) gain error.

The characterization of the nonlinear errors is done using two parameters:

Integral Non-Linearity (INL) – it is the difference between the ideal and measured transition level of each output code, normalized to the quantization step, VLSB, INL [k ] =

VT [k ] −VTideal [k ] VT [k ] −VTideal [1] = − (k − 1) VLSB VLSB with k = 1...2Nb − 1

(1.4)

Differential Non-Linearity (DNL) – it is the normalized deviation of the difference between two consecutive code transition levels, with respect to the ideal value, VLSB, DNL [k ] =

VT [k + 1] −VT [k ] −VLSB V [k + 1] −VT [k ] = T −1 VLSB VLSB

with k = 1...2Nb − 2.

(1.5) In these equations VT[k] is the input voltage where the transition from code k − 1 to code k occurs. Since these two parameters characterize the nonlinear behavior of the ADC, they are calculated after removing the gain and offset errors from its transfer function [15].2 2

Consequently, the code transition levels that appear on (2.4) and (2.5), VT[k], are from the transfer function obtained after removing the offset and gain errors.

6


Figure 1.4 shows examples of INL and DNL errors. The INL measures the (nonlinear) deviations of the real transfer function with respect to the ideal straight line: it is a measure of large signal linearity of the converter. The DNL indicates the deviations in the width of each quantization step; as this parameter examines the nonlinearity of each code independently of all the others, it measures the small signal linearity of the converter. Output Code

DNL[4]0 INL[5]0

Figure 1.4. INL and DNL examples.

Since the information used to compute these two parameters is the same (code transition levels and the value of VLSB), they are not independent of each other. It can be shown that k −1

INL [k ] = INL [1] + ∑ DNL [k ]

with k > 1

(1.6)

i =1

(1.7) DNL [k ] = INL [k + 1] − INL [k ] . There are two common ways of presenting the INL and DNL: either only the maximum values are indicated,

INL = max ( INL [k ] )

with k = 1...2Nb − 1

(1.8)

(1.9) DNL = max ( DNL [k ] ) with k = 1...2Nb − 2 or there are figures showing the values of these parameters for all output codes. In situations of extreme degradation in the linearity of the converter it may happen that some codes do not appear at the output – these are called missing codes. It may also happen that the transfer function is non-monotonic, i.e. for an increase on the input voltage there is a


7

decrease on the output code. Having DNL > −1 LSB guarantees monotonicity and the presence of all codes. The most straightforward way of measuring the static parameters is to vary the input voltage and determine the code transition levels. However, the code obtained with a certain input level may not always be the same, due the presence of noise in the input signal and in the ADC. In this way each transition level must be found by determining the input voltage that makes two successive codes appear with a probability of 0.5. This process requires a large number of conversions for each transition level, becoming a very slow process even for moderate resolutions. A commonly used alternative is the histogram method [15, 16], where a periodic signal – usually a sinewave – is applied to the input and the results from a large number of conversions are examined. The transfer function of the ADC, and therefore the static parameters just described, is obtained by comparing the number of times that each code occurs against the value that would be found in the ideal converter. For a ramp input all codes should occur with equal probability, whereas for a sinewave it is expected that the codes corresponding to its extremities appear more often than those of the middle, because in this region the input voltage varies faster. The histogram method is usually made with the maximum clock frequency and, depending on the input frequency, it may already include effects of dynamic nature.

1.2.3

Dynamic Characterization of ADCs

The dynamic characterization of an ADC is made with a sinewave input because it has several attractive properties:

There is a precise and simple mathematical description both in time and frequency domains. By filtering it is possible to approximate an imperfect sinusoidal signal to its ideal form. Moreover, its non-idealities (noise and distortion) can be easily measured. The input frequency response of the converter is obtained directly.

The parameters used in the dynamic characterization of an ADC are the same employed for any other (ideally) linear circuit. To measure these parameters a sinusoidal signal with frequency fi is applied to

8


the input and the output spectrum, obtained from a Fast Fourier Transform (FFT) of the output sequence, is examined. One relevant parameter is the signal-to-noise ratio (SNR), which is the ratio between the signal and noise power [15]. As mentioned in section 1.2.1, the quantization operation limits the achievable SNR to the value given by (1.3). The SNR of a real ADC is always smaller, due to the noise generated by electrical components inside the converter. Another important parameter is the total harmonic distortion (THD). The non-linearities of the ADC generate spectral components at frequencies multiples of fi (harmonics). The THD is the ratio between the power of all harmonics and the power of the input signal, ⎛ N H +1 ⎞ 2 ⎟ ⎜⎜ ⎟ A ⎜⎜ ∑ n .fi ⎟⎟ ⎟⎟, (1.10) THD[dB] = 10 log10 ⎜⎜ n =2 2 ⎟⎟ ⎜⎜ Af ⎟ i ⎟⎟ ⎜⎜ ⎟⎟⎠ ⎜⎜⎝ where An .fi is the amplitude of the spectral component at nfi, and NH is the number of harmonics considered. A reasonable number for NH is 9 [15]. The signal-to-noise-and-distortion ratio (SINAD) is the ratio between the signal power and the power of all undesired spectral components (noise plus distortion). This parameter measures the true performance of the converter and can be obtained from the SNR and THD, SNR[dB] ⎞ ⎛ THD[dB] − ⎟ ⎜⎜ (1.11) SINAD[dB] = −10 log10 ⎜10 10 + 10 10 ⎟⎟⎟. ⎜⎜ ⎟⎟ ⎝ ⎠ The SINAD is usually presented as a function of the input and sampling frequencies. The effective number of bits (ENOB) gives the same information of the SINAD, but in a more convenient way. This parameter results from the inversion of the SNR expression of the ideal ADC (1.3), while substituting the SNR by the SINAD,3

ENOB =

3

SINAD[dB] − 1.76 6.02

.

(1.12)

Note that in the ideal converter there is no distortion: the undesired spectral components are due just to (quantization) noise. In real ADCs distortion exists and, therefore, when assessing the undesired spectral components, it makes sense to consider the SINAD instead of the SNR.


9

The ENOB indicates the number of bits that an ideal converter would have to achieve the measured SINAD. This parameter reveals immediately how far from the ideal case is the performance of the ADC being characterized. The description just presented about the static and dynamic parameters is not intended to be exhaustive. A detailed explanation of the parameters and measurement procedures can be found in [15]. This reference also provides a list showing which parameters are most relevant in a number of systems where ADCs are currently used (audio, video, telecommunications, radar, etc.).

1.3

FLASH ADCS

1.3.1

Architecture Description

The architecture that achieves the largest conversion rate is the flash ADC, represented in Fig. 1.5. The sample-and-hold (S/H) performs the sampling operation. The pre-amplifiers subtract the sampled signal (vIS), from the reference voltages generated by the resistive ladder: the differential output voltage of a pre-amplifier is positive if vIS is larger than its reference voltage, and negative otherwise. At the output of each pre-amplifier there is a latched comparator, triggered by the clock signal. It provides the high logic level if the differential output voltage of the pre-amplifier is positive, and the low logic level in the case it is negative. When examining the outputs of all latched comparators a thermometer code is found: all comparators connected to pre-amplifiers with reference voltages lower than vIS present a high logic output level, while all the others have a low logic level – this resembles the operation of a mercury thermometer. The encoder detects the high-to-low transition in the thermometer code and provides the corresponding binary output code. The encoders used in most flash ADCs include mechanisms of correcting bubble errors (more than one high-to-low transition in the thermometer code) [11, 17–20]. In an Nb bit flash ADC there are 2Nb − 1 pre-amplifiers and latched comparators, each detecting a single code transition voltage. The overall power dissipation and area, and the input capacitance of the preamplifiers limits the utilization of this kind of converters to 6–8 bit [18, 21–24].


10

Pre-Amplifier Stage

VREFP

+ -

+

-

-

+

+

-

-

+

+

Encoder

-

Latched Comparator Stage

bNb

b1 + -

+ -

-

-

+

+

-

-

+

+

VREFN vI clk

S/H

vIS Clock buffers

Figure 1.5. Flash ADC.

1.3.2

Design Specifications of Each Building Block

An overview of the most relevant design parameters in each constituting sub-block of the flash ADC will now be presented. In the sample-and-hold the most important parameters are the input bandwidth and the linearity. The input capacitance of the pre-amplifiers can be quite significant in ADCs having moderate resolutions and, therefore, the S/H must have a large driving capability. The S/H is not strictly necessary in a flash ADC, i.e. the input voltage can be applied directly to the pre-amplifiers. In that case the


11

sampling operation occurs when the latched comparators are triggered. Several issues must then be addressed:

The distribution of the input and clock signals usually requires long metal lines, whose parasitic resistances and capacitances introduce a propagation delay. Significant timing differences in the arrival of those signals to each pre-amplifier and latched comparator cannot exist, otherwise the sampling instant becomes input level dependent, originating distortion. This issue can be solved by using a tree structure for the distribution of the clock and input signals or by matching the delay in the clock and signal lines [10]. The pre-amplifiers have a limited bandwidth and a transfer function with saturation. It can be shown [10, 25], that this introduces a variable delay in the processing of the input signal, causing third-order distortion. The bandwidth of the pre-amplifier must be several times larger than the maximum input frequency to maintain the distortion in acceptable levels. When a S/H is used, the bandwidth of the pre-amplifiers is defined by settling considerations which, in case of high-frequency input signals, leads to a significantly smaller power dissipation [25]. In the beginning of the regeneration phase the latched comparators are still sensitive to their input voltage: a fast moving input signal can still change its decision, while a slow input signal cannot. Therefore the effective sampling instant depends on the slope of the input voltage of the comparator, originating distortion [22].

When a S/H is used, the sampling instant is very well defined, leading to a better input frequency response. As usually flash ADCs have low to medium resolutions, the linearity requirements of the S/H can be met with very fast and simple open-loop circuits [24, 26, 88]. The performance at high input frequencies is then only limited by the sampling network of the S/H which, typically, is simply constituted by a capacitor and one or two CMOS switches. Because of this, most recently published flash ADCs employ a S/H. The pre-amplifier is, in most cases, a simple differential pair. Its most relevant design parameters are the offset voltage, DC gain, settling speed and input capacitance.

12

Offset Reduction Techniques in High-Speed ADCs If a pre-amplifier has an offset voltage VOS, one of the code transi-

tion levels of the ADC is shifted by that amount.4 The offset voltages have, therefore, a direct impact on the linearity of the ADC. Offset voltages exist because two equally drawn components do not present the same characteristics – there is a mismatch between them. These differences are of random nature and occur due to small variations in the fabrication process. As will be shown in section 1.6.2, the mismatches depend mainly on the area of the devices: larger components must be used to achieve lower offset voltages, thereby increasing the parasitic capacitances. This, in turn, makes the pre-amplifiers slower and their input capacitance larger. More power must then be spent in the pre-amplifiers (to make them faster) and in the S/H (to drive its larger load capacitance). There is, thus, a fundamental tradeoff between speed, power dissipation and accuracy [28]. This tradeoff can be relaxed by using offset reduction techniques: offset sampling [11, 29–35] and averaging [28, 36]. The averaging technique was proposed in [36] and is now commonly employed in high speed flash ADCs [24–27, 37]. It consists in the connection of low value resistors between the outputs of the pre-amplifiers, which correlates their output voltages. Each code transition level is defined by a weighted sum (average) of the random deviations in the elements of many pre-amplifiers, which effectively lowers the offset voltages. Chapters 2 and 3 of this book are devoted to the detailed study of this technique. Offset sampling techniques employ capacitors to sense, store, and subtract the offset voltages of the pre-amplifiers from the input. Chapter 5 analyses those techniques. The offset voltages of the latched comparators cannot be reduced by averaging and offset sampling techniques (a noteworthy exception is presented in chapter 5). So, a reasonable DC gain in the pre-amplifiers is important to reduce the input referred offset voltages of the comparators. Increasing the gain is accomplished by spending more power. To achieve, simultaneously, high gain and high bandwidth it is more power efficient to use several cascaded stages instead of a single one [38, 39]; so there are flash ADCs following that approach [26, 33– 35, 37]. 4

The offset voltages of the latched comparators and the deviations on the reference voltages are being neglected in this discussion. In reality the location of each code transition level depends on all these factors.


13

The voltage variations in the internal nodes of the pre-amplifiers are coupled, through the parasitic capacitances, to the reference voltages generated by the resistive ladder – this is represented in Fig. 1.6.

Figure 1.6. Disturbance of the reference voltages.

Variations on the reference voltages have a direct impact in the performance of the converter, because they define the code transition levels. These variations can be reduced using smaller resistances, at the cost of increased power dissipation. Note that the offset requirement of the pre-amplifiers determines the transistor sizes and, therefore, its parasitic capacitances. Thus, it also influences the power dissipation in the resistive ladder. Mismatches between resistances cause random deviations on the reference voltages. Smaller deviations are obtained with resistors having a larger area. The most important design parameters of the latched comparator are the offset voltage and the regeneration speed. If a low offset is required, large devices must be used; this enlarges the parasitic capacitances, slowing the regeneration process and increasing the power dissipation. The input referred offset voltage of the comparator can be reduced by having a larger gain in the pre-amplifier stage(s) preceding it, but this has also a cost in power dissipation. From this discussion one may conclude that the offset voltage requirements, which impose a minimum area for the components, trade directly with the overall area, speed and power dissipation of the converter. The offset voltage is, in this way, the fundamental design parameter in CMOS flash ADCs and, as will be seen, also in all other high-speed architectures.


14

1.3.3

The Interpolation Technique

The output voltage of a pre-amplifier is zero when vIS is equal to its reference voltage: we are at the zero crossing of the pre-amplifier. The notion of zero crossing is relevant because the latched comparator can be regarded as a zero crossing detector: its digital output level only depends on whether it has a positive or negative input voltage. In this way, in a flash ADC the only important information is the location of the zero crossings of the pre-amplifiers, since those are the code transition voltages.5 For example, the linearity of the pre-amplifier is completely irrelevant. This observation led to the application of the Interpolation Technique [25–27, 29, 37, 40], which eases some of the problems in the flash converter. This technique consists on the connection of small resistive ladders between the outputs of consecutive pre-amplifiers, as shown in Fig. 1.7. The Interpolation Factor (IF) is the number of interpolation resistors. +

V1

-

vIS

+

V2

-

+

vON1 vOP1

vINTP1

vINTN1

vINTP2

vINTN2

vINTP3

vINTN3

+

vON2 vOP2

Figure 1.7. Resistive interpolation (IF = 4).

The pre-amplifiers behave linearly when their differential input voltage is small, and saturate when it becomes arbitrarily large. Figure 1.8 shows the output voltages of pre-amplifiers with consecutive reference voltages, and also the signals obtained by interpolation: extra 5

The offset voltages of the latched comparators are being neglected in this discussion.


15

zero crossings are created, which allows to substitute each group of IF pre-amplifiers by just one. In this way, there is a reduction of the input capacitance, layout area and power dissipation of the pre-amplifier stage. The power dissipated on the resistive ladder decreases because there are now less pre-amplifiers disturbing the reference voltages. The number of necessary reference voltages is also reduced by a factor of IF. In [34] the extensive utilization of interpolation allowed to eliminate the reference ladder altogether. zero crossings

vO

vINTN1 vINTP1

vINTP3 vINTN3 vON2

vOP1 vON1

vOP2 V1

V2

vIS

Figure 1.8. Output voltages of consecutive pre-amplifiers, and the voltages obtained by interpolation (IF = 4).

As illustrated in Fig. 1.9, there are deviations in the zero crossings generated by interpolation, due to the nonlinear transfer function of the pre-amplifiers. In this way the linearity of the pre-amplifiers, which was unimportant in flash ADCs without interpolation, now becomes relevant: both pre-amplifiers must be approximately linear in the interpolation range, as in the case shown in Fig. 1.8. Although this is not a strict linearity requirement, it sets an upper bound to the interpolation factor that may be used, for a given VFS. Speed related constrains also limit the usable interpolation factor and, simultaneously, set an upper limit to the value of the resistors. When a S/H is not used the differences of propagation time in the interpolation ladder are relevant [67] while, when a S/H is employed, there are settling specifications to be met. The addition of resistors between the outputs of the pre-amplifiers lowers their output resistance, decreasing the gain. To avoid this, the first ADCs employing resistive interpolation used low output impedance


16

buffers after the pre-amplifiers (usually a emitter/source follower) to drive the interpolation ladder [40]. Ideal zero crossing locations

vO

3/4 1/4

vOP1

vON2

vOP2

vON1 V1

V2

vIS

Figure 1.9. Interpolation errors that occur when the two pre-amplifiers are not linear in the interpolation range (IF = 4).

However, it was understood that connecting low value resistors between the outputs of the pre-amplifiers implements both the interpolation and averaging techniques [25–27, 37]. The simultaneous utilization of interpolation and averaging is examined in section 3.5.11. Contrarily to the common belief [27], using interpolation in an averaged pre-amplifying stage does not further decrease its input capacitance and power dissipation: although there are less pre-amplifiers, each one has larger devices and consumes more power. Still, the utilization of interpolation can yield a reduction on the layout area and complexity. There are alternative ways of performing interpolation: current interpolation [41, 78, 81], capacitive interpolation [34, 42, 43] and active interpolation [79]. However, the resistive interpolation shown in Fig. 1.7 (also called voltage interpolation) is the most common, and has the advantage of being easily combined with averaging. It is also possible to combine resistive interpolation with active interpolation. One should note that interpolation does not reduce the number of latched comparators: for an Nb bit flash ADC with interpolation there Nb are 2 pre-amplifiers and, still, 2Nb – 1 latched comparators. IF The interpolation technique is used not only in flash ADCs but also in two-step and folding converters.


17

1.4

TWO-STEP FLASH ADCS

1.4.1

Two-Step Flash ADC with DAC and Subtractor

The exponential growth of the overall power and area of the flash converter makes it practical only for resolutions up to 6 to 8 bit. The two-step flash ADC, shown in Fig. 1.10, mitigates its limitations. vODAC

vIS

S/H

vI

vI

vI

vI

residue

Coarse ADC (NbMSB)

DAC

+

Σ

−

NbMSB

Fine ADC (NbLSB)

NbLSB

Figure 1.10. Two-step flash ADC.

The S/H samples the input signal and the coarse flash ADC obtains the most significant bits (MSBs), which the DAC uses to generate a rough approximation of the input signal. The sampled input is, then, subtracted from the output voltage of the DAC yielding the residue, that corresponds to the error made in the coarse quantization. Finally, the fine ADC quantizes the residue and obtains the least significant bits (LSBs). Examples of ADCs using this architecture can be found in [44–48]. The coarse and fine sub-converters are flash ADCs. The number of necessary pre-amplifiers and comparators is reduced from 2Nb – 1, in a full flash ADC, to 2NbMSB + 2NbLSB – 2. For example, an 8-bit flash ADC needs 255 pre-amplifiers and comparators, where a two-step converter, with NbMSB = NbLSB = 4, only needs 30. Although the coarse ADC only resolves NbMSB bit, the deviations in its code transition levels must be lower than the quantization step of the converter, VLSB. If this does not occur, the residue will be out the input range of the fine flash ADC, as shown in Fig. 1.11(a). This limitation can be eased by using redundancy: the resolution of the fine ADC is increased in order to enlarge its full-scale input range – Fig. 1.11(b). Usually the resolution is increased by 1 bit [45–48], which


18

doubles the input range and allows to have deviations in the code transition voltages of the coarse ADC as high as ± 1 VFS . There are, 2 2NbMSB however, cases of ADCs using a different amount of redundancy [44]. residue

Fine ADC is saturated

Input range of fine ADC

VT[k+1]

VT[k]

vI

Deviations on the code transition levels of the Coarse ADC

(a) residue

Fine ADC does not saturate Extension of the fine ADC input range, by adding one more bit of resolution and maintaining its quantization step

VT[k+1]

VT[k]

vI

Deviations on the code transition levels of the Coarse ADC

(b)

Figure 1.11. Residue quantization in the presence of a large INL in the coarse ADC: (a) no redundancy; (b) 1 bit redundancy in the fine ADC.

In the architecture shown in Fig. 1.10, the fine ADC has a small full-scale input range – only VFS 6 – and its quantization step corre2NbMSB sponds to VLSB. Consequently, the pre-amplifiers and comparators must have low offset voltages, because these affect directly the linearity of the converter [45, 48]. To ease this specification, in some two-step ADCs the residue voltage is amplified before being applied to the fine sub-converter [46, 49]. If the residue amplifier has a gain of 2NbMSB , the input ranges of the coarse and fine sub-converters are the same, and a single flash ADC may be used to obtain the MSBs and the LSBs [47]. 6

Redundancy is not considered here. As mentioned above, if 1 bit of redundancy is used the fullscale input range of the fine ADC doubles.


19

In the two-step architecture there are much less pre-amplifiers and comparators than in the flash ADC. Moreover, if redundancy and residue amplification are used, the offset requirements of those circuits become relaxed. However, this converter employs a DAC, a subtractor and, eventually, an amplifier, whose linearity, gain error and settling speed are critical parameters that limit the resolution and sampling frequency [11, 49]. In a flash ADC there are no special linearity requirements for any of its constituting blocks (except for the S/H, if it is used). One should also note that the architecture shown in Fig. 1.10 is intrinsically slower than the flash ADC: a new sampling is only performed after a coarse quantization, plus a digital-to-analog conversion followed by a subtraction have been completed. A possibility is to apply the input signal directly to the coarse ADC, which then provides the MSBs to the DAC, at the same time the S/H outputs the sampled value to the subtractor [7]. Another possibility is to use two cascaded S/Hs, where the first one is already sampling the input signal while the output voltages of the DAC and the subtractor are still settling [45]. This leads, ultimately, to the pipeline ADC which has several cascaded stages, each one performing the following operations: analog-to-digital conversion, digital-to-analog conversion, subtraction, amplification and sampling. The analog-to-digital conversion is done by a flash ADC, and the remaining operations are performed using a Multiplying DAC (usually implemented with a single amplifier [50]) whose linearity, gain error and settling speed determine the overall performance of the converter.

1.4.2

Two-Step Subranging Flash ADC

The subranging ADC performs the same internal operations of the two-step converter shown in Fig. 1.10. However, the digital-to-analog conversion and the subtraction are done in a way that avoids using highly linear components, therefore improving high frequency performance [42, 43, 51–60]. Figure 1.12 shows the architecture of this ADC: the S/H provides the sampled signal to both the coarse and the fine flash ADCs. The coarse ADC quantizes the MSBs, making a rough estimation of input signal “position”. Then, the set of reference voltages that are closer to the input signal are selected and applied to the fine ADC, which quantizes the LSBs.


20

2NbLSB − 1 resistors between each reference voltage used by the Coarse ADC Resistive Ladder

Selection of references for the Fine ADC

Coarse ADC

VREFP

+ -

+ -

+ -

-

-

+

+

-

-

+

+

[2NbMSB − 1]

[2NbMSB − 2]

-

-

+

+

Encoder MSB

2NbLSB − 1 switches selected simultaneously

NbMSB

[1]

VREFN

Fine ADC + -

+

-

+

+

-

-

+

+

[2NbLSB − 1]

[2NbLSB − 2]

Encoder LSB

-

-

+ -

+ -

-

-

+

+

-

-

+

+

} 2NbLSB − 1 reference voltages

vI

S/H

vIS

Figure 1.12. Two-step subranging ADC.

[2]

[1]

NbLSB


21

The resistive ladder performs two operations: it generates the reference voltages to the coarse ADC and, in combination with the reference selection switches, it realizes the digital-to-analog conversion. The subtraction between the (sampled) input signal and the DAC result is performed in a distributed way, by the pre-amplifiers of the fine ADC. In this way, the subranging architecture makes the operations depicted in Fig. 1.10, but does not have blocks with critical linearity requirements: only zero crossings are important. The deviations on the code transition levels of the two-step subranging converter are caused by the offset voltages of the pre-amplifiers and latched comparators inside the fine flash ADC. Offset sampling techniques [42, 43, 51, 53, 55–59], eventually combined with averaging [60], are employed to obtain low offsets with small occupied area and power dissipation. Redundancy eases very significantly the offset requirements of the pre-amplifiers and comparators of the coarse ADC [43, 54, 56, 59, 60]. More details about the utilization of redundancy in this kind of converters are given on section 5.4.3, when the implementation of a 6-bit 1 GHz ADC is described. Another possibility is the utilization of the same flash ADC to decide both the MSBs and the LSBs [55, 57], in which case no redundancy is necessary [58]. Although in this architecture the number of pre-amplifiers and latched comparators is reduced from 2Nb – 1 to 2NbMSB + 2NbLSB – 2, it is still necessary to generate 2Nb – 1 reference voltages, each having a switch to select it. Using interpolation in the fine ADC reduces not only the number of pre-amplifiers, but also the number of reference voltages and switches [43, 58–60]. An alternative solution, that uses buffers to drive a separate resistive ladder for the fine ADC, is presented in [54]. A critical issue in the two-step subranging converter is the settling of the reference voltages applied to the fine ADC. Note, though, that even in a full flash ADC the reference voltages are disturbed and take some time to settle. The two-step subranging architecture shown in Fig. 1.12 is still intrinsically slower than the flash ADC: before the S/H acquires the next sample, the coarse ADC must quantize the MSBs and the selected reference voltages have to settle, so that the fine ADC correctly


22

obtains the LSBs. Several techniques are used to increase the sampling frequency:

Usage of a S/H without reset, which samples the input signal while the selection of the reference voltages is still being done [43]. Usage of two time-interleaved fine ADCs and one coarse ADC: while the coarse ADC and one fine ADC are sampling the input signal, the other fine ADC is obtaining the LSBs concerning the previous sample [6, 52, 59]. In the cases where the same flash sub-converter decides both the MSBs and the LSBs, there are two flash ADCs working in time interleaving [55, 57, 58]. Make the coarse ADC decide in a small fraction of the clock cycle. This leaves sufficient time for the settling of the reference voltages and pre-amplifiers in the fine ADC [60]. This solution cannot be used for very high fs, due to the limited time to make the coarse conversion.

To further reduce hardware and power dissipation, it is possible to have more than two conversion steps: for example, a three-step ADC was described in [61]. One could think of using even more conversion steps and this leads, ultimately, to the successive approximation (SAR) ADC, where 1 bit is obtained in each clock cycle. Although that architecture has been mainly used in low speed converters, it is possible to reach high sampling frequency by adding several SAR ADCs in timeinterleaving [13] – note that this is analogous to what was done in [55, 57, 58] where, as mentioned above, there are two time interleaved ADCs in a two-step converter.

1.5

FOLDING AND INTERPOLATION ADCS

1.5.1

Architecture Description

The folding technique was proposed in [62], and used primarily in ADCs with bipolar transistors [63–76]; in the last few years it has also been applied in data converters implemented in CMOS technologies [77–89]. The initial architecture is depicted in Fig. 1.13, where there are two flash ADCs which decide simultaneously and independently the most significant and least significant bits [62–64].


Coarse flash ADC

23

NbMSB bits

Nb = NbMSB+NbLSB

vI

Folding Circuit

residue

Fine flash ADC

NbLSB bits

clk

Figure 1.13. Initial architecture of folding ADCs.

The residue quantized by the fine flash converter is generated by the folding circuit which, conceptually, has the transfer function shown in Fig. 1.14(a). The residue is obtained directly from the input signal and not from a coarse quantization plus a digital-to-analog conversion followed by a subtraction operation, as in the two-step flash ADC. Practical implementations used the transfer function represented in Fig. 1.14(b), and the differences to the one in Fig. 1.14(a) are taken in consideration in the encoding process. vO

vO

(a)

vI

(b)

vI

vO

(c)

vI

Figure 1.14. Transfer function of folding circuits in the first folding ADCs: (a) conceptual; (b) used in practice; (c) high-frequency limitations.

The most fundamental limitation of these early folding architectures is the linearity required for the folding circuits, which further degrades as the input frequency increases: if a full-scale sinusoidal signal is used, the output voltage of the folding circuit has spectral components at much higher frequencies; its limited bandwidth originates non-linearities which are equivalent to the rounding of the tips of the transfer function, as represented in Fig. 1.14(c). Note that this would not occur if there was an input S/H.


24

This problem was addressed in [65] by using two folding circuits in parallel, having transfer functions shifted with respect to each other. As shown in Fig. 1.15, there is always one folding circuit operating in the most linear region of the transfer function. However, even in that implementation, the nonlinearity of the folding circuits had to be compensated by using a nonlinear distribution of the reference voltages in the fine flash converters.

vI

Folding Circuit 1

Folding Circuit 2

residue 1

residue 2

Error Correction and Encoding

Coarse flash ADC

Fine flash ADC 1

bNb

b1

Fine flash ADC 2

clk Linear range of folding circuit 2 (LSBs are obtained by fine flash ADC 2)

Linear range of folding circuit 1 (LSBs are obtained by fine flash ADC 1)

residue 1

vI residue 2

vI

Figure 1.15. Double folding ADC.

Increasing the number of folding circuits connected in parallel relaxes their linearity requirements. In fact, if there is a sufficiently


25

large number of folding circuits, the linearity becomes irrelevant: only their zero crossing locations are important. This is the principle of operation of the most recent folding ADCs. It is interesting to note that to achieve higher sampling rates, there was an evolution in both two-step and folding ADCs towards architectures where only zero crossings are relevant. Modern folding circuits have differential outputs and the transfer function represented in Fig. 1.16, whose shape is rounded and the zero crossings have very well defined locations. A folding circuit is composed by a number of differential pairs, each defining one zero crossing, as will be seen in section 1.6.3. A total of 2Nb – 1 zeros must be generated, since they correspond to the code transition voltages of the ADC. vO

ΔVF

vON

vOP V1

V2

V3

V4

V5

vI

Figure 1.16. Transfer function of modern folding circuits (FF = 5).

The folding factor (FF) is defined as the number of zero crossings in the transfer function of a folding circuit. Two consecutive zero crossings of the same folding circuit are ΔVF Volt apart. The usable folding factor is limited by the settling speed, systematic zero crossing deviations, offset voltage and the output common-mode voltage value (this is discussed in section 1.6.3). It is common to have FF between 3 and 9. Several folding circuits, with transfer functions shifted with respect to each other, must be connected in parallel to increase the number of zeros. It will be considered that there are FB folding circuits, each with FF zeros, yielding a total of FFFB zero crossings. For an Nb bit converter one must, therefore, have (1.13) FF FB = 2Nb − 1. As each zero of a folding circuit is generated by one differential pair, 2N b – 1 differential pairs are needed in a folding converter. This is exactly the same number of differential pairs used in the pre-amplifier stage of a full flash ADC.

26


It was shown that interpolation reduces the number pre-amplifiers in a flash ADC. This technique can also be used to obtain extra folding characteristics and decrease the number of necessary folding circuits (Fig. 1.17). The total number of zeros crossings generated in this way, NTOT, is NTOT = FFFBIF. (1.14) The distance between zeros of consecutive folding circuits, ΔVB, is ΔVB = vO

ΔVF = I FVLSB . FB

(1.15) Output voltages of the folding circuits

ΔVB

Zero crossings

Interpolation characteristics

VLSB

vI

Figure 1.17. Transfer function of two consecutive folding circuits, and the characteristics obtained by interpolation (FF = 5 and IF = 4).

All converters employing folding also use interpolation – for this reason they are called folding and interpolation ADCs. The characteristics of adjacent folding circuits must be sufficiently linear in the interpolation range to avoid systematic zero crossing deviations (the situation is similar to the interpolation between pre-amplifiers, shown in Figs. 1.8 and 1.9). Again, although this is not a stringent limitation, it sets an upper limit to the interpolation factor that may be used. In the flash ADC each latched comparator is connected to a preamplifier. In folding and interpolation ADCs the latched comparators examine the outputs of the folding and interpolation circuits. As there are FB folding circuits and an interpolation by a factor of IF, the number of latched comparators that decide the LSBs, NCOMP, is N (1.16) NCOMP = FB I F = TOT , FF which is significantly smaller than in a flash ADC. To understand the reason for this reduction let us examine Fig. 1.18, which shows the input voltages of a latched comparator in a flash and in a folding and


27

interpolation ADC. This figure also exhibits the digital output values of that latched comparator. A coarse flash ADC must be used to distinguish these regions

Digital output of the comparator

Digital output of the comparator

high

low

high

low

high

low

high

low

Input voltage of the comparator

Input voltage of the comparator

V1 (a)

vI

V1

V2

V3

V4

V5

vI

(b)

Figure 1.18. Input voltages of a latched comparator and its digital output in: (a) flash ADC; (b) folding and interpolation ADC.

In the flash ADC the digital output of the comparator depends on the location of one zero crossing while, in the folding and interpolation ADC, it depends on FF zero crossings: for this reason the number of necessary comparators is reduced by a factor of FF. The digital output levels of the comparators that are connected to the folding circuits change periodically with the input signal. In the example of Fig. 1.18(b) there are three zones that can not be distinguished using only information from those comparators. A separate (coarse) flash ADC distinguishes between those regions and indicates the MSBs. Its resolution depends on the number of regions defined by the folding circuits, which is determined by FF. As in two-step flash converters, misalignments between the coarse flash ADC and the folding and interpolation core, which determines the LSBs, lead to large errors on the transfer function of the converter. This is solved by using redundancy [82], or by detecting the input signal position with respect to the error prone zones [67, 71, 78]. The architecture of the folding and interpolation ADC is shown in Fig. 1.19. The utilization of a S/H is not mandatory, but highly recommended. This will be further discussed on section 1.5.3.


28 . VREFP

Coarse flash ADC

Interpolation

+

Folding Circuit 0

[0]

-

+

FF Resistive Ladder

Comparator Stage

[1]

-

+

Folding Circuit 1

[IF]

-

FF

+

Folding Circuit FB-1


Folding Stage

bNb

b1

[(FB−1)IF]

-

+

FF

[(FB−1)IF+1]

-

VREFN IF resistors

vIS vI

clk

+

S/H

[FBIF−1]

-

Clock buffers

Figure 1.19. Folding and interpolation ADC.

The interpolation resistors connect to successive folding circuits, which have consecutive folding characteristics. The only particular cases are the first and last folding circuits which, as Fig. 1.20 shows, have consecutive zero crossings. There is, however, one detail: the interpolation resistors must connect the positive output of Folding Circuit 0 to the negative output of Folding Circuit FB − 1 and vice-versa. In the example shown in Fig. 1.20, the zero crossings of folding circuit 0 should occur at V1, V2 and V3. Near vI = V3 the output voltages


29

of circuits 1 and 3 are symmetric with respect to the ones of folding circuit 0 and, therefore, the introduction of interpolation does not change the position of this zero crossing. The situation near V1 is quite different: the referred symmetry does not exist, and the interpolation resistors force a shift in the position of this zero crossing. If V1 is the lower extremity of the input range there will be systematic deviations in the transition levels of first codes of the ADC. On the other extremity of the input range – the last zero crossing of folding circuit FB − 1 – a similar situation occurs. Figure 1.20 shows that this symmetry occurs naturally everywhere except in the extremities. A way to solve this problem is to make all folding characteristics cross again between V0 and V1 by adding, in each folding circuit, one more differential pair to create a zero crossing in that range: for example, folding circuit 0 would then have another differential pair with V0 as reference voltage. For this reason, in folding and interpolation converters there are zero crossings outside the input range. In this way the total number of zero crossings – NTOT given by (1.14) – is larger than 2Nb − 1. vO

vON0 vON1

vON3 vON3

vOP0−vON3

vON1 vOP1

vOP0−vOP1 vOP0 V0

vOP1 V1

vOP0−vON3=vON0−vON1 vOP0−vOP1=vON0−vOP3

vOP3 vOP3 V2

V3

vI

Figure 1.20. Symmetry issues near the lower extremity of the input range (vI = V1) – example for FB = 4.

If sufficiently high interpolation resistances are used, the zero crossings of the folding circuits would not be significantly deviated. However, the time constant introduced by such a solution would be prohibitively large for an high speed ADC. Moreover, when the averaging technique is employed to reduce the offset voltages of the folding circuits, there must be low resistances between their outputs. This subject will be further analyzed on section 2.7.4, where the termination of averaged folding circuits is addressed.


30

Examining the outputs of the latched comparators connected to the folding and interpolation circuits one finds a circular code, as depicted in Fig. 1.21. This code repeats itself in each folding period. folding period vOP0

vOP2

vON1

vON3

vON0

vON2

vOP1

vOP3

0 0 0 1

0 0 0 0

1 0 0 0

1 0

1 0

1 1 1 0

1 1 1 1

0 1 1 1

0 0 1 1

0 0 0 1

C0 C1 C2 C3

Output of Comparators

vI

Figure 1.21. Circular code (example for FB = 4 and no interpolation).

1.5.2

Cascaded Folding

As will be seen in section 1.6.3, the folding circuit most widely used in CMOS data converters is composed by FF differential pairs, having the following practical limitations to the maximum folding factor that can be implemented:

The load capacitance rises with FF, due to the increasing number of differential pairs connected to the output nodes. This limits the achievable sampling frequency. Each differential pair must become completely unbalanced – i.e. the tail current must flow entirely in one of its transistors – when its differential input voltage is ΔVF. If this does not happen there will be systematic zero crossing deviations and the gain decreases. For large FF, ΔVF is small and a large W/L ratio must be used. However, W/L can not be increased indefinitely.


31

The standard deviation of the offset voltage of each zero crossing increases with FF.

The common mode of the output voltages decreases when FF increases, which may place the transistors of the differential pairs in the triode region.

The cascaded folding technique was introduced in [69, 80] to mitigate these problems, allowing to reach resolutions as high as 13 bit [83], while maintaining a reasonably small number of differential pairs in the folding core. It consists on the cascaded connection of folding and interpolation circuits, to increase the overall folding factor. An example is shown in Fig. 1.22, where the folding circuits in the first stage have a folding factor of 5 and, in the second stage, have a folding factor of 3. The resultant signal has a folding factor of 15, which corresponds to the multiplication of the folding factors of the two stages. Figure 1.23 represents the architecture of an ADC with NFstg cascaded folding stages, where FF[k], FB[k] and IF[k] are the folding factor, number of folding circuits and interpolation factor of the kth folding stage. The number of necessary reference voltages corresponds to the number of differential pairs in the first folding stage, FF [1] FB [1]. Note that by cascading folding circuits no new zero crossings are created – this operation simply joins more zero crossings in the same signal. In a cascaded folding architecture the zero crossings are created by the differential pairs in the first stage, and then by the interpolations made in each stage. In this way, the total number of zero crossings is N Fstg

NTOT = FF [1] FB [1] ∏ I F [k ].

(1.17)

k =1

The overall folding factor, FFTOT, is the product of the folding factors of all stages, FFTOT =

N Fstg

∏ FF [k ].

(1.18)

k =1

There is one latched comparator connected to each output of the last folding stage. The number of comparators that decide the LSBs is, therefore, NCOMP = FB ⎡⎣⎢N Fstg ⎤⎦⎥ I F ⎡⎢⎣N Fstg ⎤⎦⎥ .

(1.19)


32

Circuit of the Second Folding Stage

Circuits of the First Folding Stage V1 V4 V7 V10 V13 V2 V5 V8 V11 V14 V3 V6 V9 V12 V15

+ − + − + +

vOF1_1 vOF1_2 vOF1_3

− + −

−

vOF2

+ −

+ + − + − +

vOPF1_1

vONF1_1 vOPF1_2

vONF2

vONF1_2

vOPF2 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10V11V12V13V14V15

vOPF1_3

vI

vONF1_3 V1 V2 V3 V4 V5 V6 V7 V8 V9V10V11V12V13V14V15

vI

Figure 1.22. Cascaded folding (FF[1] = 5 and FF[2] = 3). Folding and Interpolation Core

Resistive Ladder

VREFP

Folding and Interpolation Stage 1: FF[1]FB[1]

FF[1] FB[1] IF[1]

Folding and Interpolation Stage NFstg: FB[1]IF[1]

FB[NFstg-1]IF[NFstg-1]

FF[NFstg] FB[NFstg] IF[NFstg]

Comparator Stage:

FB[NFstg]IF[NFstg]

VREFN

Figure 1.23. Cascaded folding architecture.

NCOMP = FB[NFstg]IF[NFstg]


33

The choice of the parameters in each stage is not arbitrary – it is dictated by the boundary conditions: the number of outputs of one stage must be equal to the number of inputs of the next, FB [k ] I F [k ] = FB [k + 1] FF [k + 1]. Using (1.18) and (1.20) in (1.17), allows to write NTOT = FFTOT FB ⎡⎣⎢N Fstg ⎤⎦⎥ I F ⎡⎣⎢N Fstg ⎤⎦⎥ . Using (1.19) and (1.21) leads to

(1.20) (1.21)

NTOT . (1.22) FFTOT Equations (1.21) and (1.22) are similar to (1.14) and (1.16), which characterize an ADC with a single folding stage. Thus, in what concerns the total number of zero crossings and comparators, the cascaded folding architecture is equivalent to one having a single stage, where FF = FFTOT, FB = FB[NFstg] and IF = IF[NFstg]. Using (1.18), (1.20), (1.21) it is possible to calculate the number of differential pairs in the kth folding stage, NDP[k], NCOMP =

NTOT . (1.23) N ⎛k −1 ⎞⎛ ⎞⎟ ⎟⎟ ⎜⎜ Fstg ⎜⎜ ⎟ ⎜⎜∏ FF [ j ]⎟⎟ ⎜⎜ ∏ I F [ j ]⎟⎟ ⎟ j =k ⎝ j =1 ⎠⎝ ⎠⎟ Equation (1.23) indicates that to minimize the number of differential pairs in a certain stage, one should have larger folding factors in previous stages and larger interpolation factors on the later stages. When the overall folding factor is increased, the resolution of the coarse flash ADC must also be increased. Another aspect to have in consideration is that the folding factors of all stages, except of the first one, must be an odd number. This condition is necessary to generate valid folding signals when cascading folding circuits [82]. One disadvantage of using cascaded folding is that the interconnections between the folding circuits of subsequent stages originates a complex layout, with significant parasitic capacitances – this will be addressed in section 4.3.5. N DP [k ] = FF [k ] FB [k ] =

1.5.3

Design Specifications of Each Building Block

The utilization of a sample-and-hold in a folding and interpolation ADC is not mandatory, but highly recommended. If a full scale sinewave with a frequency fi is directly applied to a folding circuit, its strongly nonlinear transfer function originates an output voltage with

34


strong harmonics at frequencies much higher than fi. The bandwidth of a CMOS folding circuit is limited by the load capacitance introduced by its FF differential pairs. The limited bandwidth of the folding circuit affects its output voltage in three ways [90]:

1. Attenuates the waveform 2. Introduces a group delay 3. Changes the relative positions of the zero crossings of the output signal The first two effects are of minor importance, but the third originates distortion. This poses a stringent restriction to the maximum input signal frequency, and explains the limitations encountered in CMOS folding and interpolation converters without S/H [77, 78]. The presence of a S/H is specially important in ADCs using cascaded folding, due to the large folding factors obtained – in fact practically all published ADCs using this technique employ it. When a S/H is used the folding circuits respond to an input signal resembling a step: their output voltages must settle so that the comparators detect the correct zero crossings. This settling specification is much less stringent than the bandwidth requirement found in the absence of a S/H. However, when there are several cascaded folding stages the settling time can still be significant. The case of a converter with two stages is considered in Fig. 1.24, which represents the output voltage of the S/H and also the output voltages of three consecutive folding circuits in each of the two stages. When the clock signal (clk) is low the folding circuits are reset, and their differential output voltages are zero. When clk is high the output of the S/H settles towards the sampled value, and may pass through various zeros of each folding circuit. In this way the output voltages of the folding circuits vary non-monotonically – this effect is more pronounced at the second stage because the overall folding factor is larger. The latched comparators examine the folding/interpolation outputs of the second stage – only the zero crossings on those signals are relevant. At t = 2TS one of those outputs has a zero voltage (the sampled input voltage corresponds to a zero crossing of that circuit). Note that the output voltage would not be zero if the sampling frequency was increased – an error would occur. The achievable sampling frequency is, in this case, limited by the simultaneous settling time of the S/H and folding stages.


35

clk

Output Sample-and-Hold

First Folding Stage Zero output voltages

Second Folding Stage TS

0

2TS

3TS

t

Figure 1.24. Illustration of the output voltages of the S/H and folding stages (NFstg = 2).

One technique that eases this problem is the introduction of a trackand-hold at each folding/interpolation output, as shown in Fig. 1.25. The interstage track-and-holds are composed of simple CMOS switches and the input capacitance of the differential pairs of the next stage. This technique, called pipelined folding, was proposed in [82, 83]. Stage i

Stage i+1

Folding Circuit k

Folding Circuit k+1

Figure 1.25. Pipelined folding technique.

As Fig. 1.26 shows, each folding stage now settles independently, which relaxes the settling specifications and allows to reduce the over-


36

all power dissipation. This technique has, however, the drawback of introducing a new source of offset voltage: the mismatches in the charge injection of the switches. clk

Output Sample-and-Hold

First Folding Stage

Zero output voltages

Second Folding Stage 0

TS

2TS

3TS

t

Figure 1.26. Illustration of the output voltages of the S/H and folding stages (NFstg = 2), when the pipelined folding technique is used.

Another technique, which was proposed in [84] and more recently used in [88], is particularly well adapted to the notion that only the zero crossings are relevant. Figure 1.27 shows the output signals of the various blocks when this technique is used. In the previous examples the input signal was applied to a S/H, whose output voltage is zero during half clock period (reset phase), and settles to the sampled value during the other half clock period (amplification phase). In the case shown in Fig. 1.27 a track-and-hold (T/H) is used: when clk is low its output voltage follows the input (track phase), while when clk is high it remains constant (hold phase). The folding stages are reset during the track phase and, thus, their output voltages are zero. When the T/H is holding its output voltage, the folding stages are at their amplification phase. Since the output of the T/H remains unchanged, the output voltages of the folding circuits that are at the zero crossing remain zero during this phase; all the other output voltages go smoothly toward their final values. In this way the zero crossing is at the right place during the entire amplification phase. Ideally almost no settling time would be needed to guarantee the correct operation of the converter. However the incomplete settling of a


37

given stage increases the input referred offset voltages of the next stages (this is further discussed in section 3.2). clk

Output Track-and-Hold

First Folding Stage Zero output voltages

Second Folding Stage 0

TS

2TS

3TS

t

Figure 1.27. Illustration of the output voltages of the T/H and folding stages (NFstg = 2), when the equalizing technique is used.

To implement this technique one may also use a nonresetting S/H – as the one presented in [43] – instead of a T/H. The important fact is that the voltage applied to the folding circuits remains unchanged during their amplification phase. The positions of the zero crossings generated by the folding and interpolation circuits are deviated due to systematic errors or to random mismatches in the components. The errors of systematic nature,

Deviations in the zero crossings of the extremities, represented in Fig. 1.20, which are originated by asymmetries between the output voltages of the folding circuits Interpolation errors, due to the nonlinearity of the folding signals Deviation in the first and last zero crossing of each folding circuit, in certain bias conditions. This is a problem of the folding circuit most commonly used in CMOS technologies, described in section 1.6.3

38


can be reduced to negligible levels by conveniently choosing the architecture parameters and the bias conditions of the folding circuits. The mismatches between the components originate random deviations on the zero crossings. The most important specifications of the folding circuits are similar to those found in the pre-amplifiers of flash ADCs7: offset voltage, DC gain, settling speed and input capacitance. Once again the offset voltage requirement imposes a minimum area for the components, trading directly with the overall area, speed and power dissipation of the converter. Averaging [36, 69, 72, 80, 84, 87, 88] and offset cancellation techniques [83, 85, 89] have been used to lower the offset voltages and ease this tradeoff. The relevant parameters of resistive ladder and the latched comparators are the same found in the flash ADC, mentioned in section 1.3.2. This converter combines two techniques that significantly decrease the number of active elements, with respect to the flash ADC: folding decreases the number of latched comparators and the interpolation decreases the number of differential pairs connected to the input. The introduction of cascaded folding stages allowed to reach resolutions up to 13 bit [83], while maintaining a reasonable number of differential pairs and latched comparators.

1.6

BUILDING BLOCKS OF CMOS HIGH-SPEED ADCS

1.6.1

The MOS Differential Pair

The MOS differential pair, represented in Fig. 1.28, is the fundamental building block of the pre-amplifiers and folding circuits. Its transfer function will now be derived using the quadratic drain current model for the MOS transistor, β 2 (1.24) iD = (vGS −Vt ) 2 where W , (1.25) β = μCox L 7

Actually, as will be shown in section 1.6.3, the offset voltages in the folding circuits are larger than in a pre-amplifier stage, for the same component sizes. Furthermore the bandwidth of the folding circuits is also smaller due to the presence of several differential pairs connected to the output nodes, instead of a single one.


39

and vGS is the gate-to-source voltage, Vt is the threshold voltage, μ is the carrier mobility, Cox is the gate capacitance per unit of area and W and L are the gate dimensions of the transistor. VDD

R0

R0

iDN

iDP

vON vIP vD

vOP

CL MN

MP

vIN ISS

Figure 1.28. Differential pair with NMOS transistors.

Analyzing the differential pair of Fig. 1.28 leads to β 2 iDP = (vGSP −Vt ) , 2 β 2 iDN = (vGSN −Vt ) , 2 iDP + iDN = I SS , vD = vGSN − vGSP .

(1.26) (1.27) (1.28) (1.29)

Solving simultaneously (1.26)–(1.29) allows to obtain the differential output current in the absence of mismatches, iDIFF0 = iDP − iDN, when the differential pair is non-saturated. Defining VOVD as the overdrive voltage of the transistors when the differential input voltage is zero, VOVD = vGSN − Vt = vGSP − Vt, it can be verified that for vD = ± 2VOVD the differential pair becomes completely unbalanced (the current ISS flows just through one of the transistors). Gathering all this information,


40

iDIFF 0

⎧⎪ I SS ⎪⎪ ⎪⎪ 2 ⎪ v 1⎛ v ⎞ = ⎨⎪⎪−I SS D 1 − ⎜⎜ D ⎟⎟⎟ ⎪⎪ VOVD 4 ⎜⎝VOVD ⎠⎟ ⎪⎪ −I SS ⎪⎪ ⎪⎩⎪

⎧⎪ −I SS R0 ⎪⎪ ⎪⎪ ⎪ ⎛ vD ⎞⎟2 v 1 D ⎪ ⎟ 1 − ⎜⎜⎜ vODIFF = ⎪⎨I SS R0 ⎪⎪ 4 ⎝VOVD ⎠⎟⎟ VOVD ⎪⎪ ⎪⎪ I SS R0 ⎪⎩⎪ A graphical representation of (1.31) is

if vD < − 2VOVD if

vD ≤ 2VOVD

if

vD > 2VOVD ,

(1.30)

if vD < − 2VOVD if

vD ≤ 2VOVD

if

vD > 2VOVD .

(1.31)

shown in Fig. 1.29.

vODIFF ISSR0

− 2VOVD 2VOVD

vD

−ISSR0 Figure 1.29. Differential output voltage of a MOS differential pair.

As previously mentioned, each code transition of the flash, two-step subranging or folding and interpolation ADCs occurs when one of the differential pairs preceding the comparators has zero output voltage. If there are no mismatches this occurs for vD = 0 which, as Fig. 1.29 shows, is the most linear part of the transfer function. The gain of the differential pair is

G0 =

∂vODIFF ∂v D

= gm 0R0, vD = 0

(1.32)

where gm0 is the transconductance of the transistors for zero differential input voltage, I (1.33) gm 0 = SS . VOVD


41

This leads to

I SS R0 . (1.34) VOVD The gain is, therefore, the ratio between the output voltage range, ISSR0, and the overdrive voltage of the transistors. The transient behavior is dominated by the pole associated with the output nodes, which originates the response of a first order system, with the time constant G0 =

τ = R0C L , (1.35) where CL includes the drain capacitance of transistors, the input capacitance of the next stage and the parasitic capacitance of the metal connections. The drain capacitance of the MOS transistors is composed by the drain-to-bulk capacitance, CDB, and the gate-to-drain capacitance, CGD. CDB is the depletion capacitance of the pn junction formed by the drain and the substrate, and CGD results from the small overlap existing between the gate and the drain – both are proportional to W [91]. The input capacitance of a differential pair is dominated by the gate-to-source capacitance of the transistors which, in strong inversion, can be approximated by [91] 2 CGS WLC ox . (1.36) 3 Note that CGS is proportional to the gate area, WL. The input voltages applied to a differential pair must remain within certain limits to guarantee its correct operation: too low input voltages make the transistors in the current source enter the triode region, while high input voltages force the transistors of the differential pair into the triode region. It is common to use transistors instead of resistors as loading devices: these can be connected as diodes [24, 84], biased in the triode region [87] or constitute a cross-coupled pair, which uses a positive feedback mechanism to increase the equivalent load resistance [80].

1.6.2

Effect of Mismatches

Two components having the same dimensions and fabricated in the same die, eventually even near each, do not present the same electrical characteristics: for example, two identical resistors have different resistances and two equally sized transistors have different drain currents in the same bias conditions. In this case there is a mismatch between


42

those two identical devices. These differences are of random nature and occur due to variations in the fabrication process. Although several improvements have been proposed in the last few years, the most widely used mismatch model is, currently, the one proposed by Pelgrom et al. in [92] – we will use it through the text. More details about the derivation of this model can be found in [93]. A parameter P that characterizes a given electrical component (resistance, capacitance, threshold voltage, etc.), depends on the local value of n process parameters, h1,...,hn (mobility, oxide thickness, concentration of implanted ions, etc.), (1.37) P = f (h1, h2 ,..., hn ). The difference of the electrical parameters of two similar devices is8 n ∂f (1.38) ΔP = ∑ Δhi , i =1 ∂hi leading to

⎛ ∂f ⎟⎞2 2 ⎜ ⎟⎟ σ (Δhi ). (1.39) σ (ΔP ) = ∑ ⎜ ⎟ ⎜ i =1 ⎝ ∂hi ⎠ In this way, it is possible to characterize the mismatch on the electrical parameters, ΔP, by analyzing the variations on the process parameters, Δhi, which can be of two kinds: 2

n

Small random variations from point to point with a correlation distance much smaller than the dimensions of the component. In a transistor there are several examples that fall in this category: distribution of ions, local mobility fluctuations, oxide granularity and fluctuations on the oxide charges. The small correlation distance implies that no relation exists between the random deviations in two different devices. Random variations with a long correlation distance. These are caused by gradients created during the fabrication process.

Consequently, the process parameters vary randomly from point to point in the area occupied by the component being considered – a function hi(x,y) may be defined. The component is characterized by the average value of hi(x,y), in the region it occupies [92, 93],

8

The correlation between different process parameters is being ignored.


hi =

1 area

∫∫

hi (x , y )dxdy.

43

(1.40)

region occupied by the device

The difference on hi in two identical devices is, therefore, ⎛ ⎟⎟⎞ ⎜⎜ ⎟⎟ 1 ⎜⎜⎜ Δhi = hi (x , y )dxdy − hi (x , y )dxdy ⎟⎟⎟. (1.41) ⎜⎜ ∫∫ ∫∫ ⎟⎟ area ⎜region occupied region occupied ⎟⎟ ⎜⎜ ⎟⎟⎠ ⎜⎝ by device 1 by device 2 For rectangular devices having a width W and a length L, and suffering from the random variations mentioned above, it can be shown [93] that Ah2 (1.42) σ 2 (Δhi ) = i + Sh2i Dx2 , WL where Ahi is the area proportionality constant and Shi describes the variation of hi with the distance between the devices, Dx. The variance of the electrical parameter, P, can be obtained substituting (1.42) in (1.39), which leads to an expression similar to the one found for process parameters, (1.42), AP2 (1.43) + SP2 Dx2 . WL Constants AP and SP must be obtained for a given process.9 If the two devices are near each other (Dx small), (1.43) can be approximated by σ 2 (ΔP ) =

AP2 , (1.44) WL which corresponds to neglect the random variation with long correlation distance (gradients). This leads to the conclusion that the matching of the components depends primarily on their area. For the resistors and capacitors it is common to specify σ 2 (ΔP )

⎛ ΔR ⎟⎞ AR2 , σ 2 ⎜⎜⎜ ⎟⎟ = ⎝ R ⎠ WRLR

9

(1.45)

AP and SP depend on the matching constants associated with each process parameter, Ahi and

Shi . In practice, AP and SP are calculated directly: for example, the matching constant associated to the resistors, AR, is obtained by measuring the resistances of a large number of resistors (electrical parameter), and not by making a statistical characterization of the variations on the process parameters, like the thickness of the conducting polysilicon layer and the concentration of implanted ions on it.


44

⎛ ΔC ⎟⎞ AC2 , (1.46) = σ 2 ⎜⎜⎜ ⎟ ⎝ C ⎟⎠ WC LC where WR, LR and WC, LC are the sizes of the devices, and AR and AC are the matching constants that are specific for a given technology. Equation (1.24) indicates that there are two parameters that characterize the operation of the transistor: Vt and β. According to [92], σ (ΔVt ) = 2

AV2t

(1.47) WL ⎛ Δβ ⎞⎟ Aβ2 , (1.48) σ 2 ⎜⎜ ⎟= ⎜⎝ β ⎠⎟⎟ WL where W and L are the gate sizes and AVt and Aβ are the matching parameters, specific for each technology. Although Vt and β have common process parameter dependencies, the experimental data suggests a low correlation between ΔVt and Δβ [92]; they can, thus, be considered independent random variables. It can be shown that AVt is proportional to oxide thickness [94] which explains the fact that this parameter decreases as technology scales down [28]. Aβ , on the other hand, has remained almost unchanged [28]. The effect of mismatches in the MOS differential pair represented in Fig. 1.30, will now be considered. These mismatches shift the zero crossing of the differential pair: it will have a zero output voltage for vD = VOS. The offset voltage (VOS) is obtained dividing the output voltage found when vD = 0, by the DC gain, given by (1.32), vODIFF

vD = 0

. (1.49) G0 Let us now calculate the VOS caused by each mismatch. For the Vt mismatch, and considering the situation at vD = 0, equations (1.26)– (1.29) can be re-written as VOS = −

iDP

iDN

β = 2

2 ⎡ ⎛ ΔVt ⎟⎞⎤ ⎜ ⎢vGSP − ⎜Vt + ⎟⎥ , ⎜⎝ ⎢⎣ 2 ⎟⎠⎥⎦

2 ⎛ ΔVt ⎞⎟⎤ β⎡ ⎜ ⎢ ⎥ = vGSN − ⎜⎜Vt − ⎟ , ⎝ 2 ⎢⎣ 2 ⎠⎟⎥⎦ iDP + iDN = I SS , vGSP = vGSN .

(1.50) (1.51) (1.52) (1.53)


45

VDD R0−ΔR0/2

R0+ΔR0/2 iDN

Vt−ΔVt/2

iDP vOP

vON

β −Δβ /2

vIP MN

vD

MP

vIN

Vt+ΔVt/2

ISS

β +Δβ /2

Figure 1.30. MOS differential pair with mismatches.

Solving (1.50)–(1.53) simultaneously and considering that ΔVt Vt, I SS leads to a differential output voltage of ΔVt . Applying (1.49) VOVD yields the offset voltage due to the Vt mismatch, (1.54) VOS ΔV = −ΔVt . t Similar calculations give to the offset voltage due to mismatches in β, VOVD Δβ . (1.55) 2 β The differential output voltage when there are mismatches in the VOS

load resistors is –

I SS 2

Δβ / β

=

Δ R 0; applying (1.49) leads to

VOVD ΔR0 . 2 R0 The overall offset voltage is, thus, ⎛ Δβ ΔR0 ⎟⎞ V ⎟, VOS = −ΔVt + OVD ⎜⎜⎜ + 2 ⎝ β R ⎟⎟⎠ VOS

ΔR0 / R0

and its variance is given by

=

0

(1.56)

(1.57)


46

2 ⎡ ⎛ Δβ ⎞ ⎛ ⎞⎤ VOVD ⎟ + σ 2 ⎜⎜ ΔR0 ⎟⎟. ⎢σ 2 ⎜⎜ (1.58) ⎟ ⎟ ⎜⎝ R0 ⎟⎠ 4 ⎢⎢⎣ ⎜⎝ β ⎟⎠⎟ ⎦ The application of (1.45), (1.47) and (1.48) in (1.58) leads to the standard deviation of the offset voltage, as a function of the component sizes and bias conditions,

σ 2 (VOS ) = σ 2 (ΔVt ) +

σ (VOS ) =

2 VOVD Aβ2 AR2 V2 4 . + OVD WL 4 WRLR

AV2t +

(1.59)

Considering WL = WRLR = 5 μm2, VOVD = 0.2 V, AV = 8 mV.μm, t Aβ = 2%.μm and AR = 2.5%.μm, yields σ(VOS) = 3.85 mV. The evaluation of (1.59) considering each mismatch separately indicates their relative importance, AVt (1.60) σ (VOS )ΔV = = 3.56 mV, t WL Aβ V (1.61) σ (VOS )Δβ / β = OVD = 0.89 mV, 2 WL AR V (1.62) σ (VOS )ΔR / R = OVD = 1.11 mV . 0 0 2 WR LR The most important contribution to the offset voltage is, by far, from the Vt mismatch. If lower offset voltages are needed, the area of the components must be increased, making the circuit slower due the larger parasitic capacitances. Several techniques are employed to obtain low offset voltages with small devices: averaging, that is studied in chapters 2 and 3, and offset cancellation methods, described in chapter 5.

1.6.3

CMOS Folding Circuit

There are several circuits with the transfer function depicted in Fig. 1.16; an analysis of the most relevant can be found in [95–97]. Figure 1.31 shows the folding circuit most commonly used in CMOS technologies: it is composed by FF differential pairs, each subtracting the input from one reference voltages. In this way each differential pair defines the location of one zero crossing. The operation of the circuit can be easily understood if one considers the transfer function of each differential pair, and notes that (1.63) iON = iD 1 + iD 4 + iD 5 + iD 8 + iD 9


47

iOP = iD 2 + iD 3 + iD 6 + iD 7 + iD 10.

(1.64)

VDD R0

iON

iOP

vON iD1

iD2

vI

iD3

iD4

V1 vI

iD5

iD6

V2 vI

ISS

iD7

iD8

V3 vI

ISS

R0 vOP iD10

iD9

V5

V4 vI

ISS

ISS

ISS

iD2

ISS

iD1

0

iD4

ISS

iD3

0

iD6

ISS

iD5

0

iD8

ISS

iD7

0

iD10

ISS

iD9

0

vON ISSR0

VDD−5/2ISSR0 vOP V2

V1

V3

V4

V5

vI

ΔVF

Figure 1.31. Folding circuit commonly used in CMOS ADCs (FF = 5).

The spacing between consecutive zero crossings of a folding circuit, ΔVF, is the difference between two successive reference voltages. If an


48

even FF is required, an extra current source must be connected to one of the outputs, to balance the output voltages. In Fig. 1.31 it was assumed that when the input signal equals the reference voltage of a certain differential pair, all the others are completely unbalanced. Figure 1.32 shows the situation at vI = V1, which is the zero crossing defined by the first differential pair; it is considered that all the other differential pairs, except the second, are completely unbalanced. VDD R0

iOP = 5/2ISS+ΔI

iON = 5/2ISS−ΔI

vON ISS/2

ISS/2

vI

ΔI

ISS−ΔI

V1 v I ISS

0

V2 vI ISS

0

ISS V3 vI ISS

0

ISS

R0 vOP ISS

V4 vI ISS

V5 ISS

Figure 1.32. Situation at the first zero crossing (vI = V1), considering that the second differential pair is still not completely unbalanced.

Instead of a zero differential output voltage, in this situation we have (1.65) vODIFF = vOP − vON = −2R0ΔI . There is, thus, a systematic zero crossing deviation that would be avoided if all the differential pairs, except the one defining the zero crossing, were completely unbalanced. This occurs by guaranteeing that (1.66) 2VOVD < ΔVF . When condition (1.66) is not met, the W/L of the differential pair transistors must be made larger, to decrease VOVD. However W/L cannot be increased indefinitely.10 Figure 1.33 represents the same folding circuit of Fig. 1.32, but now at vI = V2: in this situation there is no systematic deviation. In fact, this kind of deviations only occur in the two extremity zero crossings (in our example, the ones corresponding to reference voltages V1 and 10

When W/L increases the transistors will eventually come out of the strong inversion towards moderate and then weak inversion; in that case (1.24) is no longer valid, and the differential pairs no longer saturate for 2VOVD . Decreasing the input voltage that makes the differential pairs saturate by increasing W/L becomes more and more difficult, as one goes towards moderate and weak inversion.


49

V5). Thus, if condition (1.66) can not be met, a way to solve this issue is to add two dummy differential pairs, one with a reference voltage below V1 and the other with a reference voltage above V5 [95, 97]. However, this increases the total number of differential pairs and reference voltages to generate, having impact on the power dissipation, area and input capacitance of the folding stage. Another possible solution is to add pre-amplifiers (simple differential pairs) before the folding stage [78]. Considering that the gain of those pre-amplifiers is GPA, condition (1.66) is relaxed, (1.67) 2VOVD < GPAΔVF . For a certain VFS, this issue sets an upper bound to the folding factor that may be implemented. VDD R0

iOP = 5/2ISS

iON = 5/2ISS

vON ISS−ΔI

ΔI

vI

ISS/2

V1 vI ISS

ΔI

ISS/2

ISS−ΔI

V2 vI ISS

0

V3 vI ISS

0

ISS

R0 vOP ISS

V4 vI ISS

V5 ISS

Figure 1.33. Situation at the second zero crossing (vI = V2), considering that the first and third differential pairs are still not completely unbalanced.

In a flash ADC the offset voltage and the gain of the pre-amplifiers are very important parameters. Although folding circuits have a much more nonlinear transfer function, these parameters can still be defined near each zero crossing, where the circuit is approximately linear:

The DC gain of a folding circuit, G0, is the derivative of the output voltage with respect to the input voltage, calculated at a zero crossing, G0 =

∂vODIFF ∂vI

. The gain is positive or negvI =Vk

ative depending on the zero crossing. The offset voltage is the difference between the ideal and the real location of a zero crossing. This parameter is associated to each zero, and a folding circuit is characterized by the (different) offset voltages of its FF zeros.


50

It was shown that to avoid systematic deviations, all differential pairs except the one defining the zero being considered, must be completely unbalanced. In this way, the gain of the circuit is determined only by that differential pair, G0 = gm0R0. (1.68) The gain is lower if, at a zero crossing, there are more differential pairs not completely unbalanced. The output common-mode voltage is v + vON F (1.69) VCMo = OP = VDD − F I SS R0, 2 2 which decreases with FF. This fact limits the usable FF because the transistors enter the into triode region if the output voltages become too low. This problem can be eased by connecting current sources in parallel with the resistors, as represented in Fig. 1.34. VDD R0

iON

IDD

IDD

iOP

R0

vON

vOP

vI

V1 vI ISS

V2 vI ISS

V3 vI ISS

V4 vI ISS

V5 ISS

Figure 1.34. Utilization of current sources to increase the output common-mode voltage.

In this case, the output common-mode voltage becomes ⎛F ⎞ (1.70) VCMo = VDD − ⎜⎜ F I SS − I DD ⎟⎟⎟ R0. ⎝ 2 ⎠ The load capacitance also rises with FF, due to the increasing number of differential pairs connected to the output nodes. The use of cascode transistors [82], or transimpedance amplifiers [77], which isolate the output nodes from the drains of the transistors in the differential pairs, improves the transient response but are difficult to implement with low supply voltages. To calculate the offset voltages of the folding circuits, the zero crossings where its gain circuit is positive (V1, V3 and V5 in Fig. 1.31) must be distinguished from those where the gain is negative (V2 and V4 in Fig. 1.31). The first case is presented in Fig. 1.35, where IFN and IFP


51

are the currents of the remaining differential pairs, which are assumed to be completely unbalanced. The offset voltage is given by [96, 97] ⎪⎧⎛ Δβ ⎟⎞ V ΔR0 + VOS [k ] = −ΔVt [k ] + OVD ⎪⎨⎜⎜ ⎟ [k ] + FF 2 ⎪⎪⎩⎜⎝ β ⎠⎟⎟ R0 FF ⎫ ⎡k −1 ⎛ ΔI ⎞ ⎛ ΔI ⎞ ⎤ ⎪ ⎪ + 2 ⎢⎢ ∑ (−1)i +1 ⎜⎜⎜ SS ⎟⎟⎟ [i ] + ∑ (−1)i ⎜⎜⎜ SS ⎟⎟⎟ [i ]⎥⎪ . (1.71) ⎥⎬ ⎟ ⎟ I I ⎝ SS ⎠ ⎝ SS ⎠ ⎥⎦ ⎪ ⎢⎣ i =1 ⎪ i =k +1 ⎪ ⎭ VDD R0−ΔR0/2

R0+ΔR0/2 iON

iOP

vON

vOP

IFN

IFP vI

Vt−ΔVt[k]/2

β −Δβ [k]/2

Vk Vt+ΔVt[k]/2 ISS+ΔISS[k]

β +Δβ [k]/2

Figure 1.35. Mismatches in a folding circuit – zero crossing where there is a positive gain (k odd).

In the case represented in Fig. 1.36 the gain is negative; the contribution of each mismatch to the offset voltage is equal in absolute value, but has the opposite signal: ⎧⎪⎛ Δβ ⎞ V ⎟⎟ [k ] + F ΔR0 VOS [k ] = ΔVt [k ] − OVD ⎪⎨⎜⎜ F ⎟ ⎟ ⎜ ⎪ 2 ⎪⎩⎝ β ⎠ R0 FF ⎡k −1 ⎛ ΔI ⎞ ⎛ ΔI ⎞ ⎤ (1.72) + 2 ⎢⎢ ∑ (−1)i +1 ⎜⎜ SS ⎟⎟⎟ [i ] + ∑ (−1)i ⎜⎜ SS ⎟⎟⎟ [i ]⎥⎥ . ⎜⎝ I SS ⎟⎠ ⎜⎝ I SS ⎟⎠ ⎥ ⎢⎣ i =1 i =k +1 ⎦


52

VDD R0−ΔR0/2

R0+ΔR0/2 iON

iOP

vON

vOP

IFN

IFP vI

Vk

Vt−ΔVt[k]/2

β −Δβ [k]/2

Vt+ΔVt[k]/2 ISS+ΔISS[k]

β +Δβ [k]/2

Figure 1.36. Mismatches in a folding circuit – zero crossing where there is a negative gain (k even).

Comparing the offset voltages of a folding circuit, given by (1.71) and (1.72), with the one of a single differential pair (1.57), leads to the following conclusions:

The mismatches in Vt and β cause a similar offset voltage,11 but a mismatch between the load resistors is FF times worst. There is a new source of offset – the mismatches between the tail currents of the differential pairs.

The offset voltages of the various zeros of a folding circuit are not completely independent random variables – they all have identical contributions from the mismatch between the load resistors and between the tail currents. The variance of the offset voltages is σ 2 (VOS ) = σ 2 (ΔVt ) +

11

2 VOVD 4

⎡ ⎛ Δβ ⎞ ⎛ ⎞ ⎛ ⎞⎤ 2 2 ⎜ ΔR0 ⎟ 2 ⎜ ΔI SS ⎟ ⎟ ⎢σ 2 ⎜⎜ ⎟⎟⎥⎥ . (1.73) ⎢ ⎝⎜ β ⎠⎟⎟⎟ + FF σ ⎜⎜⎜ R ⎟⎟⎟ + 4 (FF − 1) σ ⎜⎜⎜ I ⎟ ⎝ ⎠ ⎝ ⎠ SS ⎦⎥ 0 ⎣⎢

If there are other non-saturated differential pairs, in addition to the one defining the zero being considered, the offset voltage expression must also include the contribution from their Vt and β mismatches.


53

Equation (1.73) will now be evaluated, using the example of section 1.6.1 (WL = WRLR = 5 μm2, VOVD = 0.2 V, AV = 8 mV.μm, t

Aβ = 2%.μm and AR = 2.5%.μm), and considering FF = 5. This allows to compare the offset voltage of a folding circuit with the one found in a simple differential pair. In what concerns the current sources, it can be shown that [98], ⎡ ⎛ AV ⎞⎟2 ⎤⎥ ⎛ ⎞ 1 ⎢ 2 2 ⎜ ΔI SS ⎟ ⎜ t ⎟⎟ ⎥ , ⎟ (1.74) A + 4 ⎜⎜ σ ⎜ = ⎜⎝ I SS ⎟⎟⎠ 2WCS LCS ⎢⎢ β ⎝⎜VOVDcs ⎠⎟ ⎥ ⎣ ⎦ where WCS and LCS are the sizes of the current source transistor and VOVDcs is its overdrive voltage. Considering WCSLCS = 30 μm2 and ⎛ ΔI ⎞ VOVDcs = 0.3 V, yields σ ⎜⎜⎜ SS ⎟⎟⎟ = 0.735% . The contribution of each ⎝ ISS ⎟⎠ mismatch to the offset voltage is: σ (VOS )ΔV =

AVt

= 3.56 mV, WL Aβ V σ (VOS )Δβ / β = OVD = 0.89 mV, 2 WL AR V σ (VOS )ΔR / R = FF OVD = 5.59 mV, 0 0 2 WR LR

(1.75)

t

σ (VOS )ΔI

SS

/ I SS

= FF − 1

VOVD 2WCS LCS

(1.76) (1.77)

⎛ AV ⎞⎟2 t Aβ2 + 4 ⎜⎜⎜ ⎟⎟ = 2.94 mV . (1.78) ⎜⎝VOVDcs ⎠⎟

This leads to a total value of σ (VOS ) = 7.31 mV, which is significantly larger than the one obtained for the simple differential pair, in section 1.6.1. The main contributors for this increase are the mismatches in the load resistors and in the tail currents. So, although the pre-amplifiers of a flash ADC can be substituted by folding circuits – which gather zero crossings in the same signal thus reducing the number of comparators – for the same component sizes the folding circuits present larger offset voltages. Furthermore their bandwidth is smaller due to the extra capacitance introduced by having several differential pairs connected to the output nodes, instead of just a single one.


54

1.6.4

Latched Comparators

As seen in previous sections, the latched comparator works synchronously with the clock signal and indicates, through its digital output level, whether its differential input signal is positive or negative. There is a large variety of CMOS comparators, which may be classified in three categories: static, class AB and dynamic [3, 4]. The fact that dynamic comparators are the most power efficient, lead to the selection a comparator of this kind – the one represented in Fig. 1.37 (adapted from [99]) – for the ADC prototypes described in chapters 4 and 5. This comparator will now be considered to illustrate the operation and tradeoffs usually encountered in the design of these circuits. VDD

M5a

M3a

latch

M4a

latch

vON

vOP M4b

M2a

M2b vDN

vIP

M3b

M1a

latch

M5b

vDP M1b

vIN

M6

Figure 1.37. Dynamic latched comparator.

When latch is low (reset phase), the transistors M4a/M4b and M5a/M5b reset the output nodes and the drains of the differential pair (M1a/M1b) to VDD. M6 is off and no supply current exists. When latch goes high the reset transistors are switched off, and current starts flowing in M6 and in the differential pair: vDN and vDP decrease because the parasitic capacitances at those nodes are discharged by the currents flowing in M1a/M1b. When vDN/vDP become smaller than VDD − Vt, transistors M2a/M2b turn on and their drain currents start discharging the parasitic capacitances of the output nodes. Then, as shown in Fig. 1.38, both output voltages decrease.


Regeneration phase

55

Reset phase

VDD vOP VDD−Vt

vON 0 t M3a/M3b turn on M2a/M2b turn on Figure 1.38. Output voltages of the latched comparator.

Let us now assume that the input voltage is positive: in this case, the drain current of M2a is larger than the one flowing in M2b, thus decreasing vON faster than vOP. This, in turn, makes the gate-to-source voltage of M2a (vGS2a) increase faster than vGS2b, which further enlarges the difference between the currents in these transistors – there is a positive feedback mechanism. When the output voltages become lower than VDD − Vt, the transistors M3a/M3b turn on, accelerating the regeneration process and making vOP return to VDD. Thus, after regeneration is completed one of the output nodes is at VDD; the other output and both drains of the differential pair have a 0 V potential. In this situation, there is no supply current, which maximizes power efficiency. In this way, after the latch signal goes high the output voltages take some time to reach digital levels – regeneration time. The simplified case represented in Fig. 1.39(a) is considered, to analyze how this parameter depends on the transistor sizes. The situation in the beginning of the regeneration phase can be studied with the small signal equivalent circuit shown in Fig. 1.39(b),12 where 12

This model is only valid for low differential output voltages, because when vOP and vON get near VDD or GND the transistors enter either the triode or the cutoff region. As will be shown, the regeneration time is larger when there is a small differential output voltage in the beginning of the regeneration phase. This model is, therefore, perfectly adequate.


56

gm = gmp + gmn

(1.79)

C a = C L + C DBp + C DBn + CGSp + CGSn

(1.80)

Cb = 2 (CGDp + CGDn ).

(1.81)

CGSp CDBp

CGSp

MP

CGDp

CGDp

MP

CDBp

Cb

vop

von

vOP

CL CDBn

MN

vON

CGDn

CGDn CGSn

CGSn

MN CDBn

CL

gmvon

Ca

Ca

gmvop

(b)

(a)

Figure 1.39. Cross-coupled CMOS inverters: (a) circuit; (b) small signal model.

Analyzing Fig. 1.39(b) leads to (vodiff[t] = vop[t]−von[t]) dvodiff [t ]

gm vodiff [t ] = 0. dt 2Cb + C a Considering an initial differential output voltage of vodiff[t = 0] = ΔVi, yields −

t τreg

vodiff [t ] = ΔVie , where the regeneration time constant is τreg =

(1.82) (1.83)

(1.84)

C L + (C DBp + CGSp + 2CGDp ) + (C DBn + CGSn + 2CGDn ) 2Cb + C a = . (1.85) gm gmp + gmn

The transistors should be sized to minimize τreg, so that the output voltages reach digital levels quickly. Note that:

Increasing the length of the transistors decreases their transconductance and enlarges their CGS. Thus, all devices should have the minimum length (L = Lmin).

The parasitic capacitances of a transistor are proportional to W.

For a given current,13 the transconductance is proportional to W .


57

The regeneration time constant can, therefore, be written as C + kCPWP + kCNWN τreg = L (1.86) kGP WP + kGN WN where kCP, kCN, kGP and kGN are the proportionality constants. If the load capacitance is much larger than the parasitic capacitances of the transistors, τreg is approximated by CL . (1.87) kGP WP + kGN WN In this situation it is desirable to increase WP and WN in order to reduce τreg. If the parasitic capacitances of the transistors dominate, kCPWP + kCNWN τreg , (1.88) kGP WP + kGN WN and the regeneration transistors should be as small as possible, since increasing WP and WN will increase τreg. Thus, for a certain CL, τreg can be minimized by properly choosing WP and WN. In fact, τreg presents a minimum for CL 1 (1.89) WPopt = 2 kCP kCP kGN 2 +1 kCN kGP τreg

CL . (1.90) 2 kCN kCN kGP +1 2 kCP kGN Usually CL is small, resulting in low values for WPopt and WNopt. Equation (1.84) indicates that the regeneration time depends on ΔVi and, therefore, on the differential input voltage of the comparator (vIP − vIN): as it decreases, the regeneration time goes towards ∞ (metastability). In practice the random electrical noise makes the comparator decide in a finite amount of time. The most relevant contributors to the offset voltage of the comparator represented in Fig. 1.37 are the mismatches between transistors M1a/M1b and M2a/M2b. If a low offset is required, large devices must be WNopt =

13

1

We are considering Fig. 1.39 as a simplified model of the circuit shown in Fig. 1.37, where the currents that flow in the cross-coupled inverters (M2a, M2b, M3a, M3b) are set by the transistors beneath them (M6, M1a, M1b). So the drain currents of the transistors that perform regeneration do not depend (significantly) of their width, and are assumed constant in the following analysis.


58

used, introducing significant parasitic capacitances. This increases power dissipation and limits the regeneration speed.14 The nodes where the drains of M1a/M1b connect have rail-to-rail excursion. As represented in Fig. 1.40, those large voltage variations are coupled, through the parasitic capacitances of these transistors, to the input of the comparator. Since the circuit preceding it does not have zero output impedance, this disturbs the input voltage and may degrade the accuracy of the converter. This input voltage disturbance is called kickback noise. M5a

latch

latch

M2a

M5b

M2b

Thévenin equivalent of preceding circuit + -

M1a

latch

M1b

M6

Figure 1.40. Kickback noise due to capacitive coupling, in the comparator represented in Fig. 1.37.

In this comparator there is another kickback noise source: the variation of the operating region of the differential pair transistors. In the reset phase there is no current flowing and M1a/M1b are in cutoff. In the beginning of the regeneration phase current starts flowing and their vDS is large: these transistors are, therefore, in saturation. Then, as the voltages at their drains approach 0, they will enter the triode region. These operating region changes are accompanied by variations in their gate charge, thereby causing input voltage variations. The most common solution to reduce kickback noise is to add a preamplifier before the comparator [11, 39]; reference [130] utilizes source

14

Since minimum length devices are used, the offset specification determines the width of the transistors. If a low offset is required, the width of M2a/M2b is most probably larger than the value that minimizes τreg.


59

followers. This, although effective, introduces static consumption reducing the power efficiency. References [129, 132] present comparators where the drains of the input differential pair are isolated from the regeneration nodes using switches that are opened when regeneration starts. This inhibits current flow in the differential pair transistors, which go into the triode region; furthermore the voltages at their drains still vary considerably, originating kickback noise. In [129] a pre-amplifier is still used. MOS switches can be inserted at the inputs of the comparator, and opened during the regeneration phase [86]. This performs a sampling function and isolates the input nodes, thereby eliminating the kickback noise during that phase. However, the input voltages are still disturbed when the sampling switches close, because the input voltage being applied differs, in general, from the previously sampled voltage. Finally, a neutralization technique [91] is used in [133, 134], which only accomplishes moderate improvements [3, 4]. So existing techniques either increase considerably the power dissipation or cannot achieve a truly effective kickback noise reduction. The authors have proposed two new techniques in [3, 4] that practically eliminate the kickback noise, with only a minor impact in power dissipation. One of those techniques is particularly suited to class AB comparators, and since those are not used in the prototypes described in this book, it will not be described here. The other technique can be used in any latched comparator, being specially suited to the cases where the circuit preceding it is in reset during the regeneration phase of the comparator. Two modifications to the comparator are required:

1. Insert sampling switches before the differential pair, which are opened during the regeneration phase. The kickback noise is eliminated in this phase, and a sampling function is implemented, which may be convenient in some applications. This has the downside of increasing the offset voltage, due to the mismatches in the charge injection of the input switches15 that are added. 2. Detect when the latched comparator has already decided and make an asynchronous reset of the sampled input voltage. This prevents the previous sampled voltage from disturbing the next comparison.

15

It may be shown that this contribution is minimized by decreasing the size of the switches.


60

Figure 1.41 exemplifies the application of this technique. The latched comparator regenerates in ph1. Two inverters buffer its outputs and a SR latch memorizes the comparison result. It is assumed that, in the reset phase, the outputs of the latched comparator go to VDD, as in the one of Fig. 1.37. This is a typical arrangement [24, 77, 79, 129, 131]. vIP vIN

M3

M1 M2 ph2

M4

B

ph1 ph2

ph1

S

Q

R

Q

VDD

ph2

M8

A

M7

M6

M5

Figure 1.41. Application of kickback noise reduction technique (© 2006 by IEEE).

The transistors that implement the kickback reduction are inside the shaded area. In the reset phase (ph1 = latch = low, ph2 = high) the input switches, M1/M2, are on. Node A is pushed to VDD by M8, turning off the input reset transistors, M3/M4. The outputs of the latched comparator are at VDD, which means that M5 and M6 are off; M7 is also off because node B is low. At the end of ph2 M1/M2 turn off, therefore preventing any kickback noise during the regeneration process. M8 is then also turned off, leaving node A near VDD. Some time after ph1 changes to high (regeneration phase), the output voltages of the comparator reach full-scale levels, forcing one of the SR latch inputs to VDD, and turning either M5 or M6 on. This pushes nodes A to low and B to high, which turns on M3/M4 and resets the sampled input voltage. This can be done because the latched comparator has already decided. In this way, any influence from previously sampled input voltages is eliminated. Transistor M7 ensures that M3/M4 are maintained on in the non-overlap time between the end of ph1 and the beginning of ph2; this guarantees that the reset of the sampling nodes only ends when ph2 goes high, and M1/M2 turn on. Simulations using the comparator of Fig. 1.37 in a 0.18 μm technology will now be presented to demonstrate the effectiveness of this


61

technique. Figure 1.42 shows the circuit used to evaluate the kickback noise, where the stage preceding the comparators is modeled by its Thévenin equivalent (RTH = 8 kΩ). RTH/2 + -

(a)

(b),(c)

RTH/2

Figure 1.42. Circuit used to evaluate the kickback noise (© 2006 by IEEE).

The simulation results are shown in Fig. 1.43. Curve (a) is the voltage at the terminals of the Thévenin equivalent voltage source of the preceding stage (see Fig. 1.42 above), which is assumed to be in reset during the regeneration phase of the comparator (ph1); this situation is usual in parallel type converters [24]. 350

(b)

300

(a) (b)

250 Input voltage [mV]

0

200

-0.5

(c)

-1

(b)

150

(c)

(a) 6

10

8

100 50 0

Phases [V]

-50 2

ph2

ph1

0 0

2

4

6

8

10

12

t [ns]

Figure 1.43. Simulation results of the kickback noise reduction technique (© 2006 by IEEE).

Curve (b) is the input voltage, when just the sampling switches (M1 and M2 in Fig. 1.41) are added to the comparator of Fig. 1.3716 – this is the technique used in [86], which eliminates kickback noise in the regeneration phase (ph1 on). However, it creates a large kickback on 16

The results obtained without adding the input sampling switches – i.e. by simply simulating the comparator of Fig. 1.37 – are not shown in order not to complicate Fig. 1.43. In that case there are large input voltage disturbances every time the latch signal of the comparator, in this case ph1, has a transition.

62


the reset phase (ph2 on), due to the charge previously stored in the sampling nodes. In the results shown in Fig. 1.43 the kickback near t = 7.5 ns is so large that the input voltage does not have time to reach negative values (it should get near –1 mV): the comparator makes, in this case, a wrong decision. Finally, curve (c) is obtained with the solution of Fig. 1.41 – the input voltage always goes smoothly to the final values and the kickback noise is eliminated. In this example the reset transistors (M3/M4) have W/L = 1.2/0.18 μm, therefore leaving the input capacitance almost unchanged. When this technique is used the power dissipation increases from 268 to 297 μW (about 10% variation). The extra power dissipation is of dynamic nature, which is desirable in systems where the operating frequency varies [135]. The σ(VOS) of the comparator increases from 1.33 to 1.50 mV, due to the mismatches in the charge injection of the input switches (M1/M2), which have W/L = 0.7/0.18 μm.

1.6.5

Considerations About the Yield

The offset voltages of the pre-amplifiers, folding circuits and latched comparators define the code transition levels of an ADC.17 Since the offset voltage is a random variable, there is always a non-zero probability of having a certain code transition level arbitrarily far from the ideal value. In this way, when defining the maximum INL and DNL it becomes necessary to indicate also the percentage of ADCs which are expected to meet those specifications – the yield. For example one can specify that 95% of the ADCs should have a maximum INL below 1/2 LSB; this is represented by Y(INL < 0.5) = 0.95. The yield specification determines the necessary σ(VOS) which, in turn, sets the area of the components in each constituting block of the converter. An yield near 100% may lead to a very low σ(VOS) requirements, having a very significant impact in its speed, area and power dissipation. One should note that the number of fabricated circuits that are functional and comply with the specifications is ultimately limited by the fabrication yield, which is the percentage of circuits that have not suffered from defects in the fabrication process (mask defects, crystalline defects in the epitaxial layer, etc.). This is usually in the range of 17

The random variations of the reference voltages are being neglected.


63

10–90% and depends on the process complexity and maturity, and on the die size [91]. Therefore, it may actually be useless to specify very high yield values for the INL or DNL. The flash ADC represented in Fig. 1.5 will now be considered. Noting that the mismatches in a pre-amplifier and latched comparator set the offset in the transition from code k − 1 to code k, VOS[k], the INL given by (1.4) can be written as V [k ] (1.91) INL [k ] = OS , VLSB and its standard deviation is σ (INL) =

σ (VOS )

. (1.92) VLSB Let P(INL < ξ) be the probability of having the |INL| of a certain code smaller than ξ LSB – this corresponds to the probability of |VOS[k]| < ξVLSB occurring. Considering that the offset voltage has a normal distribution with 0 mean, results in ξVLSB

1 2πσ (VOS ) −ξ∫ V

P (INL < ξ ) =

−

e

v2 2σ (VOS ) 2

dv .

(1.93)

LSB

Since the offset voltages of different pre-amplifiers and comparators are independent random variables, the probability of having the overall INL of the converter below ξ LSB is Nb −1

Nb −1

2 Y ( INL < ξ ) = ⎡⎣P (INL < ξ )⎤⎦

2 ⎡ ⎤2 ξVLSB − v 2 ⎢ ⎥ 1 2σ (VOS ) =⎢ e dv ⎥ ∫ ⎢ 2πσ (VOS ) ⎥ −ξVLSB ⎢⎣ ⎥⎦

. (1.94)

The value of σ(VOS) that leads to the required yield is obtained by solving (1.94) numerically. Figure 1.44 shows Y(INL < 0.5) as a function of σ(VOS)/VLSB, for a 7 bit flash ADC. For example, to have Y(INL < 0.5) = 90% it is required that σ(VOS)/VLSB = 0.15, and for Y(INL < 0.5) = 99.9% one must have σ(VOS)/VLSB = 0.11. As the area of the components is inversely proportional to σ2(VOS) – see (1.45) to (1.48) – to have a 99.9% yield, the area needs to be about 86% larger than when the yield is 90%.


64

1 0.9 0.8

Y(INL 8 the resultant σ(VOS)pre-amp is smaller than the specified value. 1.8 1.6 1.4

σ(VOS)pre-amp

1.2 1 0.8 0.6 0.4 0.2 0 3.75

4.75

5.75

6.75

7.75

8.75

9.75

10.75

11.75

G0

Figure 3.33. Variation of σ(VOS)pre-amp with G0.

Figure 3.35 shows the required values for R0 and R1 as a function of G0. They have the same overall dependence, because one of the design requirements is R0/R1 = 20. Having R0/R1 fixed, the resistances are mainly determined by settling requirements: as α is fixed the small variations on R0 and R1 are caused by the alterations on the total load capacitance, due to the changes on the required W. Equation (2.32) indicates that, when R0/R1, VR and VSAT (which is proportional to VOVD) remain unchanged, the DC gain is proportional to ISSR0. Since R0 has only small variations, one concludes that ISS must increase almost proportionally to G0. This is indeed what happens, as shown in Fig. 3.36. Finally, to maintain VSAT unchanged while having ISS increasing, the W/L ratio must also increase.8 This was, in fact, observed in Fig. 3.34.

8

According to the quadratic drain current model, VOVD =

I SS V = SAT . W 2 L

μC ox

Chapter 3: Averaging – Transient Analysis and Design

35

3

30

2.5 2

20

L [μm]

W [μm]

25

183

15

1.5 1

10

No limitation on minimum L

0.5

5 0 3.75

4.75

5.75 6.75

7.75 G0

8.75

0 3.75

9.75 10.75 11.75

100

4.75

5.75

6.75

7.75 G0

8.75

9.75 10.75 11.75

4.75

5.75

6.75

7.75 G0

8.75

9.75

35 30

W/L

WL [μm2]

25

10

20 15 10

1 3.75

5

No limitation on minimum L 4.75

5.75

6.75

7.75 G0

8.75

0 3.75

9.75 10.75 11.75

10.75 11.75

20000

1000

18000

900

16000

800

14000

700

12000

600 R1 [Ω]

R0 [Ω]

Figure 3.34. Variation of W, L, WL and W/L with G0.

10000 8000

500 400

6000

300

4000

200 100

2000 0 3.75

4.75

5.75

6.75

7.75 G0

8.75

9.75 10.75 11.75

0 3.75

4.75

5.75

6.75

7.75 G0

Figure 3.35. Variation of R0 and R1 with G0.

8.75

9.75 10.75 11.75


184

200

4

180

3.5

160

3

120

ISSR0 [V]

ISS [μA]

140

100 80

2 1.5

60

1

40

0.5

20 0 3.75

2.5

4.75

5.75

6.75

7.75 G0

8.75

9.75 10.75 11.75

0 3.75

4.75

5.75

6.75

7.75

8.75

9.75

10.75 11.75

G0

Figure 3.36. Variation of ISS and ISSR0 with G0.

To summarize, as G0 is specified to be larger:

The required σ(VOS)pre-amp and, therefore, the transistor area (WL) decreases. ISS increases, having a direct impact on the power dissipation. The W/L ratio increases. The values of R0 and R1 have small variations, which depend on W.

All this is observed for G0 > 4.0. For gain values smaller than 4.0, W/L and ISS increase when G0 becomes smaller. This happens because the required offset voltage is very low, leading to a large WL and, consequently, to the fast increase of W. This, in turn, increases the load capacitance, therefore forcing a smaller R0 (and R1) to maintain the same α. As G0 is proportional to ISSR0, this abrupt decrease on R0 must be accompanied by an increase of ISS which, to maintain VSAT unchanged, forces W/L to increase. The increase on the pre-amplifier gain reduces the input referred offset voltage of the latched comparators. In this way, the offset voltages of the pre-amplifiers may be larger, which allows to use smaller transistors, leading to a lower input capacitance. However, this trades with the power dissipation. The reduction on the input capacitance allows to decrease the power dissipation on the circuit driving the pre-amplifiers (the T/H in the architecture being considered). So, although the input capacitance reduction is accomplished by increasing the power dissipation of the pre-amplifier stage, the overall consumption may still decrease. The


185

power optimization of the ADC should be made with a global perspective. It is not possible to increase G0 indefinitely, since the large ISSR0 values required make the transistors in some differential pairs enter the triode region.

3.5.6

Application Example: Variation of α

Let us now consider the same design requirements of the example in section 3.5.4, except that α varies between 0.75 and 0.99. When α is changed, the required standard deviation of the offset voltage varies according to (3.44); this is represented in Fig. 3.37. 1.4 1.2

σ(V OS)pre-amp

1 0.8 0.6 0.4 0.2 0 0.75

0.80

0.85

0.90

0.95

1.00

α

Figure 3.37. Variation of σ(VOS)pre-amp with α.

One should note that, in our example, α could never be smaller than 0.74 because the input referred offset voltage of the comparator, σ (VOS )comp

, would become larger than the specified σ(VOS)total. αG0 The variation of the transistor sizes is shown in Fig. 3.38. The area of the transistors, WL, decreases due to the increase of the required σ(VOS)pre-amp, shown in Fig. 3.37. Figure 3.39 shows the variation of the required values for R0 and R1 with α.


186

3.5

30

3

25

2.5 L [μ m]

W [μ m]

20 15 10

2 1.5 1

5

0.5

0 0.75

0.80

0.85

0.90

0.95

0 0.75

1.00

0.80

0.85

0.80

0.85

α

90

α

0.90

0.95

1.00

0.90

0.95

1.00

0.95

1.00

25

80 20

70

15

50 W/L

WL [μ m2]

60

40 30 20

10

5

10 0 0.75

0.80

0.85

0.90

0.95

0 0.75

1.00

α

α

Figure 3.38. Variation of W, L, WL and W/L with α.

1400

30000

1200

25000

1000 R1 [Ω]

R0 [Ω]

20000 15000 10000

600 400

5000 0 0.75

800

200

0.80

0.85

0.90

0.95

1.00

0 0.75

0.80

0.85

α

0.90 α

Figure 3.39. Variation of R0 and R1 with α.

As α increases the transient response must be faster, which forces the resistances to be smaller: this is clearly observed for α > 0.8. As seen in Fig. 3.38, when 0.75 < α < 0.8 there is a significant decrease on the W, which reduces the load capacitance. Thus, in this case, the resistors do not need to be significantly decreased.


187

Figure 3.40 shows the dependence of the required values of ISS and ISSR0 with α. According to (2.32) since G0, VR, VSAT and R0/R1 are not changed, the value of ISSR0 remains (almost) unchanged.9 For this to happen, ISS must increase to compensate for the reduction of R0. 180

1.6

160

1.4

140

1.2 ISSR0 [V]

ISS [μA]

120 100 80 60

1 0.8 0.6

40

0.4

20

0.2

0 0.75

0.80

0.85

0.90

0.95

α

1.00

0 0.75

0.80

0.85

0.90

0.95

1.00

α

Figure 3.40. Variation of ISS and ISSR0 with α.

Just as in the previous section the W/L ratio must become larger, to maintain VSAT unchanged while ISS increases. This is, in fact, observed in Fig. 3.38. To summarize, when the required α increases:

The σ(VOS)pre-amp value and, therefore, the transistor area (WL) decreases The values of R0 and R1 decrease

ISS increases, having a direct impact on the power dissipation

The W/L ratio increases

Adjusting the settling speed of the pre-amplifiers impacts the input capacitance and the power dissipation: there is, again, a tradeoff between these two parameters.

3.5.7

Application Example: Variation of N

In this section the same design requirements of the example presented in section 3.5.4 are considered, except that N is varied between 7 and 25. As seen in chapter 2, the increase of N leads the reduction of the standard deviation of the offset voltage, with respect to the value 9

ISSR0 would be unchanged if the drain current of the transistors followed the quadratic model exactly.


188

found in the absence of averaging. At that chapter N was adjusted by maintaining VOVD (the transistor sizes and tail current value were fixed) and varying VR. Now VR is set by the architecture parameters, therefore taking a fixed value; N is varied by changing VSAT (which is proportional to VOVD), as shown in Fig. 3.41. This is the usual case in the design of data converters, since the full-scale input range is usually fixed, and only the biasing conditions of the transistors can be adjusted. 0.9 0.8 0.7

VSAT [V]

0.6 0.5 0.4 0.3 0.2 0.1 0 6

11

16 N

21

26

Figure 3.41. Variation of VSAT with N.

The variation of the transistor dimensions is shown in Fig. 3.42. The required transistor area first decreases with N but, for N > 15 it starts increasing. To clarify this behavior it is indicated, in the same figure, the required transistor area if there were only mismatches in Vt, and if there were only β mismatches. When N increases, the required area concerning Vt mismatches decreases but, when only β mismatches are considered, the required area gets larger. The total area is the sum of these two values. When averaging is not used, the σ(VOS) due to mismatches in β increases proportionally to VOVD, as indicated by (1.58). When averaging is employed, the increase of N reduces σ(VOS) with respect to the value found in the absence of averaging, but this value is increasing with VOVD – the later effect is stronger. Note that Fig. 2.15 shows the σ(VOS)Δβ/β decreasing with N, but in that case VOVD was maintained constant and N was varied by adjusting VR. The overall gate area variation is not very large.


18

189

1.4

16

1.2

14 1

10

L [μ m]

W [μ m]

12

8 6

0.8 0.6 0.4

4 0.2

2 0

6

11

16

21

0

26

6

11

16 N

6

11

16 N

N 9

30

7

Total required area

6

25

5

W/L

WL [μ m2]

26

35

8

4 Required area when Required area 3 there are only Vt when there are only mismatches β mismatches 2

20 15 10 5

1 0

21

6

11

16 N

21

26

0

21

26

Figure 3.42. Variation of W, L, WL and W/L with N.

Having the R0/R1 ratio fixed, the resistances are determined by settling related issues. Since α is fixed, the variations on R0 and R1 depend on: 1. The variations on the total load capacitance, caused by the alterations on the required W. Examining Fig. 3.42 leads to the conclusion that as N increases, the load capacitance becomes smaller and, thus, the resistances may be larger. 2. The value of N; when it increases there are more differential pairs farther from the one being considered that have relevant contributions. Therefore the resistances must decrease to allow a faster propagation of those contributions, through the averaging network.

Figure 3.43 shows that both these effects influence R0 and R1, although the second one is more relevant for most values of N. The overall resistance variations are small.


19000

940

18500

920

18000

900

17500

R1 [Ω]

R0 [Ω]

190

17000

880 860 840

16500

820

16000 15500

800 6

11

16

21

780

26

6

11

N

16

21

26

N

Figure 3.43. Variation of R0 and R1 with N.

In the absence of averaging, to maintain the gain while VOVD increases, one must enlarge ISSR0 as (1.34) indicates. With averaging the situation is more complex (see (2.32)), but the same overall behavior is found, as seen in Fig. 3.44 (note that N is proportional to VSAT and, therefore, to VOVD). 3.5

200 180

3

160

2.5

120

ISSR0 [V]

ISS [μA]

140

100 80 60

2 1.5 1

40 0.5

20 0 6

11

16 N

21

26

0

6

11

16 N

21

26

Figure 3.44. Variation of ISS and ISSR0 with N.

To increase VSAT, the tail current must become larger and W/L must be reduced. To summarize, as N increases:

The required transistor area (WL) has small variations (in this case), and presents a minimum for a certain value of N. This minimum occurs because as N gets larger, the required area concerning Vt mismatches decreases, but the area concerning β mismatches increases. This behavior is due to the fact that σ(VOS) is reduced with respect to the value found in the absence of averaging but, in what concerns the contribution from β mis-


191

matches, that value is increasing with VOVD (see (1.58)), and the averaging effect does not overcome that increase. The values of R0 and R1 are determined from two effects: the variation of the load capacitance and the propagation time of the contributions of the differential pairs through the averaging network. In the example just presented this second effect is more relevant, and makes the resistances decrease as N becomes larger. The overall resistance variations are small. To increase N by enlarging VSAT, ISS must become larger and W/L must be reduced.

It can be concluded that the transistor gate area may be minimized by adjusting VSAT, possibly with a cost on power dissipation. Note that the optimum N may, for a certain R0/R1, lead to a ISSR0 value that forces the transistors in some differential pairs into the triode region. In that case a non-optimum N must be used.

3.5.8

Application Example: Variation of R0/R1

In this section all the design requirements of the example considered in the section 3.5.4 are maintained, except the resistance ratio, which is varied between 0.25 and 200. When R0/R1 is increased, the averaging effect becomes stronger and, for the same σ(VOS)pre-amp, the required gate area becomes smaller, as shown in Fig. 3.45. Above a certain R0/R1 value (about 20 in this example) there is no significant reduction on the required area. Both W and L are reduced for larger R0/R1. As shown in Fig. 3.46, the resistance ratio is increased by lowering R1 and enlarging R0. Figure 3.47 shows the dependence of the required values for ISS and ISSR0 with R0/R1. The variation of the ISSR0 product can be understood by examining (2.32): VSAT (and, therefore, VOVD) remains unchanged in this example and the g[R0/R1,VOVD,VR] function decreases with R0/R1. ISSR0 must, thus, increase. The tail current (ISS) varies only by a small amount, which means that the increase of ISSR0 is accomplished almost entirely by enlarging R0. Since VSAT is supposed to remain unchanged, the W/L follows, roughly, the variations of ISS.


192

2

25

1.8 1.6

20

1.4 L [μ m]

W [μ m]

15

10

1.2 1 0.8 0.6

5

0.4 0.2

0 0.1

1

10 R0/R1

100

0 0.1

1000

40

11.4

35

11.2

10 R0/R1

100

1000

10 R0/R1

100

1000

100

1000

11

30

10.8

25

10.6

W/L

WL [μ m2]

1

20

10.4

15

10.2

10

10

5

9.8

0 0.1

1

10 R0/R1

100

9.6 0.1

1000

1

Figure 3.45. Variation of W, L, WL and W/L with R0/R1.

35000

100000

30000 10000

1000

20000

R1 [Ω]

R0 [Ω]

25000

15000

100

10000 10

5000 0 0.1

1

10 R0/R1

100

1000

1 0.1

1

10 R0/R1

Figure 3.46. Variation of R0 and R1 with R0/R1.


193

3

82 80

2.5

78 2 ISSR0 [V]

ISS [μA]

76 74 72

1.5 1

70 0.5

68 66 0.1

1

10 R0/R1

100

1000

0 0.1

1

10 R0/R1

100

1000

Figure 3.47. Variation of ISS and ISSR0 with R0/R1.

To summarize, as R0/R1 increases:

The required transistor area (WL) decreases; above a certain R0/R1 value (about 20 in the example just considered) the area reduction is not very significant. R0 increases and R1 decreases.

ISS and W/L have small variations.

The gate area of the transistors decreases considerably by maximizing R0/R1, without requiring ISS – and therefore the power dissipation – to change very significantly. However R0/R1 cannot increase indefinitely, since the large ISSR0 values that are required place the differential pair transistors in the triode region. In this way, the design should be made targeting to the maximum ISSR0 value, which automatically sets the largest usable R0/R1 ratio. Section 3.5.10 addresses the situation where, instead of R0/R1, one specifies ISSR0.

3.5.9

Application Example: Variation of fs

In this section we maintain the same design requirements of the example in section 3.5.4, except the duration of the amplification phase, which is varied between 0.5 and 10 ns. This is equivalent to changing the sampling frequency. The variation of the dimensions of the transistors is shown in Fig. 3.48. The gate area, WL, is held constant because the sampling frequency does not influence the offset requirement or the averaging effect.


194

Figure 3.49 shows the variation of the R0 and R1. When the duration of the amplification phase increases, the transient response may be slower, and the resistances can increase. 1.8

16

1.6

14

1.4

12

1.2

10

L [μ m]

W [μ m]

18

8 6

0.6

4

0.4

2

0.2

0

0

2 4 6 8 Duration of amplification phase [ns]

0

10

6

2

4

6

8

10

45 40

5.9

35

5.85

30 W/L

5.8 5.75 5.7

25 20

5.65

15

5.6

10

5.55

5

5.5

0

Duration of amplification phase [ns]

5.95

WL [μ m2]

1 0.8

0

2

4

6

8

0

10

0



10

100000

5000

90000

4500

80000

4000

70000

3500

60000

3000 R1 [Ω]

R0 [Ω]

Figure 3.48. Variation of W, L, WL and W/L with the duration of the amplification phase.

50000 40000

2500 2000

30000

1500

20000

1000

10000

500

0

0 0


10

0

2

4

6

8

10


Figure 3.49. Variation of R0 and R1 with the duration of the amplification phase.

Figure 3.50 shows the dependence of the required values of ISS and ISSR0 with the duration of the amplification phase. According to (2.32)


195

as G0, VR, VSAT and R0/R1 are not changed, the value of ISSR0 remains (almost) unchanged.10 For this to happen, ISS is reduced to compensate for the increase of R0. 350

1.6

300

1.4 1.2 1

200

ISSR0 [V]

ISS [μA]

250

150 100

0.6 0.4

50 0

0.8

0.2 0

2

4

6

8


10

0

0


10

Figure 3.50. Variation of ISS and ISSR0 with the duration of the amplification phase.

Finally, one should note that to maintain VSAT unchanged while having ISS decreasing, the W/L ratio must also decrease. This is observed in Fig. 3.48. To summarize, as fs increases:

The required transistor area (WL) does not change. R0 and R1 decrease to allow a faster settling of the output voltages. ISS and W/L increase.

The tradeoff between power dissipation and sampling frequency is clear.

10

ISSR0 would be unchanged if the drain current of the transistors followed the quadratic model exactly.


196

3.5.10 Application Example: Specifying the ISSR0 Product Figure 3.51 shows the differential pair with the largest reference voltage, VREFP, when it becomes completely unbalanced, v I = V R EFP –

2VO V D . To guarantee that the transistor MP does not

enter the triode region one must have R0ISS 5.0

Bandwidth

>280 MHz

{

Extra differential pairs

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

NVR = 312.5 mV

VFS = 1 V

VREFP−VREFN = 26/16VFS = 1.625 V

VR = 8 LSB

{

NVR = 312.5 mV

Figure 4.2. Pre-amplifier stage.

The latched comparators have σ(VOS)comp = 7 mV and an input capacitance of CINcomp = 5.5 fF. The required standard deviation of the offset voltage of the pre-amplifiers is, therefore, σ (VOS )pre −amp = σ (VOS )total 2

⎛ σ (VOS ) ⎞2 ⎜⎜ comp ⎟ ⎟⎟ = 1.13 mV . −⎜ ⎟ ⎜⎜⎝ G0 ⎠⎟

(4.5)


212

The metal interconnections (see Fig. 3.32) have CWireAmp = 5 fF and CWireComp = 2 fF. The matching parameters for this technology are AVt = 8.5 mV.μm and Aβ = 0.2%.μm. The automatic tool described in section 3.5.3 will be used to design this pre-amplifier stage. However, some issues regarding the specifications listed in Table 4.2 must be addressed before using it:

Given the process and temperature variations, how to guarantee the minimum gain and bandwidth requirements. The design procedure does not deal directly with a bandwidth specification. The design procedure only accounts the mismatches in the differential pair transistors.

In order to fulfil the minimum gain specification at all corners, the HSPICE simulations performed by the design procedure are made in the conditions at which it occurs:

Maximum temperature (125ºC) and with the model for the slow corner of the transistors

Fast corner of the resistors, where R, = 65 Ω /,

In this way the design tool indicates the values of R0 and R1 at that cor1 ner. The same is valid for the tail current, because I SS ∝ . R The bandwidth variations are dominated by the process variations in the resistors. The minimum bandwidth occurs at their slow corner, when R, = 105 Ω /, . If in this process corner the bandwidth is 280 MHz, when the resistors are at the fast corner – situation being considered when running the design tool – the bandwidth should be near 105 280 MHz = 452 MHz.2 This is, therefore, the specification that 65 must be considered. The design procedure is not prepared to deal directly with a bandwidth specification; it expects information that characterizes the step response of the pre-amplifier stage. We will make the approximation of considering that, in an averaged pre-amplifier stage, the correspon2

The variations on the parasitic capacitances are being neglected.

Chapter 4: Integrated Prototypes Using Averaging

213

dence between the step response and the –3 dB bandwidth value is similar to the one found in a first order system: a bandwidth of 1 452 MHz corresponds to τ = = 0.352 ns , and at t = 1 ns3 2π 452 × 106 1×10−9 ⎞ ⎛ − ⎟ ⎜⎜ ×10−9 ⎟ 0.352 ⎟⎟ = 0.942 . (4.6) α = ⎜1 − e ⎜ ⎟⎟ ⎜⎝ ⎠ In this way, the design procedure verifies if, at t = 1 ns, α equals 0.942. The σ(VOS)pre-amp specified in Table 4.2 includes the contributions from all the mismatches – in the differential pair transistors, in the resistors and in the current sources. As mentioned in section 3.5, the design procedure only considers the mismatches in the differential pair transistors, which are the main contributors to the offset voltage. A part of the total offset budget should be reserved for the other mismatches: it was stipulated that the differential pair transistors are responsible for σ(VOS)diff pair = 0.85 × σ(VOS)pre-amp = 0.96 mV; the remaining part is left to the contributions of the mismatches in the resistors and current sources, whose area is obtained after knowing the solution indicated by the design tool (W, L, ISS, R0, R1). Finally, Table 4.3 presents the set of specifications used as input to the design procedure. Table 4.3. Pre-amplifier specifications used as input for the design procedure, which considers the situation of maximum temperature (125ºC), the slow corner for the transistors and the fast corner for the resistors.

3

Specification

Value

R0/R1

2

N

5

σ(VOS)diff pair

0.96 mV

G0

5.0

α (at t = 1 ns)

0.942

If there was a T/H, this would correspond to the duration of the amplification phase. In this case, the operation of the pre-amplifier stage does not depend of the sampling frequency. This choice is, thus, perfectly arbitrary. If a another time instant was chosen, there would be a different α, but the sizes indicated by the design tool would be similar.


214

The design tool yielded the following results: W = 58.2 μm, L = 0.37 μm, R0 = 4117 Ω, R1 = 2059 Ω and ISS = 261 μA. As mentioned before, it indicates the resistances at the minimum gain situation, where R, = 65 Ω /, . As in typical conditions R, = 85 Ω /, , one has: 85 (4.7) R0 = 4117 = 5384 Ω 65 85 (4.8) R1 = 2059 = 2693 Ω. 65 The value of the tail current sources is 261 μA when R, = 65 Ω /,. 1 Since I SS ∝ , in typical conditions R 65 (4.9) I SS = 261 = 200 μA. 85 The termination proposed in section 2.7.2 was used in this ADC: there are five extra differential pairs in each side of the averaging network, and equations (2.4) and (2.93) indicate RTERM = Req = R0 and ITERM = ISS. The HSPICE simulation results are shown in Table 4.4. A comparison with Table 4.2, leads to the conclusion that only the minimum value of the bandwidth is slightly below the specification, but still has an acceptable value. This fact is not surprising, given the approximations that were done. Thus, following the process just described, it is possible to use the design tool presented in the previous chapter, to guarantee a set of specifications across process and temperature corners. Table 4.4. HSPICE simulation results of the pre-amplifier stage. Parameter

MIN

TYP

MAX

G0

5.0

5.8

6.2

σ(VOS)pre-amp (mV)

0.97

1.05

1.13

Bandwidth (MHz)

261

344

472

A DC sweep simulation was performed to obtain the deterministic INL, caused by interpolation errors and termination problems. A maximum value of ±0.035 LSB was obtained, arising solely from interpolation errors; no relevant zero crossing deviations caused by termination issues, are observed in any corner.


215

The total input capacitance of the pre-amplifier stage is around 0.95 pF.

4.2.4

Resistive Ladder

The resistive ladder is composed of 26 resistors, that generate the reference voltages for each of the 27 pre-amplifiers, as shown in Fig. 4.2. Each ADC has its own resistive ladder whose extremities connect to the same reference voltage generator. This guarantees, as much as possible, that the two ADCs have similar offset and gain errors. The sizing of the resistors depends on two phenomenons:

The random variations on the reference voltages, which set the area of the resistors (WRLR).

The disturbances on the reference voltages, caused by the capacitive coupling to nodes that vary with the input signal – see Fig. 4.3. This sets the values of the resistors, and therefore their aspect ratio, LR/WR.

These two conditions set the physical dimensions of the resistors, LR and WR. Note that the technology design rules always impose limitations to the sizes that may be used. For example, there is always a rule stating the minimum length the resistors, LRmin; if LR < LRmin, then LR must increase to LRmin and WR must be adjusted to maintain the aspect ratio, thus leading to resistors with an area larger than strictly necessary. In the 7-bit ADC being described, each resistor in the ladder has 33 Ω and an area of 200 μm2. Therefore, the ladder has a total resistance of 26 × 33 Ω = 858 Ω. Since VREFP − VREFN = 1.625 V, there is a current of about 1.9 mA flowing in it. The maximum random variations occur at the middle reference voltage, where Monte-Carlo simulations indicate σ(ΔVR) = 0.05 LSB. The variations on the reference voltages, due to the capacitive coupling in the pre-amplifiers, were obtained in a transient simulation at which a full-scale (1 V), maximum frequency (40 MHz) sinusoidal signal was applied to them. In these conditions the reference voltage variations are below ±0.22 LSB.

216


vI iLADDER VREFP

VREFN

iLADDER

Figure 4.3. Voltages at the differential pairs and reference ladder, when the input voltage is directly applied to the pre-amplifiers.

4.2.5

Reference Voltage Generator

The reference voltages should remain as constant as possible when the converter is operating. In this ADC, a reference voltage generator receives VBG and generates the voltages to apply to the extremities of the resistive ladder, as represented in Fig. 4.4. It employs a transconductance amplifier, and its differential output voltage is (assuming a large Gm) VREFP −VREFN =

Rb VBG . Ra

(4.10)


217

pads

Ra -

VBG

+

Gm

CDEC

VREFP

Rb

+

Rladder

-

bonding wires CDEC

Ra Rb

VREFN pins

Figure 4.4. Reference voltage generator.

A low output resistance is important to have load independent reference voltages. The necessity of guaranteeing a low output impedance comes from the fact that the reference ladder cannot be regarded as a simple resistive load, where a constant current flows. Figure 4.3 helps to understand this phenomenon: the perturbations on the reference voltages arise because the ladder must provide the charge currents for the parasitic capacitances of the transistors, when there are voltage variations in the internal nodes of the differential pairs. Thus the reference voltage generator does not “see” a simple resistive load, but something more complex, which changes as time passes. It must present a low output impedance to avoid reference voltage fluctuations, which would result in full-scale (VFS) variations. For the circuit represented in Fig. 4.4 the output resistance is 2 (Ra + Rb )

, (4.11) 2Gm Ra + 1 which, in the usual situation where 2GmRa 1, can be approximated by ROUT =

R ⎞ 1 ⎛⎜ (4.12) ⎜1 + b ⎟⎟⎟ . Gm ⎜⎝ Ra ⎠⎟ Since the Ra/Rb ratio cannot be freely adjusted because it sets the differential output voltage, the only way of reducing the output resistance is to increase Gm. Since the current to be supplied to the resistive ladder depends (in a nonlinear way) on the input signal,4 it has high frequency components. ROUT

4

The input signal variations make the voltages at the internal nodes of the differential pairs vary which, in turn, disturbs the reference voltages. This is a nonlinear phenomenon since it depends on the transfer function of the differential pairs and on the values of the parasitic capacitances. In ADCs with a S/H the reference voltages also have a clear dependence on the clock signal.

218


To guarantee a low output impedance up those high frequencies, the amplifier would have to have a very large gain-bandwidth product. This is only attainable with a significant power dissipation. Instead we use large external decoupling capacitors (CDEC = 100 nF) connected to the extremities of the reference ladder, which provide the “instantaneous” (high-frequency) current, demanded by the resistive ladder; the reference voltage generator must only track the average value of VREFP – VREFN, and supply the necessary current to restore the charge lost by the decoupling capacitors. In other words, the external capacitors ensure the low impedance at high frequencies, and the reference voltage generator must only present a low output resistance at low frequencies, thus avoiding the need for wideband amplifier. As mentioned in the previous section VREFP – VREFN should equal 1.625 V, which corresponds to 1.3 × VBG (VBG = 1.25 V). There is only one reference voltage generator for the two I/Q ADCs. Since the ladder in each ADC has a total resistance of 858 Ω, the reference generator has a load of 429 Ω. The DC current supplied by this circuit is, there1.625 fore, = 3.79 mA. 429 The differential output voltage is given by (4.10); we have chosen Ra = 25 kΩ and Rb = 32.5 kΩ, which leads to Rb/Ra = 1.3 and guarantees that only a low current is drawn from the bandgap voltage generator. Figure 4.5 shows that the transconductance amplifier is composed of a voltage amplifier, with a DC gain of A0, which controls the vGS of the two transistors that provide the current to the resistive ladder. With this implementation, we achieve Gm = 99.5 S which, from (4.12), yields ROUT = 0.02 Ω. The current drawn from the supply by the reference voltage generator is 4.12 mA, from which 3.79 mA flow in the resistive ladders. Thus, the reference generator only consumes about 8% (0.33 mA) of the total supply current.

4.2.6

Latched Comparators

The latched comparator used in this ADC is represented in Fig. 4.6, employing the regenerative stage described in section 1.6.4 (Fig. 1.37). Two input sampling PMOS switches were added, to prevent the comparators from being sensitive to their input voltage during the regeneration process. This is particularly relevant when there is no S/H, because that sensitivity translates into an input dependent sam-


219

pling instant [22], which causes harmonic distortion (this is discussed in section 1.3.2). Rb

pads

CDEC

Mp VREFP

Ra -

VBG

+

-

A0

Rladder

+

Ra

bonding wires CDEC

VREFN Mn

pins

Rb

Figure 4.5. Implementation of the reference voltage generator.

Regenerative Stage VDD

M5a

M3a

latch

M4a

vIP

M7a

M3b

latch

vON

vOP

M2a

M2b

M1a

M1b

M5b

M4b

vON vOP M7b

SR latch S

Q

R

Q

vIN

latch

latch latch

M6

Figure 4.6. Latched comparator.

The SR latch memorizes the result from the previous comparison when the regenerative stage is in the reset phase (latch is low). The latched comparator was designed to have σ(VOS)comp = 7 mV. The regeneration time, i.e. the time needed to have a valid output logic level after the rising edge of the latch signal, must be below Ts/2 = 4.1 ns. HSPICE simulations indicate that in the worst case conditions (slow transistor corner at maximum temperature), it is

220


smaller than 2.4 ns. This is measured with a differential input voltage, vIP – vIN, equal to VLSB.5 Each comparator has an input capacitance of 5.5 fF and consumes 130 μW in typical conditions. This low input capacitance is accomplished because the input switches (M7a/M7b) are small – 1 μm/0.36 μm – and the transistors on the differential pair (M1a/M1b) are also not very large – 6 μm/0.36 μm, due to the relaxed σ(VOS)comp specification. There is another important characteristic found in all dynamic latched comparators6: when the input signal is being applied, the transistors of the differential pair are in cutoff, presenting the minimum possible gate capacitance, since there is no inversion layer (channel) formed.

4.2.7

Digital Encoder

The digital encoder translates the thermometer code provided by the latched comparators, into the binary output code. The first operation performed inside the encoder is the bubble correction. High input slew rate conditions or timing differences between the signal/clock paths can lead to the existence of a high logic value above a low logic value, in the thermometer code. These errors, which are usually referred to as bubbles because they resemble the bubbles in a mercury thermometer, lead to more than one high-to-low transition, thereby causing large errors in the output code of the ADC. Figure 4.7 shows examples of bubble errors, where the dashed line corresponds to the best guess of the correct high-to-low transition [18]. The bubble correction scheme proposed in [18] is used in this ADC, where the output of each comparator is examined relatively to its two nearest neighbors, and it is changed if it disagrees with both. This approach removes the bubbles in examples 1, 2 and 3, generating the thermometer code corresponding to the best guess. Case 4 corresponds to a very serious performance degradation, and should not occur in practice. 5

As seen in section 1.6.4, the regeneration time of a comparator depends on its differential input voltage; conceptually, as it decreases, the regeneration time goes towards ∞ (metastability). In practice the random electrical noise makes the comparator decide in a finite amount of time. When determining the regeneration time of latched comparators by simulation, it is convenient to apply a small input signal: VLSB = 7.8125 mV was chosen. Since the minimum gain of the pre-amplifiers is 5 this corresponds, in the worst case, to the situation where the input voltage is 1/5 LSB away from the nearest zero crossing.

6

See [3, 4] for a discussion on the main comparator architectures.


221

Figure 4.8 represents the second operation performed by the digital encoder: the detection of the high-to-low transition in the (bubble corrected) thermometer code. A “1-of-N code” is generated that indicates the input signal magnitude with a single bit having a high logic value. This code is used to address one of the 128 lines in the ROM that performs the last operation in the encoder: the attainment of the binary output code. The schematic of the ROM is shown in Fig. 4.9. Depending on the selected line, there is a NMOS or a PMOS transistor forcing a low or a high digital level in each output line.

0

0

0

0

0

1

1

0

0

0

0

1

1

0

0

1

0

1

1

0

1

1

1

0

1

0

1

1

1

1

1

1

Example 2

Example 3

Example 4

Example 1

Best Guess

Figure 4.7. Examples of bubble errors [18]. 0

0

0

0

0

0

0

0

1

1

1

0

1

0

1

0

Thermometer Code (after bubble correction)

1-of-N Code

Figure 4.8. Detection of the high-to-low transition.

Two inverters buffer each output line of the ROM. Latches are connected after those inverters, to synchronize the data output. Those latches can be controlled directly by the input clock or by a decimated version of the clock (fs/8). The ADC still operates at the nominal frequency when the decimated clock is used, but it only outputs data once in every 8 clock cycles; since the ADC latency is smaller than 8 clock


222

cycles, it is guaranteed that no switching noise is being generated by the output pads when it is converting each of the samples that is outputted. T127

T127

T64

T64

T1

T1 T0

T0

b6

b5

b4

b3

b2

(MSB)

b1

b0 (LSB)

Figure 4.9. ROM.

4.2.8

Layout and Measurement Results

There must be special concerns in the layout of the pre-amplifier stage with the voltage drops in some metal connections (IR drops), because the linearity of the converter may be directly affected. One example are the connections between the averaging/interpolation resistors, which must all be equal; if this does not happen there are


223

variations on the effective value of R1, causing systematic zero crossing deviations. Another case, represented in Fig. 4.10, is the IR drop in the ground metal line that connects all differential pairs. This IR drop makes every current source transistor have a different VGS and, therefore, a different current. When averaging is used this causes systematic zero crossing deviations. Typically, the ground connection is a wide metal line, to guarantee a low IR drop. The solution represented in Fig. 4.11 was devised which, if well implemented, makes all differential pairs have the same tail current: there is a separate ground line for each differential pair, where only its tail current flows. A current source forces ISS into a similar line, that connects the gates of all transistors. It can be verified that all the current source transistors have an equal VGS and, thus, an equal drain current, ISS. ISS ISS2

ISS1

VB VGS

ISS3

VGS1

ISS1+ISS2+...+ISSk

Ra

ISSk

VGS3

VGS2 Rb

Rb

Ground Line

VGSk

ISSk

Rb

Figure 4.10. IR drop in the ground metal line causes different tail current values in every differential pair. ISS

ISS VGS=VB

ISS Ra

Multiple Ground Lines

ISS

ISS Ra

VGS=VB

ISSk

ISS

Rb

(k−3)Rb

Rb VGS=VB

VGS=VB

VGS=VB

ISS Ra+Rb

ISS Ra+2Rb ISS Ra+(k−1)Rb

Figure 4.11. Solution devised to eliminate the differences between tail current values.

224


The layout of the I/Q ADC, is shown in Fig. 4.12. The total occupied area is 0.77 mm2 and the power dissipation is 100 mW. Each flash ADC occupies 0.3 × 1.20 mm = 0.36 mm2.

Flash ADC − Channel Q

Flash ADC − Channel I

600 μm

1280 μm

Reference Voltage Level Generator Converters Figure 4.12. Layout of the I/Q 7-bit 120 MHz ADC.

The INL and DNL are shown in Fig. 4.13, remaining below ±1 LSB. Figures 4.14 and 4.15 show the results from the FFT (65536 points) of the output codes, when fi = 10.3 MHz (low input frequency) and when fi = 44.3 MHz (value a bit above the maximum specified frequency). In both situations the converter is operating at full speed (120 MHz), but the output code is only updated once in every 8 clock cycles – the output data is decimated. This is done to reduce the substrate noise generated by the switching of the buffers in output pads.


1

225

Max(DNL)= 0.95LSB

DNL [LSB]

0.5

0

-0.5 Min(DNL)= -0.79LSB

-1

16

1

32

48

32

48

64 Output Digital Code

80

96

112

128

64

80

96

112

128

Max(INL)= 0.81LSB

INL [LSB]

0.5

0

-0.5 Min(INL)= -0.58LSB

-1

16

Output Digital Code

Figure 4.13. Typical INL and DNL, measured with fs = 120 MHz and fin = 10.3 MHz.

0 THD=-45.1dB

(-0.49) ( 1)

-10

SNR=41.8dB SINAD=40.1dB

-20

Power Spectral Density [dB]

-30 -40 -50

(-54.85) ( 7)

(-59.08) (-61.00) ( 4) ( 3)

-60

(-53.35) ( 9)

(-56.84) ( 6)

(-50.19) ( 2) (-52.24) ( 5)

-70 (-76.05) ( 8)

-80 -90 -100

1

2

3

4 Frequency [Hz]

5

6

7 x 10

6

Figure 4.14. FFT of the output samples, with fs = 120 MHz and fin = 10.3 MHz. The output data was decimated by a factor of 8.


226

0 -10

THD=-40.2dB

(-0.67) ( 1)

SNR=39.6dB SINAD=36.9dB

-20


-30 -40

(-43.92) ( 2)

(-47.87) ( 3)

-50

(-50.29) ( 4)

(-50.54) ( 5) (-53.68) ( 9)

(-58.25)

-60

( 6)

-70

(-69.52)

(-65.37) ( 8)

( 7)

-80 -90 -100

1

2

3

4 Frequency [Hz]

5

6

7 x 10

6

Figure 4.15. FFT of the output samples, with fs = 120 MHz and fin = 44.3 MHz. The output data was decimated by a factor of 8.

Analyzing the results shown in Figs. 4.14 and 4.15, allows to conclude that:

The SINAD is limited by the SNR, although when fi = 44.3 MHz, the contribution from the THD is almost identical. When fi increases, the THD degrades faster than the SNR. The third order distortion has a maximum value (–47.2 dB) which is not far from the design target of –50 dB. The second harmonic is the most relevant, for both input frequency cases.

The main cause for the dominant presence of the second harmonic is the interaction between the 500 Ω Electrostatic Discharge (ESD) protection resistor existing at the input – see Fig. 4.16(a) – and the non-linear input capacitance of the pre-amplifier stage. This problem would be eliminated by placing one ESD resistor before the gate of each MOS transistor, as shown in Fig. 4.16(b). In a fully differential design this problem would not occur.


vI

500 Ω

vI

227

500 Ω

500 Ω

(a)

(b)

Figure 4.16. Placement of the ESD resistor: (a) at the input; (b) before the gate of each transistor.

4.3

10-BIT 100 MS/S FOLDING AND INTERPOLATION ADC

4.3.1

Specifications and Architecture

This 10-bit 100 MS/s ADC was intended to be used in a High Definition Television (HDTV) demodulation system. It was implemented in a 0.25 μm CMOS technology having a 2.5 V ± 10% supply voltage. The ADC should process 1 Vpp differential or single-ended input signals, with frequencies up to 50 MHz. This converter uses the folding and interpolation architecture depicted in Fig. 4.17. The S/H samples the input signal and provides a gain of 1.5. This eases the offset requirements of the folding circuits, which now have a differential full-scale input range of VFS = 1.5 V. In case of single-ended inputs, the S/H also makes the single-ended to differential conversion. There are three cascaded folding and interpolation stages with the same parameters (FF, FB and IF). Moreover, the total number of differential pairs in each of those stages equals the number of latched comparators. This originates a modular architecture and simplifies layout – for example the width of each differential pair in any folding stage equals the width of a latched comparator. As will be seen in section 4.3.3, this architecture has less differential pairs in the folding stages, and about half the latched comparators of previously published 10-bit folding and interpolation ADCs [80, 87].


228

This is achieved by using three cascaded folding stages, instead of a pre-amplifier stage followed by two folding stages. vIP vIN

S/H 2 VREFP

VREFN


72

16

Latched Comparator Stage (NCOMP=72)

72

Third Folding Stage (FF[1] = 3, FB[1] = 24, IF[1] = 3)

72

Second Folding Stage (FF[1] = 3, FB[1] = 24, IF[1] = 3)

First Folding Stage (FF[1] = 3, FB[1] = 24, IF[1] = 3)

Resistive Ladder

Coarse ADC (16 Pre-amplifiers and Latched Comparators)

72

b9 b0

Figure 4.17. 10-bit folding and interpolation ADC architecture.

Figure 4.18 depicts the timing diagram showing the operation of this ADC, which is controlled by two non-overlapping clock phases (ph1 and ph2). S/H

Folding Stages

Sample S#1/ Hold S#0

Amplify S#1


Amplify S#2


Amplify S#0

Reset

Amplify S#1

Reset

Amplify S#2

Regenerates S#0

Reset/Memorizes S#0

Regenerates S#1

Reset/Memorizes S#1

ph1

ph2

ph1

ph2

Latched Reset/Memorizes S#(-1) Comparators ph2

Figure 4.18. Timing diagram showing the operation of the 10-bit ADC.

During ph1 the S/H amplifies the input voltage that was sampled in the previous ph2. Its output voltage value at end ph1 is maintained unchanged during the next ph2. The folding circuits are reset in ph1, and perform the amplification when the output of the S/H is held constant (ph2). This situation is similar to the one shown in Fig. 1.27, where the output voltages of the folding circuits that are at the zero crossing remain zero during this phase. The outputs of the third folding stage are applied to the latched comparators during ph2, which perform the regeneration in the next ph1.


229

The bias current and the reference voltage generators are similar to those presented in sections 4.2.2 and 4.2.5. An amplifier generates the common-mode voltage, VCM, which is used at the S/H (in the sampling network and to set its output common-mode voltage value), and in the reference voltage generator (to set the common-mode of VREFP and VREFN). This circuit is the single-ended version of the reference voltage generator. The coarse ADC has 16 comparators to indicate in which folding period (see Figs. 1.18(b) and 1.21) the input is situated. Its thermometer output code is decoded in the way already described for the 7-bit flash ADC. The circular code found at the outputs of the comparators connected to the last folding stage, is also decoded by detecting high-to-low or low-to-high transitions. This decoding process is practically equal to the one used for the thermometer code. An error correction algorithm [82] is then implemented to obtain the ADC output code, where the utilization of redundancy overcomes the problems caused by the misalignments between the coarse ADC comparators and the folding core.

4.3.2

Sample-and-Hold

The S/H must be capable of sampling the input signal once every clock cycle, while maintaining the output voltage value during the entire clock period. It must also accommodate differential or singleended input signals, and implement a gain of 1.5. A closed loop S/H was chosen to achieve the linearity required for a 10 bit ADC. Figure 4.19(a) depicts the S/H employed in this converter, which uses non-overlapped clock phases to guarantee charge conservation at the input nodes of the amplifier. Phases ph1′/ph2′ rise simultaneously with ph1/ph2, but have an earlier falling edge to avoid signal dependent charge injection [116] (bottom plate sampling). Figure 4.19(b) and (c) show the equivalent circuits in the two operating phases. This S/H combines the characteristics of the circuit proposed in [43], which is capable of making the single-ended to differential conversion and implement a gain, with the ones found in the S/H of [117] which maintains a feedback path during the non-overlap time of the phases (this is fundamental for high speed operation). During ph2 the input voltage is applied to the capacitors C1a/C1b. The sampling operation occurs at the falling edge of ph2′ when the switches connected to VCM, on the right side of C1a/C1b, open. In this phase, the output voltage of the S/H corresponds to the previous sam-


230

ple. Capacitors C2a/C2b implement the necessary negative feedback around the amplifier, therefore determining the differential output voltage. Capacitors C3a/C3b sample the output while C4a/C4b are reset to VCM. ph2'

ph2

VCM

VCM

C4a ph1'

ph1

ph2

VCM VCM ph2

ph1'

vIN

ph2'

ph1

vIP ph2

C2a

ph2'

C1a

C1b

C3a

+

ph1' ph1'

ph1

-

vON

+

vOP

-

ph2'

ph1' ph2 ph2'

C2b ph1'

VCM

C3b VCM ph2

ph1'

ph1

C4b

VCM ph2'

VCM ph2

(a)

VCM

C4a

VCM

VCM

C4a C3a

C3a C2a

C1a vIN

+

VCM vIP

-

vON

+

vOP

-

C1b

VCM

vAP

vX

vAN

+

vON vOP

C2b C3b

C3b C4b

+

-

C1b

C2b VCM

C2a

C1a

C4b

VCM

(b)

(c)

Figure 4.19. Sample-and-Hold: (a) schematic; (b) sampling/hold phase (ph2); (c) amplification phase (ph1).

At the end of ph2 the charge stored in each capacitor is ⎧ II ⎪⎪⎪qC1a = (VCM − vIP )C 1 ⎨ II ⎪⎪q = (V − v )C 1 CM IN ⎪⎩ C1b

(4.13)


⎧ ⎪qCII ⎪ 2a ⎪ ⎨ II ⎪ ⎪⎪qC 2b ⎩ ⎧ ⎪qCII ⎪ 3a ⎪ ⎨ II ⎪ q ⎪⎪ ⎩ C 3b

II = (vAP − vONprevious )C 2 II = (vAN − vOPprevious )C 2

= (VCM − vONprevious )C 3 = (VCM − vOPprevious )C 3

231

(4.14)

(4.15)

⎧ ⎪ qCII4a = 0 ⎪ ⎪ (4.16) ⎨ II ⎪ = 0. q ⎪ ⎪ ⎩ C 4b In ph1 the input terminals of C1a/C1b are shorted together and, due to the negative feedback, the amplifier has zero differential input voltage7: these capacitors now have the same voltage at their terminals. In this way, the difference of charges previously stored in C1a/C1b during ph2 (which is proportional to vIP – vIN) is redistributed to the other capacitors. Since this charge redistribution occurs independently of having a differential or single-ended input signal, this S/H may perform a single-ended to differential conversion. At the end of ph1, I ⎧ I ⎪⎪⎪qC1a = (vAP − vX )C 1 (4.17) ⎨ I ⎪⎪q = (v I − v )C 1 AN X ⎪⎩ C1b ⎧⎪q I = v I − v ( AP ON )C 2 ⎪⎪ C 2a (4.18) ⎨ I ⎪⎪q = (v I − v )C AN OP 2 ⎪⎩ C 2b I ⎧ I ⎪⎪⎪qC 3a = (vAN − vON )C 3 (4.19) ⎨ I I ⎪⎪⎪qC 3b = (vAP − vOP )C 3 ⎩ ⎧⎪q I = v I − v ⎪⎪ C 4a ( AP ON )C 4 (4.20) ⎨ I I ⎪⎪qC 4b = (vAN − vOP )C 4 . ⎪⎩ The fact that the charge at the input nodes of the amplifier is conserved, leads to

⎧⎪q I + q I + q I + q I = q II + q II + q II + q II C 2a C 3b C 4a C 1a C 2a C 3b C 4a ⎪⎪⎨ C1a ⎪⎪q I + q I + q I + q I = q II + q II + q II + q II . C 2b C 3a C 4b C 1b C 2b C 3a C 4b ⎪⎩ C1b 7

The finite gain and offset voltage of amplifier are being ignored here.

(4.21)


232

Noting that vAN = vAP results in C1 C 3 −C2 (4.22) vIDIFF + vODIFFprevious C 4 + C 3 −C2 C 4 + C 3 −C2 where vIDIFF = vIP – vIN, and vODIFFprevious = vOPprevious – vONprevious is the output voltage in the previous clock period. When C3 = C2, (4.22) is simplified to C (4.23) vODIFF = 1 vIDIFF . C4 In that case there is a perfect cancellation between the charges stored in C2a/C2b and in C3b/C3a, due to the cross-connection of these capacitors during ph1 – see Fig. 4.19(c). Thus, in what concerns the charge redistribution that occurs in this phase, it is as if only capacitors C1a/C1b and C4a/C4b exist. The finite gain of the amplifier and the mismatches in C2a/C2b/C3a/C3b make the output voltage dependent of the previous samples, just as in a discrete low pass-filter. This is not a limitation in practice. In addition, the finite amplifier gain introduces a gain error in the transfer function of the ADC; since the amplifier gain is signal dependent, this originates distortion. The common approach is to guarantee that, in the worst case conditions (maximum output voltage) the gain is still high enough, thereby causing a negligible error in the vODIFF. As previously mentioned, during ph1 the output voltages settle from vODIFFprevious to vODIFF (amplification phase). The settling speed depends on the values of the capacitors, on the load, and of the characteristics of the amplifier. In the next ph2 (hold phase), C1a/C1b sample again the input voltage. Capacitors C3a/C3b and C4a/C4b are disconnected from input nodes of the amplifier, but C2a/C2b maintain the negative feedback and, as the charge they store is not changed, vODIFF is kept unmodified. Figure 4.20 represents the output voltage of the S/H in consecutive clock cycles. Considerations about the required gain, noise, settling speed and the effect of charge injection when the MOS switches open, led to the following choice of capacitances: C1 = 900 fF, C2 = C3 = 200 fF and C4 = 600 fF. The amplifier must support an output voltage excursion of ±0.75 V and, due to the effects mentioned above, its gain should be larger than 80 dB. The load of the S/H corresponds to the input capacitance of the vODIFF =


233

first folding stage, which is approximately 5 pF. The amplifier must settle during the time where ph1′ is high which, in the worst case conditions, is about 3.5 ns. The selected topology, a two stage amplifier, is shown in Fig. 4.21. A cascode compensation is used (CC = 2.2 pF), which enables a faster transient response, when compared to the traditional Miller compensation [118, 119]. Output Voltage of the S/H

ph2

ph1

ph1

ph2

ph2

ph1

ph2

ph1

t

Ts

Figure 4.20. Differential output voltage of the S/H represented in Fig. 4.19.

M4a

M3a

VB3

VB2

M3b

vO1N

vO1P

M2a

VB1

VB4

M7b

vOP

vON

CCa

CCb

vCN

M2b

vCN vIP

M7a

M4b

vCP

vCP M1a

M5

M1b

vIN

VCMFB1

vO1N

M6a

M8

M6b

vO1N

VCMFB2

Figure 4.21. Two-stage amplifier used in the S/H.

The first stage is a high-gain telescopic amplifier, which has low output voltage excursion due to the moderate gain of the second stage. Both stages have independent switched capacitor common-mode feedback networks. The S/H dissipates about 42 mW. The most relevant simulation results, across supply voltage, process and temperature variations, are shown in Table 4.5.


234

Table 4.5. HSPICE simulation results of the S/H. MIN

TYP

MAX

Amplifier DC gain

83.1

91.5

99.0

Amplifier unit gain frequency (GHz)

1.57

2.06

2.56

THD (dB)

–71.9

–66.8

–61.1

–86.3

–79.8

–74.9

SNR (dB)

59.9

60.4

60.8

Settling error (LSB)

0.04

0.11

0.36

(fi 50 MHz; single-ended input) THD (dB) (fi 50 MHz; differential input)

(full-scale output voltage excursion)

4.3.3

Folding Stages

In the single-ended input case considered in chapters 2 and 3 each zero crossing was defined by a single differential pair, that subtracted the input signal from a given reference voltage. This was adequate for the ADC presented in the previous section, which had a single-ended input, but now the first folding stage must process the differential output voltage of the S/H. That is performed by the double differential pair represented in Fig. 4.22, where each differential pair works in a single-ended fashion, subtracting one of the input signals (vIP or vIN) from a reference voltage (VRP or VRN), originating an output proportional to (vIP – vIN) – (VRP – VRN). The operation of this circuit will now be examined, to highlight the equivalence existing between it and the simple (single-ended) differential pair that was considered in the theoretical work presented in the previous chapters. Figure 4.23 represents its transfer function in two situations: when the common-mode of the input voltages, v + vIN , equals the common mode of the reference voltages, VCMi = IP 2 V +VRN and when VCMi ≠ VCMr . There are two axis, indiVCMr = RP 2 cating how vIP and vIN vary when vIDIFF is increased. In the case depicted in Fig. 4.23(a), when vIP = VRP we have vIN = VRN; then,


235

vIDIFF is enlarged by increasing vIP towards higher reference voltages, and decreasing vIN towards lower reference voltages. VDD

R0

R0

iDN

iDP vOP

vON vIP

i1

i3

i2

W/2

W/2

VRP

VRN

i4 vIN

W/2

W/2

ISS/2

ISS/2

Figure 4.22. Double differential pair.

iDP

iDN i4

ISS

iDP

0

ISS

iDN

0

ISS/2

i4

ISS/2

i3

0

i3

0

i2

ISS/2

i2

ISS/2

i1

0

i1

Lower reference voltages

Higher reference voltages

vIP=VCMi+vIDIFF/2


vIP=VCMi+vIDIFF/2

VRP

VRP Higher reference voltages

0



vIN=VCMi−vIDIFF/2

VRN

(a)



vIN=VCMi−vIDIFF/2

VRN

(b)

Figure 4.23. Transfer function of the circuit represented in Fig. 4.22: (a) the input and reference voltages have the same common-mode; (b) the input and reference voltages have a different common-mode.

In Fig. 4.23(b) when vIP = VRP we have vIN ≠ VRN , and vice-versa. However, although the two differential pairs have non-coincident zero crossings, the zero of the overall transfer function remains unchanged: its location occurs when i1 − i2 + i3 − i4 = 0 ⇔ gm (vIP −VREFP ) − gm (vIN −VREFN ) = 0 ⇔

(vIP − vIN ) − (VREFP −VREFN ) = 0,

(4.24)


236

where the same transconductance is considered for both differential pairs.8 The fact that the zero of the overall transfer function occurs when the two differential pairs are not at their zero crossings – where they have the maximum transconductance – results in a DC gain reduction. So, it must be ensured that VCMi VCMr. For a differential full-scale input range of VFS = 1.5 V, vIP and vIN vary between VCMi ± VFS/4 = VCMi ± 0.375 V. The reference voltages that define the zero crossings inside the input range are the ones between VCMr ± VFS/4 = VCMr ± 0.375 V; thus the reference voltages at the extremities are 0.75 V apart. In the desirable situation where VCMi = VCMr, the differential pair represented in Fig. 4.24 presents exactly the same transfer function9 and transient response of the circuit shown in Fig. 4.22. It is, therefore, possible to study the folding architecture considering that it has a single-ended input voltage, with a full-scale input range of 0.75 V. This ADC uses a folding and interpolation architecture with several cascaded stages, to reduce the number of comparators. Most of the ADCs found in the literature combine several folding stages with a preamplifying stage [80, 87, 103, 104]. A pre-amplifier can be regarded as a folding circuit with FF = 1; this allows to use the expressions derived in section 1.5.2, even when employing a pre-amplifying stage.

8

When VRP ≠ VRN the transistors in the two differential pairs have different source-to-bulk voltages, vSB (the bulk of the transistors are connected to GND). A drain current expression more 2 β (v – Vt ) , where both Vt and α1 depend on vSB [114]. The α1 2 GS dependence of α1 on vSB implies that the two differential pairs have different transconductances for the same tail current. So, in reality, when VCMr ≠ VCMi there will be zero-crossing deviations, which may be meaningful if VRP differs significantly from VRN and if VCMr differs significantly from VCMi. When VCMr=VCMi this transconductance difference does not cause zero-crossing deviations.

accurate than (1.24) is iD =

9

The DC gain in the circuit of Fig. 4.22 is defined as G0diff = it is G 0se =

∂ (vOP − vON ) ∂vIP

∂ (vOP − vON ) ∂ (vIP − vIN )

, while in Fig. 4.24

. Since the differential output voltage evolution is the same,

G 0se = 2G0diff . It can also be shown that σ (VOS )se =

σ (VOS )diff

. Note that these relations are 2 consistent with the fact that, in the single-ended equivalent of Fig. 4.24, the full-scale input range (0.75 V) is half of the one found at differential input case (1.5 V). Considering the differential case or the single-ended equivalent is, therefore, perfectly equivalent.


237

VDD

R0

R0

iDN

iDP vOP

vON

vIP

W

W

VRP

ISS

Figure 4.24. Single-ended equivalent of the circuit represented in Fig. 4.22.

The following architecture constrains were considered:

Use folding factors not larger than 3. As seen in section 1.6.3, increasing FF enlarges the load capacitance and the offset voltages, and reduces the output common mode voltage. Use the same number of differential pairs in all stages, to have a modular architecture and layout. Since the folding operation gathers zeros in the same signal and interpolation generates new signals, this is accomplished by having stages with the interpolation factor equal to the folding factor. As FF = 3, then IF = 3 is used in all stages. Use no more than three cascaded stages, to avoid a long settling time.

An architecture having one pre-amplifying and two folding stages, that complies with these conditions, will now be considered:

First stage (pre-amplifier stage): FF[1] = 1, FB[1] = 48 and IF[1] = 3

Second stage (folding stage): FF[2] = 3, FB[2] = 48 and IF[2] = 3

Third stage (folding stage): FF[3] = 3, FB[3] = 48 and IF[3] = 3

238


Note that the boundary conditions, given by (1.20), are respected. The total number of zeros is obtained from (1.17), NTOT = 1296. The cascaded folding stages produces a total folding factor of FFTOT = FF[1]FF[2]FF[3] = 9. Each folding stage has FF[2] × FB[2] = FF[3] × FB[3] = 144 differential pairs. The number of latched comparators is, from (1.19), NCOMP = FB[3] × IF[3] = 144. To ensure layout modularity, the width of each differential pair in these stages and the width of each latched comparator should be the same. In the pre-amplifier stage it would be possible to use FB[1] = 144 and IF[1] = 1, leading also to 144 (double) differential pairs. Instead, an interpolation by 3 is considered for this stage, which reduces the number of double differential pairs to 48. Although its power dissipation and input capacitance are not modified (see section 3.5.11), less reference voltages are required. Figure 4.25 shows that the 1024 zero crossings inside the input range are situated in the middle of the folding range, where all the 1296 zero crossings generated by folding stages lie. In this way there are 136 zeros outside the input range, in each side.

Folding Range (0.949 V) 1296 zero crossings

1024 zero crossings

136 zero crossings

Input Range (0.75 V)

136 zero crossings

Figure 4.25. Distribution of zero crossings in the architecture being considered.

Each pre-amplifier generates a zero crossing; all the remaining zeros are created by the interpolations on the subsequent stages. Between the zeros of consecutive pre-amplifiers, there are IF[1]IF[2]IF[3] = 27 regions created by interpolation, each of them corresponding to VLSB. The difference between two consecutive reference voltages is obtained by considering the (single ended) value of the VLSB, 0.75/1024 = 0.732 μV, (4.25) VR = I F [1] I F [2 ] I F [ 3 ]VLSB = 27VLSB = 19.78 mV.


239

From the 48 differential pairs existing in the pre-amplifying stage, 5 are outside the input range, in each side. To terminate the averaging network with no further differential pairs one must have N ≤ 5, which corresponds to VSAT ≤ 5VR = 98.9 mV. Such low VSAT cannot be implemented with CMOS differential pairs. Simulations indicate that in the worst case conditions – slow transistor corner at maximum temperature – VSAT must not be smaller than 250 mV to obtain reasonable W/L values. This corresponds to 13 extra pre-amplifiers in each side of the averaging network. As there are already 5 it is necessary to add 8 more, therefore increasing the total number of differential pairs in the first stage from 48 to 64. Figure 4.26 illustrates this modification. The resistive ladder must, of course, generate the reference voltages for all the 64 differential pairs. Note that the 16 extra differential pairs just added are not connected to the next stage – they are only necessary to terminate the averaging network of the pre-amplifiers. Thus, the comparators only detect the 1296 zero crossings inside the folding range, and the parameters that characterize the architecture – FF[k], FB[k] and IF[k] – remain the same. 8 extra differential pairs (0.158 V)

Folding Range (0.949 V) 1296 zero crossings

1024 zero crossings

136 zero crossings

Input Range (0.75 V)

Total Range (1.265 V)

136 zero crossings

8 extra differential pairs (0.158 V)

Figure 4.26. Inclusion of eight extra differential pairs, to ensure the proper termination of the averaging network in the pre-amplifier stage.

A way of reducing the power dissipation and layout area is to transform the pre-amplifier stage into a folding stage, which is done by grouping the differential pairs that now exist as separate pre-amplifiers,


240

to form folding circuits. According to (1.23), this decreases the number of differential pairs in the following stages and, since the overall folding factor increases, less latched comparators are needed. As discussed in section 2.7.4, since the averaging network of a folding stage is circular, no special terminating circuit is required. However, it is necessary to guarantee that there are N differential pairs with reference voltages above and below the limits of the input range. Thus at least 64 differential pairs are, again, needed in the first stage. The pre-amplifier stage is substituted by a folding stage containing FB[1] = 24 circuits, each with three differential pairs (FF[1] = 3). This leads to a total of 72 differential pairs, instead of the 64 previously mentioned. This small increase is, by far, compensated by the reduction of elements in the following stages. Figure 4.27 shows the transfer function of those folding circuits.

1

5

9

13

vOFOLD[24]

vOFOLD[13]

vOFOLD[1]

17

21

25

29

33

37

41

45

49

53

57

61

65

69

72 vIDIFF

27 LSB

Previous Folding Range

Figure 4.27. Transfer function of the folding circuits used in the first stage.

The folding range found in the situation where the first stage had pre-amplifiers – see Fig. 4.26 – is also indicated in this figure. In that case, the differential pairs that were outside the folding range were used to terminate the pre-amplifier array, and did not connect to the next stage – thus, their zero crossings were not detected by the comparators. Now the outputs of all folding circuits in the first stage connect to differential pairs in the second one, which means that the total number of detected zeros is now much larger. The architecture used in this ADC has three stages with equal parameters, ensuring modularity:

First stage (folding stage): FF[1] = 3, FB[1] = 24 and IF[1] = 3

Second stage (folding stage): FF[2] = 3, FB[2] = 24 and IF[2] = 3

Third stage (folding stage): FF[3] = 3, FB[3] = 24 and IF[3] = 3


241

The total number of zeros is now NTOT = 1944. The cascaded folding stages produces a total folding factor of FFTOT = FF[1]FF[2]FF[3] = 27. Each of the folding stages has 72 differential pairs, which is half of the value that was previously necessary. The number of latched comparators is also reduced to half, NCOMP = FB[3] × IF[3] = 72.10 Table 4.6 shows the specifications chosen for each stage. The transistors in the differential pairs are responsible for 80% of the σ(VOS) values indicated in the table. The remaining 20% are reserved to the mismatches in the resistances and current sources. The latched comparators have σ(VOScomp) = 2 mV. Table 4.6. Design specification of the folding stages. First stagea

Second stage

Third stage

G0

5

2.5

4

α

0.925

0.925

0.75

σ(VOS) (mV)

0.22

0.56

0.75

ISSR0 (V)

0.88

0.7

0.7

N

13

10

10

a The gain and σ(VOS) specifications of this stage are for the single-ended equivalent of Fig. 4.24 (see footnote 9 of this chapter).

The folding stages are in the amplification phase when the differential output voltage of the S/H is held constant (see Fig. 4.18). The folding circuits settle as shown in Fig. 1.27, where the output voltages of the ones that are at the zero crossing, remain zero during this phase. All other output voltages approach their final values smoothly. The first stage contributes directly to the overall zero crossing deviations. In line with what was discussed in section 3.2, the offset voltages of the second folding stage are referred to the input dividing by α1G01, instead of just by the DC gain, G01. To determine the contri10

This 2× reduction in the number of latched comparators and differential pairs of the second and third stages, can be understood with the aid of Fig. 4.27. Restricting the attention to the previous folding range, it can be concluded that the first folding stage now being used has the same characteristics of one having circuits with FF = 2. Since to generate the 1296 zero crossings inside the previous folding range, the first stage now presents FF[1] = 2 instead of FF[1] = 1 (pre-amplifiers), according to (1.23) there is a 2× reduction in the number of differential pairs in the two last following stages. A similar reasoning also justifies the 2× reduction in the number of comparators.


242

bution from the remaining stages – latched comparators and last stage folding circuits – one must account for the settling in the cascaded stages that precede each of them. Performing these calculations leads to σ (VOS ) = 0.29 mV which corresponds to VLSB/2.5, that is sufficiently small to guarantee INL < 1 LSB in most ADCs. To achieve a smaller σ(VOS) it would be necessary to decrease the first stage contributions, which are dominant. However, since specifying σ(VOS1) = 0.22 mV already implies that this stage has an input capacitance of about 5 pF, it was decided not to further decrease σ(VOS1) because the S/H would consume too much. Each stage is designed with the procedure presented in the previous chapter, but using the gain and output voltage expressions of folding stages, instead of the ones for averaged pre-amplifiers. The strategy explained in section 4.2.3 is utilized to guarantee the specifications across process and temperature variations. Let us now discuss if it is more convenient to start by designing the last or the first stage. Apart from the specifications presented in Table 4.6, to design a stage it is necessary to know:

The input capacitance of the differential pairs belonging to the next stage. The latched comparators must first be designed, so that the third folding stage can be sized, then the second, and finally the first. The output voltages of the previous stage. The currents in each differential pair of the first stage are determined by the input and reference voltages. Likewise, the currents in the differential pairs in any of the remaining stages depend on the output voltages of the one preceding it.

These are contradictory conditions: to design a stage it is necessary to know the input capacitance of the next stage, and the output voltages of the previous one. Figure 4.28 shows the process that was utilized, which has two design cycles and overcomes this contradiction. The latched comparators are sized at the beginning, to obtain their input capacitance. Then, the stages are designed sequentially, starting from the last and ending in the first one. Thus, when designing a certain stage, the input capacitance of the differential pairs belonging to the next one is already known. However, as mentioned above, it is necessary to know the output voltages of the previous stage. On the first design cycle it is considered that the circuits in all stages are perfectly


243

linear, each having the gain mentioned in Table 4.6. This allows to estimate the output voltages of any stage. Design of Latched Comparator to obtain its CIN

Estimation of output voltages of all stages, considering perfectly linear circuits

1st Design Cycle Design of 3rd stage

Design of 2nd stage

Design of 1st stage

Calculation of the output voltages of all stages, considering differential pairs with the sizes just obtained

2nd Design Cycle Design of 3rd stage

Design of 2nd stage

Design of 1st stage

Final sizes

Figure 4.28. Design of cascaded folding stages.


244

The output voltages of the folding circuits are calculated more accurately after this initial sizing. This information is used in the second design cycle to obtain new sizes for the components in all stages. Further iterations could be performed, where after each design cycle more accurate output voltage values are obtained, so that a new design cycle starts. However, the two depicted in Fig. 4.28 already indicate values that satisfy the specifications quite reasonably. The sizes of the components obtained by this method are shown in Table 4.7. HSPICE simulations show that, with these dimensions, the specifications are met. Monte-Carlo simulations were performed with the three folding stages connected together, to obtain the INL for all the zero crossings, which was found to be typically below ±1 LSB. The folding circuits in all stages have current sources to increase the output common-mode voltage, as represented in Fig. 1.34 (IDD = 0.75ISS). Table 4.7. Sizes of the components. First stagea

Second stage

Third stage

W (μm)

116.9

14.7

16

L (μm)

0.9

1

0.48

ΙSS (μA)

168.9

68.4

66

R0 (Ω)

5206

10233

10600

R1 (Ω)

337

548

1883

a The W and ISS values indicated are for the single-ended equivalent circuit, presented in Fig. 4.24. As shown in Fig. 4.22, the transistors of the double differential pairs have W/2, and each tail current is ISS/2.

The reset switches of the folding circuits open in the beginning of the amplification phase, letting the output voltages settle. There will be charge currents flowing through the CGD parasitic capacitances of the differential pair transistors which, in the first stage, must be provided by the resistive ladder. Consequently the reference voltages are disturbed, and the output voltages of the folding circuits that are at the zero crossing do not remain zero during the amplification phase, as they should. The solution depicted in Fig. 4.29 is used to solve this problem: the MOS neutralization capacitors have a value equal to the CGD of the differential pair transistors, and provide the charge currents mentioned above, avoiding the perturbation of the reference voltages.


245

Note that this technique, known has neutralization [91], has the inconvenience of increasing the load capacitance at the folding circuits. vON

vOP

iCGD vIP

(W/4,Lmin)

(W/2,L)

(W/2,L)

ISS/2

iCGD

VRP

VRN

vIN

ISS/2

Resistive Ladder

Figure 4.29. Usage of Neutralization in the differential pairs of the first stage, to avoid disturbing the reference voltages.

4.3.4

Latched Comparators

The latched comparator used in this converter is similar to the one employed in the 7-bit ADC, shown in Fig. 4.6. The offset specifications are more stringent, σ(VOS) < 2 mV, leading to larger devices. For example, the transistors in the differential pair now have an area of 36 μm2. The simulations indicate σ(VOS) = 1.8 mV, a worst case regeneration time of 2.2 ns and an input capacitance of 60 fF. The power dissipated by each comparator is about 300 μW. In what concerns the operation of the comparator there is one small difference: the PMOS input switches, M7a/M7b, are now controlled by ph 2 , while the gates of M4a/M4b/M5a/M5b/M6 connect to ph1. In this way the input switches open slightly before the regeneration process begins. Figure 4.30 represents the output voltage of one folding circuit of the third stage. As mentioned in the previous sections, the folding stages are reset during ph1, which forces their output voltages to be nearly zero; during ph2 they perform the amplification. Since the output of the S/H is held constant, the output voltages of the folding circuits that are at the zero crossing, remain zero during this phase – this is case occurring in the last ph2 represented in Fig. 4.30 (dashed line).


246

Output voltage of folding circuit affected by the kickback noise of the comparator vODIFFfold Output voltage in the ideal case

0 ph2

ph1

ph2

t

Figure 4.30. Output voltage of a folding circuit in the situations with and without the kickback noise generated by the comparator.

The input switches of the latched comparators open at the end of ph2, sampling the output voltages of the third folding stage. In the first ph2 shown in Fig. 4.30, a large differential output voltage is sampled and stored at the parasitic capacitance of the input nodes of the comparator (gates of M1a/M1b). In the beginning of the next ph2 M7a/M7b are switched on again, and the charges previously stored in the sampling nodes disturb the output voltage of the folding circuit – kickback noise. At high sampling rates there might not be enough time to recover from this situation. This ADC uses the technique suggested in section 1.6.4, where the sampled input voltage is reset asynchronously somewhere during ph1, when it is detected that the latched comparator has already made a decision. This prevents the previously sampled voltage from disturbing the next comparison. The simulation results of the comparator used in this 10-bit ADC are similar to those shown in Fig. 1.43, which indicate that the kickback noise is virtually eliminated.

4.3.5


There is a number of difficulties in the layout of cascaded folding stages, which imposes a careful floorplan and the consideration of all parasitic elements. Each one of these difficulties will now be addressed, and the solutions utilized will be discussed. The IR drop in the ground line that connects to the folding circuits in a certain stage originates different tail currents, causing systematic zero crossing deviations. The solution depicted in Fig. 4.11 is used to overcome this problem. There is a separate GND line for each folding


247

circuit, where a current of 3ISS flows. A similar line having the same current flowing, connects the gates of the current source transistors. The connections between the averaging resistors must all be equal to avoid variations on the effective value of R1, which would cause systematic zero crossing deviations. One cannot simply place the folding circuits sequentially because, as shown in Fig. 4.31(a), there would be a very long connection between the first and last circuit. The floorplan used in all the folding stages is depicted in Fig. 4.31(b). It was ensured that the metal connections at the extremities have the same length of all the others. 1

1

2

24

3

2

4

23

21

11

23

14

23

12

24

13

(a)

(b)

Figure 4.31. Arrangement of folding circuits in a stage: (a) sequential; (b) alternated, to have all connections to the averaging resistors with the same length.

The connections between consecutive stages are rather complex. For example, the differential pairs of the folding circuit 19 of the second stage, must connect to the outputs of the folding circuits 7, 15 and 23 of the first stage, which are not near. The only reasonable way of making the interconnections is to have a vertical bus with all the out-


248

puts, and use another metal layer to make the horizontal connections to the folding circuits. This is represented in Fig. 4.32. First Stage

Second Stage

Output voltage bus

Third Stage

Output voltage bus

1

1

1

24

24

24

2

2

2

23

23

23

11

11

11

14

14

14

12

12

12

13

13

13

Figure 4.32. Floorplan of the cascaded folding stages.

Minimizing the number of lines in the output buses is fundamental to save layout area and decrease the parasitic capacitances. In Fig. 4.33(a) the bus includes the outputs of the folding circuits, as well as of the interpolations: there are 24 × 3 × 2 = 144 signal lines, which occupy a large layout area. Another problem of this solution is that both the folding and the interpolation outputs are connected to long lines, each having significant parasitic capacitances.


k

k

k

k+1

k+1

R1/3

R1

R1/3

k+1

249

R1/3

R1/3 W/3

W/3

W/3

W/3

R1/3 W

W

W

W

R1/3

(a)

(b)

(c)

Figure 4.33. Possible interconnection schemes between stages: (a) output bus includes also interpolation signals; (b) interpolation resistors are placed near the inputs of the next stage; (c) active interpolation.

The number of lines could be minimized by placing the interpolation resistors near the inputs of the next stage, as shown in Fig. 4.33(b). In this case the bus would only have the 24 × 2 = 48 output lines of the folding circuits. The layout area would be smaller and the parasitic capacitances on the interpolation taps would be largely reduced. However, in this solution it is impossible to guarantee that all metal connections between the folding circuits and the averaging/interpolation resistors present the same parasitic resistance, originating systematic zero crossing deviations. Figure 4.33(c) depicts the solution employed. The averaging resistors are placed near the outputs of the folding circuits and, thus, no static current flows in the bus lines. The transistors in the differential pairs of the next stage are broken in three smaller ones, to implement an active interpolation. In this way, the number of lines in the bus is minimized, saving layout area and reducing the parasitic capacitances, without having IR drop problems. The active interpolation is utilized at the outputs of the first and second stages while, in the third stage, resistive interpolation is still used, because the connections to the comparators are direct. The capacitive coupling between different outputs disturbs the output voltages of the folding circuits. Thus, the output of the folding circuit that is at the zero crossing may not remain zero during the amplification phase. One way to solve this issue is to use shielding lines connected to GND, as depicted in Fig. 4.34(a). The load capacitance introduced in each output node is (4.26) C L = Cbot + 3C lat ,


250

because the Clat between the two differential outputs produces the same effect of a capacitance with a value of 2Clat, connected from each of them to GND. Cbot can be minimized by using the highest metal layers available. Clat can only be reduced by separating the metal lines as much as possible. This is limited by the layout area occupied by the output bus which, in addition to the 48 signal lines, would need 25 more shielding lines. Figure 4.34(b) shows the solution utilized, which does not have shielding lines thus saving layout area. The lateral parasitic capacitances appear between consecutive output nodes, i.e. these capacitances are in parallel with the averaging resistors, as represented in Fig. 4.35(a). Clat

Clat

Clat

vOP1

GND

vON1

Cbot

Clat vOP2

GND

Cbot

Cbot

Substrate (GND)

(a) Clat vOP2

Cbot

Clat

Clat vOP24

vOP3

Cbot

Cbot

Clat vON1

Clat vOP2

Cbot

Cbot

Substrate (GND)

(b) Figure 4.34. Parasitic capacitances in the output bus: (a) with shielding lines; (b) solution utilized, without shielding lines.

Figure 4.35(b) shows the output voltages assuming that folding circuit k is at a zero crossing. At instant t1 somewhere in the amplification phase,


251

... ≈ vOP [k + 2, vI , t1 ] − vOP [k + 1, vI , t1 ] ≈ ≈ vOP [k + 1, vI , t1 ] − vOP [k, vI , t1 ] ≈ ≈ vOP [k, vI , t1 ] − vOP [k − 1, vI , t1 ] ≈ ≈ vOP [k − 1, vI , t1 ] − vOP [k − 2, vI , t1 ] ≈ ...

(4.27)

and

... ≈ vON [k + 2, vI , t1 ] − vON [k + 1, vI , t1 ] ≈ ≈ vON [k + 1, vI , t1 ] − vON [k, vI , t1 ] ≈ ≈ vON [k, vI , t1 ] − vON [k − 1, vI , t1 ] ≈ ≈ vON [k − 1, vI , t1 ] − vON [k − 2, vI , t1 ] ≈ ...

CL

R0

CL

CL

R0

CL

CL

R1 ilat

CL

ilat

Clat

ilat

Clat

R0

CL R1

Clat

ilat

R1

R1

k

CL R1

R1

R1

k−1

R0

(4.28)

k+1

Clat

R1

k+2

(a) vOP[k+2,vI,t]

vOP[k+2,vI,t]

vOP[k+1,vI,t]

vOP[k+1,vI,t]

vOP[k,vI,t]

vOP[k,vI,t] t

t vOP[k−1,vI,t]

vOP[k−1,vI,t]

vOP[k−2,vI,t]

vOP[k−2,vI,t]

(b)

Figure 4.35. Lateral capacitance appear in parallel with resistors R1: (a) circuit; (b) output voltages.


252

If (4.27) and (4.28) contained exact equalities, the currents flowing in the capacitors Clat would all be equal and simply flow transversely from one Clat to the next. In that situation the differential pairs would not have to provide the charge currents for those capacitors and, therefore, the presence of Clat would not affect the transient response of the folding circuits. However (4.27) and (4.28) are approximations that only hold for the output voltage of the folding circuits nearer the one at the zero crossing. Thus Clat affects the transient response of the folding circuits but, as simulations show, it is far better to have them between consecutive outputs, than connected to GND.11 The layout parasitic extractor used indicates that Clat = 62 fF. Transient simulations of the folding circuits were performed with these capacitances, and no degra11

This situation can be studied theoretically following the process presented in chapter 3. The first step consists in substituting R0 and R1 respectively by Z0 = R0//(1/sCL) and Z1 = R1//(1/sClat) in (2.11) and (2.12), to extend the DC expressions of B and C to s-domain, ⎡ ⎤ ⎢ 1 + 2 R0 1 + sC lat R1 ⎥ ⎢ ⎥ R1 R1 1 + sC LR0 ⎢ − 1⎥⎥ B [s ] = R0 1 + sC lat R1 2 (1 + sC lat R1 ) ⎢⎢ ⎥ ⎢ 1 + 4 R 1 + sC R ⎥ ⎥⎦ 1 L 0 ⎣⎢

R0 1 + sC lat R1 R1 1 + sC LR0 . R0 1 + sClat R1 R 1 + sC lat R1 1+2 + 1+4 0 R1 1 + sC LR0 R1 1 + sC LR0 2

C

[s ] =

Comparing these equations with the ones obtained for Clat = 0, (3.2) and (3.3), leads to the conclusion that now B[s] appears divided by 1 + sC lat R1, and all

placed by

R0 1 + sC lat R1 . Since R0 1 + sC lat R1 = R0 R1 1 + sC LR0 R1 1 + sC LR0 R1

R0 1 terms were reR1 1 + sC LR0

⎛⎜ ⎞ ⎟⎟ ⎜⎜⎜ 1 1 ⎟⎟⎟ , making ⎜⎜ + ⎟ 1 C R ⎟ ⎜⎜ 1 + sC LR0 + L 0 ⎟⎟⎟ ⎜⎜ sC lat R1 C lat R1 ⎟⎟⎟⎠ ⎝⎜

1 R C or 0 lat , reduces the effect caused by Clat. This behavior is confirmed by sC lat R1 CL SPICE simulations. R1

B C lat R , where B = 0 , C[s] equals the DC value given by (2.12), and B [s ] = 1 sC + CL R1 lat R1 is again the DC value, (2.11). In this case all differential pairs in the averaging network contribute simultaneously, with a time constant of ClatR1 = CLR0, and the offset voltage no longer varies with time (see section 3.4.2 for the discussion about the time dependence of the offset voltage in averaging networks).

When


253

dation on the transient response is visible, with respect to the case where Clat = 0. All outputs must have equal parasitic capacitances, since any imbalance disturbs the output voltages of the folding circuits that are at the zero crossing – these will not remain zero during the amplification phase. A simple bus of straight lines cannot be used, because the ones at the extremities would have different parasitic capacitances. The solution utilized, which guarantees that all outputs have the same parasitic capacitances between them and to the substrate, is illustrated in Fig. 4.36 for the case of FB = 4. Note also that the placement of folding circuits is according to order shown in Fig. 4.31(b). The layout of the ADC is shown in Fig. 4.37. The occupied area is 0.93 mm2 and the power dissipation is 175 mW. This ADC had a test mode at which the S/H is turned off, allowing to apply a low frequency input signal directly to first folding stage. Figure 4.38 shows the INL and DNL with and without the S/H, for fs 10 MHz and fi 1 MHz. Figure 4.39 displays the FFT (65536 points) at the same conditions. Once again a decimation of the output data is used to reduce the switching noise generated by the output pads. INL and DNL are similar in the two cases, having values in the range indicated by the Monte-Carlo simulations of the folding stages. This means that the S/H does not have a significant contribution for INL and DNL. The SNR is larger in the case at which the S/H is bypassed. Using the measurement results indicated in Fig. 4.39, it is possible to show that the S/H alone limits the SNR to 59.6 dB, which is a value slightly below the ones obtained in the simulations (see Table 4.5). Figures 4.40 and 4.41 show the results when the sampling frequency is increased to 100 MHz. A degradation of the INL and DNL is clearly visible. The results obtained in normal operation and with the S/H bypassed are somehow similar, which seems to indicate that the loss of performance originates from the folding stages. The increase of the INL is accompanied by the degradation of the THD. The values of the SNR also become worst. Figure 4.42 shows the FFT obtained when the input frequency is increased to 44 MHz and the sampling frequency is maintained at 100 MHz. An additional loss of performance is visible.

254


vOP1 vOP2 vOP3 vOP4 vON1 vON2 vON3 vON4 vOP1

1

4

2

3 vON4 vOP1 vOP2 vOP3 vOP4 vON1 vON2 vON3 vON4

Figure 4.36. Bus of the output signals of a folding stage (example for FB = 4).


255

Error Correction and Encoding Comparators

S/H

Coarse ADC

VREF Generator

Latched Comparators Folding Stages

Pre-amps

VCM Generator

Reference Ladder

Phase Generator and Buffers

1370 μm

680 μm

Bias Current Generator

Figure 4.37. Layout of the 10-bit 100 MHz folding and interpolation ADC.

As depicted in Fig. 2.4 when averaging is not used, the code transition levels are uncorrelated, originating an INL resembling a discrete wideband noise signal. When averaging is employed, consecutive code transition levels become correlated and the INL presents only “slow variations”. This is observed in the situation shown in Fig. 4.38, at which the sampling frequency is low. In Fig. 4.40, where the sampling frequency is larger, the INL is no longer that smooth – it becomes more “noisy”. This is caused by the offset voltages of the latched comparators, which are uncorrelated. Since the dynamic gain12 of the folding stages is reduced when fs becomes larger, the input referred offset of the comparators is increased. The same happens with the input referred offset voltages of the second and third folding stages. For these reasons, the offset voltages – and thus the INL/DNL – are expected to increase with sampling frequency. However, according to the extensive simulations that were performed, this does not explain the degradation observed.

12

This parameter is discussed in section 3.2.


256

DNL [LSB]

0.5

Max(DNL)= 0.32LSB

0

-0.5

1.5

Min(DNL)= -0.24LSB 128

256

384

256

384


640

768

896

1024

512

640

768

896

1024

Max(INL)= 0.91LSB

1

INL [LSB]

0.5 0 -0.5 -1 -1.5

Min(INL)= -1.14LSB 128

Output Digital Code

(a)

DNL [LSB]

0.5

Max(DNL)= 0.39LSB

0

-0.5

1.5


256

384


640

768

896

1024

256

384


640

768

896

1024

Max(INL)= 0.80LSB

1

INL [LSB]

0.5 0 -0.5 -1 -1.5


(b)

Figure 4.38. Typical INL and DNL, measured with fs 10 MHz and fi 1 MHz: (a) Normal operation; (b) S/H bypassed.


257

0 SNR=56.9dB THD=-59.9dB SINAD=55.1dB

(-0.43) ( 1)


-20

-40

(-62.36) ( 3)

-60

(-69.92) ( 2)

-80

-100

(-77.49) ( 4) (-89.54) ( 5)

(-69.63) ( 9)

-120

1

(-93.46) ( 8)

2

(-92.95) (10)

3 Frequency [Hz]

(-76.88) ( 7)

(-70.20) ( 6)

4

5

6 x 10

(a) 0

5

SNR=58.7dB THD=-59.3dB SINAD=56.0dB

(-0.48) ( 1)


-20

-40

(-62.89) ( 3)

-60

-80

-100

-120

(-71.95) ( 2)

(-70.25) ( 5)

(-76.98) ( 4)

(-66.75) ( 9)

1

(-92.12) ( 8)

2

(-69.69) ( 6)

(-95.88) (10)

3 Frequency [Hz]

(b)

4

(-75.60) ( 7)

5

6 x 10

5

Figure 4.39. FFT of the output samples, with fs 10 MHz and fi 1 MHz: The output data was decimated by a factor of 8. (a) Normal operation; (b) S/H bypassed.


258

1

Max(DNL)= 0.85LSB

DNL [LSB]

0.5

0

-0.5

-1

3


256

384

256

384


640

768

896

1024

640

768

896

1024

Max(INL)= 2.63LSB

2 INL [LSB]

1 0 -1 -2 -3



(a) 1

Max(DNL)= 0.85LSB

DNL [LSB]

0.5

0

-0.5

-1

3


256

384

256

384


640

768

896

1024

640

768

896

1024

Max(INL)= 2.03LSB

2

INL [LSB]

1 0 -1 -2 -3



(b)

Figure 4.40. Typical INL and DNL, measured with fs 100 MHz and fi 1 MHz: (a) Normal operation; (b) S/H bypassed.


259

0 (-0.54) ( 1)



-20

-40

(-58.36) ( 2)

-60

(-59.88) ( 3) (-65.94) ( 9)

-80

(-71.79) ( 4)

(-64.37) ( 8)

(-60.19) ( 5)

(-65.77) ( 7)

(-61.79) ( 6)

(-72.87) (10)

-100

-120

1

2

3 Frequency [Hz]

4

5

6 x 10

6

(a) 0


(-0.50) ( 1)


-20

-40

(-58.91) ( 2)

-60

(-59.18) ( 3)

(-64.89) ( 8)

(-64.75) ( 9)

-80

(-73.67) (10)

(-70.84) ( 5)

(-68.86) ( 7)

(-62.16) ( 6)

(-89.64) ( 4)

-100

-120

1

2

3 Frequency [Hz]

(b)

4

5

6 x 10

6

Figure 4.41. FFT of the output samples, with fs 100 MHz and fi 1 MHz: The output data was decimated by a factor of 8. (a) Normal operation; (b) S/H bypassed.


260

0 (-0.43) ( 1)



-20

-40 (-50.14) ( 3)

(-54.86) ( 2)

-60 (-71.46) ( 4)

(-74.90) ( 5)

-80 (-64.42) (-61.41) ( 8) ( 6)

-100

-120

1

2

(-66.37) ( 9)

(-89.96) (10)

3 Frequency [Hz]

4

(-66.60) ( 7)

5

6 x 10

6

Figure 4.42. FFT of the output samples, with fs 100 MHz and fi 44 MHz: The output data was decimated by a factor of 8.

Chapter 5 Offset Cancellation Methods 5.1

INTRODUCTION

The previous chapters presented the complete theoretical study of the averaging technique, and the description of two ADCs using it. Although averaging may accomplish a significant offset reduction, there are a number of tradeoffs (see sections 3.5.4 to 3.5.10) and practical limitations (for example signal headroom at low supply voltages) that restrict its effectiveness. Moreover, this technique is not applicable to latched comparators.1 To ensure that their offset voltages have a negligible impact on the linearity of the ADC, the stages preceding them must have a reasonably high gain. Averaging has been commonly used in flash and in folding and interpolation converters, but not in two-step ADCs. This happens because the offset reduction is achieved by averaging the random deviations of many components. Therefore, it is only effective when the stages being averaged have a significant number of differential pairs, as in flash and folding ADCs. The fine flash sub-converters existing in two-step subranging ADCs usually have a small resolution – therefore, only a few pre-amplifiers – but must exhibit very low offset voltages. Averaging is not advantageous in this situation. The analog sampling capability inherent in CMOS technologies, provides the means whereby offsets can be sensed, stored in capacitors, and subtracted from the input. However, when a MOS switch is off, there are leakage currents at the pn junctions of its drain and source terminals. Moreover, gate currents are becoming increasingly relevant in sub 0.1 μm technologies [120]. All these currents discharge the sampled offset value, therefore forcing to its periodic sensing and storage. Several offset cancellation techniques are currently employed in the pre-amplifiers of high-speed flash [29, 31–34] and two-step subranging ADCs [43, 51, 53, 55–60]. As will be shown in the next sections, there are practical limitations to the amount of offset reduction that can be achieved with these techniques. Moreover, most of them are not usable 1

The authors of [24] also apply averaging to latched comparators. However they use static comparators (see [3, 4] for a discussion on the existing types of comparators), and the situation ends up being similar to the one found in pre-amplifiers.

P.M. Figueiredo and J.C. Vital, Offset Reduction Techniques in High-Speed Analog-to-Digital Converters, © Springer Science + Business Media B.V. 2009

261

262


in folding circuits, because these have one output but multiple inputs, each with an associated offset voltage. Finally, the existing offset cancellation methods cannot be easily adapted to remove the offset voltage of latched comparators. Section 5.2 presents an overview of the operation and limitations of existing offset cancellation methods. The combination of the two new techniques proposed in section 5.3 overcomes those limitations, cancelling the offset voltage of the complete comparator chain, and presenting practically no residual offset. Minimum size devices can then be used, thus maximizing speed and minimizing power dissipation. The last section of this chapter describes a 6-bit 1 GHz ADC [6] that employs the techniques mentioned above. This converter uses a two-step subranging architecture, being implemented in a 90 nm CMOS technology, and supplied at 1.2 V. An excellent linearity is obtained with an extremely low power dissipation of 55 mW, thus confirming the effectiveness of the offset cancellation methods proposed in this chapter. This ADC also employs a new reference voltage selection method, which guarantees the fast selection of the important reference voltages for the fine sub-converters, and halves the number of switches connected to the resistive ladder. This technique allows to overcome the main speed bottleneck of the two-step architecture. To the best knowledge of the authors, this is the highest sampling frequency two-step converter ever presented.

5.2

OFFSET CANCELLATION TECHNIQUES

This section presents the techniques currently utilized in high-speed ADCs to reduce the offset voltages of the circuits preceding the comparators. Their operation and practical limitations are described, and the residual offset voltages are calculated.

5.2.1

Input Offset Storage (IOS)

Figure 5.1 illustrates the application of the Input Offset Storage (IOS) technique to the comparator chain composed of a pre-amplifier, offset storage capacitors (CS) and a latched comparator. CP is the parasitic capacitance at each charge conservation node, which includes: the input capacitance of the pre-amplifier, parasitic capacitances at the

Chapter 5: Offset Cancellation Methods

263

drains of the transistors in switches S3a/S3b, and the capacitance of metal interconnections. VCM S1a vI

S2a

ph1

CP CS

ph2

S1b

S3a

vIA CP

S2b

ph1

VCM

ph1 + -

G0

+

ph1

S3b

Figure 5.1. Input Offset Sstorage (IOS).

The comparator examines its input in ph2 – normal operation. During the offset sampling phase, ph1, the switches S2a/S2b/S3a/S3b turn on, resetting the input and closing a unity gain loop around the pre-amplifier. In this situation its differential input voltage, GV (5.1) vIA = 0 OSa , 1 + G0 is stored on the capacitors. In (5.1) G0 is the DC gain of the pre-amplifier, and VOSa is its offset voltage. Note that vIA approaches VOSa for high G0. When a MOS transistor is turned off, the charges in its conducting channel are released and removed through the MOS source and drain terminals2 [121, 122]. In this way, when S3a/S3b open their transistors inject a certain amount of charge into the capacitors. The mismatches between S3a and S3b cause a difference Δq in the injected charges, therefore disturbing the (differential) voltage sampled in CS. The offset voltage of the latched comparator, VOSl, is not cancelled by this technique. To refer it to the input, in addition to the pre-amplifier gain one must also consider the attenuation introduced by the capacitive divider formed by CS and CP. Thus, the introduction of offset storage capacitors actually increases the contribution of VOSl. The total residual offset is ⎛ C ⎞⎡ V V ⎤ Δq . (5.2) VOS = ⎜⎜⎜1 + P ⎟⎟⎟ ⎢ OSa + OSl ⎥ + C S ⎠⎟ ⎣⎢ 1 + G0 G0 ⎦⎥ C S ⎝

2

The fraction of charges that flows to substrate can usually be neglected [122].


264

This offset can be minimized by enlarging the gain of the pre-amplifier, G0, but this reduces its settling speed. The pre-amplifiers of fast ADCs are normally simple differential pairs with resistive loads, having G0 < 10. It is important to make CS significantly larger than CP to decrease the CP/CS term, which originates from the capacitive attenuation mentioned above. Moreover, VOS is ultimately limited by the charge injection of the switches, whose effect can only be reduced by increasing CS. Figure 5.2(a) shows how this technique is implemented in practical high-speed ADCs [29, 55, 56]: in addition to storing the offset voltage, the capacitors also sample the input signal and subtract it from the reference voltages, VRP and VRN. The input signal and the offset voltage of the pre-amplifier are sampled simultaneously, during ph1. To avoid signal dependent charge injection, the switches that close the unity gain loop around the preamplifier are opened slightly before the ones connected to the input signal (bottom plate sampling). VRP vIP

ph1'

ph2

CP ph1

vIN

CS CP

VRN

+ -

G0

+

ph1

ph2

ph1

ph1'

ph1'

(a) VRP vIP

ph1

CP ph2

vIN VRN

ph2 ph1'

CS CP

ph1

(c) + -

G0

ph1'

+

ph1

(b)

Figure 5.2. Practical implementation of IOS: (a) sampling the input voltage; (b) sampling the reference voltages; (c) phases.

VRP and VRN are applied to the capacitors during ph2, which then provide to the pre-amplifier the subtraction between the input, the reference voltages and G0VOSa . At that phase the pre-amplifier performs 1 + G0


265

the amplification so that, in the subsequent ph1, the latched comparator regenerates. Figure 5.2(b) shows another possible implementation [33, 56, 60], where the offset and the reference voltages are sampled in ph1, and the capacitors are connected to the input signals during ph2. This solution is equivalent to the one of Fig. 5.2(a), except that the input signal sampling, essential in any ADC, must be made somewhere else. In spite of these implementation differences, the offset voltage is given by (5.2). As mentioned before, a large CS decreases the capacitive attenuation and the effect of charge injection mismatches. However, in the solution of Fig. 5.2(a) it leads to a high input capacitance and, in the implementation of Fig. 5.2(b), the settling time of the reference voltages will be degraded.

5.2.2

Output Offset Storage (OOS)

Figure 5.3 illustrates the application of the Output Offset Storage (OOS) technique. The offset sampling phase is, again, ph1, where switches S2a/S2b/S3a/S3b turn on. VCM S1a vI

S2a

VCM

ph1 +

ph2 -

S1b

S2b

S3a

ph1

S3b

ph1

CP

G0

+

vOA

CS CP

ph1

VCM

VCM

Figure 5.3. Output Offset Storage (OOS).

S2a/S2b and S3a/S3b force, respectively, a zero differential voltage at the inputs of the pre-amplifier and of the latched comparator. The preamplifier amplifies its own offset voltage, vOA = G0VOSa , which is stored on the capacitors. This eliminates the contribution from VOSa to the residual offset, because a zero voltage difference at the pre-amplifier input yields a zero input voltage for the latched comparator. When S3a and S3b open, their mismatches produce a difference Δq in the charges they inject into the capacitors, therefore disturbing the sampled value. VOSl is not stored in the capacitors and, thus, it is not cancelled by OOS. The residual offset is

266


⎛ C ⎞V Δq , (5.3) VOS = ⎜⎜1 + P ⎟⎟⎟ OSl + ⎟ ⎜⎝ C S ⎠ G0 G0C S which, for the same G0, is smaller than the one obtained using IOS, (5.2). Note that the charge injection mismatch is now divided by G0, because the capacitors are after the pre-amplifier. Once again the residual offset voltage is minimized by increasing G0. However, in addition to reducing the operating speed, a high G0 causes the pre-amplifier to saturate during ph1, if G0VOSa exceeds the maximum output voltage swing. The offset voltage would not be correctly stored in this case. Thus, usually G0 < 10. Having a large CS is desirable to reduce the attenuation introduced by the capacitive divider, and the effect of charge injection mismatches. However it limits the settling speed of the pre-amplifier in the offset sampling phase. In the amplification phase the capacitance “seen” by the pre-amplifier corresponds to series of CS and CP,3 which is smaller than CP – the settling is faster. As shown in the previous section, a switched capacitor network existing before the pre-amplifiers can subtract the input and reference voltages. This is a fundamental operation in any comparator of a parallel type ADC. With IOS one can use the capacitors that are already there to perform the offset sampling. As shown in Fig. 5.4, with OOS either double differential pairs (see Fig. 4.22) are used, or a switched capacitor network is added before the pre-amplifier. This last solution also implements the sampling operation, but introduces an additional capacitive divider and a new source of offset – the charge injection mismatches between the switches connected to the input nodes of the pre-amplifier.

3

The parasitic capacitance from the bottom plate of CS to the substrate (GND) can take values around 0.2CS. If the bottom plate of CS was connected to the comparator input, the attenuation of the capacitive divider would increase. Thus, it is usually connected to the outputs of the preamplifier, affecting its settling speed in both phases.


267

VCM vIP

ph2

VRP VRN vIN

ph1' ph1

ph1 ph2

+ + -

CP G0

-

CS

+

ph1

CP ph1'

Double differential pair

ph1'

VCM

ph2

(a) VCM VRP vIP

ph2

CP1 ph1

vIN VRF

VCM

ph1'

ph1'

CP2

+

CS1

-

CP1

(c)

G0

+

CS2 CP2 ph1'

ph1' ph2

VCM

VCM

(b)

Figure 5.4. Practical implementation of OOS in comparators used on parallel type ADCs: (a) utilization of a double differential pair; (b) addition of a sampling network; (c) phases.

5.2.3

Multi-stage Offset Storage

The techniques just described may not suffice if the latched comparator has a large offset voltage: the gain in OOS cannot be very large, and a single high gain IOS stage is slow. A possible solution is to use several fast pre-amplifiers with low gain. Figure 5.5 shows NPstg cascaded pre-amplifier stages using OOS, preceding the latched comparator. As in the single stage case, the offset voltages of all pre-amplifiers are cancelled. To obtain the input referred offset voltage of the latched comparator, one must divide VOSl by the gain of all preceding stages. Considering also the charge injection mismatches in each stage, allows to write the residual offset as4

4

In the evaluation of this expression note that

0

∏ a [ j ] = 1, for any a[j]. j =1


268

Δq [1] /C S [1] VOSl + + ⎛ ⎞ ⎡ ⎤ G0 [1] ⎛ ⎞ C N ⎟ ⎜ 1 C [ ] S Pstg ⎢ ⎥ ⎟ S ⎣ ⎦ ⎜ ⎤ ⎟⎟ ⎜⎜G [1] ⎟⎟ ... ⎜G ⎡N ⎜⎝⎜ 0 C S [1] + C P [1] ⎠⎟ ⎜⎜ 0 ⎣⎢ Pstg ⎦⎥ C S ⎡⎢N Pstg ⎤⎥ + C P ⎡⎢N Pstg ⎤⎥ ⎟⎟⎟ ⎠ ⎜⎝ ⎣ ⎦ ⎣ ⎦ Δq [2 ] /C S [2 ] + + ... + ⎛ ⎞⎟ C S [1] ⎜ ⎟ ⎜ G0 [2 ]⎜G0 [1] ⎟ ⎜⎝ C S [1] + C P [1] ⎠⎟

VOS =

+

Δq ⎡⎣⎢N Pstg ⎤⎦⎥ /C S ⎡⎣⎢N Pstg ⎤⎦⎥ ⇔ ⎛ ⎞⎟ ⎡N Pstg − 1⎤ ⎛ ⎞ C ⎜ C 1 [ ] S ⎢ ⎥ ⎟ ⎟ S ⎣ ⎦ ⎟⎟ ... ⎜⎜G0 ⎡N Pstg − 1⎥⎤ ⎟ G0 ⎡⎢⎣N Pstg ⎥⎦⎤ ⎜⎜⎜G0 [1] ⎦ C ⎡N ⎤ ⎡ ⎤ ⎟⎟ ⎜⎝ C S [1] + C P [1] ⎟⎠ ⎜⎜⎜⎝ ⎢⎣ S ⎣⎢ Pstg − 1⎦⎥ + C P ⎣⎢N Pstg − 1⎥⎦ ⎟ ⎠

⇔ VOS =

VOSl

N Pstg

C [i ] ∏ G0 [i ] C [i ] S+ C [i ] S P i =1

+

N Pstg

∑ i =1

Δq [i ] /C S [i ] . ⎛ i −1 ⎞⎟ CS [ j ] ⎜ G0 [i ]⎜⎜∏ G0 [ j ] ⎟⎟⎟ C S [ j ] + C P [ j ] ⎟⎠ ⎜⎜⎝ j =1

(5.4)

Comparing (5.4) to (5.3) leads to the conclusion that, as expected, the contribution from the offset voltage of the latched comparator is reduced. However, the offset caused by the charge injection of the first stage switches, S1a/S1b, remains unchanged. Moreover there are additional contributions from the charge injection mismatches in the subsequent stages. Therefore the resultant offset may not be much smaller than the one achieved with single stage OOS. VCM

VCM

S0a

S1a +

vI

G0[1]

-

S0b VCM

VCM

CP[1] +

S2a +

G0[2]

CS[1]

-

CP[1] S1b VCM

VCM

CP[2] +

SNPstga +

CP[NPstg] -

G0[NPstg]

CS[2]

-

CP[2]

+

S2b VCM

CS[NPstg] CP[NPstg]

SNPstgb VCM

Figure 5.5. Multi-stage output offset storage.

A way of reducing the effect of charge injection mismatches, is to turn off the offset sampling switches as depicted in Fig. 5.6 [124] – sequential clocking. S1a/S1b are opened first, and the difference of the charges they inject, Δq[1], disturbs the input voltage of pre-amplifier 2. This can be regarded as a change in its offset voltage. Consequently, the offset caused by Δq[1] is amplified by pre-amplifier 2, and stored on the capacitors at its outputs. Later, switches S2a/S2b, S3a/S3b,...,SNPstga/SNPstgb are opened successively, so that the only charge injection affecting the output is due to switches SNPstga/SNPstgb. The residual offset voltage becomes


VOS =

VOSl N Pstg

∏ G0 [i ] C i =1

C S [i ] S [i ] + C P [i ]

+

269

Δq ⎡⎢⎣N Pstg ⎤⎥⎦ /C S ⎡⎢⎣N Pstg ⎤⎥⎦ , (5.5) ⎛N Pstg −1 ⎞⎟ C j [ ] ⎜ S ⎟⎟ G0 ⎡⎣⎢N Pstg ⎤⎦⎥ ⎜⎜ ∏ G0 [ j ] C S [ j ] + C P [ j ]⎟⎟⎠ ⎜⎝ j =1

which is smaller than (5.4), and represents an effective improvement with respect to (5.3). Note that (5.5) is only valid if the delay between the edges of the clock pulses controlling S1a/S1b to SNPstga/SNPstgb is long enough to allow the complete offset storage on the capacitors of the subsequent pre-amplifiers. This is a serious restriction to the use of sequential clocking in high-speed converters. S1a/S1b S2a/S2b

SNPstga/SNPstgb S0a/S0b t

Figure 5.6. Sequential clocking in multi-stage comparators.

A simple technique that can be applied to high-speed comparators using OOS, and eliminates the offset caused by charge injection mismatches will be presented in section 5.3.2. Figure 5.7 shows NPstg cascaded pre-amplifier stages using IOS. The sequential clocking scheme presented in Fig. 5.6 could, again, be utilized to cancel the contributions of all charge injection mismatches, except the one from SNPstga/SNPstgb. However, as stated above, this solution cannot be used in high-speed ADCs. In the following analysis it is considered that all sampling switches open simultaneously, introducing charge injection errors that are not compensated. VCM

S2a

S1a CP[1]

vI

CP[2]

+

G0[1]

CS[1]

-

S0b VCM

+

+

G0[2]

CS[2]

-

SNPstga

CP[NPstg]

S0a +

+

CS[NPstg]

CP[NPstg]

-

CP[2]

CP[1] S1b

S2b

Figure 5.7. Multi-stage input offset storage.

-

G0[NPstg]

SNPstgb

+


270

The unity gain closed loop around the ith pre-amplifier makes it have a differential input/output voltage of G0 [i ]VOSa [i ] . Except for 1 + G0 [i ] the last amplifier, this voltage is stored simultaneously on the capacitors that precede and follow it, thus cancelling its offset. The input referred offset of the latched comparator is obtained as before. The residual offset voltage is, thus, VOS =

VOSl

N Pstg

C S [i ] ∏ G0 [i ] C [i ] + C P [i ] S i =1

N Pstg

+

Δq [i ]/C S [i ]

∑ ⎛i−1 i =1 ⎜ ⎜⎜∏G0 [ j ] ⎜⎜ C ⎝ j =1

+

VOS ⎡⎣⎢N Pstg ⎤⎦⎥

(

⎞⎟ CS [ j ] ⎟⎟ ⎟⎟ S [ j ] + C P [ j ]⎠

N Pstg −1

) ∏ i =1

G 0 ⎡⎢⎣N Pstg ⎤⎥⎦ + 1 .

C S [i ] G 0 [i ] C S [i ] + C P [i ]

+

(5.6)

When using multi-stage (instead of single-stage) IOS, the contributions from mismatches in the pre-amplifiers and the latched comparator are significantly reduced. It is even possible to eliminate VOS[NPstg] from the residual offset, by adding another capacitor between the last pre-amplifier and the latched comparator [43]. However the offset caused by the charge injection of the first stage switches – S1a/S1b – remains unchanged, and there are additional contributions from the charge injection mismatches in subsequent stages. The most commonly used technique is multistage IOS [31, 32, 34, 42, 43, 51, 53, 57, 59]. Reference [35] closes a unity gain feedback loop around two pre-amplifier stages. This solution is equivalent to a single-stage IOS having a high gain amplifier, but stability must be carefully evaluated. Reference [60] combines OOS in the first two stages with IOS in the last one. NPstg is usually between 2 and 4. Since sequential clocking cannot be used in high-speed ADCs, averaging is sometimes employed to reduce the offsets caused by charge injection mismatches [42, 60]. The authors of these two references have also conceived a pipelining scheme, to avoid having all stages settling simultaneously, thereby increasing the operating speed. Reference [60] describes the tradeoffs associated to this solution. In conclusion, multistage offset sampling techniques reduce the offsets of latched comparators and pre-amplifiers, but increase the contribution from charge injection mismatches.


5.2.4

271

Utilization of Auxiliary Differential Pairs

The techniques described in the previous sections employ capacitors in the signal path, that store and cancel the offset voltages. Nonetheless, their presence introduces attenuation and decreases the settling speed of the pre-amplifiers. In IOS a large CS also degrades the settling of the reference voltages, or originates a significant input capacitance. An alternative approach is described in this section, which uses an auxiliary differential pair that isolates the signal path from the offset storage capacitors, while performing offset cancellation. Figure 5.8 presents a single-ended model of such implementation. The auxiliary differential pair, gm2, is connected to the output of the main differential pair, gm1. R0 is the load resistance. As one of the plates of CS is connected to GND, this capacitor may be implemented with a MOS transistor, occupying less area. VOS1

vI

S2

ph1

i1

+

ph2 -

gm1

vOA

VOSl + -

+ -

S1

R0

+ -

VOS2

-

vS CS

i2

+

gm2 S3 ph1

Figure 5.8. Offset cancellation using an auxiliary differential pair (single-ended model).

In the offset sampling phase, ph1, switches S2 and S3 are turned on, and a unity gain loop is closed around gm2, charging CS. In normal operation S1 is on, and the auxiliary differential pair adds a DC current to the output of the main amplifier, that (ideally) cancels its offset voltage. The residual offset voltage obtained with this technique will now be calculated. The input of gm1 is grounded during ph1, which means that i1 = gm1 (−VOS 1 ). The output current of the auxiliary differential pair is i2 = −gm 2 (vS + VOS 2 ) = −gm 2 (vOA + VOS 2 ), and the output voltage is given by vOA = R0 (i1 + i2 ).

(5.7) (5.8) (5.9)

272


Solving these three equation leads to the voltage being sampled in CS, during this phase, G01VOS 1 + G02VOS 2 , (5.10) G02 + 1 where G01 and G02 are, respectively, the gain of the main and auxiliary stage, G01= gm1R0 and G02= gm2R0. The charge injected by S3 when in opens at the end of ph1, disturbs vS = vOA = −

the voltage at the capacitor, setting it to5 G01VOS 1 + G02VOS 2 Δq . (5.11) + G02 + 1 CS In normal operation the input voltage is applied by S1, and the output current of the main differential pair becomes (5.12) i1 = gm1 (vI −VOS 1 ). The voltage at the capacitor is given by (5.11), resulting in ⎛ G V ⎞ + G02VOS 2 Δq (5.13) + +VOS 2 ⎟⎟⎟. i2 = −gm 2 ⎜⎜⎜− 01 OS 1 G02 + 1 CS ⎝ ⎠⎟ Solving (5.9), (5.12) and (5.13) simultaneously, leads to the output voltage of the pre-amplifier, G V + G02VOS 2 Δq . (5.14) vOA = G01vI − 01 OS 1 − G02 G02 + 1 CS The residual offset corresponds to the input voltage that makes the latched comparator stand at its decision threshold, VOSl, V VOS 2 V g Δq VOS = OS 1 + + OSl + m 2 . (5.15) g G02 + 1 G01 + m 1 G01 gm 1 C S gm 2 Once again VOSl appears divided by the gain of the main amplifier, because this technique does not compensate the offset of the latched comparator. The charge injection term is weighted by the ratio of the transconductances of the auxiliary and main differential pairs – in a typical design one has gm2/gm1 = 1/3 to 1/10. A large CS reduces the charge injection term, but affects the output voltage settling speed during ph1. The offset voltage of the main differential pair is divided by, roughly, the gain of the auxiliary stage. VOS2 is divided by the sum G01 and gm1/gm2 (which is larger than one). vS = −

5

As seen in the previous sections, in a differential design Δq is the difference between the charges injected by the pair of sampling switches.


273

This technique has been used in operation amplifiers [123] and highspeed flash [33] and folding ADCs [85].

5.3

NEW OFFSET CANCELLATION TECHNIQUE

All previously described techniques present a residual offset voltage, that can be reduced by increasing the gain of pre-amplifiers. However this either makes them slower or forces the power dissipation to increase. The contributions from charge injection mismatches are reduced by using larger offset sampling capacitors6; nonetheless, this also degrades the settling of the pre-amplifiers. Moreover, in IOS a large CS affects the settling of the reference voltages, or originates a significant input capacitance. Most of the techniques just described employ capacitors in the signal path, which form capacitive dividers with the parasitics existing at the charge conservation nodes, causing attenuation. Once again, increasing the offset sampling capacitors eases this problem. None of those techniques reduces the offset voltages of the latched comparators. The only way of making them negligible is to implement a high gain between the input and the latched comparators, possibly using several cascaded pre-amplifier stages. For all these reasons there is a tradeoff between accuracy, speed and power dissipation. This section starts by presenting a technique to eliminate the offsets of the pre-amplifiers and latched comparators. This allows to use minimum size devices, thereby maximizing the operating frequency and minimizing the power dissipation. Moreover, since the offsets of the latched comparators are eliminated, the gain of the pre-amplifiers becomes less relevant. The ADC described in section 5.4 employs this technique in the fine sub-converters. In that ADC, there is a switched capacitor sampling network before each pre-amplifier. When the mismatched sampling switches open there will be different charges injected into the capacitors, causing an offset voltage that is not compensated by the method mentioned above (it eliminates all offset voltages from the pre-amplifier onwards). A

6

In some cases (single and multi-stage OOS, multistage IOS), increasing the gain of the pre-amplifiers also helps. As mentioned above, this leads to the reduction of their settling speed or to the increase of power dissipation.


274

simple way of removing these charge injection differences is presented in section 5.3.2. The simultaneous utilization of these two techniques originates a comparator that is virtually offset free.

5.3.1

Offset Calibration in the Pre-amplifier and Latched Comparator

Figure 5.9 presents a single-ended model of the technique being proposed. In addition to the main differential pair, which has the transconductance gm1, there is an auxiliary amplifier, gm2, whose input voltage is held by CS. A discrete time feedback loop, composed of the latched comparator, the auxiliary differential pair, and the switched capacitor network preceding it, adjusts the calibration voltage, vCAL, to accomplish the offset cancellation. VOS1

vI

-

S2

VMIN

i1

vOA

VOSl

R0

VOS2

S4

+

+ -

VMAX

S3 S5

gm1

+ -

+

+ -

S1

CP

vCAL

-

gm2

i2

CS

Selection Logic

Figure 5.9. Proposed offset cancellation technique (single-ended model).

The auxiliary amplifier will, for now, be ignored (i2 = 0). In normal operation S1 is on, and the input voltage is applied to the main differential pair. During the offset sensing phase, S2 shorts the input of gm1 to GND, which amplifies its own offset yielding the output voltage (5.16) vOA = −gm 1R0VOS 1. If the latched comparator is now triggered, it will decide high if −gm 1R0VOS 1 > VOSl and low otherwise (note that the threshold of the latched comparator is VOSl). Thus, this decision is determined by the offset voltage of the complete chain – pre-amplifier plus latched comparator.


275

A simple selection logic takes this result and adjusts the calibration voltage at the input of the auxiliary differential pair. This is made by pre-charging CP to either VMAX or VMIN, depending on the decision of the comparator, and then switching CP to CS by turning S3 on. CP is not an explicit device – it is the parasitic capacitance at the node. Therefore CS can be made much larger than CP, and the calibration voltage is adjusted in small steps – discrete amplitude adjustment. When vOA is above the threshold of the comparator it decides high. Then, CP is pre-charged to VMAX making vCAL increase, thus reducing vOA towards VOSl. In this way, the calibration voltage is adjusted in order to place the latched comparator at its threshold point, when the input voltage of the pre-amplifier is zero. The offset voltages from the pre-amplifier onwards are, thus, eliminated – we denote VCALopt as the calibration voltage value at which this occurs. This situation is achieved after the latched comparator has been triggered several times, i.e. after several offset sensing phases. Thereafter, the comparator decides high and low alternately, maintaining vCAL near VCALopt. Note that this is accomplished independently of VOS1 and VOS2. The evolution of the calibration voltage throughout the offset sensing phases will now be analyzed. The consequences of employing a discrete amplitude adjustment of vCAL will also be examined. The charge injection of S3 will, for now, be ignored. This calibration method uses a discrete time feedback loop, which updates vCAL after each offset sensing phase. To study the circuit behavior in those phases, the voltages and currents should be considered discrete time quantities. We denote vOA[n] as the output voltage of the pre-amplifier at the nth offset sensing phase, where the calibration voltage has been adjusted n times. In this notation vOA[0] corresponds to the initial condition, before any adjustment. Considering vCAL[0] = 0, (5.17) implies that (5.18) i2 [0] = −gm 2VOS 2 . The output current of the main differential pair only depends on its offset, (5.19) i1 = −gm 1VOS 1 . The initial output voltage is, therefore, vOA [0] = −R0 (i1 + i2 [0]) = −R0 (gm 1VOS 1 + gm 2VOS 2 ).

(5.20)


276

The nth comparator decision indicates if vOA[n–1]–VOSl is positive or negative. As a result of that, CP is then pre-charged to either VMAX or VMIN. Considering VMAX = ΔVCAL/2 and VMIN = –ΔVCAL/2, the voltage applied to CP is sign function,7

Δ VCAL 2

sgn (vOA [n – 1 ] – VOSl ) , where sgn(x) is the

⎧⎪ 1 if x > 0 ⎪⎪ ⎪ sgn (x ) = ⎪⎨ 0 if x = 0 ⎪⎪ ⎪⎪−1 if x < 0. ⎪⎩

(5.21)

As a consequence of the nth comparator decision, the calibration voltage changes from vCAL[n–1] to vCAL [n ] =

CS CS + CP

vCAL [n − 1] +

CP

Δ VCAL

CS + CP

2

sgn (vOA [n − 1] − VOSl ).

(5.22)

The modification on the calibration voltage between phases n−1 and n, i.e. the calibration voltage step, is vCAL [n ] − vCAL [n − 1] =

which depends on:

CP CS +CP

⎡ ΔVCAL ⎤ ⎢ sgn (vOA [n − 1] −VOSl ) − vCAL [n − 1]⎥ , ⎢⎣ 2 ⎥⎦

(5.23)

The outcome of the comparator regarding vOA at phase n−1, through the sgn (vOA [n − 1] −VOSl ) term

The calibration voltage value at the offset sensing phase n−1

Let us consider that vCAL lies somewhere between VMAX and VMIN, i.e. within ±ΔVCAL/2. Then the term depending on the decision of the ΔVCAL comparator, sgn (vOA [n − 1] −VOSl ) , is always larger than 2 vCAL [n − 1]. Thus, although the calibration voltage step depends on vCAL [n − 1], whether it increases or decreases is always determined by the outcome of the comparator. The fact that vCAL is adjusted in discrete steps, prevents it from being exactly at VCALopt, although it remains near that value. This causes small fluctuations on the code transition levels of the ADC. As 7

Due to the electrical random noise, the latched comparator is never exactly at its threshold.


277

each comparator, and thus each code transition level, has fluctuations which are uncorrelated between them and to the input signal, an effect similar to random noise is produced. The magnitude of those fluctuations will now be quantified. In the situation where vCAL [n ] ≈ VCALopt , i.e. when the calibration voltage is around the value that makes vOA = VOSl, (5.23) can be approximated by vCAL [n ] − vCAL [n − 1]

When

VCALopt = 0

CP CS + CP

the

⎡ ΔVCAL ⎤ ⎢ sgn (vOA [n − 1] −VOSl ) −VCALopt ⎥ . (5.24) ⎢⎣ 2 ⎥⎦

calibration

voltage

is

changed

by

CP ΔVCAL , every time the comparator decides high or low. CS + CP 2 Let us now address the situation where VCALopt is slightly below ΔVCAL/2, i.e. VCALopt = ΔVCAL/2–εV with ΔVCAL/2 εV. When the comparator decides high, vCAL is increased by ±

⎡ ΔVCAL ⎛ ΔVCAL ⎞⎤ CP CP ⎢ (5.25) − ⎜⎜⎜ − εV ⎟⎟⎟⎥ = ε , ⎢ ⎥ ⎝ 2 ⎠⎦ C S + C P V CS + CP ⎣ 2 which is a small quantity. When it decides low, the calibration voltage step is ⎡ ΔVCAL ⎛ ΔVCAL ⎞⎤ CP CP ⎢− − ⎜⎜⎜ − εV ⎟⎟⎟⎥ − ΔVCAL , (5.26) ⎢ ⎥ ⎝ ⎠ CS + CP ⎣ 2 2 CS + CP ⎦ which corresponds to twice the value found when VCALopt = 0. This is the worst case (largest) calibration voltage step. In this situation the ADC code transition level detected by that comparator, is deviated by g CP (5.27) − m2 ΔVCAL . gm 1 C S + C P This example unveils a relevant detail about this offset cancellation method: when VCALopt differs from 0, the calibration voltage varies by different amounts depending on the outcome of the latched comparator. The most extreme situation is the one just described. If vCAL reaches ΔVCAL/2, then εV = 0 and according to (5.25) the calibration voltage cannot not further increase, even if the comparator decides high. Thus, vCAL always lies between ±ΔVCAL/2. Offset voltages that require a VCALopt out of this range are not cancelled: it is possible to correct (input referred) offset voltages up to g ΔVCAL . (5.28) VCALrange = ± m 2 gm 1 2

278


Note that the maximum code transition level adjustment step, (5.27), corresponds to VCALrange divided by 1/2(CS/CP + 1). One can easily implement CS/CP > 200, which yields 1/2(CS/CP + 1) > 100.5; consequently it is possible to make a fine adjustment of the offset voltage using the technique being described. The calibration range is determined by running Monte-Carlo simulations and obtaining the maximum offset voltage of the uncalibrated comparator chain.8 The code transition level deviation given by (5.27) must be made small. Using minimum size transistors for S3–S5 minimizes CP. Then three parameters can be adjusted: gm1/gm2, CS and ΔVCAL. As shown above, gm1/gm2 and ΔVCAL also determine the offset calibration range. Each of the techniques discussed in the previous sections had some of the following tradeoffs associated to the increase of the offset sampling capacitors: reduction of the settling speed of the pre-amplifiers either on normal operation or in the offset sampling phase, increase of the input capacitance of the ADC, degradation of the settling of the reference voltages. In this case there is no tradeoff, and CS can be freely

increased.9 It should be implemented with a MOS transistor, to minimize the occupied area. The output voltage expression will now be derived. Equation (5.22) yields vCAL[n] as a function of vCAL[n – 1] which, in turn, depends on vCAL[n – 2], and so on. Following this process, results in (note that vCAL[0] = 0) ⎞⎟n −1−k CP ΔVCAL n −1 ⎛⎜ C S ⎟ sgn (vOA [k ] −VOSl ) . (5.29) ⎜ ∑ CS + CP 2 k =0 ⎜⎜⎝C S + C P ⎟⎟⎠ The output current of the auxiliary differential pair is (5.30) i2 [n ] = −gm 2 (vCAL [n ] + VOS 2 ). Substituting (5.19), (5.29) and (5.30) in the output voltage expression, (5.31) vOA [n ] = R0 (i1 + i2 [n ]), vCAL [n ] =

and having (5.20) in consideration, leads to vOA [n ] = vOA [0] − gm 2R0

CP ΔVCAL CS +CP 2

⎞⎟n −1−k ⎜ CS sgn (vOA [k ] −VOSl ). (5.32) ⎜ ∑ ⎜⎜ ⎟⎟⎟ k =0 ⎝C S + C P ⎠ n −1 ⎛

8

The offset voltages can take arbitrarily large values, but with a reduced probability. The calibration range must be several times larger than the uncalibrated σ(VOS) to guarantee high yield.

9

The only downside of enlarging CS is the increase of the ADC startup time.


279

This equation yields the output voltage evolution through the offset sensing phases, starting from vOA[0]. Although it does not offer much insight, it can be used to perform numerical evaluations. The case of an 8 bit ADC will considered as application example, where VFS = 1 V and, thus, VLSB = 3.91 mV. The main pre-amplifier has gm1 = 500 μS and an offset voltage of VOS1= 10.5 mV. In this example the offset of the latched comparator is VOSl = 5.63 mV and R0 = 5 kΩ. The total input referred offset voltage is

VOSl 5.63 × 10−3 = 10.5 × 10−3 + gm 1R0 2.5 = 12.75 mV = 3.26 LSB. (5.33) The offset calibration method being described is now applied. It is considered that gm2 = gm1/4 and VOS2 = –20.5 mV; the offset sampling capacitance has CS = 750 fF, CP equals 2.5 fF, and ΔVCAL = 0.2 V. According to (5.28) VCALrange equal ±25 mV, i.e. 6.4 LSB. The evolution of the output voltage of the pre-amplifier, throughout the offset sensing phases, is shown in Fig. 5.10. It starts from the initial value indicated by (5.20), –13.4 mV, and goes towards VOSl, which is VOSuncalibrated = VOS 1 +

reached at the 110th offset sensing phase. Thereafter vOA always remains near VOSl. Figure 5.10(c) shows that the discrete amplitude adjustment of the calibration voltage causes peak-to-peak output voltage variations of 415 μV, that originate negligible fluctuations on the code transition 415 μ V levels: = 166 μ V = 0.04 LSB . gm 1R0 The fact that vCAL varies by a different amount, depending on whether the comparator output is high or low, is reflected in the output voltage variations, being clearly visible in Fig. 5.10(c). The charge injection of S3 has been ignored in the former analysis, but it does not affect the calibration effectiveness. When S3 opens its charge injection modifies vCAL and, therefore, the output voltage of the pre-amplifier. In the next offset sensing phase, the comparator examines vOA which contains the contribution from the previous charge injection of S3. Therefore the next calibration voltage adjustment takes that charge injection in consideration, thus compensating it.


280

10

[mV]

0

vOA[n]

5

−5 −10 −15 0

100

200

300

400

500

600

700

800

900

1000

n (a) 5.8 5.75

[mV] vOA[n]

5.7 5.65 5.55

5.6 5.5 5.45 5.4 5.35 5.3 250

300

350

400

450

500

n (b) 5.8 5.75

vOA[n]

[mV]

5.7 5.65

VOSl

5.6

415 μ V

5.55 5.5 5.45 5.4 5.35 5.3 250

260

270

280

290

300

n (c)

Figure 5.10. Evolution of the output voltage of the pre-amplifier throughout: (a) offset sensing phases 0 to 1000; (b) offset sensing phases 250 to 500; (c) offset sensing phases 250 to 300.


281

In technique described in section 5.2.4 there was also a capacitor holding the input voltage of the auxiliary differential pair (see Fig. 5.8). In that case, the charge injection of S3 is not cancelled because it occurs when the feedback loop around the auxiliary differential pair is opened. The utilization of the discrete time feedback loop, disclosed in this section, overcomes this problem by ensuring that the charge injection is considered in the future adjustments of the calibration voltage. To guarantee a stable calibration operation, the next offset sensing phase can only happen after the previous calibration voltage adjustment has been completely performed, i.e. after S3 opens. It is also necessary to guarantee equal conditions in the offset sensing phases and in normal operation. For example the comparator cannot quantize of the input signal with S3 closed, because those are not the conditions where the offset is sensed. In previously proposed offset compensation methods it was necessary to have a large pre-amplifier gain, in order to reduce the residual offset voltage. In the technique just described there is no such need, since the offset voltage is eliminated regardless of that parameter. This allows to maximize the speed and minimize the power dissipation of the pre-amplifier. Actually, it is even possible to eliminate the preamplifier and add the auxiliary differential pair in parallel to the input differential pair of the latched comparator. This offset calibration method is employed in the fine sub-converters of the two-step subranging ADC described in section 5.4. The offset calibration is done in background, using the otherwise idle states of the fine ADCs. A possible way of employing this technique in flash ADCs is to add an extra comparator that substitutes the one currently being calibrated [31, 32]. In that case it must be ensured that the capacitors CS are not significantly discharged by the leakage currents, in the time between two consecutive calibration voltage adjustments.

5.3.2

Elimination of Charge Injection Differences

In the ADC presented in the next section, each pre-amplifier is preceded by a switched capacitor network, as represented in Fig. 5.11. The differential input signal is applied to the capacitors during ph1, when the switches S1a/S1b connect the charge conservation nodes to the internal common-mode voltage of the ADC, VCM, which has a value that guarantees the correct biasing of the pre-amplifier. S2 shorts vCP and vCN in the sampling phase. Its utilization is not strictly necessary –


282

for example, it was not mentioned in the discussion about the OOS technique – but, as will be shown, it is advantageous to use it. Sra VRP

vIP

ph2 ph1

VCM CS ph1'

S1a

ph1

vCP

Sia ph1'

Sib vIN

ph1 ph2

VRN Srb

ph1'

S2

Pre-amplifier

ph2

vCN CS ph1'

S1b

VCM

(a)

(b)

Figure 5.11. Input sampling network.

During ph2, the capacitors are connected to VRP and VRN, providing a differential output signal, vCP – vCN, that is proportional to the subtraction between the input and reference voltages. This circuit is quite versatile since it can be used with low supply voltages, it performs both the sampling operation and subtraction between input and reference voltages, and provides an AC decoupling that increases the usable input common-mode range. However, it has two undesirable characteristics: introduces attenuation, and has an offset voltage that is caused by the mismatches of the switches connected to the charge conservation nodes. Increasing CS eases both those problems, but enlarges the input capacitance of the ADC. The attenuation introduced by this circuit increases the input referred offset voltage of the pre-amplifier and latched comparator. This is not problematic in the ADC described in the next section, since the calibration practically eliminates those offset voltages. However the offset of the input sampling network is not removed by the calibration. This section presents a simple solution to do it. The time constant during the sampling phase is τS = RSAMPCS, where RSAMP is r (5.34) RSAMP = rONi + ON 2 // rON 1 , 2 and rONi, rON1 and rON2 are the on resistances of the switches Sia/Sib, S1a/S1b and S2. Thus, the presence of S2 decreases RSAMP significantly. In the sampling phase, the channel charge of the transistors in Sia/Sib depends of the input signal amplitude, in a nonlinear way. The


283

charges in S1a/S1b and S2 are input signal independent, because the voltage at their drain/source terminals is fixed – VCM. Switches S1a/S1b/S2 open first, at the falling edge of ph1′, injecting a signal independent charge into vCP and vCN. The input switches open later, at the falling edge of ph1, but their charge injection does not modify the values stored on the sampling capacitors, because these have their bottom plates floating. In this way an input signal dependent charge injection is avoided. The technique just described was proposed in [116], and is usually called bottom plate sampling. If S1a and S1b are perfectly matched, the charge injection mentioned above only causes a non-problematic common-mode shift, i.e. (vCP + vCN)/2 moves away from VCM. When there are mismatches either vCP or vCN receives more charge, and the differential output voltage is modified – an offset is introduced. One should note that the main purpose of S1a and S1b is to set the convenient common-mode voltage at the input of the pre-amplifier. The switch S2 can, alone, guarantee the input signal sampling. If S1a and S1b are opened slightly before S2, they will inject different charges into the capacitors, therefore disturbing the output voltage. However, as S2 is still on, it eliminates those charge injection differences. The sampling phase ends when S2 is turned off: since there is a single switch opening, no offset is produced. Therefore, if S1a and S1b open slightly before S2 the offset caused by charge injection differences is eliminated. The simple circuit represented in Fig. 5.12 is simulated, to verify this fact. VCM 10 fF ph1''

S1a vCP

5 kΩ VCM VDD/2 = 1.65 V

VCM

ph1'

+ -

S2 vCN

VCM

10 fF ph1''

S1b

VCM

Figure 5.12. Circuit used to evaluate the effect of charge injection mismatches.

Switches S1a/S1b/S2 are implemented with a NMOS transistor having W = 5 μm and L = 0.35 μm. The common-mode generator is represented by its Thévenin equivalent.


284

Figure 5.13 shows the results of a Monte-Carlo simulation, obtained when ph1′ and ph1′′ are coincident. As expected, the output voltage becomes different from 0 when the switches turn off. In Fig. 5.14 S1a and S1b open slightly before S2. The charge injection of S1a/S1b disturbs momentarily the output voltages, but it is successfully eliminated by S2. 5 4

vCP−vCN

[mV]

3 2 1 0 −1 −2 −3 −4 −5 4.5

5.0

5.5 t [ns] (a)

6.0

6.5

6.0

6.5

3.5

Clock phases

[V]

3.0

ph1', ph1''

2.5 2.0 1.5 1.0 0.5 0.0 4.5

5.0

5.5 t [ns] (b)

Figure 5.13. Monte-Carlo simulation results of the circuit represented in Fig. 5.12, in the case where ph1′and ph1′′ are coincident.

This technique can be applied in comparators using OOS, to eliminate the contributions of charge injection mismatches to the residual offset voltage. Note that the only existing method that can (almost) achieve this – sequential clocking (see Fig. 5.6) – can only be used in multistage pre-amplifiers, and it is too slow to be employed in highspeed ADCs. Although the implementation details differ a bit from what was just discussed, this technique is utilized in the ADC described in the next section (and presented in [6]). Recently the authors became aware that


285

the clocking scheme shown in Fig. 5.14(b) had already been used in pipeline ADCs [125, 126], but without any explanation, and in places where ensuring low offset voltages was not critical. 5 4

vCP−vCN

[mV]

3 2 1 0 −1 −2 −3 −4 −5 4.5

5.0

5.5 t [ns] (a)

6.0

6.5

6.0

6.5

3.5 3.0 [V] Clock phases

ph1' 2.5 2.0

ph1''

1.5 1.0 0.5 0.0 4.5

5.0

5.5 t [ns] (b)

Figure 5.14. Monte-Carlo simulation results of the circuit represented in Fig. 5.12, in the case where ph1′′ ends slightly before ph1′.

5.4

6-BIT 1 GHZ TWO-STEP SUBRANGING ADC

5.4.1

Specifications and Architecture

Optical and magnetic data storage frontends and Ultra WideBand (UWB) communication systems require moderate resolution ADCs with high fs, capable of handling high frequency input signals with a good linearity. The 6-bit 1 GHz ADC described in this section is intended to those applications. It is implemented in a 90 nm digital CMOS technology using six metals. It has a differential full-scale input range (VFS) of 1 V.

286


Although the flash architecture is usually chosen to implement ADCs with very high sampling frequencies, a two step subranging architecture was selected because it has less hardware, which hopefully results in smaller power dissipation and area. As shown in Fig. 1.12, there is a coarse flash ADC that makes a rough estimation of the input signal position, and quantizes the MSBs. Then, the set of reference voltages that are closer to the input signal are selected and applied to the fine ADC, which quantizes the LSBs. Though this architecture uses less comparators, it is intrinsically slower than the flash ADC: after sampling the input signal, the coarse ADC must quantize the MSBs and then the selected reference voltages have to settle, so that the fine ADC correctly obtains the LSBs. Thus, at least two clock cycles are needed to let the sub-converters perform the coarse and fine quantizations successively. Figure 5.15 depicts the architecture, where two time interleaved fine ADCs are used to increase the effective sampling rate [52, 59]. There is no frontend S/H because the input signal is sampled in a distributed way, by the switched capacitor networks that precede each comparator of the fine and coarse ADCs. Those networks also subtract the input from the reference voltages. Figure 5.16 shows the time interleaving diagram (the operations indicated in the shaded areas will be addressed later). The first sample, vI[1], is taken simultaneously by the coarse ADC and the fine ADC A, at the end of ph1. The coarse ADC quantizes the MSBs during ph2, so that the set of reference voltages nearer vI[1] are applied to the fine ADC A in ph3. Its comparators regenerate in ph4, finalizing the quantization of vI[1]. In ph3 the coarse ADC and the fine ADC B sample vI[2], and a similar quantization process occurs. In this way, the input is sampled by the coarse ADC and one of the fine ADCs in every clock cycle. Redundancy is utilized to ease the offset requirements for the comparators of the coarse ADC. The fine sub-converters have a 4 bit resolution, but the offset voltages in their comparators must be smaller than the LSB (1/64 = 15.625 mV), because they determine directly the ADC code transition levels. The offset cancellation methods described in section 5.3 are used to guarantee that this occurs. The high frequency performance of the ADC is further improved by employing a solution that guarantees the fast selection of the important reference voltages, and halves the number of switches connected to the resistive ladder.


287

Reference Ladder

Fine ADC A (4 bit)

Coarse ADC (2.5 bit)

Fine ADC B (4 bit)

Encoder and Error Correction

vI

b5 ... b0

Figure 5.15. 6-bit time-interleaved two-step subranging architecture (© 2006 by IEEE). ph1

ph2

ph3

ph4

ph1

clk Coarse ADC

Samples vI[1]

Makes decision about vI[1]

Samples vI[2]


Samples vI[3]

Fine ADC A

Samples vI[1]

Regenerates offset voltage

Connects input capacitors to reference voltages


Samples vI[3]

Fine ADC B



Samples vI[2]

Regenerates offset voltage


Figure 5.16. Timing diagram showing the operation of the 6-bit ADC (© 2006 by IEEE).

5.4.2

Fine Flash ADCs

Figure 5.17 shows 1 of the 16 comparators used in fine ADC A (fine ADC B is equal, except for the timing). The input signal is sampled in a distributed way by the input capacitive networks, during ph1.10 As shown in Fig. 5.16 the reference voltages indicated by the coarse quantization are applied to the fine ADC A in ph3, and vCP – vCN becomes proportional to the difference between the sampled input signal and 10

Although that is not explicitly indicated in Fig. 5.17, S2 opens slightly before the input switches, to implement bottom plate sampling.


288

Selection Logic

VMAX CCAL CP

vCALP

ISS

W W

clk

Selection according to the MSBs

VCM

{ VREFs

vIN

ph3

ph1

ph1

vIP

ph4

CS ph1

S2

S1b

vCN

vCP S1a ph4

VCM ph3

{ VREFs

Input Capacitive Network

VMIN

VMAX

R0 R0

Pre-Amplifier

Auxiliary Differential Pair

W/4

W/4

ISS/4

CCAL

vCALN

CP

VMIN

clk

Latched Comparator

those reference voltages. This is applied to a static pre-amplifier, which is followed by a dynamic latched comparator. An auxiliary differential pair was added to implement the offset calibration.

Figure 5.17. Comparator used in the fine ADCs (© 2006 by IEEE).


289

The inputs of the pre-amplifier are shorted during the sampling phase, ph1, and thus it amplifies its own offset voltage. During ph2 the fine ADC A is waiting for the coarse quantization (see Fig. 5.16), so it could be idle. Instead, its latched comparators decide based on the output voltages presented by the pre-amplifiers at the end of ph1. As shown in section 5.3.1, these decision results are determined by the offset voltages of the pre-amplifiers and latched comparators. A simple selection logic takes these results and adjusts the calibration voltages at the input of the auxiliary differential pairs, in the way described in that section. The calibration process runs in background, because it uses the clock phases where the fine sub-converters would be idle. This has the advantage of guaranteeing the offset cancellation, even when VDD or the electrical parameters of the MOS transistors vary – for example, when there are temperature fluctuations or stress induced mechanisms that become accentuated with the operating time of the circuit (aging effects – Hot Carrier Injection, Negative Bias Temperature Instability, etc.). The input referred offset voltages of the pre-amplifier and latched comparator are increased by a factor of about 2, due to the attenuation introduced by the divider formed by CS and the parasitic capacitance at the input nodes of the pre-amplifier. This is not problematic since the calibration eliminates those offset voltages. The technique proposed in section 5.3.2 is used to remove the charge injection mismatches of S1a and S1b, but the implementation differs from the example given at that section. Here S1a and S1b are switched on during ph4, to set the input common-mode voltage of the pre-amplifier.11 The difference of charges they inject at the end of ph4 is eliminated by S2, in the next sampling phase, ph1. This allows to use small sampling capacitors, CS = 15 fF. The main differential pair has W = 4 μm and L = 0.09 μm, which results in a gate area of only 0.36 μm2, thus maximizing speed and minimizing power dissipation. ISS equals 160 μA and R0 = 980 Ω, which leads to a gain of about 1. Note that there is no advantage of having a large pre-amplifier gain, now that the offset of the latched comparator is cancelled. This allows to maximize the speed of the preamplifier.

11

Note that at ph4 the voltage stored on the sampling capacitors is no longer needed.

290


The auxiliary differential pair is four times smaller (0.09 μm2) and has a tail current of ISS/4. Therefore gm1/gm2 = 4. CCAL is implemented with thick oxide transistors. Although this leads to a larger occupied area, it was found that the gate leakage currents of 1.2 V devices would limit the operation for low sampling frequencies. CP is not an explicit device – it is the parasitic capacitance at the node. The switches have the minimum size. VMAX and VMIN are centered in VCM (internal common-mode voltage, 0.7 × VDD); VMAX – VMIN = ΔVCAL = 0.2 V, which is enough to saturate the auxiliary differential pair. The dynamic latched comparator and the kickback noise reduction technique described in section 1.6.4 are used in the fine ADC. All its transistors have a gate area below 1 μm2, minimizing the power dissipation and layout area. Without offset calibration, the complete comparator chain represented in Fig. 5.17 has σ(VOS) = 25 mV = 1.67 LSB. The fine flash ADCs are not implemented as separated converters: the corresponding comparators in the two fine ADCs are placed sideby-side, sharing the same local phase buffers and input/reference lines, thus minimizing interchannel mismatches. The input signal sampling occurs in every falling edge of the clock: the fine ADC A samples at the end of ph1, and the fine ADC B at the end of ph3 (see Fig. 5.16). When using time-interleaved converters, as it is the case of the fine ADCs, there must not be significant timing mismatches between them [12]. This is guaranteed by the solution depicted in Fig. 5.18. The clk2 signal, which is generated dividing the input clock by two, controls a simple multiplexer that generates ph1 and ph3 directly from the input clock. With this solution, the timing mismatch corresponds to the difference of delays between the two paths of the multiplexer. Monte-Carlo simulations were performed to verify that this was low enough. Figure 5.19 shows the result of a HSIM [127] Monte-Carlo simulation with one run, of the complete ADC working at the maximum sampling frequency. Successive ramps are applied to the ADC input, which are sufficiently slow to guarantee that the output code would, ideally, be incremented once in every four clock cycles. The calibration is disabled during the first input ramp, by pushing the inputs of the auxiliary differential pairs to GND. The transfer function of the ADC presents serious linearity errors, including missing codes. The differences between the offsets of the corresponding comparators in the two fine


291

ADCs causes the output code to alternate between different values in successive clock cycles. clk2 ph1 clk2 clk

ph3

÷2

clk

clk2

ph1 ph3

Figure 5.18. Simplified diagram showing the generation of the phases that perform the sampling in each of the two time-interleaved fine ADCs.

Some time after the offset calibration is enabled, the calibration voltages reach the optimum values and the transfer function becomes nearly ideal.

5.4.3

Coarse Flash ADC

As shown in Fig. 5.16, the coarse ADC samples the input signal simultaneously with one of the fine ADCs in ph1 and ph3 (clk), and its latched comparators must regenerate in ph2 and ph4 (clk ). Figure 5.20 shows the implementation. During clk the capacitors CS sample the reference voltages, while the latched comparator is regenerating. When clk goes high the input signal is applied to CS, and S3a/S3b are switched on. At that situation vCP – vCN is proportional to the difference between the input and reference voltages. On the falling edge of clk, that value is sampled at the input parasitic capacitances of the regenerative stage, CIP, which initiates the regeneration process. The sampling networks used in the fine and coarse ADCs are similar but operate in distinct manners (compare Fig. 5.17 to Fig. 5.20). In the fine sub-converters, CS samples the input signal, and the subtraction between the input and reference voltages only occurs later, when these are applied. In the coarse ADC, CS samples the reference voltages. In this way, when vIP and vIN are applied to CS (clk high) the


292

Offset Calibration ON

700 600

Offset Calibration OFF

0

8

16

24

32

40

48

56

64

0

100

200

300

400

500

Clock Cycle

800

900

1000

1100

1200

1300

subtraction mentioned above is (almost) instantly available at the latched comparator input. This is the only way of quantizing the MSBs in the half clock cycle immediately after applying the input voltage (see Fig. 5.16).

Output Code

Figure 5.19. Results from a Monte-Carlo simulation of the complete ADC (one run).


clk

VRP vIP vIN

clk clk

regenerative stage

VCM clk

CS clk

S1b

vCP

VRN clk

S3a

CIP

clk clk

S2

vCN clk

293

S1a

S3b

S

Q

R

Q

CIP clk

VCM

Figure 5.20. Comparators of the coarse ADC.

Although connecting to the input signals simultaneously, the operation dissimilarities of the input capacitive networks imply that the fine and the coarse ADCs may not sample exactly the same value. This is particularly relevant for high frequency input signals. The difference of sampled values can be regarded as an offset in the comparators of the coarse ADC which, if not too large, is corrected by the utilization of redundancy. Extensive simulations were performed to verify that this is the case. There is an problem in the circuit of Fig. 5.20: when clk goes low S1a/S1b/S2 open, thus sampling VRP and VRN in CS; however, S3a/S3b turn on causing a charge redistribution between CS and CIP, which destroys the reference voltage sampling just performed (the charges stored in CIP correspond to the subtraction between the reference voltages and the input signal that was sampled in the previous clock cycle.) This issue is overcome by using the kickback noise reduction technique described in section 1.6.4, where the differential voltage sampled at the comparator inputs is reset asynchronously somewhere during its regeneration phase, when it is detected that a decision was already made. This prevents the previously sampled voltage from disturbing the next comparison.

5.4.4

Redundancy

Figure 5.21 compares the situations with and without redundancy. VR1 to VR3 are the reference voltages of three consecutive comparators of the coarse ADC (LCMSB1 to LCMSB3), and the input signal is slightly below VR2. This figure shows the reference voltages provided to the comparators of the fine ADC, in the two possible outcomes of LCMSB2.


294

When redundancy is not used, the fine ADC only receives reference voltages inside the range indicate by the coarse sub-converter, as shown in Fig. 5.21(a). Due to its offset voltage, LCMSB2 may erroneously decide high, which causes the input voltage to fall outside the quantization range of the fine sub-converter, originating missing codes in the transfer function of the ADC. Input Voltage

Input Voltage VR3

vI

VR2

VR1

LCMSB3

LCMSB2

LCLSB15 LCLSB14 LCLSB13 LCLSB12 LCLSB11 LCLSB10 LCLSB9 LCLSB8 LCLSB7 LCLSB6 LCLSB5 LCLSB4 LCLSB3 LCLSB2 LCLSB1

VR3


LCMSB1

If LCMSB2 decides high

If LCMSB2 decides low (a)

Range where the threshold of LCMSB2 may lie without causing errors in the transfer function of the ADC.

vI

VR2

VR1

LCMSB3

LCMSB2


LCMSB1



If LCMSB2 decides low

(b)

Figure 5.21. Reference voltages provided to the fine ADC (example of a 4 bit fine subconverter): (a) without redundancy; (b) with redundancy.

The coarse sub-converter resolution is increased by one bit to implement redundancy, as depicted in Fig. 5.21(b). The fine ADC now quantizes a range that is larger than the quantization step of the coarse ADC. Table 5.1 shows the outputs of the comparators of the fine ADC, in the example considered in Fig. 5.21(b), for the two possible outcomes of LCMSB2. If it decides low, the location of vI is indicated by the high-to-low transition on LCLSB11/LCLSB12. If LCMSB2 decides high, the input signal position is indicated by the high-to-low transition on LCLSB3/LCLSB4. Thus, when using redundancy, its is possible to recover from an incorrect decision of the coarse comparator, as long as its offset voltage is not larger than half of the quantization step of the coarse ADC.


295

Table 5.1. Digital output levels of the fine comparators, for the two possible outcomes of LCMSB2. Fine comparator

LCMSB2 decides low

LCMSB2 decides high

LCLSB15

low

low

LCLSB14

low

low

LCLSB13

low

low

LCLSB12

low

low

LCLSB11

high

low

LCLSB4

high

low

LCLSB3

high

high

LCLSB2

high

high

LCLSB1

high

high

Since the fine ADCs have a resolution of 4 bit, to implement redundancy it is necessary to use a 3 bit coarse ADC, which has the transition levels shown in Fig. 5.22(a). Reference [128] demonstrated that the calculations necessary to obtain the output code from the raw MSBs and LSBs indicated by the sub-converters, are significantly simplified if:

All code transition voltages of the coarse ADC are shifted up by half of its quantization step. The uppermost comparator is eliminated.

In that situation the flash ADC has the code transition levels represented on Fig. 5.22(b); this is commonly designated a 2.5 bit flash ADC. In the ADC being described the offset voltages of the coarse comV 1 parators must not be larger than FS = ±62.5 mV . Monte-Carlo 23 2 simulations indicate an offset voltage standard deviation of 9 mV.


296

LCMSB7 LCMSB6 LCMSB6 LCMSB5 LCMSB5 LCMSB4

Input Range

LCMSB4 LCMSB3 LCMSB3 LCMSB2 LCMSB2 LCMSB1 LCMSB1

(a)

(b)

Figure 5.22. (a) 3 bit flash ADC; (b) 2.5 bit flash ADC.

5.4.5

Selection of the Reference Voltages

The reference voltages are obtained from a 200 Ω resistive ladder that is connected between VDD and GND. The silicided polysilicon resistors constituting it have more than enough area to guarantee low random deviations on the reference voltages. The basic two-step subranging converter is roughly two times slower than a full flash ADC, because it requires that two flash subconverters successively quantize the input signal. Employing two timeinterleaved fine ADCs, as it is done in the present case, overcomes this limitation. The two-step architecture has, however, one last speed bottleneck: the selection of reference voltages to be applied to the fine ADC, when vI is close to the threshold of a coarse comparator – situation depicted in Fig. 5.23(a). In that case LCMSB2 may take a long time to reach a decision, due to metastability12; all other coarse comparators decide quickly because they are not at their metastable region. This limitation will now be addressed. According to Fig. 5.16, the coarse comparators should reach a final decision in ph2, such that the reference voltages are applied to the

12

Metastability is discussed in section 1.6.4.


297

capacitive networks of the fine ADC A in the beginning of ph3, to let the pre-amplifiers settle in that phase. Input Voltage

VR3

vI

VR2

VR1

LCMSB3

LCMSB2

Input Voltage LCLSB15 LCLSB14 LCLSB13 LCLSB12 LCLSB11 LCLSB10 LCLSB9 LCLSB8 LCLSB7 LCLSB6 LCLSB5 LCLSB4 LCLSB3 LCLSB2 LCLSB1

LCMSB1


VR3


If LCMSB2 decides low (a)

vI

VR2

VR1

LCMSB3

LCMSB2

ρ

ν

LCLSB16 LCLSB15 LCLSB14 LCLSB13 LCLSB12 LCLSB11 LCLSB10 LCLSB9 LCLSB8 LCLSB7 LCLSB6 LCLSB5 LCLSB4 LCLSB3 LCLSB2 LCLSB1

ν

LCMSB1


ρ

LCLSB8 LCLSB7 LCLSB6 LCLSB5 LCLSB4 LCLSB3 LCLSB2 LCLSB1 LCLSB16 LCLSB15 LCLSB14 LCLSB13 LCLSB12 LCLSB11 LCLSB10 LCLSB9

If LCMSB2 decides low (b)

Figure 5.23. Selection of reference voltages to apply to the fine ADC: (a) standard solution; (b) solution utilized (© 2006 by IEEE).

It will now be considered that LCMSB2 has no offset, that it previously decided high, and that metastability causes its output to change from high to low only at the end of ph2.13 Due to the propagation delay of the digital logic that selects the reference voltages, these are modified somewhere during ph3. Until that moment the reference voltages applied to the fine ADC A are the ones corresponding to the case where LCMSB2 decides high – thus, vI is close to the references received by LCLSB3 and LCLSB4. After the output of LCMSB2 changes to low, the reference voltages nearer vI are now provided to the capacitive networks of LCLSB11 and LCLSB12. Figure 5.24 represents the output voltages of the pre-amplifiers when this situation occurs. To correctly quantize the input signal, it is necessary to wait that the output of the pre-amplifier preceding 13

If LCMSB2 is not able to reach a decision until the end of ph2, the previous comparison result (high) remains stored in the SR latch that follows its regenerative stage. This case is not problematic because the redundancy always guarantees the correct quantization of the input signal.


298

LCLSB11 becomes positive; since it goes towards a value that is near zero, the recovery time may be significant. Thus, if the input networks and the pre-amplifiers of the fine ADC do not settle in a fraction of ph3, an error of several LSBs may occur.

Output voltage of the pre-amplifiers

Recovery time of the pre-amplifiers Reference voltages change here

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

t

ph3 Figure 5.24. Settling of the output voltages of the pre-amplifiers, when the reference voltages applied to the fine ADC change during ph3, in the solution represented in Fig. 5.23(a).

Figure 5.23(b) depicts the solution utilized in the ADC being described. The comparators in each fine ADC are grouped in two blocks, ν and ρ, that have consecutive reference voltages. However, depending on the coarse decision, the comparators in block ν may have references that are larger or smaller than the ones in block ρ. When vI moves between adjacent zones of the coarse ADC, only the reference voltages in one of the blocks changes. In the example of Fig. 5.23(b) the selection of reference voltages for block ν does not depend on LCMSB2 – it is performed by the fastest coarse comparators, that are not in the metastable region. Thus, the location of vI is always indicated by the high-to-low transition on LCLSB3/LCLSB4, independently of the outcome of LCMSB2. By using this solution, it is guaranteed that the references applied to these fine comparators do not change during ph3. The late decision of LCMSB2 makes the reference voltages of block ρ change during ph3: in the beginning of that phase, the references in ρ are larger than the ones in ν; then, somewhere during ph3, they are modified to the ones immediately below. The pre-amplifiers of those


299

comparators must recover from this reference voltage modification – their outputs were initially getting negative (vI < VREF) but must become positive (vI > VREF). This is represented in Fig. 5.25. Note the output voltages of the pre-amplifiers belonging to block ν go smoothly towards their final value, since their reference voltages remain unchanged.

Output voltage of the pre-amplifiers

Recovery time Reference voltages of block ρ change here

9 10 11 12 ρ 13 14 15 16 1 2 3 4 5 ν 6 7 8

t

ph3 Figure 5.25. Settling of the output voltages of the pre-amplifiers, when the reference voltages applied to block ρ of the fine ADC change during ph3 – solution of Fig. 5.23(b).

The most critical situation occurs in the pre-amplifier preceding LCLSB16, which initially had the reference voltage farther from vI. It will now be considered that its output voltage does not have the time to become positive, making it decide low. The resultant thermometer code is shown in Table 5.2. This error is removed by the bubble correction logic employed [18], which can even correct faults in two comparators. So, to properly quantize the input signal, it is necessary to wait for the output of the pre-amplifier preceding LCLSB14 to become positive. The recovery time is now significantly smaller. This solution also reduces the number of reference selecting switches, since each comparator now only connects to half of the coarse ADC zones. This results on less parasitic capacitances in the resistive ladder, leading to a faster operation.


300

Finally, it should be noted that when the input voltage is not close to the threshold of a coarse comparator, there are no metastability problems, and the reference voltages are selected at the beginning of ph3 on both the solutions depicted in Fig. 5.23. Table 5.2. Digital output levels of the fine ADC comparators and bubble correction logic, when LCLSB16 wrongly indicates low.

5.4.6

Fine comparator

Output of comparators

After bubble correction

LCLSB8

low

low

LCLSB4

low

low

LCLSB3

high

high

LCLSB2

high

high

LCLSB1

high

high

LCLSB16

low

high

LCLSB15

high

high

LCLSB14

high

high

LCLSB9

high

high


As there is no single frontend S/H, and the input sampling is made in a distributed way, there were special cautions in the distribution of the input and clock signals. Metal tree structures [10] were used inside each sub-converter to guarantee the simultaneous arrival of those signals to each comparator. However this does not ensure the simultaneous arrival of the signals to the coarse and fine ADCs. Full RC parasitic extractions were performed to the final layout, using Assura [115], and the resultant netlist was simulated in HSIM. This allowed to observe the propagation of the input and clock signals, and make the necessary layout improvements to guarantee negligible


301

timing differences in their arrival to the coarse and fine ADCs. Other relevant internal signals were also inspected. Simulations using the flat netlists obtained from layout parasitic capacitance extractions, were performed in all levels of the hierarchy, from the latched comparator to the complete ADC. The inductance of the bonding wires was included in the top-level simulations, to consider the variations on the internal supply and reference voltages. The layout of the ADC is shown in Fig. 5.26, having the main constituting blocks identified. The total layout area is below 0.13 mm2 and the power dissipation is 55 mW. 470 μm

Coarse ADC

270 μm

Phase Generator

Fine ADCs

Bias Circuits

Digital Error Correction

Figure 5.26. Layout of the 6-bit 1 GHz two-step subranging ADC (© 2006 by IEEE).

Figure 5.27 compares the INL and DNL of the ADC in normal operation and having the calibration disabled – the improvement is evident. When it is disabled, there are missing codes (DNL = –1). These results were obtained at the maximum sampling frequency, 1 GHz, and with an input signal of 9.5 MHz. Figure 5.28 shows the FFTs obtained in these conditions. The output data is decimated by a factor of 5, due to speed limitations of the logic analyser. An odd decimation factor is used to acquire samples originating from the two time-interleaved channels. When the offset calibration is enabled, the THD becomes 11 dB better and the SNR increases more than 5 dB. The ENOB is improved from 4.6 to 5.5 bit. Figure 5.29 shows the FFT obtained with fs = 1 GHz and fin = 502 MHz, where an ENOB of 5.3 bit was obtained. Figure 5.30 shows the SINAD and THD as a function of the sampling frequency, for three different input frequencies.


302

1.5

Calibration Enabled

[-0.28,0.25]

Calibration Disabled

[-0.89,1.12]

INL [LSB]

1 0.5 0 -0.5 -1

0

1.5

16 Calibration Enabled

32 [-0.28,0.22]

48 Calibration Disabled

64 [-1.00,1.10]

DNL [LSB]

1 0.5 0 -0.5 -1

0

16

32

48

64

Output Code

Figure 5.27. Typical INL and DNL, measured with fs = 1 GHz and fin = 9.5 MHz (© 2006 by IEEE).

The harmonic distortion is always more than 7 dB better than the SINAD, which is a consequence of the excellent linearity that the offset calibration allows to achieve. The SINAD varies from 35.5 dB (ENOB of 5.6 bit) when fs = 250 MHz and fin = 10 MHz, to 33.8 dB (ENOB of 5.3 bit) when fs = 1 GHz and fin = 500 MHz. Thus, there is no significant performance degradation, in the range of input and sampling frequencies that was considered. Limitations of the test equipment did not allow to perform measurements at larger sampling and input frequencies.


303

0 (-0.49) ( 1)

-10

THD=-50.1dB SNR=35.3dB

-20

SINAD=35.1dB


-30 -40 (-51.53) ( 3)

-50 -60

(-62.79) ( 5)

(-64.64) ( 2)

-70

(-72.15) ( 4)

(-68.10) ( 6)

-80

(-65.33) ( 7)

(-70.56) ( 8)

(-70.51) ( 9)

(-71.02) (10)

-90 -100

1

2

3

4

5 Frequency [Hz]

6

7

8

9

10 x 10

7

(a) 0 (-0.55) ( 1)

-10

THD=-39.0dB SNR=30.2dB SINAD=29.6dB

-20


-30 (-41.66)

-40

( 3) (-48.12) ( 5)

(-50.73) ( 2)

-50

(-62.06) ( 4)

-60 -70

(-55.50) ( 6)

(-55.97) ( 7)

(-62.55) ( 8)

-80

(-49.08) ( 9)

(-69.95) (10)

-90 -100

1

2

3

4

5 Frequency [Hz]

6

7

8

9

10 x 10

7

(b) Figure 5.28. FFT of the output samples, with fs = 1 GHz and fin = 9.5 MHz. The output data was decimated by a factor of 5; (a) offset calibration enabled; (b) offset calibration disabled.


304

0 -10

(-1.06) ( 1)

THD=-41.7dB SNR=34.6dB

-20

SINAD=33.8dB


-30 -40 -50 -60

(-45.09) ( 3)

(-48.90) ( 2)

(-52.02) ( 5)

(-59.56) ( 4)

-70

(-63.08) (-62.64) ( 9) ( 7)

(-68.51)(-65.66)(-68.68) ( 6) ( 8) (10)

-80 -90 -100

1

2

3

4

5 Frequency [Hz]

6

7

8

9

10 x 10

7

Figure 5.29. FFT of the output samples, with fs = 1 GHz and fin = 502 MHz. The output data was decimated by a factor of 5.

60

SINAD and |THD|

[dB]

55

fi = 10 MHz

50

45

fi = 500 MHz fi = 300 MHz

40

fi = 10 MHz

35

SINAD

fi = 500 MHz 30 250

|THD|

fi = 300 MHz 500

750

1000

Sampling Frequency [MHz]

Figure 5.30. SINAD and THD as a function of the sampling frequency, for three different input frequencies (10, 300 and 500 MHz). (© 2006 by IEEE).

Chapter 6 Conclusions 6.1

OVERVIEW OF THE RESEARCH WORK

This book analyzed, described the design, and presented the test results of Analog-to-Digital Converters employing the three main highspeed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one were reviewed, and the techniques usually employed to improve their performance were presented. It was shown that the linearity of those converters is mainly limited by the offset voltages of the pre-amplifiers, folding circuits and latched comparators. In CMOS technologies, the utilization of offset reduction techniques is mandatory to achieve high frequency operation with low power dissipation and occupied area. The two most widely used techniques, averaging and offset sampling, were thoroughly examined and characterized in this book. An overview of the relevant conclusions and novel contributions made throughout this book will now be presented. Chapter 1 described the analog-to-digital conversion architectures better suited for high-speed operation: the flash, the two-step flash and the folding and interpolation converters. From the various types of twostep flash ADCs, the one more appropriate for high-speed operation is a variant called two-step subranging flash ADC, where the digital-toanalog conversion and subtraction operations are done in a distributed way. Apart from the S/H, none of these three architectures needs components with special linearity requirements. The circuits preceding each comparator have zero output voltage when the input signal of the ADC is at a code transition level. Therefore, the latched comparators work as zero crossing detectors, indicating the input signal position. In flash ADCs the comparators are preceded by pre-amplifiers, each constituted by a single differential pair which subtracts the input signal from a reference voltage. In folding and interpolation converters these differential pairs are grouped together in folding circuits, which allows to reduce the number of latched comparators. Two-step subranging converters are composed of a coarse and a fine flash ADC. P.M. Figueiredo and J.C. Vital, Offset Reduction Techniques in High-Speed Analog-to-Digital Converters, © Springer Science + Business Media B.V. 2009

305

306


The accuracy of these converters is limited by the offset voltages of the differential pairs, which may be reduced by increasing the area of its components. This, however, increases the parasitic capacitances, leading to a larger power dissipation and input capacitance, or to the reduction of the maximum operating frequency. For the same component sizes the offset voltages of folding circuits are larger than in simple pre-amplifiers. The two-step flash requires a S/H to work properly. In flash and in folding and interpolation converters the utilization of a S/H is not mandatory, but improves considerably the input frequency response. These S/Hs are usually done with very fast and simple open-loop circuits, or implemented in a distributed way to reduce the requirements on their linearity. Another relevant matter discussed in that chapter was the settling in cascaded folding stages, which sets the maximum operating frequency. Several techniques have been introduced in the last few years to improve the dynamic performance of these stages, while lowering the power dissipation. There is one particularly interesting, in which the zero crossings are at the right place during the entire amplification phase. This technique, which is very well adapted to the notion that only the zero crossings are relevant, can also be used in flash ADCs. The latched comparator is a fundamental building block of all high speed analog-to-digital converters. The principles of operation, relevant design parameters, and the tradeoffs usually encountered in these circuits are discussed. Also, a kickback noise reduction technique is proposed, that is later employed in the 6- and 10-bit converter prototypes. Averaging is one of the most widely used offset reduction techniques, and was studied in great detail in this book. Previous published work presented only approximated results for the INL and DNL in averaged pre-amplifying stages. Other fundamental parameters like the gain and the expressions for the output voltages were never reported. Chapter 2 presented general and exact expressions for all the relevant DC parameters in averaged pre-amplifying and folding stages (output voltage, gain and the standard deviation of the INL and DNL). These expressions are general, in the sense that are valid for differential pairs using any kind of transistors and for any type of mismatches, including those in the current sources and on the resistors. The expressions are exact because no approximations are made in their derivation – their accuracy depends exclusively on how the currents of the transistors in the differential pairs are determined.

Chapter 6: Conclusions

307

The general expressions obtained for averaged pre-amplifying stages were particularized for MOS differential pairs. Their evaluation was then compared to HSPICE simulation results and a good agreement was found. The amount of offset reduction depends on the number of nonsaturated differential pairs, 2N + 1, and on the ratio between the load resistor, R0, and the averaging resistor, R1. For constant VOVD it was concluded that:

The increase of R0/R1 improves INL and DNL, in what concerns mismatches in Vt, β and R0.

The increase of R0/R1 enlarges the INL and DNL due to mismatches in ISS and in R1. This is consistent with the fact that, if averaging is not used, these are not sources of zero crossing deviations. Increasing the number of non-saturated differential pairs (increasing N) by manipulating VR improves INL and DNL, with respect to the value found in the absence of averaging. Increasing N makes the DC gain go towards the value found in the absence of averaging, regardless of R0/R1.

The general expressions derived in that chapter were also evaluated in appendix A, using a piecewise linear function to approximate the transfer characteristic of the differential pairs. This approximation was used in all previously published theoretical studies, and yields the simplest but most inaccurate results. That appendix discusses the approximations and limitations of those research works. The application of averaging to a folding stage was also analyzed in chapter 2. Its circular averaging network was studied in detail to obtain the expressions for the output voltages, gain, and standard deviation of the INL and DNL. Apart from the obvious difference in the overall transfer functions, other relevant dissimilarities were found between averaged pre-amplifying and folding stages:

Given a certain VR and using the same differential pairs (W, L, ISS) and resistor values (R0, R1), the gain of a folding stage is always lower than of a pre-amplifying stage. The two values


308

only become similar if FB is sufficiently large or when the averaging effect is weak (low R0/R1).

Increasing N until approximately FB/2 improves INL and DNL (with respect to the value found in the absence of averaging) and increases the gain. From there on, those parameters are degraded. The mismatches in R0 and ISS cause larger offset voltages in folding circuits than in pre-amplifiers, either with or without averaging.

The results from the theoretical expressions are compared to HSPICE simulations and a good agreement is observed. Another subject discussed in chapter 2 was the yield of the INL and DNL in averaged stages. The correlation existing between zero crossings prevents the calculation of explicit yield expressions. One solution is to perform fast Monte-Carlo simulations, by generating random values for each mismatch, and calculating the offset in each zero crossing using the expressions derived in that chapter. A relevant conclusion was that accomplishing a certain σ(VOS) using averaging produces better yield values than when the same σ(VOS) is obtained without averaging. The solutions to terminate the averaging networks of pre-amplifying stages were addressed at the end of chapter 2. A new termination was proposed which, for signals within the input range, makes the circuit operate similarly to what would be found in an averaging network that actually extended to infinite. This new solution was shown to outperform all the existing ones. The folding stages do not need a terminating circuit because the network is circular. However, enough differential pairs with reference voltages outside the input range must still exist to avoid systematic deviations. Two appendixes present, in detail, the most complex theoretical derivations: appendix B deals with the mismatches in the resistors of the averaging network; the expressions that characterize folding stages with averaging are derived in appendix C. The main results obtained in these appendixes are referred and discussed in chapter 2. Chapter 3 started with the study of the transient behavior of averaged pre-amplifying stages. The output voltage expression derived in chapter 2 was extended to s-domain, and a numerical Laplace Inversion algorithm was used to obtain the time-domain response, which agrees remarkably with HSPICE simulation results. An approximation


309

that provides further insight into the behavior of the circuit, while avoiding the utilization of the numerical inversion algorithm, was then proposed. In the examples considered, this approximation only presented significant errors for t < 50 ps. It was also shown that the contributions of the differential pairs take time to propagate through the averaging network. Due to this fact, the offset voltages vary with time, between the value found when averaging is not used (at t → 0+ the contributions from the neighbor differential pairs have not arrived), and the DC value for which all differential pairs fully contribute. This effect can be ignored for very low or very high R0/R1, or when the output voltages are allowed to approach their DC values. At this point, expressions for all the relevant parameters of the averaged pre-amplifying stage had been derived, allowing to create an automatic design procedure which yields the dimensions of the components that achieve the set of design specifications. It is implemented as a computer program and has an interface with HSPICE, from where it obtains accurate values for the differential drain current, transconductance and parasitic capacitances of a differential pair. The dimensions of the components indicated by the design tool are final, since the theoretical expressions are exact and the parameters of the differential pairs are obtained from HSPICE, and not from the expressions usually employed for hand analysis, which are less accurate. The capabilities of the design tool were demonstrated by designing the pre-amplifier stage of a 7-bit 200 MS/s flash ADC in just 10 s. The complete stage was then simulated in HSPICE using the dimensions indicated by the design tool, and the specifications are meet with a remarkable accuracy. Several application examples were given, and the effect of varying each design specification was studied. The tradeoffs between power, speed and accuracy are evident in some of these examples. Another important conclusion is that, given a specified VR, there is an optimum N value: as N is increased (by enlarging VOVD), the required area set by Vt mismatches decreases, but the necessary area due to β mismatches increases. This behavior is due to the fact that averaging reduces σ(VOS) with respect to the value found in the absence of averaging – however, in what concerns the contribution from β mismatches, that value is increasing with VOVD, and the stronger averaging effect obtained with a larger N does not overcome that increase.


310

Finally, it was shown that for a given set of specifications and as long as R0/R1 is high enough to yield a strong averaging effect, the utilization of interpolation does not change the power dissipation and input capacitance of an averaged stage. Still, by using moderate interpolation factors it is possible to decrease the layout area and complexity. Chapter 4 described the design and measurement results of a 7-bit 120 MHz flash IQADC and a 10-bit 100 MHz folding and interpolation converter, both using averaging. Particularly relevant contributions made in that chapter were:

The utilization of the design procedure described in chapter 3 to meet the specifications across process, supply voltage and temperature corners; it is also shown that the gain variations with process and temperature are smaller when averaging is used. The application of the design procedure to size cascaded (folding) stages. The non-zero resistance of the metal interconnections causes IR drops that may affect the linearity of a converter. An example is the IR drop in the ground line, which originates different tail current values depending on the layout position of a differential pair – this causes zero crossing deviations when averaging is used. A solution is devised to compensate these IR drops, ensuring that all the differential pairs have the same tail current. The layout of cascaded folding stages is quite complex, imposing a careful floorplan and the consideration of all parasitic elements. The solutions utilized are discussed in detail.

Chapter 5 reviewed existing offset cancellation methods, which are the main alternative to the utilization of averaging in high-speed ADCs. Although those techniques reduce – or even eliminate – the offset contribution from the pre-amplifier, there is always a residual value caused by charge injection mismatches and by the offset of the latched comparator. Moreover, most of those techniques require the presence of capacitors in the signal path, which introduce attenuation. These problems can be relaxed by increasing the gain of the pre-amplifiers, and the value of the offset storage capacitors. However this reduces the operating speed, increases power dissipation and, in some cases, enlarges the input capacitance of the ADC.


311

A method was described that eliminates the contributions of all offsets existing from the pre-amplifier onwards (including the latched comparator). A second technique removes the charge injection mismatches in the input sampling network. The combination of those two techniques lead to a virtually offset free comparator. This was successfully used in the 6-bit 1 GHz two-step subranging ADC described at the end of that chapter. An excellent linearity was obtained with a low power dissipation of 55 mW, thus confirming the effectiveness of the proposed methods. This ADC also employs a new reference voltage selection method, which guarantees the fast selection of the important reference voltages, and halves the number of switches connected to the resistive ladder. This technique allows to overcome the main speed bottleneck of the two-step architecture. To the best knowledge of the authors, this was the highest sampling frequency two-step converter ever presented. The broad range of architectures and techniques analyzed in this book, allowed to address the major challenges encountered in the design of high-speed ADCs. Careful analysis resulted in a more profound understanding and optimization of existing techniques. New ideas were explored, matured and demonstrated in the everlasting desire to advance the state-of-the-art.

Appendix A Averaging with Piecewise Linear Differential Pairs A.1

INTRODUCTION

The general expressions derived in chapter 2 for the output voltages, gain and variance of the INL and DNL are evaluated in this appendix, considering that the MOS differential pair represented in Fig. 2.9 has the piecewise linear transfer function depicted in Fig. A.1. iDIFF[k,vI] ISS

VSAT -VSAT

vI-kVR

-ISS

Figure A.1. Piecewise linear transfer function.

Approximating the transfer characteristic of the differential pairs by a piecewise linear function, yields results that are simpler but less accurate than those obtained using the quadratic model for the drain current of the MOS transistors, in chapter 2. All previously published studies concerning the averaging technique, [26, 80, 104, 106], used the transfer function shown above. Moreover, each of these references made their own additional simplifications, which lead to different results for the variance of the INL and DNL. The approximations and limitations of those research works are discussed in this appendix. This helps to clarify the relation between the work presented in this book and the one exhibited in the references mentioned above: while a general theoretical foundation is developed and presented in this book, those references derived expressions for particular cases, under simplified conditions. Since previously published works have not addressed averaging in folding stages, we will not consider them in this appendix.

313

314

A.2


OUTPUT VOLTAGE AND GAIN

In this case the differential output current is given by

⎧ ⎪ I SS if vI − kVR < −VSAT ⎪ ⎪ ⎪ (A.1) iDIFF 0 [k, vI ] = ⎪ ⎨−gm 0 (vI − kVR ) if vI − kVR ≤ VSAT ⎪ ⎪ −I SS if vI − kVR > VSAT ⎪⎪ ⎪ ⎩ where I (A.2) gm 0 = SS VSAT and VSAT is the differential input voltage at which the differential pair saturates, as shown in Fig. A.1. Equation (A.1) can be used in (2.17)– (2.19) to obtain the output voltages in the absence of mismatches. The sums in those expressions do not need to extend to ±∞: it can be demonstrated that for a certain input voltage value, the differential output voltage expression, (2.19), can be written as

vODIFF [ j, vI ] = −B

r +j

∑

C k − j −1iDIFF [k, vI ]

(A.3)

k =−r + j

⎧⎪ ⎢ v ⎥ ⎫⎪ ⎢ vI ⎥ 1 I where r = Max ⎪ ⎨ ⎢⎢ ⎥⎥ − N − 1 − j , ⎢⎢ ⎥⎥ + N + 1 − j ⎪⎬. ⎪⎪ ⎣VR ⎦ ⎪ V ⎪⎭⎪ ⎣ R⎦ ⎩⎪ Let us consider the example given on sections 2.3.4 and 2.4.4, where R0 = 4 kΩ and R1 = 400 Ω, which yields B = 456 Ω and C = 0.73. The differential pairs have gm0 = 710 μS and ISS = 155 μA which, from (2.28), leads to VOVD = 0.218 V . The differential pairs saturate for a input voltage of VSAT = 2VOVD = 0.308 V. When the differential pairs are modeled with a piecewise linear function, the transconductance, gm0, the input saturation voltage, VSAT, and the tail current source value, ISS, are related by (A.2): it is

1

⎢v ⎥ ⎢ I ⎥ ⎢V ⎥ ⎣ R⎦

means “the integer immediately below vI/VR”.

Appendix A: Averaging with Piecewise Linear Diff. Pairs

315

not possible to have simultaneously the values mentioned before for gm0, ISS and VSAT.2 To compare the results obtained in this appendix with the ones of sections 2.3.4 and 2.4.4 we choose:

The same transconductance (gm0 = 710 μS), to have an equal gain in the absence of averaging (gm0R0 = 2.84).

The same input saturation voltage (VSAT = 0.308 V) to maintain the number of non-saturated differential pairs, for a certain VR. Note that N is the integer immediately below VSAT/VR, independently of the model used for transfer function of the differential pair.

With these values for gm0 and VSAT, (A.2) leads to ISS = 219 μA, which differs from the value of the example given in sections 2.3.4 and 2.4.4. This is a price to pay for the simplicity of the model. It will be considered, as in the sections mentioned above, VR = 45 mV which leads to N = 6. Figure A.2 shows the output voltage of differential pairs –10, 0 and +7, calculated using (A.3). The same figure also represents the output voltages of those differential pairs when averaging is not utilized (R1 → ∞). When averaging is used the output voltage range is maintained, ±I SS R0 = ±0.876 V, but its shape is rounded and the gain decreases. Note that the output voltage of a certain differential pair still varies even after it has become saturated. The usage of averaging does not RI affect the output common mode value, which remains at VDD − 0 SS . 2 To evaluate the gain using (2.21), it is necessary to know the transconductance of all differential pairs, for zero input voltage – gm[k,0]. The value for any input voltage, gm[k,vI], can be calculated by differentiating (A.1), ⎧⎪ 0 if vI − kVR > VSAT ⎪ (A.4) gm [k, vI ] = ⎪⎨ ⎪⎪−gm 0 if vI − kVR ≤ VSAT . ⎪⎩ 2

In sections 2.3.4 and 2.4.4 the transfer function of the differential pair is derived using the quadratic drain current model of MOS transistors. In that case, from (2.28) and noting that

VSAT = 2VOVD one concludes that gm 0 = 2I SS /VSAT , which differs from (A.2). Therefore, the three parameters in these equations (gm0, ISS and VSAT) cannot be all simultaneously equal in the two transfer function models being considered.


316

Figure A.3 compares the transconductance given by (A.4), with the one obtained using the quadratic drain current model for the MOS transistors of the differential pair, (2.27). Output voltages without Averaging

0.75 vODIFF[-10,vI]

0.5 0.25

-1.0

-0.5

0.5

vI

vODIFF[7,vI]

-0.25 vODIFF[0,vI]

1.0

-0.5 -0.75

Output voltages with Averaging

Figure A.2. Output voltage of differential pairs –10, 0 and 7 with and without averaging.

gm[k,vI]

−VSAT

0

VSAT

vI−kVR

Transconductance function considered in chapter 2

−gm0 Transconductance function considered in this appendix

Figure A.3. Comparison of the transconductance functions used in this appendix and in chapter 2.


317

Noting that N, which is the number of non-saturated differential pairs in each side of the one whose zero crossing is being considered (see Fig. 2.5), is the integer immediately below VSAT/VR, allows to write the transconductance for zero input voltage, if k > N ⎪⎧⎪ 0 (A.5) gm [k, 0] = ⎨ ⎪⎪−gm 0 if k ≤ N . ⎪⎩ Substituting (A.5) in (2.21) leads, finally, to

1 + C − 2C N +1 . (A.6) ∑ C (1 − C ) k =−N Let us now calculate the maximum and minimum values of the gain when N is varied. For large N the gain approaches the value found in the absence of averaging. In fact, noting that 0 < C < 1, (A.6) yields 1 +C (A.7) lim G0 = gm 0B = gm 0R0 . N →∞ C (1 − C ) When N is 0 the only non-saturated differential pair is the one whose zero crossing is being considered – all others are completely unbalanced: ⎛ Req ⎞⎟ gm 0R0 (A.8) = gm 0 ⎜⎜R0 // lim G0 = ⎟. N →0 2 ⎠⎟ R0 ⎝⎜ 1+4 R1 In this case the gain is determined simply by transconductance of the single non-saturated differential pair, gm0, and by the load resistance it “sees”. As shown in section 2.3.1, Req is the equivalent resistance to the right and to the left of each output node; therefore the R load resistance “seen” by that differential pair is R0 // eq . 2 Equations (A.7) and (A.8) yield the maximum and minimum gain values in an amplifier stage using averaging. Although these results were derived using the piecewise linear transfer function, they are general and do not depend on the shape of the transfer function. Returning to the example being considered in this appendix, applying (A.6) leads to G 0 = g m 0B

N

C k −1 = gm 0B

1 + 0.73 − 2 × 0.737 (A.9) = 2.48 . 0.73 (1 − 0.73) Figure A.4 represents the gain as a function of N; Table 2.1 has the values chosen for VR in each case. Various resistance ratio cases were G0 = 710 × 10−6 × 456


318

considered, maintaining R0 at 4 kΩ and varying R1. The HSPICE simulation results presented in section 2.3.4 are also show in Fig. A.4. The same overall behavior is found comparing Figs. A.4 and 2.12. However the results given by (A.6) are too optimistic, specially for larger values of R0/R1 which is the most common situation. This happens because the differential pairs are modeled by a transfer function which, as shown in Fig. A.3, overestimates the transconductance when the input voltages are different from zero. The results obtained in chapter 2 match much better the ones obtained from HSPICE. 3

Case without averaging

R0/R1 = 0.1 R0/R1 = 0.5

2.8 2.6

R0/R1 = 1

2.4

R0/R1 = 2

2.2 2 1.8 1.6

R0/R1 = 10

1.4 1.2 1 1

2

3

4

5

6

7

N Figure A.4. Gain as a function of N, for several resistance ratio values. The dots are from HSPICE simulations and lines are from (A.6).

A.3

EFFECT OF MISMATCHES – INL AND DNL

This section derives the INL and DNL caused by the various mismatches. All previous studies on the averaging technique, [26, 80, 104, 106], focused on the shift of the transfer function caused by the mismatches between the pair of transistors in the differential pair. The authors of [104, 106] also considered the mismatches between the tail current sources (ISS). However, this was done only for a very particular case. The mismatches in the resistors were always ignored. In this section every mismatch is addressed using the piecewise linear transfer function. This allows to derive and analyze all the results presented in [26, 80, 104, 106], and compare the accuracy of such expressions with the ones obtained in section 2.4.4.


A.3.1

319

Mismatches in the Transistors of the Differential Pair

The transfer function of differential pair k is shifted by ΔV[k], due to the mismatches between its pair of transistors, as shown in Fig. A.5. The differential output current is now ⎧⎪ I SS if vI − kVR + ΔV [k ] < −VSAT ⎪⎪ ⎪⎪ iDIFF [k, vI ] = ⎨−gm 0 (vI − kVR + ΔV [k ]) if vI − kVR + ΔV [k ] ≤ VSAT (A.10) ⎪⎪ ⎪ if vI − kVR + ΔV [k ] > VSAT . −I SS ⎪ ⎪⎩

For small ΔV[k], this expression can be approximated,

(A.11) iDIFF [k, vI ] iDIFF 0 [k, vI ] + fΔV [k, vI ] ΔV [k ], where iDIFF0[k,vI] is given by (A.1). Equation (A.11) is in the general form of (2.40) and, thus, (2.43) and (2.48) can be used to calculate the standard deviation of INL and DNL. iDIFF[k,vI] ISS

VSAT

-VSAT

vI-kVR

ΔV[k]

-ISS

Figure A.5. Shift of ΔV[k] in the piecewise linear transfer function of differential pair k.

The fΔV[k,vI] function is calculated using (2.41), which yields the same results that were obtained for the transconductance, gm[k,vI]: (A.4) for any vI and (A.5) for vI = 0, ⎧ if k > N ⎪ ⎪ 0 (A.12) fΔV [0, vI ] = ⎨ ⎪ −gm 0 if k ≤ N . ⎪ ⎪ ⎩ The variance of the offset voltage is calculated using (2.43),


320 N

σ 2 (VOS )ΔV =

∑ C 2 k −2gm2 0

k =−N

⎡ N ⎤ ⎢ ∑ C k −1gm 0 ⎥ ⎢ ⎥ ⎢⎣k =−N ⎥⎦

2

σ 2 (ΔV ) =

1 − C 1 + C 2 − 2C 2N +2 2 σ (ΔV ).(A.13) 1 + C (1 + C − 2C N +1 )2

The variance of the difference between the offset voltages of two consecutive pre-amplifiers is obtained applying (2.48), 2 2N −2 + 2gm 0C

σ 2 (VOS [1] −VOS [ 0 ])

ΔV

k =−(N −1)

=

(C

k −1 −1

(−gm 0 ) − C

⎡ N ⎤2 k −1 ⎢ ⎥ C g m0 ⎥ ⎢ ∑ ⎢⎣k =−N ⎥⎦ 2

=2

N

∑

(1 − C ) 1 +C

1 − C + 2C 2N +1

(

1 + C − 2C N +1

2

)

σ 2 (ΔV ) .

k −1

)

(−gm 0 )

2

σ 2 (ΔV ) =

(A.14)

These expressions will now be evaluated for the example being considered. In order to make a comparison with the results achieved in section 2.4.4, σ(ΔV) takes the value obtained in that section for σ(ΔVt), 1.172 mV. A Vt mismatch shifts the entire transfer function of the differential pair, in a way similar to what is represented in Fig. A.5 for the ΔV mismatch. This fact can be verified examining (2.53), where the ΔVt[k] term is always summed directly to the input voltage. Note, thought, that this does not always happen: for example a mismatch in β does not causes a simple shift in the transfer function of the differential pair. Figure A.6 represents the standard deviation of the offset voltage, which is proportional to the INL. Figure A.7 represents the standard deviation of the difference between the offset voltages of two consecutive differential pairs, which is proportional to the DNL. The HSPICE simulation results presented in section 2.4.4 are also show in these figures. Comparing Fig. A.6 with Fig. 2.14 and Fig. A.7 with Fig. 2.19 leads to the conclusion that the theoretical values obtained in section 2.4.4 are closer to HSPICE Monte-Carlo simulation results. This is specially true for larger values of the resistance ratio and for smaller values of N. In the absence of averaging, σ (INL)ΔV = σ (ΔV ) and

σ (DNL)ΔV = 2σ (ΔV ), which means that the DNL is larger. However, the improvement in the DNL due to averaging is more substantial than in the INL. Using (A.13) and (A.14) one can determine the value of the resistance ratio that makes σ(INL)ΔV = σ(DNL)ΔV, for each value of N; this is represented in Fig. A.8. It can be concluded that this occurs for R1 2R0; usually R1


321

is significantly smaller than R0, which makes the DNL smaller than the INL. 1200


1100

R0/R1 = 0.1

σ(VOS)ΔV [μV]

1000 900 800 700

R0/R1 = 0.5

600

R0/R1 = 1

500

R0/R1 = 2

400

R0/R1 = 10

300 200

2

3

4

5

6

7

8

N Figure A.6. Standard deviation of the offset voltage, due to ΔV mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.13).

1800


σ(VOS[1]-VOS[0])ΔV [μV]

1620 1440

R0/R1 = 0.1

1260 1080 900

R0/R1 = 0.5

720 540

R0/R1 = 1

360

R0/R1 = 2

180

R0/R1 = 10

0 2

3

4

5

6

7

8

N Figure A.7. Standard deviation of the difference between the offset voltages of two consecutive pre-amplifiers, due to ΔV mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.14).


322

1 0.9

R0/R1

0.8 0.7 0.6 0.5 0.4 1

2

3

4

5

6

7

N

Figure A.8. Resistance ratio that makes σ(INL)ΔV = σ(DNL)ΔV, as a function of N.

The results obtained in other research works will now be examined. Equation (A.13) is equivalent to the result derived in [104]. The same authors also presented, later in [106], an expression equivalent to (A.14).3 Reference [80] studies the averaging network when R0 is very large, reaching the conclusion that the standard deviation of the INL is reduced by a factor of 2N + 1 and that the standard deviation of the DNL improves by a factor of 2N + 1. When R0 → ∞ it can be verified that C → 1 which, using (A.13) and (A.14), leads to lim σ (VOS )ΔV =

R0 →∞

3

σ (ΔV ) 2N + 1

(A.15)

In these references the notation differs significantly with respect to the one adopted in this book. According to [104,106] the voltage at node 0, caused by a current source at node k, is given by R0h (0)b k iD [k, vI ] where h(0) is a normalized coefficient and b = e

− acosh(1+R1 /(2R0 ))

. Equation

(2.10) is equivalent to this result. In fact, noting that acosh (1 + R1 / (2R0 )) > 0 and that

(

)

acosh (x ) = ln x + x 2 − 1 it is straightforward to show that the variable C, given by (2.12),

equals b of [104,106]. Therefore, the normalized coefficient, h(0), whose expression is not given in [104, 106], equals BC−1/R0. In these references the total number of non-saturated differential pairs, 2N + 1, is named WZX. The variable Wn is the number of differential pairs suffering a deviation in the output current, due to a mismatch. For the mismatches between the two transistors in the differential pair, Wn = 2N + 1. Equations (10) and (13) of [106] are equivalent to, respectively, (A.13) and (A.14).


323

2σ (ΔV ) . R0 →∞ 2N + 1 Remembering that in the absence of averaging, σ (VOS ) lim σ (VOS [1] −VOS [0])ΔV =

ΔV

(A.16)

= σ (ΔV )

and σ (VOS [1] −VOS [0]) = 2σ (ΔV ), the conclusions of [80] are conΔV firmed. In the ADC described in that reference, R0 is implemented using an active load to ensure a large value. The authors of [26] derive the INL and DNL improvement under the assumption that the differential pairs do not saturate. In this situation N → ∞ which, from (A.13) and (A.14), leads to (1 − C ) (1 + C 2 ) 2 2 (A.17) lim σ (VOS )ΔV = σ (ΔV ) N →∞ (1 + C )3

⎛ 1 − C ⎟⎞3 2 ⎜ lim σ (VOS [1] −VOS [0])ΔV = 2 ⎜⎜ ⎟ σ (ΔV ) . N →∞ ⎝ 1 + C ⎟⎠ These expressions are equal to those presented in [26]. 2

A.3.2

(A.18)

Mismatches in the Tail Current Sources

The effect of a mismatch in the tail current source of a differential pair is represented in Fig. A.9. It is considered, as done in [104, 106], that this mismatch does not affect the transconductance of the differential pair. In this case, the input voltage at which the differential pair saturates shifts by ΔISS[k]/gm0.4 So the ISS mismatch only changes the output current when the differential pair is unbalanced. The differential output current is given by ⎧⎪ ΔI SS [k ] ⎪⎪ I − ΔI [k ] if v − kV < −V SS I R SAT + ⎪⎪ SS gm 0 ⎪⎪ ⎪ ΔI SS [k ] (A.19) iDIFF [k, vI ] = ⎪⎨−gm 0 (vI − kVR ) if vI − kVR ≤ VSAT − ⎪⎪ gm 0 ⎪⎪ ΔI SS [k ] ⎪⎪ . ⎪⎪ −I SS + ΔI SS [k ] if vI − kVR > VSAT − gm 0 ⎪⎩ For small ΔISS[k], this expression can be approximated by

4

Another possibility would be to maintain VSAT and change the gm0 value accordingly, using (A.2). In real differential pairs both VSAT and gm0 vary.


324

⎛ ΔI ⎞ iDIFF [k, vI ] iDIFF 0 [k, vI ] + fΔI SS / I SS [k, vI ]⎜⎜ SS ⎟⎟⎟ [k ] ⎜⎝ I SS ⎟⎠ where iDIFF0[k,vI] is given by (A.1) and fΔI SS / I SS

⎧⎪−I SS ⎪⎪ ⎪ [k, vI ] = ⎪⎨ 0 ⎪⎪ ⎪⎪ I SS ⎪⎩

(A.20)

if vI − kVR < −VSAT

(A.21)

if

vI − kVR ≤ VSAT

if

vI − kVR > VSAT .

iDIFF[k,vI] ISS ISS-ΔISS[k] -VSAT

VSAT vI-kVR

-(ISS-ΔISS[k]) -ISS ΔISS[k]/gm0

Figure A.9. Effect of a ΔISS[k] mismatch on the transfer function of differential pair k.

Particularizing this expression for vI = 0 yields, finally, ⎧⎪−I ⎪⎪ SS if k > N ⎪ (A.22) fΔI SS / I SS [k, 0] = ⎪⎨ 0 if k ≤ N ⎪⎪ ⎪I if k < N . ⎪⎩⎪ SS The fact that, under the approximation being considered, this mismatch does not affect the differential output current of a non-saturated differential pair, makes fΔI SS / I SS [k, 0] = 0 for k ≤ N . Note that this does not happen when the quadratic drain current model is used, as (2.61) shows. Using (A.22) in (2.43) and (2.48) leads to

Appendix A: Averaging with Piecewise Linear Diff. Pairs −(N +1)

σ 2 (VOS )ΔI

∑

SS

=

/ I SS

k =−∞

ΔI SS / I SS

2 2I SS C 2N +

=

−(N +1)

∑

k =−∞

2

2 = 4VSAT

∑

2

C 2k −2 (−I SS )

k =N +1

⎡ N ⎤ ⎢ ∑ C k −1gm 0 ⎥ ⎢ ⎥ ⎣⎢k =−N ⎦⎥

2 = VSAT

σ 2 (VOS [1] −VOS [ 0 ])

∞

2 C −2k −2I SS +

325

2

⎛ ΔI ⎞ σ 2 ⎜⎜⎜ SS ⎟⎟⎟ = ⎜⎝ I SS ⎠⎟

⎛ ⎞ 1 −C 2C 2N +2 2 ⎜ ΔI SS ⎟ ⎟ σ ⎜ ⎟ 1 + C (1 + C − 2C N +1 )2 ⎜⎜⎝ I SS ⎠⎟

(A.23)

=

⎡C −(k −1)−1I − C −k −1I ⎤ 2 + SS SS ⎦⎥ ⎣⎢

∞

∑

k = N +2 2

(1 − C )

C 2N + 2

1 +C

(1 + C − 2C N +1 )

2

⎡C (k −1)−1 (−I ) − C k −1 (−I )⎤ 2 SS SS ⎦⎥ ⎣⎢

⎡ N ⎤ k −1 ⎢ gm 0 ⎥⎥ ⎢ ∑ C ⎣⎢k =−N ⎦⎥ ⎛ ⎞ Δ I ⎟ σ 2 ⎜⎜⎜ SS ⎟⎟ . ⎜⎝ I SS ⎟⎠

⎛ ΔI σ 2 ⎜⎜⎜ SS ⎝⎜ I SS

⎟⎟⎞ = ⎟⎟⎠

(A.24)

These expressions can now be evaluated for the example being considered in this appendix. In order to make a comparison with the results achieved in section 2.4.4 the same value, 0.527%, is considered for σ(ΔISS/ISS). Figure A.10 represents the standard deviation of the offset voltage, which is proportional to the INL. Figure A.11 represents the standard deviation of the difference between the offset voltages of two consecutive differential pairs, which is proportional to the DNL. The HSPICE simulation results presented in section 2.4.4 are also show in these figures. The same overall behavior is observed comparing Fig. A.10 with Fig. 2.16 and Fig. A.11 with Fig. 2.21. However the results obtained in section 2.4.4 are much closer to HSPICE Monte-Carlo simulation results. Equation (A.12) indicates that a ΔV mismatch only changes the differential output current of non-saturated differential pairs. On the other hand, (A.22) shows that a mismatch on ISS only modifies the output current of differential pairs that are saturated. It is possible to have the situation where the standard deviation of the error currents due to the ΔV mismatch, equals the standard deviation of the error currents resulting from the ISS mismatch, ⎛ ΔI ⎞ ⎛ ΔI ⎞ σ (ΔV ) . gm 0σ (ΔV ) = I SS σ ⎜⎜⎜ SS ⎟⎟⎟ ⇔ σ ⎜⎜⎜ SS ⎟⎟⎟ = VSAT ⎝ I SS ⎠⎟ ⎝ I SS ⎟⎠

(A.25)


326

540 480

σ(VOS)ΔISS/ISS [μV]

420

R 0/R 1 = 10

360 300 240 180

R 0/R 1 = 2

120

R 0/R 1 = 1

60

R 0/R 1 = 0.5 0 R /R = 0.1 0 1


-60 1

2

3

4

5

6

7

N

Figure A.10. Standard deviation of the offset voltage, due to ISS mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.23). 270 R /R = 10 0 1

σ(VOS[1]-VOS[0])ΔISS/ISS [μV]

240 210 180 150 120

R 0/R 1 = 2

90 R 0/R 1 = 1

60 30

R 0/R 1 = 0.5

0 R 0 /R 1 = 0.1


-30 1

2

3

4

5

6

7

N

Figure A.11. Standard deviation of the difference between the offset voltages of two consecutive pre-amplifiers, due to ISS mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.24).


327

In these circumstances all differential pairs, saturated and non-saturated, have error currents with the same standard deviation.5 It was for this very particular case that [104, 106] accounted the ISS mismatches in the calculation of the INL and DNL. Conversely, although (A.23) and (A.24) are derived using the same approximations (piecewise linear differential pairs, ISS mismatch only affects the currents of saturated differential pairs), they yield results for the general case.

A.3.3

Mismatches in Resistors R0

Although all previous published works ignored the mismatches in the resistors, we will still evaluate them here using the piecewise linear transfer function approximation, and compare the results against those obtained in chapter 2. The INL and DNL due to mismatches in the transistors and current sources were determined calculating the deviations caused by those mismatches in the output currents of the differential pairs. The existence of mismatches in the resistors also influences the current that flows through them, just like the mismatches on transistors influence their collector/drain currents. Those current deviations are calculated in appendix B to determine the fΔR0 / R0 [k, vI ] and fΔR1 / R1 [k, vI ] functions. For the mismatches in R0,

I SS . 2 Substituting (A.26) in (2.43) and (2.48) leads to fΔR0 / R0 [k, vI ] =

2 I SS ⎟⎞ 2 k −2 ⎛ ⎜ C ⎟ ⎜⎜ ∑ ⎝ 2 ⎟⎠ k =−∞

(A.26)

∞

σ 2 (VOS )ΔR

0

5

/ R0

=

2

⎛ ΔR0 ⎞⎟ ⎟= σ 2 ⎜⎜ ⎜⎝ R0 ⎟⎟⎠

⎡ N ⎤ ⎢ ∑ C k −1gm 0 ⎥ ⎢ ⎥ ⎢⎣k =−N ⎥⎦ 2 ⎛ ΔR0 ⎟⎞ V 1 −C 1 +C 2 ⎟ σ 2 ⎜⎜ = SAT 2 ⎜⎝ R0 ⎟⎟⎠ 4 1 + C (1 + C − 2C N +1 )

(A.27)

There were two possibilities to model the effect of ISS mismatches in the transfer function of the differential pairs: maintain gm0 and change VSAT or maintain VSAT and change the gm0. We have opted by the first possibility as [104, 106] did, although they do not state that explicitly. But, when choosing the second possibility, the situation considered on those references – all differential pairs, saturated and non-saturated, have error currents with the same standard deviation – never occurs. Moreover, using (A.25) together with (A.13), (A.14), (A.23) and (A.24) leads to the expressions presented in [104, 106], when Wn → ∞.


328

∞

σ 2 (VOS [1] −VOS [ 0 ])ΔR

=

0 / R0

=

⎡ I I − C k −1 SS ∑ ⎢⎢⎣C k −1 −1 SS 2 2 k =−∞ 2

2 VSAT 2

⎤2 ⎥ ⎥⎦

⎛ ΔR0 ⎞⎟ ⎟⎟ = σ 2 ⎜⎜⎜ ⎝⎜ R0 ⎠⎟

⎡ N ⎤ ⎢ ∑ C k −1gm 0 ⎥ ⎢ ⎥ ⎢⎣k =−N ⎥⎦ ⎛ ΔR0 ⎟⎞ (1 − C )2 1 −C . ⎟. (A.28) σ 2 ⎜⎜⎜ 2 ⎜⎝ R0 ⎟⎟⎠ 1 + C (1 + C − 2C N +1 )

These expressions will now be evaluated for the example being considered in this appendix. In order to make a comparison with the results achieved in section 2.4.4, the same value is chosen for σ(ΔR0/R0), 0.593%. Figure A.12 represents the standard deviation of the offset voltage, which is proportional to the INL. Figure A.13 represents the standard deviation of the difference between the offset voltages of two consecutive differential pairs, which is proportional to the DNL. The HSPICE simulation results presented in section 2.4.4 are also show in these figures. The same overall behavior is observed comparing Fig. A.12 with Fig. 2.17 and Fig. A.13 with Fig. 2.22. However, in this case there are more profound differences between the results obtained in this appendix and in section 2.4.4: not even the values found in the absence of averaging are equal. To understand why, note that when averaging is not used (A.27) reduces to ⎛ ΔR0 ⎟⎞ V (A.29) ⎟⎟ . σ (VOS )ΔR / R = SAT σ ⎜⎜⎜ 0 0 2 ⎝ R0 ⎟⎠ When the quadratic drain current model of the MOS transistors is used, (1.58) yields ⎛ ΔR0 ⎟⎞ V ⎟. (A.30) σ (VOS )ΔR / R = OVD σ ⎜⎜ 0 0 ⎜⎝ R ⎟⎟⎠ 2 0

As in that case VSAT = 2VOVD ,

1 VSAT ⎛⎜ ΔR0 ⎞⎟ (A.31) ⎟. σ⎜ ⎜⎝ R0 ⎠⎟⎟ 2 2 For the same VSAT, the values obtained from (A.29) and (A.31) difσ (VOS )ΔR

0 / R0

=

fer by a 2 factor. In this way the values indicated in Figs. A.12 and A.13 for the case without averaging are 2 larger than those presented in Figs. 2.17 and 2.22. When averaging is used the results shown in Figs. A.12 and A.13 are also larger than those obtained in chapter 2.


329

1000 Case without averaging 900

σ(VOS)ΔR0/R0 [μV]

800

R0/R1 = 0.1

700 600

R0/R1 = 0.5

500

R0/R1 = 1

400

R0/R1 = 2

300

R0/R1 = 10

200 2

3

4

5

6

7

8

σ(VOS[1]-V OS[0])ΔR0/R0 [μV]

N Figure A.12. Standard deviation of the offset voltage, due to R0 mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.27).

1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0

Case without averaging R 0/R 1 = 0.1

R 0/R 1 = 0.5 R 0/R 1 = 1 R 0/R1 = 2 R 0/R 1 = 10 2

3

4

5

N

6

7

8

Figure A.13. Standard deviation of the difference between the offset voltages of two consecutive pre-amplifiers, due to R0 mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.28).


330

A.3.4

Mismatches in Resistors R1

The fΔR1 / R1 [k, vI ] function, which determines the error currents due to the mismatches in the resistors R1, is derived in appendix B: fΔR1 / R1 [k, vI ] =

C k −1 − k − 1 ⎛⎜⎜ ∞ B ⎜ ∑ iDIFF 0 [ p, vI ] C p−k +1 −1 − C p−k −1 ⎜⎜⎝ p =−∞ 2R1

(

⎞

)⎟⎟⎟⎟⎟ . (A.32) ⎠

This is the most complex of all mismatch functions. Substituting it in (2.43) and (2.48) leads to expressions that, unlike the others presented in this appendix, cannot be significantly simplified, 2 ⎧ ∞ ⎪ ⎪⎫⎪ ⎪ ∑ ⎨⎪ ∑ iDIFF 0 [ p, 0]c [k, p ]⎬⎪ ⎛ ⎞ ⎪⎭⎪ 2 ⎜ ΔR1 ⎟ k =−∞ ⎪ ⎪p =−∞ ⎩ ⎟(A.33) σ ⎜⎜ R1 ⎟⎟⎠ ⎛ 1 + C − 2C N +1 ⎞⎟2 ⎝ ⎜⎜ ⎟ ⎜⎜⎝ C (C − 1) ⎠⎟⎟ ∞

σ 2 (VOS )ΔR

1 / R1

⎛ B ⎞⎟2 ⎟⎟ = ⎜⎜⎜ ⎝ 2gm 0R1 ⎠⎟

2 ⎧ ∞ ⎪ ⎪⎫ ⎪ ⎪⎬ i p , 0 c k 1, p c k , p − − [ ] [ ] [ ] ( ) ⎨ ∑ ⎪ ∑ DIFF 0 ⎪⎪ ⎛ ⎞ k =−∞ ⎪ ⎪p=−∞ ⎩ ⎭⎪ σ 2 ⎜⎜ ΔR1 ⎟⎟ (A.34) ⎟ ⎜ 2 ⎛⎜ 1 + C − 2C N +1 ⎞⎟ ⎝⎜ R1 ⎠⎟⎟ ⎟ ⎜⎜⎜ C (C − 1) ⎟⎟ ⎝ ⎠⎟ ∞

σ 2 (VOS [1] − VOS [ 0 ]) ΔR

1 / R1

⎛ B ⎟⎞2 ⎟⎟ = ⎜⎜⎜ ⎝⎜ 2gm 0 R1 ⎟⎟⎠

with

(

)(

c [k, p ] = C k −1 −1 − C k −1 C

p −(k −1) −1

)

− C p −k −1 .

(A.35)

The sums do not need to be evaluated between ±∞: sufficiently high limits for k and p yield results with the required accuracy. These expressions will now evaluated for the example being considered in this appendix. In order to make a comparison with the results achieved in section 2.4.4, the same value for σ(ΔR1/R1) is considered, 0.593%. Figure A.14 represents the standard deviation of the offset voltage, which is proportional to the INL. Figure A.15 represents the standard deviation of the difference between the offset voltages of two consecutive differential pairs, which is proportional to the DNL. The HSPICE simulation results presented in section 2.4.4 are also show in these figures. Similar results are observed comparing Fig. A.14 with Fig. 2.18 and Fig. A.15 with Fig. 2.23, although the ones obtained in section 2.4.4 are still nearer HSPICE simulations results. The complexity of the expressions obtained in this sub-section to account for the mismatches in R1, is comparable to those where the quadratic drain current model is used, which are evaluated in chapter 2.


331

360 320

σ(V OS)ΔR1/R1 [μV]

280

R0/R1 = 10

240 200

R0/R1 = 2

160

R0/R1 = 1

120 80 40

R0/R1 = 0.5 R0/R1 = 0.1

0


-40 1

2

3

4

5

6

7

N

Figure A.14. Standard deviation of the offset voltage, due to R1 mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.33). 450 400

σ(VOS[1]-V OS[0])ΔR1/R1 [μV]

350

R 0/R 1 = 10

300 250

R 0/R 1 = 2 R 0/R 1 = 1

200 150 100

R 0/R 1 = 0.5

R 0/R1 = 0.1

50 0


-50 1

2

3

4

N

5

6

7

Figure A.15. Standard deviation of the difference between the offset voltages of two consecutive pre-amplifiers, due to R1 mismatch, as a function of N. The dots are obtained from HSPICE Monte-Carlo simulations and the lines are from (A.34).

Appendix B Mismatches in the Resistors of the Averaging Network B.1

INTRODUCTION

In chapter 2 the INL and DNL due to a mismatch Δψ[k] in differential pair k, were determined by calculating the deviation it causes in the differential drain/collector current, fΔψ[k,vI]Δψ[k]. In other words, the output current of differential pair k, iDIFF[k,vI], was expressed as the sum of the error current, fΔψ[k,vI]Δψ[k], with the current found in the absence of mismatches, iDIFF0[k,vI]. This is represented in Fig. 2.13. It can be concluded that the error current scales proportionally to the magnitude of the mismatch, Δψ[k], and its shape is determined by fΔψ[k,vI]. This function, which differs from mismatch type to mismatch type (examples are given in section 2.4.4), is essential in the calculation of the variance of the INL and DNL. The existence of mismatches in the resistors R0 and R1 (see Fig. 2.3) also influences the current that flows through them, just like the mismatches on transistors influence their collector/drain currents. Those current deviations are calculated in this appendix, and fΔR0 / R0 [k, vI ] and fΔR1 / R1 [k, vI ] are derived. These functions can then be used on (2.43) and (2.48) to calculate the INL and DNL due to mismatches in resistors, just like it was done for the mismatches in transistors and current sources.

B.2

MISMATCHES IN RESISTORS R0

Figure B.1 represents a mismatch between resistors R0 of the kth differential pair. Current iP[k,vI] is

VDD − vOP [k, vI ] VDD − vOP [k, vI ] − ΔiP [k, vI ] ΔR0 [k ] R0 R0 + 2 where ΔiP[k,vI] is the error current due to the mismatch in R0, iP [k, vI ] =

(B.1)

333


334

ΔiP [k, vI ] =

VDD − vOP [k, vI ] ⎛⎜ ΔR0 ⎞⎟ ⎟ [k ]. ⎜ ⎜⎝ R0 ⎠⎟⎟ 2R0

VDD

R0+ΔR0[k]/2

(B.2)

VDD

iP[k,vI]

R1 vOP[k,vI]

R1

R0−ΔR0[k]/2

iN[k,vI]

R1 vON[k,vI]

R1

Figure B.1. Mismatch in the resistances R0 of differential pair k (© 2004 by IEEE).

Similarly iN[k,vI] can be approximated by iN [k, vI ]

with

VDD − vON [k, vI ] − ΔiN [k, vI ] R0

(B.3)

VDD − vON [k, vI ] ⎛⎜ ΔR0 ⎞⎟ (B.4) ⎟ [k ]. ⎜ ⎜⎝ R0 ⎠⎟⎟ 2R0 These approximations are valid if ΔR0[k] R0, which is the common situation in the case of mismatches between similar resistances. Having (B.1) and (B.3) in account, and writing Kirchhoff current equations in node k, leads to the conclusion that the equivalent circuit of Fig. B.2 can be used. ΔiN [k, vI ] = −

VDD

VDD

R0

R0

vOP[k,vI] R1 ΔiP[k,vI]

vON[k,vI] R1

R1

R1

ΔiN[k,vI]

Figure B.2. Model used to account for mismatches in R0 (© 2004 by IEEE).

There are, thus, error current sources that model the effect of the mismatches in resistors, just like in the case of mismatches in transis-

Appendix B: Resistor Mismatches in the Av. Network

335

tors. The same formalism can therefore be used, by writing the differential error current as ⎛ ΔR0 ⎞⎟ (B.5) ⎟⎟ [k ] ΔiP [k, vI ] − ΔiN [k, vI ] = fΔR0 / R0 [k, vI ]⎜⎜⎜ ⎝ R0 ⎠⎟ with fΔR0 / R0 [k, vI ] =

2VDD − (vOP [k, vI ] + vON [k, vI ])

. (B.6) 2R0 As seen in (B.6), the determination of fΔR0 / R0 [k, vI ] depends on the

calculation of vOP[k,vI] and vON[k,vI].1 These are evaluated ignoring mis-

matches, which is reasonable because they are small.2 Using (2.17) and (2.18) leads to a rather simple solution,3 I (B.7) fΔR0 / R0 [k, vI ] = SS 2 where ISS is the tail current of the differential pairs, which can either use MOS or bipolar transistors. The fΔR0 / R0 [k, vI ] function is independent of the input voltage and of the position of the pair of resistors being considered (outputs of differential pair k). The error current is calculated using (B.5) and (B.7), yielding I ⎛ ΔR0 ⎞⎟ (B.8) ⎟ [k ]. ΔiP [k, vI ] − ΔiN [k, vI ] = SS ⎜⎜⎜ 2 ⎝ R0 ⎠⎟⎟

B.3

MISMATCHES IN RESISTORS R1

Figure B.3 represents the mismatches in the resistances which connect the outputs of differential pairs k – 1 and k. The deviation of the 1

Note that (B.6) is the general expression for fΔR0 / R0 [k, vI ], and can be used in the case of preamplifier stages or folding circuits. Equation (B.7) is the particularization of (B.6) for pre-amplifier stages. The case of folding circuits is discussed in appendix C.

2

This process is identical to the AC analysis of electrical circuits: the parameters that characterize the response of the circuit to variations on its input(s) – transconductances, for example – are determined using information – current/voltage values – from the steady state situation (operating point).

3

An alternative and easier way of evaluating (B.6) is to note that vOP [k, vI ] + vON [k, vI ] corresponds to twice the output common-mode voltage which, in a pre-amplifier stage, means that ⎛ I ⎞ vOP [k, vI ] + vON [k, vI ] = 2 ⎜⎜⎜VDD − R0 SS ⎟⎟⎟. ⎝ 2 ⎠


336

resistance from the ideal value, R1, was divided into a differential-mode component (ΔR1[k]), and a common-mode component (δR1[k]). It can be verified that, in all other mismatch sources considered until now, a common-mode component does not affect the location of the zero crossings. In this case, as will be shown, it is the common-mode component the one responsible for zero crossing deviations. These two components will now be addressed separately. VDD R0 vOP[k−1,vI]

VDD

iP[k,vI]

R0

R0 vOP[k,vI]

vON[k−1,vI]

iN[k,vI]

R0 vON[k,vI]

R1+ΔR1[k]/2+δR1[k] R1−ΔR1[k]/2+δR1[k] Figure B.3. Mismatch in the resistors R1 connected between differential pairs k and k (© 2004 by IEEE).

B.3.1

–1

Common-Mode Mismatch Component (δR1[k])

Current iP[k,vI] can be written as iP [k, vI ] =

vOP [k, vI ] − vOP [k − 1, vI ] R1 + δR1 [k ]

vOP [k, vI ] − vOP [k − 1, vI ]

− δiP [k, vI ] R1 where δiP[k,vI] is the error current, due to the δR1 mismatch,

vOP [k, vI ] − vOP [k − 1, vI ] ⎛⎜ δR1 ⎞⎟ ⎟⎟ [k ]. ⎜⎜ R1 ⎝ R1 ⎠⎟ Similarly iN[k,vI] is be approximated by

δiP [k, vI ] =

vON [k, vI ] − vON [k − 1, vI ] − δiN [k, vI ]. R1 Having in consideration that iN [k, vI ]

vON [k, vI ] − vON [k − 1, vI ] = − (vOP [k, vI ] − vOP [k − 1, vI ]), leads to v [k, vI ] − vON [k − 1, vI ] ⎜⎛ δR1 ⎞⎟ ⎟⎟ [k ] = −δiP [k, vI ]. δiN [k, vI ] = ON ⎜ R ⎝⎜ R ⎠⎟ 1

(B.9)

(B.10)

(B.11) (B.12)

(B.13)

1

These approximations are valid for ΔR1[k] R1, which is the common situation in the case of mismatches between similar resistances. Taking (B.9) and (B.11) in consideration and writing Kirchhoff current

Appendix B: Resistor Mismatches in the Av. Network

337

equations in nodes k – 1 and k, it can be concluded that the model in Fig. B.4 may be used. VDD

VDD R0

R0 R1

vOP[k−1,vI]

δiP[k,vI]

R0

R0 vOP[k,vI]

R1

vON[k−1,vI]

δiP[k,vI]

vON[k,vI]

−δiP[k,vI]

−δiP[k,vI]

Figure B.4. Model used to account for common-mode mismatches in R1 (© 2004 by IEEE).

There are, again, error currents resulting from the presence of mismatches, just like in the case of transistors and R0. However, in those cases, the mismatch in each pair of elements is modeled by current sources at the output nodes of a single differential pair. The mismatches in R1 result in error currents at the outputs of two differential pairs, as Fig. B.4 shows. However, the current sources at nodes k – 1 can be transferred to nodes k, by using a value that produces the same effect on the output voltage of differential pair 04; this is represented in Fig. B.5. VDD R0

R0 vOP[k−1,vI]

VDD

R1

δiP[k,vI]

R0

R0 vOP[k,vI]

δiP[k,vI]

vON[k−1,vI]

δiP[k]C|k−1|−|k|

R1

vON[k,vI]

−δiP[k,vI]

−δiP[k]

-δiP[k]C|k−1|−|k|

Figure B.5. Transformation to have both current sources in node k, while causing the same effect on the output voltage of differential pair 0 (© 2004 by IEEE).

The model is now resembling to the one found for the mismatches in R0. The differential output error current is ⎛ δR ⎞ fδR1 / R1 [k, vI ]⎜⎜ 1 ⎟⎟⎟ [k ] = 2δiP [k, vI ] C k −1 − k − 1 . ⎜⎝ R1 ⎟⎠

(

4

)

(B.14)

The zero crossing of differential pair 0 was considered in chapter 2 to determine the standard deviation of the INL. The objective here is to derive the fΔR1 / R1 [k, vI ] function which, when substituted in (2.43), yields the σ(INL) due to the mismatches in R1.


338

Using (B.10) leads to ⎛ δR ⎞ v [k, vI ] − vOP [k − 1, vI ] k −1 − k fδR1 / R1 [k, vI ]⎜⎜⎜ 1 ⎟⎟⎟[k ] = 2 OP C −1 R1 ⎝⎜ R1 ⎠⎟

⎛

⎞

)⎜⎜⎜⎜⎝ δRR ⎟⎟⎟⎟⎠[k ], (B.15)

(

1

1

which means that5 fδR1 / R1 [k, vI ] = 2

vOP [k, vI ] − vOP [k − 1, vI ]

R1 Substituting (2.17) in this expression yields fδR1 / R1 [k, vI ] =

(C k −1 − k − 1).

C k −1 − k − 1 ⎛⎜⎜ ∞ B ⎜ ∑ iDIFF 0 [ p, vI ] C p−k +1 −1 − C p−k −1 ⎜⎜⎝ p =−∞ R1

(

(B.16) ⎞

)⎟⎟⎟⎟⎟

(B.17)

⎠

where iDIFF0[p,vI] is the differential drain/collector current of differential pair p, for the input voltage vI, when there are no mismatches in this differential pair. The standard deviation of the error current is ⎛ δR ⎞ fδR1 / R1 [k, vI ] σ ⎜⎜ 1 ⎟⎟⎟ . ⎜⎝ R ⎠⎟ 1

⎛ ΔR ⎞⎟ The matching characterization is usually done in terms of σ ⎜⎜ , ⎜⎝ R ⎠⎟⎟ which is the standard deviation of the normalized difference of the resistances of two equal sized resistors. Considering two mismatched resistors, Ra and Rb, which were supposed to be equal to R (σ(Ra) = σ(Rb) = σ(R)), then

σ 2 (ΔR ) = σ 2 (Ra − Rb ) = 2σ 2 (R )

(B.18)

2

⎛ R + Rb ⎟⎞ σ (R ) . (B.19) σ 2 (δR ) = σ 2 ⎜⎜ a ⎟= ⎝ ⎠⎟ 2 2 which allows to conclude that ⎛ δR ⎞ 1 ⎛ ΔR ⎟⎞ (B.20) σ ⎜⎜ ⎟⎟⎟ = σ ⎜⎜⎜ ⎟. ⎝ R ⎠ 2 ⎝ R ⎠⎟ In this way the standard deviation of the error current can be writ⎛ ΔR1 ⎟⎞ ⎟, where ten as fΔR1 / R1 [k, vI ] σ ⎜⎜ ⎜⎝ R ⎟⎟⎠ 1

5

Note that (B.16) is the general expression for fδR1 / R1 [k, vI ], and can be used in the case of preamplifier stages or folding circuits. Equation (B.17) is the particularization of (B.16) for preamplifier stages. The case of folding circuits is discussed in appendix C.

Appendix B: Resistor Mismatches in the Av. Network fδR1 / R1 [k, vI ]

fΔR1 / R1 [k, vI ] = =

2

339

=

C k −1 − k − 1 ⎛⎜⎜ ∞ B ⎜ ∑ iDIFF 0 [ p, vI ] C p−k +1 −1 − C p−k −1 ⎜⎜⎝ p =−∞ 2R1

(

⎞

)⎟⎟⎟⎟⎟. (B.21) ⎠

This expression can be substituted in (2.43) and (2.48) to calculate the σ(INL) and σ(DNL),6 due to the mismatches in R1.

B.3.2

Differential-Mode Mismatch Component (ΔR1[k])

Considering only the differential-mode mismatch between the resistors R1 represented in the Fig. B.3, iP[k,vI] can be written as

vOP [k, vI ] − vOP [k − 1, vI ] ΔR1 [k ] R1 + 2 vOP [k, vI ] − vOP [k − 1, vI ] − ΔiP [k, vI ] (B.22) R1 where ΔiP[k,vI] is the error current due to the differential mismatch in R1, iP [k, vI ] =

ΔiP [k, vI ] =

vOP [k, vI ] − vOP [k − 1, vI ] ⎛⎜ ΔR1 ⎞⎟ ⎟ [k ] . ⎜ ⎜⎝ R1 ⎠⎟⎟ 2R1

(B.23)

Noting that

vON [k, vI ] − vON [k − 1, vI ] = − (vOP [k, vI ] − vOP [k − 1, vI ]), it can easily be verified that

(B.24)

(B.25) ΔiN [k, vI ] = ΔiP [k, vI ] . A differential-mode mismatch in R1 generates equal error currents on the positive and on the negative side of the network. This does not affect the differential output voltages of the differential pairs. Thus the location of the zero crossings remains unchanged and, therefore, this is not a source of offset voltage.

6

The derivation of (B.21) is based on the transformation represented in Fig. C.5, which is only valid to calculate the output voltage of differential pair 0 (and, therefore, VOS[0]). Since the DNL also depends of VOS[1], one might wonder if (B.21) can be used directly in (2.48). It may be shown that it can.

Appendix C Averaging in Folding Stages C.1

INTRODUCTION

A large portion of chapter 2 is devoted to the study of averaged preamplifying stages (see Fig. 2.3). The averaged folding stage represented in Fig. C.1 is analyzed in this appendix. It has FB folding circuits (numbered from 0 to FB – 1), each having FF differential pairs. As in the pre-amplifier stages, R0 are the load resistors and R1 are the averaging resistors. Note that R1 now connects consecutive folding circuits, not single differential pairs. The pre-amplifier stages were analyzed considering that the averaging network was infinite.1 The averaging network of a folding stage, on the other hand, does not have boundaries – it is circular.2 Figure C.2 shows the folding stage model, where iFOLDP[q,vI] and iFOLDN[q,vI] are the output currents of the folding circuit3 q, for an input voltage vI; its positive and negative output voltages are designated vOP[q,vI] and vON[q,vI]. There are 2FB output nodes, numbered from 0 to 2FB – 1; the voltage at node j is called vO[j,vI]. The positive and negative outputs of the same folding circuit are FB nodes apart: for example, node 1 corresponds to the positive output of folding circuit 1 and node FB + 1 corresponds to its negative output. In this way vO[1,vI] = vOP[1,vI] and vO[FB + 1,vI] = vON[1,vI]. All the theoretical results derived in chapter 2 for the infinite averaged pre-amplifier stage are based on (2.16) (repeated here for convenience),

vO [ j, vI ] k = −BC k − j −1iD [k, vI ],

(C.1)

1

Although in practice this is not true, it is possible to terminate the network making it behave as the ideal, infinite, one (see section 2.7.2).

2

Although this network does not have boundaries, there are still deviations in the zero crossings of the differential pairs with reference voltages near the extremities. This is discussed in sections 1.5.1 and 2.7.4.

3

The output currents of a folding circuit correspond to the sum of the currents of its FF differential pairs. 341


342

which yields the voltage at the node j, vO[j,vI]|k, originated by a current source connected to node k, iD[k,vI] (see Fig. 2.7 for the particular case of j = 0). To study averaging in folding stages a similar result must be established for circular networks. This is achieved by analyzing the circuit represented in Fig. C.3(a), where the output nodes are numbered as in Fig. C.2, and there is only one current source, iF[q,vI], at node q. vO[j,vI]|q is the voltage at node j originated by that single current source, while the total voltage at that node, vO[j,vI], results from the contributions of all current sources, according to the superposition theorem. VREFP Folding Circuit 0

iFOLDP[0,vI]

vON[0,vI]

iFOLDN[0,vI]

FF

R1

Folding Circuit 1

Resistive Ladder

R0

vOP[0,vI]

iFOLDP[1,vI]

R1

R0

vOP[1,vI] vON[1,vI]

iFOLDN[1,vI]

R0

R0 VDD

FF

R1

Folding Circuit FB−1

iFOLDP[FB−1,vI]

R0

vOP[FB−1,vI] vON[FB−1,vI]

iFOLDN[FB−1,vI]

FF

R1

R1

VREFN vI

Figure C.1. Folding stage with averaging.

R1

R0

iFOLDN[FB−1,vI]

R1

343

iFOLDN[1,vI]

R1

iFOLDN[0,vI]

FB+1 R1

iFOLDP[1,vI]

R1

iFOLDP[0,vI]

R1

0

vO[0,vI]=vOP[0,vI]

R0

1

vO[1,vI]=vOP[1,vI]

R0

FB−1

FB R1 iFOLDP[FB−1,vI]

vO[FB+1,vI]=vON[1,vI] vO[FB,vI]=vON[0,vI] vO[FB−1,vI]= vOP[FB−1,vI]

R0

VDD

R0

R0

2FB−1

vO[2FB−1,vI]= vON[FB−1,vI]

R0

Appendix C: Averaging in Folding Stages

Figure C.2. Model of the folding stage shown in Fig. C.1. vO[j,vI] refers to the voltage at the node j, while vOP[q,vI] and vON[q,vI] are the positive and negative output voltages of folding circuit q. There are FB folding circuits and 2FB nodes.

R1 R1

iF[q,vI]

vO[q,vI]|q R1

q vO[j,vI]|q vO[0,vI]|q

0

R1

1

vO[1,vI]|q

R1

j

R0 R0 R0

R1 vO[0,vI]|q

0

R0

(a)

2FB−1 R1

vO[FB−1,vI]|q vO[q+1,vI]|q

R0 R0

iF[q,vI]

q+1

R0

R1

2FB−1 R1

vO[q+1,vI]|q vO[q,vI]|q vO[j,vI]|q vO[1,vI]|q

1

R0

R1

j

R0

R1

q

R0

R1

q+1

R0 R0

vO[FB−1,vI]|q


344

(b)

Figure C.3. Circular network having a current source connected to node q that causes a voltage vO[j,vI]|q in node j (j and q are arbitrary). The arrows indicate: (a) the two smaller paths between nodes q and j; (b) a longer path, that includes a complete loop around the circular network.

Comparing Figs. C.2 and C.3(a) leads to the conclusion that, depending on q, iF[q,vI] represents the positive or negative output current of a folding circuit: for example, if q = 1 it corresponds to iFOLDP[1,vI] (current flowing in the positive output of folding circuit 1), while when q = FB + 2 it equals iFOLDN[2,vI] (current flowing in the negative output of folding circuit 2).


345

In a pre-amplifier stage there was a single path between two arbitrary nodes, and it was relatively easy to calculate the voltages caused by any current source. In a circular network there is an infinite number of paths between arbitrary nodes q and j; the two most obvious are indicated in Fig. C.3(a) by the arrows with the dashed lines. However, as shown in Fig. C.3(b), there are longer paths including an integer number of complete loops around the network. The analysis of the circular network is, therefore, a bit more involved. In the next section an equivalence between circular and infinite networks is demonstrated. This allows to calculate the output voltages of the folding stages, by using (C.1). The DC gain and offset expressions are derived afterwards.

C.2

EQUIVALENCE BETWEEN CIRCULAR AND INFINITE NETWORKS

Let us consider the network N represented in Fig. C.4, with two accessible ports and containing independent sources. I1

V1

I2

N

V2

Figure C.4. Linear network N, with two ports.

The relation between the currents and voltages at the two ports is given by [136] ⎛m11 m12 ⎟⎞ ⎜⎛V1 ⎟⎞ ⎛n11 n12 ⎞⎟ ⎛⎜I 1 ⎞⎟ ⎛u s 1 ⎞⎟ (C.2) ⎟ ⎜⎜ ⎟⎟ + ⎜⎜ ⎟ ⎜⎜ ⎟⎟ = ⎜⎜ ⎟ ⎜⎜⎜m ⎝ 21 m22 ⎟⎟⎠ ⎜⎝V2 ⎟⎟⎠ ⎝⎜n21 n22 ⎠⎟⎟ ⎝⎜I 2 ⎠⎟⎟ ⎜⎝u s 2 ⎠⎟⎟ where us1/us2 are non-zero due to the independent sources existing inside N, and mjk/njk are real rational functions of s, determined by the other elements of N (resistors, capacitors, controlled sources, etc.). For a set of values of V1, V2, I1 and I2, all internal currents and voltages of N are univocally determined, i.e. there is a single, well defined, solution. Let us now consider the situation depicted in Fig. C.5, where terminals 1 and 2 of N are shorted together, implementing a circular network. The voltages and currents in the two ports are, in this case, V 1 = V 2 = Vx (C.3)


346

I1 = −I2 = Ix.

(C.4)

− Ix

Ix

1

2

N

Vx

Vx

Figure C.5. Circular network.

Vx and Ix are univocally determined by the network parameters; in fact, substituting (C.3) and (C.4) in (C.2), yields ⎛m11 m12 ⎟⎞ ⎜⎛Vx ⎟⎞ ⎛n11 n12 ⎞⎟ ⎜⎛ I x ⎟⎞ ⎛u s 1 ⎞⎟ (C.5) ⎟ ⎜⎜ ⎟⎟ + ⎜⎜ ⎟ ⎜⎜ ⎜⎜⎜m ⎟⎟ = ⎜⎜ ⎟ ⎝ 21 m22 ⎟⎟⎠ ⎝⎜Vx ⎟⎟⎠ ⎝⎜n21 n22 ⎠⎟⎟ ⎝⎜−I x ⎟⎟⎠ ⎝⎜u s 2 ⎠⎟⎟ which can be solved to obtain Vx and Ix. Let us now examine the case shown in Fig. C.6, where one network N was substituted by two equal ones connected in series, forming a larger circular network.

−Iy2

Iy1

1 Vy1

N

−Iy1

Iy2

1

2 Vy2

Vy2

2

N

Vy1

Figure C.6. Circular network composed of two sub-networks N.

Since the situation at the ports of these two networks is indistinguishable, it is expected that Vy1 = Vy2 and Iy1 = Iy2. In fact, applying (C.2) to the ports of both networks leads to ⎛m11 m12 ⎞⎟ ⎜⎛Vy 1 ⎞⎟ ⎛n11 n12 ⎞⎟ ⎜⎛ I y 1 ⎞⎟ ⎛u s 1 ⎞⎟ ⎜⎜ (C.6) ⎟⎟ = ⎜⎜ ⎟ ⎟ ⎜⎜ ⎟⎟ + ⎜⎜ ⎟ ⎜⎜ ⎝⎜m21 m22 ⎠⎟⎟ ⎝⎜Vy 2 ⎠⎟⎟ ⎝⎜n21 n22 ⎠⎟⎟ ⎝⎜−I y 2 ⎠⎟⎟ ⎝⎜u s 2 ⎠⎟⎟

⎛m11 m12 ⎟⎞ ⎛⎜Vy 2 ⎟⎞ ⎛n11 n12 ⎟⎞ ⎜⎛ I y 2 ⎟⎞ ⎛u s 1 ⎟⎞ ⎜ ⎟ = ⎜ ⎟. (C.7) ⎟⎜ ⎟ + ⎜ ⎟⎜ ⎜⎝⎜m21 m22 ⎟⎟⎠ ⎜⎜Vy 1 ⎟⎟⎟ ⎜⎝⎜n21 n22 ⎟⎟⎠ ⎜⎜−I y 1 ⎟⎟⎟ ⎜⎜⎝u s 2 ⎟⎟⎠ ⎝ ⎠ ⎝ ⎠ As the right-hand terms of these equations are equal, this results in


347

m12 ⎞ ⎛⎜Vy 1 ⎞⎟ ⎛n11 n12 ⎞ ⎛⎜ I y 1 ⎞⎟ ⎛m11 m12 ⎞ ⎛⎜Vy 2 ⎟⎞ ⎛n11 n12 ⎞ ⎛⎜ I y 2 ⎞⎟ ⎛m ⎟⎟ ⎜ ⎟ + ⎜⎜ ⎟⎟ ⎜ ⎟⎟ ⎜ ⎟ + ⎜⎜ ⎟⎟ ⎜ ⎜⎜ 11 ⎟⎟ = ⎜⎜ ⎟⎟. (C.8) ⎟ ⎟ ⎜⎝m21 m22 ⎠⎟⎟ ⎜⎜⎝Vy 2 ⎠⎟⎟ ⎝⎜n21 n22 ⎠⎟⎟ ⎝⎜⎜−I y 2 ⎠⎟⎟ ⎝⎜m21 m22 ⎟⎠⎟ ⎝⎜⎜Vy 1 ⎟⎟⎠ ⎝⎜n21 n22 ⎟⎠⎟ ⎝⎜⎜−I y 1 ⎠⎟⎟

This relation only holds for any network (i.e. for any mjk/njk) if Vy1 = Vy2 = Vy and Iy1 = Iy2 = Iy. Substituting this in (C.6) or (C.7), results in ⎛m11 m12 ⎟⎞ ⎜⎛Vy ⎞⎟ ⎛n11 n12 ⎞⎟ ⎜⎛ I y ⎞⎟ ⎛u s 1 ⎞⎟ ⎜⎜ (C.9) ⎟ = ⎜⎜ ⎟. ⎟ ⎜ ⎟ + ⎜⎜ ⎟⎜ ⎜⎝m21 m22 ⎟⎟⎠ ⎜⎝⎜Vy ⎠⎟⎟⎟ ⎝⎜n21 n22 ⎠⎟⎟ ⎜⎝⎜−I y ⎠⎟⎟⎟ ⎝⎜u s 2 ⎠⎟⎟ Comparing (C.9) with (C.5) leads to the conclusion that Vy = Vx and Iy = Ix. Thus, in what concerns the voltages and the currents inside and at the ports of N, the situations shown in Figs. C.5 and C.6 are perfectly equivalent. If, as shown in Fig. C.7, there are three or more networks N, a similar reasoning leads to the conclusion that all port voltages and currents are Vx and Ix. When considering an arbitrarily large number of such networks one approaches the last case of Fig. C.7. This leads to the conclusion that, to calculate the internal currents and voltages of a network N, connected in the way represented in Fig. C.5 (circular network), one can analyze the infinite network shown at the bottom of Fig. C.7. Ix

−Ix

1

Ix

Ix Vx

−Ix

Ix

2

−Ix

1

Ix

2

N

2

Vx Vx

Ix

−Ix

1

2

Vx Vx

N

Ix

2

Vx

N

−Ix

1

Ix

2

N

Vx

Vx

−Ix

1

Vx

Circular Network composed of 3 networks N

Vx

N

−Ix

1

Vx Vx

N

−Ix

1

Vx Vx

N

1

Vx

Ix

2

Vx

2

Vx

N

Circular network composed of k networks N (k arbitrary)

−Ix

1

2

N

Vx

Infinite network

Figure C.7. Circuits where each of sub-networks N have voltages/currents equal to the ones found in the network represented in Fig. C.5.


348

C.3

OUTPUT VOLTAGE AND GAIN

C.3.1

Calculation of the Output Voltage

The expressions for the output voltages and DC gain of a folding stage with averaging are derived in this section. The first step is the calculation of the voltage at node j, vO[j,vI]|q, caused by the current source connected to node q, iF[q,vI] – see Fig. C.3. The total voltage at that node, vO[j,vI], results from the contributions of all the current sources, according to the superposition theorem, i.e.

vO [ j, vI ] = ∑ vO [ j, vI ] q . q

Let us consider that the shaded area of Fig. C.3 corresponds to the network N mentioned in the previous section: we have, therefore, the situation depicted in Fig. C.5. According to the equivalence just demonstrated, the internal voltages of N in Fig. C.5 are equal to the ones found in each of the sub-networks N, that form the infinite network represented in Fig. C.7. Thus, vO[j,vI]|q can be calculated by analyzing the circuit shown in Fig. C.8. This voltage is determined by summing the contributions of all the repetitions of iF[q,vI],4 that appear at the nodes q + 2FB p (p ∈ ]). Since the network now being analyzed is infinite, (C.1) can be used, yielding

vO [ j, vI ] q = −B

∞

∑

C

q +2FB p − j −1

iF [q, vI ].

(C.10)

p =−∞

According to equivalence demonstrated in the last section, the voltages at the nodes j + 2FB p (p ∈ ]) of the network represented in Fig. C.8, are all equal for any j. As two nodes of the circular network cannot be more than 2FB –1 nodes apart, q–j < 2FB, which leads to ∞

∑

C

q +2FB p − j −1

=

p =−∞

−1

∑

p =−∞

∞

− q +2FB p − j )−1 C ( + C q − j −1 + ∑ C q +2FB p− j −1. (C.11) p =1

After some algebra,

C q − j −1 + C 2FB − q − j −1 (C.12) iF [q, vI ]. 1 − C 2FB Equation (C.12) represents, for circular networks, the same that (C.1) represents for infinite networks. vO [ j, vI ] q = −B

4

This is equivalent to consider all the paths existing between node q and j, mentioned in the introduction of this appendix.

2FB−1 vO[j,vI]|q

−2FB

−j

−q

iF[q,vI]

−1

0

j

q

iF[q,vI]

2FB

2FB+j

2FB+q

4FB−1

349

iF[q,vI]


Figure C.8. Infinite network used to calculate vO[j,vI]|q.

To determine the voltage at node j, vO[j,vI], one must consider the contributions from the current sources in all nodes, i.e. from the output


350

currents of all folding circuits. The examination of Fig. C.2 leads to the following conclusions:

The positive output currents of the folding circuits connect to nodes 0 to FB − 1.

The negative output currents of the folding circuits connect to nodes FB to 2FB − 1.

The positive output current of folding circuit q is connected to node q, while its negative output current connects to node q+FB.

Having these observations in consideration, and applying the superposition theorem using (C.12), leads to the output voltage at node j: vO ⎡⎣ j, vI ⎤⎦ = −B

FB −1 ⎡

⎢ C q − j −1 + C 2FB − q − j −1 C iFOLDP ⎡⎣q, vI ⎤⎦ + 1 − C 2FB ⎢⎣

∑ ⎢⎢

q =0

(q +FB )− j −1

+ C 2FB − 1 − C 2FB

(q +FB )− j −1

⎤ ⎥ iFOLDN ⎡⎣q, vI ⎤⎦ ⎥ ⎥ ⎥⎦

. (C.13)

Figure C.2 also shows that the positive and negative output voltages of folding circuit j, vOP[j,vI] and vON[j,vI], are given by vOP [ j, vI ] = VDD + vO [ j, vI ]

(C.14)

(C.15) vON [ j, vI ] = VDD + vO [ j + FB , vI ]. The differential output voltage of this folding circuit is, therefore, vODIFF [ j, vI ] = vOP [ j, vI ] − vON [ j, vI ] = vO [ j, vI ] − vO [ j + FB , vI ]. (C.16) Decomposing the output currents of the folding circuits into a common mode, ICM, and a differential mode component, iFOLDDIFF[q,vI], iFOLDP [q, vI ] = ICM + iFOLDN [q, vI ] = ICM −

iFOLDDIFF [q, vI ] 2

iFOLDDIFF [q, vI ]

, 2 and using (C.13) in (C.16) leads, after some algebra, to FB −1

(C.17) (C.18)

C q − j −1 − C FB − q − j −1 iFOLDDIFF [q, vI ]. (C.19) ∑ 1 + C FB q =0 This equation yields the differential output voltages as the weighted sum of the differential output currents of the folding circuits (iFOLDDIFF[q,vI]). However, most times it is more convenient to have vODIFF[j,vI] expressed as a function of the currents in each differential pair: thus iFOLDDIFF[q,vI] must be decomposed in the sum of the currents of its FF differential pairs. vODIFF [ j, vI ] = −B


351

We consider that the middle differential pair5 of the folding circuit 0 has a reference voltage of 0 V; the remaining differential pairs either have a positive or a negative reference voltage. As in the pre-amplifier stage studied in chapter 2, the difference between consecutive reference voltages is VR. Table C.1 indicates the reference voltage of each differential pair in a stage having FB = 4 folding circuits, each with FF = 5 differential pairs (numbered from 1 to 5). In agreement with the convention adopted in the beginning of this paragraph, the third differential pair of folding circuit 0 (the middle one) has the 0 V reference voltage; the ones adjacent are the second differential pair of folding circuit 3 (VREF = –VR) and the third differential pair of folding circuit 1 (VREF = VR). Table C.1. Reference voltages for each differential pair (example for FF = 5, FB = 4). k −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 (VREF = kVR) Folding circuit 0 1 Folding circuit 1 Folding circuit 2

2 1

3 2

1

Folding circuit 3

4 3

2 1

4 3

2

5 5 4

3

5 4

5

The first differential pair of folding circuit 0 has the lowest reference voltage (–8VR) and the last differential pair of folding circuit 3 has the highest reference voltage (11VR). In the general case, the reference ⎛

F

– 1⎞

⎛

F +1

⎞

F ⎟⎟V to ⎜⎜F – 1⎟⎟⎟V R . The lowest voltages range from – ⎜⎜FB F ⎟⎠ ⎜⎝ B ⎜⎝ 2 2 ⎠⎟⎟ R reference voltage is always connected to the first differential pair of folding circuit 0, and the highest reference voltage connects to the last differential pair of folding circuit FB − 1. From now on, each differential pair in the folding stage will be designated according to its reference voltage. For example, the first differential pair of folding circuit 2 has the reference voltage −6VR and, therefore, it is called differential pair −6. This notation, which is similar to the one used for the pre-amplifier stages in chapter 2, is illus-

5

As mentioned in section 1.6.3, the folding circuit must have an odd number of differential pairs. If an even FF is required an extra current source must be connected to one of the outputs, which can be regarded as a differential pair that is completely unbalanced.


352

trated in Fig. C.9 with the folding circuit 2 of the example being considered. Its output currents are iFOLDP [2, vI ] = iDP [−6, vI ] + iDN [−2, vI ] + iDP [2, vI ] + iDN [6, vI ] + iDP [10, vI ] (C.20) iFOLDN [2, vI ] = iDN [−6, vI ] + iDP [−2, vI ] + iDN [2, vI ] + iDP [6, vI ] + iDN [10, vI ];(C.21)

this leads to iFOLDDIFF [2, vI ] = iDIFF [−6, vI ] − iDIFF [−2, vI ] + iDIFF [2, vI ] − iDIFF [6, vI ] + iDIFF [10, vI ],

(C.22) where iDIFF[k,vI] = iDP[k,vI] − iDN[k,vI] is the differential output current of differential pair k, for an input voltage vI. VDD

R0

R1

R1

R0

R1

iFOLDN[2,vI]

R1

iFOLDP[2,vI]

vOP[2,vI]

vON[2,vI] iDP[−6,vI]

iDN[−6,vI]

iDP[−2,vI]

iDN[−2,vI] vI

−6VR

iDP[2,vI]

iDN[2,vI]

vI

−2VR

ISS Differential pair −6

iDP[6,vI]

iDN[6,vI]

vI

2VR

iDP[10,vI]

iDN[10,vI]

vI

6VR

vI

10VR

ISS

ISS

ISS

ISS

Differential pair −2

Differential pair 2

Differential pair 6

Differential pair 10

Figure C.9. Folding circuit 2 of the example considered in Table C.1.

For arbitrary FF and FB the differential pair k, which has the reference voltage kVR and the differential output current iDIFF[k,vI], belongs to folding circuit (C.23) q = M [k, FB ], where M[k,FB] is the remainder of the division of k by FB. As indicated by (C.22), some differential pairs have a positive contribution to the output current, and some others have a negative contribution. Under the convention that was adopted, the contribution of differential pair k to the output current of folding circuit q is (C.24) (−1)Q [k ,FB ] iDIFF [k, vI ], where Q[k,FB] is the integer division of k by FB. Table C.2 presents the value of these functions for the example being considered. Using (C.23) and (C.24) allows to write (C.19) as FB

vODIFF [ j, vI ] = −B

FF +1 −1 2

∑F −1

k =−FB

F

2

C

M [k , FB ]− j −1

F − M [k , FB ]− j −1

−C B 1 + C FB

(−1)

Q [k , FB ]

iDIFF [k, vI ].(C.25)


353

Table C.2. Functions that determine the contribution of each differential pair (example for FF = 5, FB = 4). k −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 (VREF = kVR) M[k,FB]

0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3

Q[k,FB]

−2 −2 −2 −2 −1 −1 −1 −1 0 0 0 0 1 1 1 1 2 2 2 2

(−1)

Q [k ,FB ]

1 1 1 1 −1 −1 −1 −1 1 1 1 1 −1 −1 −1 −1 1 1 1 1

The output voltage expression, (C.25), is exact – for example it includes the systematic deviations mentioned in sections 1.5.1 and 1.6.3. Its accuracy depends exclusively on how the output currents of the differential pairs are determined:

Considering that the differential pairs have a piecewise linear transfer function (iDIFF[k,vI] given by (A.1)), yields the simplest but most inaccurate results. Considering that the differential pairs have the transfer function given by (2.26), obtained with the quadratic drain current model of the MOS transistors, yields results with a reasonable accuracy. Considering the transfer function obtained directly from a SPICE simulator, as it is done in the automatic design procedure presented in chapter 3, leads to the most accurate results.

The application examples presented in the following sub-sections use the quadratic drain current model. The resultant expressions are evaluated and compared to SPICE simulations in section 2.5, and a reasonable agreement is found.

C.3.2

Calculation of the Gain

The DC gain is calculated near vI = 0 (according to the convention being utilized, this is zero crossing of the middle differential pair of folding circuit 0). Differentiating (C.25) leads to


354

G0 =

∂vOFOLD [0, vI ] ∂v I FB

= −B

= vI = 0

FF +1 −1 2

M k ,F −1 F −M k ,F −1 C [ B ] −C B [ B ] (−1)Q [k ,FB ] gm [k, 0] . (C.26) ∑F −1 FB 1 +C F

k =−FB

2

Noting that only 2N + 1 non-saturated differential pairs define the gain because all others have gm[k,0] = 0, results in M k ,F −1 F −M k ,F −1 C [ B ] −C B [ B ] (−1)Q [k ,FB ] gm [k, 0]. (C.27) ∑ FB 1 +C k =−N As mentioned in section 1.6.3, practical designs must respect condition (1.66) to maximize the gain and avoid a certain type of systematic zero crossing deviations. Noting that ΔVF is the distance between consecutive zero crossings of the same folding circuit, ΔVF = FBVR, (C.28)

G0 = −B

N

and that, by definition, 2VOVD > NVR , condition (1.66) can be rewritten as (C.29) NVR < FBVR ⇔ N < FB . Under this condition, and since −N ≤ k ≤ N , ⎧⎪ k if k ≥ 0 (C.30) M [k, FB ] = ⎪⎨ ⎪⎪FB + k if k < 0, ⎩ ⎧⎪ 0 if k ≥ 0 (C.31) Q[k, FB ] = ⎪⎨ ⎪− ⎪⎩ 1 if k < 0, which allows to simplify (C.27) into C k −1 − C FB − k −1 (C.32) gm [k, 0]. ∑ 1 + C FB k =−N The particularization for the case of MOS differential pairs, using the quadratic drain current model, is done substituting (2.30) in (C.32), yielding G0 = B

N

2

C k −1 − C FB − k −1 1 − (k γ ) . (C.33) ∑ 2 1 + C FB k =−N (k γ ) 1− 2 Comparing (C.33) with the gain of a pre-amplifier stage with averaging, (2.31), leads to the conclusion that, given a certain VR and using the same differential pairs (W, L, ISS) and resistor values (R0, R1), the G 0 = g m 0B

N


355

gain of a folding stage is always lower than of a pre-amplifier stage. In fact (C.33) only approximates (2.31) when FB is sufficiently large, such that C FB 1, and also sufficiently larger than N, to have C k −1 C FB − k −1 for all k. In section 2.3.4 it was concluded that when N is increased, the gain of a pre-amplifier stage always increases, approaching the value found in the absence of averaging, gm0R0 (see Fig. 2.12). In a folding stage this does not happen; in fact, ⎧ k −1 F ⎪ ⎪ − C FB − k −1 > 0 if k < B C ⎪ ⎪ 2 ⎪ ⎪ F ⎪ k −1 ⎪ (C.34) − C FB − k −1 = 0 if k = B ⎨C ⎪ 2 ⎪ ⎪ ⎪ F ⎪ C k −1 − C FB − k −1 < 0 if k > B , ⎪ ⎪ 2 ⎪ ⎩ which means that if N exceeds FB/2, the last terms in (C.32) are negative, decreasing the gain.

C.4

EFFECT OF MISMATCHES

In averaged pre-amplifier stages there was one general expression for the INL and another for the DNL, and the particularization for each kind of mismatch was done by using the respective fΔψ[k,vI] function. In the case of a folding stage it is necessary to distinguish between the mismatches associated to each differential pair (Vt, β and ISS), and those associated with each folding circuit (R0 and R1).

C.4.1

INL due to Mismatches in the Transistors and Current Sources

As any other choice produces a similar result, the zero crossing of differential pair 06 is considered to calculate σ(INL). According to (2.39), the offset at this zero crossing is the ratio between the output voltage of folding circuit 0 at vI = 0, and the DC gain. Substituting (C.25) (with j = 0 and for vI = 0) and (C.26) in (2.39), and taking (2.40) in consideration leads to

6

In the convention being followed, this is the middle differential pair of folding circuit 0.


356 FB

VOS [0]Δψ = −

FF +1 −1 2

∑F −1 (C

k =−FB

FB

M [k ,FB ]−1

FB −M [k ,FB ]−1

−C

)(−1) [

Q k ,FB ]

fΔψ [k, 0 ] Δψ [k ]

F

2 FF +1 −1 2

∑F −1 (C

, (C.35) M [k ,FB ]−1

−C

FB −M [k ,FB ]−1

)(−1) [

Q k ,FB ]

gm [k, 0 ]

F

k =−FB

2

from which the variance can be obtained: FB

σ 2 (VOS )Δψ =

FF +1 −1 2

∑F −1 (C

k =−FB

M [k ,FB ]−1

−C

FB −M [k ,FB ]−1

)f 2

2 Δψ [k , 0 ]

F

2

⎡ FB FF +1 −1 ⎤2 ⎢ ⎥ 2 − − − M k , F 1 F M k , F 1 Q k ,F ⎢ C [ B ] − C B [ B ] (−1) [ B ] gm [k, 0 ]⎥⎥ ⎢ ∑ ⎢k =−F FF −1 ⎥ B 2 ⎣⎢ ⎦⎥

(

σ 2 (Δψ )

(C.36)

)

The variance of the INL is calculated by substituting the previous result in (2.38). To illustrate the application of this expression, we will consider the Vt mismatches in a folding stage designed to respect condition (C.29). Using (2.30), (C.30) and (C.31), allows to write the denominator of (C.36) as ⎡ FB FF +1−1 ⎤2 ⎢ ⎥ 2 M [k ,FB ]−1 FB −M [k ,FB ]−1 Q[k ,FB ] ⎢ ⎥ = − − C C 1 g k , 0 ( ) [ ] ∑ m ⎢ ⎥ ⎢k =−F FF −1 ⎥ B ⎢⎣ ⎥⎦ 2 2 ⎡ ⎤ ⎢ ⎥ 2 ⎥ ⎢ I N 1 k γ − ( ) ⎥ . = ⎢⎢ SS ∑ C k −1 − C FB − k −1 2 ⎥ ⎢VOVD k =−N (k γ ) ⎥⎥ ⎢ 1− ⎢⎢⎣ 2 ⎥⎥⎦

(

)

(

)

(C.37)

Noting that the mismatch function, fΔVt [k, 0], is given by (2.56), allows to write the numerator of (C.36) as FB

FF +1 −1 2

∑F −1 (C

k =−FB

=

M [k ,FB ]−1

−C

FB −M [k ,FB ]−1

)f 2

2 ΔVt

[k, 0 ] =

F

2

I SS VOVD

N

2

∑ (C k −1 −C F − k −1 ) B

k =−N

⎡1 − (k γ )2 ⎤ 2 ⎣⎢ ⎦⎥ 2

1−

(k γ ) 2

,

(C.38)


357

which leads to N

2

∑ (C k −1 − C F − k −1 ) B

k =−N

σ (VOS )ΔV =

N

∑ (C

t

k −1

−C

FB − k −1

k =−N

)

⎡1 − (k γ )2 ⎤ 2 ⎢⎣ ⎥⎦ 2 (k γ ) 1− 2 σ (ΔVt ). 2 1 − (k γ )

(C.39)

2

1−

(k γ ) 2

If FB is sufficiently larger than N such that C k −1 C FB − k −1 for all k, equation (C.39) approaches the result obtained in a pre-amplifier stage. For β mismatches the conclusions are similar. An identical approach is followed to calculate the effect of the mismatches in ISS, using the fΔI SS / I SS [k, vI ] function given by (2.61). However, the result obtained in that case does not approach the one found in averaged pre-amplifier stages. As shown in section 1.6.3, these mismatches cause zero crossing deviations on the folding circuits even when averaging is not employed, while in a pre-amplifier stage deviations only exist when averaging is used. Therefore, this kind of mismatches is always more problematic in folding stages, either with or without averaging.

C.4.2

DNL due to Mismatches in the Transistors and Current Sources

The standard deviation of the DNL is obtained from (2.45). The offset voltage corresponding to the zero crossing of differential pair 0, VOS[0]Δψ, is given by (C.35). For the differential pair 1 (the one having the reference voltage VREF = VR), a similar calculation leads to FB

FF +1 −1 2

⎛

∑F −1 ⎜⎜⎜⎝C

VOS [1]Δψ = −

k =−FB

M [k ,FB ]−1 −1

−C

FB − M [k ,FB ]−1 −1 ⎞

⎟⎟ (−1)Q [k ,FB ] f [k − 1, 0 ] Δψ [k ] Δψ ⎟⎠

F

2 FB

FF +1 −1 2

∑F −1 (C

k =−FB

. (C.40) M [k ,FB ]−1

−C

FB −M [k ,FB ]−1

)(−1)

Q [k ,FB ]

gm [k, 0 ]

F

2

The variance of VOS[1]Δψ − VOS[0]Δψ is, therefore,


358

FB

FF +1 −1 2

∑F −1 ⎡⎣⎢nψ−1 − nψ ⎤⎦⎥

k =−FB

σ 2 (VOS [1] −VOS [0])Δψ =

2

F

σ 2 (Δψ )

2

⎡ ⎤2 ⎢ ⎥ Q [k ,FB ] M [k ,FB ]−1 FB −M [k ,FB ]−1 ⎢ ⎥ −C C gm [k, 0]⎥ (−1) ⎢ ∑ ⎢ ⎥ FF −1 ⎢k =−FB 2 ⎥ ⎣⎢ ⎦⎥ F +1 FB F −1 2

(

(C.41)

)

with

(

n ψ −1 = C

M [k ,FB ]−1 −1

−C

FB − M [k ,FB ]−1 −1

(

)(−1)

Q [k ,FB ]

fΔψ [k − 1, 0] (C.42)

)

M k ,F −1 F −M k ,F −1 n ψ = C [ B ] − C B [ B ] (−1)Q [k ,FB ] fΔψ [k, 0].

(C.43)

. The application of this expression will be done considering the Vt mismatches. Under condition (C.29) the denominator of (C.41) equals (C.37). Regarding the numerator, since fΔV [k, 0] ≠ 0 only when t

–N ≤ k ≤ N ,

(

)

⎛ M ⎡k ,F ⎤ −1 −1 ⎞ F − M ⎣⎡k , FB ⎦⎤ −1 −1 ⎟ M ⎡k , F ⎤ −1 F −M ⎡k , F ⎤ −1 ⎟⎟ fΔVt [k − 1, 0] − C ⎣ B ⎦ − C B ⎣ B ⎦ −C B n ψ −1 − n ψ = ⎜⎜C ⎣ B ⎦ fΔVt [k, 0] = ⎝⎜ ⎠⎟ ⎧⎪ 0 ⎪⎪ ⎪⎪ M ⎣⎡k , FB ⎦⎤ −1 F −M ⎡k , F ⎤ −1 ⎪⎪⎛⎜C M ⎣⎡k ,FB ⎦⎤ −1 −1 − C FB − M ⎣⎡k ,FB ⎦⎤ −1 −1 ⎟⎟⎞ f fΔVt [k, 0] −C B ⎣ B⎦ ⎟⎠⎟ ΔVt [k − 1, 0] − C ⎪⎪⎜⎝⎜ ⎪⎪ = ⎪⎨⎪ ⎪⎪ ⎜⎜⎛C M ⎣⎡k ,FB ⎦⎤ −1 −1 − C FB − M ⎣⎡k ,FB ⎦⎤ −1 −1 ⎟⎟⎞ f ⎟⎟⎠ ΔVt [k − 1, 0] ⎝⎜ ⎪⎪⎪ ⎪⎪ ⎡ ⎤ ⎡ ⎤ M k , F −1 F −M k , F −1 ⎪⎪ C ⎣ B⎦ −C B ⎣ B⎦ fΔVt [k, 0] ⎪⎪ ⎪⎩ ⎪

(

(

)

)

if k < −N or k > N + 1 if

− (N − 1) ≤ k ≤ N

if

k = N +1

if

k = −N

(C.44)

Using (C.30) and (C.31) leads to

(C

(C

M [k ,FB ]−1

M [k ,FB ]−1 −1

−C

−C

FB −M [k ,FB ]−1

)(−1)

FB − M [k ,FB ]−1 −1

Q [k ,FB ]

)(−1)

Q[k ,FB ]

= C k −1 − C FB − k −1

(C.45)

= C k −1 −1 − C FB − k −1 −1. (C.46)

Taking (C.41), (C.44), (C.45), (C.46), and (2.56) in consideration yields, finally,


(

2C

N −1

−C

FB −N −1

2

)

⎡1 − N γ 2 ⎤ 2 ⎢⎣ ( ) ⎥⎦ + 2 (N γ ) 1− 2

⎡ ⎢ ⎢ N ⎢ k −1 −1 F − k −1 −1 + ∑ ⎢C −C B ⎢ k =−(N −1) ⎢ ⎢ ⎣⎢

(

σ (VOS [1] −VOS [0])ΔV =

359

N

t

∑

k =−N

(C

)

2

1 − (k − 1) γ 2 1−

k −1

2 (k − 1) γ 2

−C

(

−C

k −1

−C

FB − k −1

)

)

1 − (k γ )

2

1−

2 FB − k −1

2

(k γ ) 2

2

1 − (k γ )

⎤2 ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥⎦

σ (ΔVt )

2

1−

(k γ ) 2

(C.47)

C.4.3

INL and DNL due to Mismatches in the Resistors

The zero crossing deviations are obtained dividing the output voltages by the DC gain. In this appendix two different but equivalent output voltage expressions are presented, (C.19) and (C.25), and one must decide which to use. The mismatches in Vt, β and ISS cause deviations in the output current of each differential pair. For those cases the most suitable equation is (C.25), which expresses the output voltages as a function of the currents in each differential pair, iDIFF[k,vI]. The error currents originated by the mismatches on the resistors add directly to the total output current of each folding circuit, iFOLDDIFF[q,vI]. Therefore, in this situation it is more convenient to use (C.19) instead of (C.25), yielding FB −1

∑ (C q −1 − C F −q −1 ) fΔψ [q, 0] Δψ [q ] B

VOS [0]Δψ = −

q =0 FB

FF +1 −1 2

, (C.48)

∑F −1 (C M [k,F ]−1 −C F −M [k,F ]−1 )(−1)Q[k,F ] gm [k, 0] B

k =−FB

B

B

B

F

2 FB −1

∑ (C q −1 −1 − C F −q −1 −1 ) fΔψ [q − 1, 0] Δψ [q ] B

VOS [1]Δψ = −

FB

q =0 FF +1 −1 2

. (C.49)

∑F −1 (C M [k,F ]−1 −C F −M [k,F ]−1 )(−1)Q[k,F ] gm [k, 0] B

k =−FB

F

2

B

B

B


360 This leads to

FB −1

B

σ 2 (VOS )Δψ =

2

∑ (C q −1 − C F −q −1 )

fΔ2ψ [q, 0 ]

q =0

⎡ FB FF +1 −1 ⎤2 ⎢ ⎥ 2 M k ,F −1 F −M k ,F −1 Q k ,F ⎢ C [ B ] − C B [ B ] (−1) [ B ] gm [k, 0 ]⎥⎥ ⎢ ∑ ⎢k =−F FF −1 ⎥ B 2 ⎣⎢ ⎦⎥

(

FB −1

σ 2 (VOS [1] −VOS [0])Δψ =

σ 2 (Δψ ) (C.50)

)

∑ ⎢⎣⎢(C q −1 −1 −C F − q−1 −1 ) fΔψ [q − 1, 0] − (C q −1 −C F −q−1 ) fΔψ [q, 0]⎥⎦⎥ ⎡

B

⎤

B

q =0

⎡ F FF +1 −1 ⎤2 ⎢ B 2 ⎥ ⎡ ⎤ ⎡ ⎤ ⎡ ⎤ M k ,F −1 F −M k ,F −1 Q k ,F ⎢ C ⎣ B ⎦ − C B ⎣ B ⎦ (−1) ⎣ B ⎦ gm [k, 0]⎥⎥ ⎢ ∑ ⎢ ⎥ F −1 ⎢k =−FB F2 ⎥ ⎣⎢ ⎦⎥

(

2

σ 2 (Δψ),

(C.51)

)

which can be divided by VLSB to obtain σ2(INL) and σ2(DNL). As an application example, (C.50) will be evaluated considering the case of mismatches in R0 and that, once again, condition (C.29) is respected. The denominator of (C.50) equals (C.37). Calculations similar to those presented in appendix B indicate that, for a folding stage, F I (C.52) fΔR0 / R0 [k, vI ] = F SS . 2 Therefore, the numerator of (C.50) is FB −1 ⎛ I SS FF ⎞⎟2 FB −1 q −1 2 q −1 FB −q −1 2 2 ⎜⎜ C C f q C − , 0 = − C FB −q −1 ) = [ ] ⎟ ( ) ∑ ΔR0 / R0 ⎜⎝ 2 ⎟⎠ ∑ ( q =0 q =0 ⎤ ⎛ I SS FF ⎟⎞2 1 ⎡ 1 + C 2 ⎜⎜ 1 − C 2FB ) − 2C FB FB ⎥ . ⎟⎟ 2 ⎢⎢ ( 2 ⎥ ⎝⎜ 2 ⎠ C ⎣ 1 − C ⎦ Finally, σ (VOS )ΔR

0

(C.53)

1 +C 2 (1 − C 2FB ) − 2C FB FB ⎛ ΔR0 ⎞⎟ VOVD 1 −C 2 ⎟ . (C.54) = FF σ ⎜⎜⎜ 2 N ⎜⎝ R0 ⎠⎟⎟ 2C 1 − (k γ ) k −1 FB − k −1 ∑ C −C 2 k =−N (k γ ) 1− 2

/ R0

(

)

If FB is sufficiently large this equation can be approximated by

σ (VOS )ΔR

0 / R0

FF

VOVD 2C

N

∑

k =−N

C

1 +C 2 ⎛ ΔR0 ⎞⎟ 1 −C 2 ⎜⎜ ⎟, σ 2 ⎜⎝ R ⎠⎟⎟ 1 k − γ ( ) 0 k −1 2

1−

(k γ ) 2

(C.55)


361

which is FF times larger than the value found in a pre-amplifier stage. This was expected because the same happens in the absence of averaging (compare the σ(VOS) of a single differential pair, (1.58), with the one found in a folding circuit, (1.73)).

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INDEX

A Averaging in folding stages automated design 241–244 gain 107–108, 353–355 mismatches in resistors 112–113, 335, 338, 359–361 mismatches in transistors and current sources 111–116, 355–359 output voltage 105–107, 348–353 previous research work, inexistence of 74, 313 termination 29, 134–135 transient response 138, 141, 154 Averaging in pre-amplifier stages automated design (application examples) 179–203 automated design (method) 169– 178, 196–197, 210–214 dynamic gain 139–140, 144–146, 152–154, 161, 163, 166, 255 gain 80–81 mismatches in resistors 90, 333– 339 mismatches in transistors and current sources 87–90 output voltage 77–80 previous research work 73–76, 313– 331 termination 118–134 time dependence of the offset voltage 154–169, 252 transient response

(approximated) 146–154 transient response (exact) 141–146 with MOS differential pairs 81–86, 90–103 yield 116–118, 179, 209 Averaging networks circular 103, 341–345 equivalence between circular and infinite networks 345–347 infinite 76 resistive 76 termination 118–135 with load capacitances 141 with load capacitances and capacitances between consecutive outputs 252

B Bottom plate sampling 229, 264, 283, 287 Bubble correction 220, 299 errors 9, 220–221

C Charge injection 232, 263 mismatches 36, 59, 62, 69, 263–270, 272–274, 279, 281–284, 289 signal independent; see Bottom plate sampling 379

380


Circular code 30, 229 Coarse ADC; see Two-step flash architecture Comparator; see Latched comparator

H

D

I

Differential Non-Linearity (DNL); see Performance parameters, ADC Double differential pair 234–236

Input Offset Storage (IOS); see Offset cancellation techniques Integral Non-Linearity (INL); see Performance parameters, ADC Interpolation 14–16, 21, 26, 38, 65, 214 active 16, 69, 249 and averaging, joint utilization of 16, 169–170, 178, 200–203 capacitive 16, 69 current 16 factor 14–15, 26, 31, 33, 169–170, 200, 209, 237 resistive 14, 16, 169–170 voltage; see Interpolation - resistive IR drop, compensation of 223

E Encoder 9, 138, 206, 220–222 Error correction; see Redundancy

F Fine ADC; see Two-step flash architecture Flash architecture operation with S/H or T/H 9–11, 138–140 operation without S/H or T/H 10–11, 140, 209–210 7b 120 MHz prototype 206–227 Folding circuit 46–53 factor 25, 30–31, 33–34, 49 pipelined 35–36 Folding and interpolation architecture cascaded 30–33, 38, 205, 227–228, 236–243, 246–253 coarse ADC 27, 33, 229 extra zero crossings 29, 134–135, 238–241 layout and floorplan 246–253 operation with S/H or T/H 27, 33–37 operation without S/H or T/H 33–34 single stage 24–28 10b 100 MHz prototype 227–260 Folding architecture double 24 initial 22–23

Histogram; see also Performance parameters, ADC 7

K Kickback noise; see Latched comparator

L Latched comparator 9, 11–14, 16, 21, 26–27, 31, 38, 54–62, 138–139, 206, 218–220, 245–246, 255, 261, 274 class AB 54, 59 dynamic 54, 220, 288, 290 kickback noise 58–62, 245–246, 290, 293 offset voltage 12–13, 21, 57–58, 63–65, 101, 139, 211, 219, 241, 245, 261–263, 265, 267–268, 270, 272–273, 289 regeneration time 55–57, 219–220, 245 static 54, 261

381

Index

M Mismatches in differential pairs 44–46, 87–92 in folding circuits 50–53, 111–116, 355–361 in resistors 45, 90, 333–339, 359–361 sources of 41–44 Multistage offset cancellation; see Offset cancellation techniques

N Neutralization 59, 244–245

O Offset cancellation techniques calibration of pre-amplifier and latched comparator 274–281, 288–291 elimination of charge injection mismatches 281–285, 289 Input Offset Storage (IOS) 262– 266, 270–271, 273 multistage 267–270, 273 Output Offset Storage (OOS) 265– 267, 269–270, 273, 284 residual offset 65, 261–263, 265– 268, 270, 272–273, 281, 284 sequential clocking 268–270, 284 using auxiliary differential pair 271–273 Offset sampling; see Offset cancellation techniques Output Offset Storage (OOS); see Offset cancellation techniques

P Performance parameters, ADC Differential Non-Linearity (DNL) 5–7, 62, 64–65, 73–75, 89–90, 93–95, 98–103, 111, 115–118, 160 Integral Non-Linearity (INL) 5–6,

62–65, 73–75, 87–90, 93, 95–98, 101–103, 111, 114, 116–118, 160, 170–171 Signal-to-Noise Ratio (SNR) 4, 8 Signal-to-Noise-and-Distortion Ratio (SINAD) 8–9 Total Harmonic Distortion (THD) 8 Pipeline architecture 19

R Redundancy 17–19, 21, 27, 229, 286, 293–296 Reference ladder; see Resistive ladder Reference voltage generator 216–218, 229 Resistive ladder 9, 13, 15, 21, 38, 203, 206, 215–218, 244, 299

S Sample-and-Hold (S/H) 9–11, 15, 17, 19, 21–23, 27, 33–34, 36–37, 205–206, 218, 227–234, 241, 253, 286, 300 SAR architecture 22 Sequential clocking; see Offset cancellation techniques Signal-to-Noise Ratio (SNR); see Performance parameters, ADC Signal-to-Noise-and-Distortion Ratio (SINAD); see Performance parameters, ADC

T Termination of averaging networks 118–135 Thermometer code 9, 220–221, 229, 299 Total Harmonic Distortion (THD); see Performance parameters, ADC Track-and-Hold (T/H); see also Sample-and-Hold (S/H) 36–37, 138, 140 Transfer function of differential pairs piecewise linear 73–75, 86, 102, 134, 210, 313–316

382


quadratic 38–41, 75, 81–83, 95, 107–108, 110, 116, 144, 152, 162, 165, 173, 182, 187, 195, 315–316, 324, 328, 330, 353–354 quadratic versus piecewise linear 316, 324, 328–329 quadratic versus real 108–110 Two-step flash architecture coarse ADC 17–19, 21–22, 286, 291–296, 298–301 fine ADC 17–19, 21–22, 286–291, 293–298, 300–301 selection of reference voltages 19–22, 262, 286, 296–300 6b 1 GHz prototype 285–304 subranging 19–22, 261, 285–287 with DAC and subtractor 17–19

Y Yield with averaging 116–118, 179, 209 without averaging 62–65, 278

Z Zero crossing 14–15, 21, 25, 27, 29, 31, 33–34, 36, 46–47, 49, 53, 67, 103, 238 deviations 15, 25–26, 29–31, 34, 36–38, 44, 48–49, 64–65, 67, 69, 71–73, 87, 89, 92, 101, 105, 107, 111–112, 116, 118–120, 132, 134–135, 154, 202–203, 214, 223, 246–247, 249

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