Nanoparticle Engineering for Chemical-Mechanical Planarization: Fabrication of Next-Generation Nanodevices

Nanoparticle Engineering for Chemical-Mechanical Planarization Fabrication of Next-Generation Nanodevices Ungyu Paik • ...

Author: Ungyu Paik | Jea-Gun Park

85 downloads 940 Views 11MB Size Report

This content was uploaded by our users and we assume good faith they have the permission to share this book. If you own the copyright to this book and it is wrongfully on our website, we offer a simple DMCA procedure to remove your content from our site. Start by pressing the button below!
Report copyright / DMCA form

DOWNLOAD PDF

Nanoparticle Engineering for Chemical-Mechanical Planarization Fabrication of Next-Generation Nanodevices Ungyu Paik • Jea-Gun Park

Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an informa business

© 2009 by Taylor & Francis Group, LLC

CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2009 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-13: 978-1-4200-5911-3 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com


Contents Preface..................................................................................................................ix The Authors........................................................................................................xi 1 Overview of CMP Technology................................................................ 1 1.1 Motivation and Background...........................................................1 1.2 The Key Factors of CMP Process....................................................3 1.2.1 CMP Polishing Machines...................................................3 1.2.2 Slurry for CMP.....................................................................4 1.2.3 Pad..........................................................................................6 1.2.4 Slurry Supply Equipment and Filtering Equipment.......6 2 Interlayer Dielectric CMP......................................................................... 9 2.1 Interlayer Dielectric (ILD) CMP Process........................................9 2.2 Rheological and Electrokinetic Behavior of Nano Fumed Silica Particle for ILD CMP..............................................................9 2.2.1 The Unique Behavior of Concentrated Nano Fumed Silica Hydrosols................................................................. 10 2.2.2 Electrokinetic Behavior of Nano Silica Hydrosols........ 11 2.2.3 Geometric Consideration..................................................12 2.3 Particle Engineering for Improvement of CMP Performance.. 14 2.3.1 Surface Modification of Silica Particle............................ 14 2.3.2 Improvement of ILD CMP with Modified Silica Slurry................................................................................... 16 2.4 PAD Dependency in ILD CMP.....................................................17 2.5 ILD Pattern Dependencies.............................................................20 2.5.1 CMP Tool Dependency.....................................................20 2.5.2 Pattern Density Dependency...........................................25 3 Shallow Trench Isolation CMP.............................................................. 35 3.1 Requirement for High Selectivity Slurry.....................................35 3.2 Particle Engineering of Ceria Nanoparticles and Their Influence on CMP Performance....................................................38 3.2.1 Physical Properties of Ceria Particles.............................38 3.2.2 STI CMP Performance with Ceria Slurries....................39 3.2.3 Influence of Crystalline Structure of Ceria Particles on the Remaining Particles..............................................40 3.3 Chemical Engineering for High Selectivity in STI CMP..........45 3.3.1 Electrokinetic Behavior of the Ceria Particle, Oxide, and Nitride Films...............................................................46 3.3.2 STI CMP Performance in Different Suspension pH.....47 v © 2009 by Taylor & Francis Group, LLC

vi

Contents

3.3.3 3.4 3.5

The Conformation of Polymeric Molecules and STI CMP Performance..............................................................50 Force Measurement Using Atomic Force Microscopy for Mechanism.......................................................................................55 Pattern Dependence of High-Selectivity Slurry.........................60

4 Copper CMP.............................................................................................. 79 4.1 Introduction.....................................................................................79 4.2 High Selectivity for Copper CMP.................................................82 4.3 Copper CMP Pattern Dependence...............................................88 4.3.1 Dishing Dependency on Feature Size and Pattern Density................................................................................88 4.3.2 Pattern Effects on Planarization Efficiency of Cu Electropolishing.................................................................94 4.3.3 Cu Pad Size and Linewidth Affect Dishing................. 102 4.3.3.1 Pattern Dependence of Dishing and Erosion Phenomena....................................................... 104 4.3.3.2 TaN Cap Process for Cu Corrosion Prevention and Thermal Stability Improvement.................................................... 105 5 Nanotopography......................................................................................111 5.1 What Is Nanotopography?........................................................... 111 5.2 Why Nanotopography Is Important.......................................... 113 5.3 Impact of Nanotopography on CMP.......................................... 114 5.3.1 General Introduction....................................................... 114 5.3.2 Spectral Analysis of the Impact of Nanotopography on Oxide CMP and Fourier Transform Method.......... 116 5.3.3 Impact of Nanotopography on Silicon Wafer on Oxide CMP.......................................................................120 5.3.3.1 Wafering Method Dependency of Impact of Nanotopography on Oxide CMP..................120 5.3.3.2 Slurry Characteristic Dependency of Impact of Nanotopography on Oxide CMP..............126 5.3.3.3 Effect of Wafer Nanotopography on Remaining Polysilicon Thickness Variation after Polysilicon CMP.....................................130 5.3.3.4 Effect of VT Variation of Wafer Nanotopography on Remaining Polysilicon Thickness Variation after Polysilicon CMP.131 5.4 Equipment in Measuring the Nanotopography.......................136 5.4.1 Introduction to General Equipment Used in the Measurement of Nanotopography................................136 5.4.1.1 SQMTM (Surface Quality Monitor), from ADE, USA.........................................................138


vii

Contents

5.4.1.2 NanoMapper, from ADE Phase Shift, USA.139 5.4.1.3 DynaSearch, from Raytex, Japan.................. 141 5.4.1.4 Line Profile Comparison among Three Instruments...................................................... 143 5.4.1.5 Calibration among the Standard Deviations of Height Change Measured by Three Kinds of Instruments...................................................... 143 6 Novel CMP for Next-Generation Devices......................................... 149 6.1 The Progress of Semiconductor Devices upon Current Demand.......................................................................................... 149 6.2 Complementary Metal-Oxide Semiconductor (CMOS) Memory.......................................................................................... 151 6.2.1 Noble Metal CMP for DRAM......................................... 152 6.2.2 Poly Si CMP for NAND Flash Memory........................154 6.3 Novel CMP for New Memory..................................................... 163 6.3.1 GST CMP for PRAM........................................................ 163 6.3.2 Novel CMP for ReRAM.................................................. 170 References....................................................................................................... 171 Index................................................................................................................. 177


Preface As a result of a ubiquitous society, displays for electronic appliances such as mobile computers and mobile phones demand high efficiency. High efficiency electronics were realized with the advent of nanoscale devices. Especially for nanoscale devices, the importance of the chemical–mechanical planarization (CMP) process emerged to achieve the integration and multilevel interconnections. The CMP process supports increasing capacity. CMP technology became absolutely necessary for production processes of the next generation of semiconductor. Pursuing global planarization, planarization using CMP could not be against the trend. Therefore, it is used for production of device makers, which is dielectric CMP, shallow trench isolation CMP, and metal CMP. Chapters 2 through 4, respectively, discuss these processes. The nanotopography of the surface of silicon wafers has recently become an important issue because it may seriously affect the post-CMP uniformity of thickness variation of dielectrics. For this reason, Chapter 5 explains the importance of nanotopography. However, CMP processing has faced a new aspect: design rules below 50 nm. Because new structures and new materials are used for improving the performance of devices, the existing CMP slurry is facing its limits. Chapter 6 provides novel CMP slurry for application to memory devices beyond 50 nm technology. The authors are especially grateful to Allison Shatkin and Amy Blalock at CRC Press for their valuable guidance. Ungyu Paik Jea-Gun Park

ix © 2009 by Taylor & Francis Group, LLC

The Authors Ungyu Paik is professor and director of the Division of Materials Science Engineering at Hanyang University, Korea. He is head of the Research Center for Converging Technology in Advanced Gas Turbine System and director of the Global Research Laboratory for Nano Device Processing Laboratory. He is also a technology counselor for the Materials Laboratory of Samsung SDI Corporate Research & Development Center and Hynix semiconductor. Paik received a PhD from the Department of Ceramic Engineering at Clemson University, Clemson, South Carolina, in 1991. Prior to joining Hanyang University, he was an associate professor at the Department of Materials Engineering, Changwon National University, Korea, from 1992 to 1999 and worked as a guest researcher at National Institute of Standards and Technology, Gaithersburg, Maryland, from 1995 to 1996. Paik’s research interests are in the control of the interparticle force of nanoceramic particles and development of nanoparticle patterning technology. His newly expanded topics are focused on dispersion stability of carbon nanotubes (CNTs), quantum dot in non-volatile memory, phosphor in plasma display panel (PDP), color filter in liquid-crystal display (LCD), and so on. His technology transfer experience includes: the development of fabrication technology of ultra-thin (1.2 μm) dielectric sheet in multilayered ceramic capacitor (MLCC) and technology transfer to Samsung ElectroMechanics; the world’s first design of dispersion technology of aqueous graphite for the application of lithium ion battery anodes and technology transfer for Samsung SDI Co.; the technology development of CMP slurry for interlayer deposition and the technology transfer for Technosemichem Co.; and the initiation of technology development of high performance CMP slurry for shallow trench isolation for KC Tech Co. He has published more than 100 technical papers in the scientific literature and holds 38 patents. Also, he gave several plenary and invited talks at international conferences, including SEMICON Korea 2003, the 54th Pacific Coast Regional & Basic Science Division Meeting of the American Ceramic Society, and the 1st International Congress on Ceramics of the American Ceramic Society. He is a recognized world leader in dispersion technology. xi © 2009 by Taylor & Francis Group, LLC

xii

The Authors

Jea-Gun Park Jea-Gun Park is professor of the Division of Electrical & Computer Engineering, director of the Department of Nanoscale Semiconductor Engineering, director of the Industry-University Cooperation Foundation, and dean of the University Research at Hanyang University, Korea. He has been interested in defect engineering in semiconductor materials and nano-scale device development since he received a Ph.D. at the Department of Material Science & Engineering, North Carolina State University, U.S.A. His interests in defect engineering continued during a 17-year career at the Samsung Electronics Co., Semiconductor Division (1985-2001) and broadened beyond defect engineering to the development of “Pure Silicon Wafer” (free of agglomerated defects in CZ Si), which has been used as a standard wafer for DRAM devices. Since coming to Hanyang University in 1999, his research interests have developed “Super Silicon Wafer” (pure silicon wafer containing extremely proximity gettering effect), which has been used as a standard wafer for flash memory devices. In 2001, Prof. Jea-Gun Park and his team developed “300mm Super Silicon Wafer,” which is immune to metallic ions contamination in the semiconductor process line for the first time in the world and standardized as an international standard silicon substrate for sub-100nm C-MOSFET through his technology transfer to Japanese silicon wafer manufactures, Shinetsu Handotai, Mitsubishi Materials, and Sumitomo Metal. Nowadays, it is being applied to Samsung, Hynix, and Toshiba for mass production. In addition, he developed nano SOI process technology for giga-hertz speed CPU or MPU consisting of SOI C-MOSFET, and high mobility strained-Si C-MOSFET. Furthermore, one of his main research areas is nano-CMP slurries. In particular, he developed fumed silica slurry for inter-layer dielectric process in 2001 and transferred it to TECHNOCHEM (Korean company). In addition, he also developed nano-ceria slurry for shallow trench isolation process in 2003 and transferred it to KCTECH (Korean company). Currently, he is doing the research & development of the process technologies and slurries for high performance Cu/low-k CMP, poly-Si CMP, and GST CMP. Moreover, he is also developing flexible & transparent Si OLED (Organic Light Emission Display) as well as flexible & transparent 30nm OBLED (Organic Bistable OLED: Memory Transistor + OLED) for the application of high resolution micro display. He is focusing on the research and development for the process, device, and circuit design of PoRAM (Polymer Memory) which


The Authors

xiii

is promising next generation transistor of tera-bit non-volatile memory. Currently, professor Jea-Gun Park is taking a role as a managing director of the technology development program for the Next Generation of Terabit Non-volatile Memory sponsored by Korea MKE (Ministry of Knowledge Economy), a head of High-speed/Cap-less Memory Research Sponsored by Korea MEST (Ministry of Education, Science and Technology), a chairman of VLSI symposium in Electrochemical Society, ASIA representative of SIWEDS (Silicon Wafering Engineering & Defect Science) partly sponsored by NSF of the USA, and a steering committee member of Korea advanced national nano-FAB. As of Oct. 20, 2008, he had published 172 papers on an international journal (SCI). In addition, he has submitted 147 patents and 84 patents have been registered. Prof. Jea-Gun Park has also presented 227 talks.


1 Overview of CMP Technology

1.1 Motivation and Background Since Bardeen, Brattain, and Shockley of Bell Laboratories invented the transistor in the 1940s, semiconductor integrated circuit (IC) technology has been remarkably developed. The improvement of operation capacity and speed, thanks to the development of semiconductor technology, is playing a key role in the rapid progress of current scientific technologies. In the flow of rapid progress, it was required for semiconductors to possess super high speed, capacity, and performance, and as a result, integration of the transistor is increasing. Since the beginning of the 21st century, the design rule of semiconductors was set below 100 nm. Samsung Electronics developed 64 Gb NAND flash memory using 30 nm technology in 2007, Hynix developed 2G DRAM2 using 66 nm technology, and Intel developed the Core™2 Quad Processor using 65 nm technology. Although these remarkable developments pursue a miniature through vertical high integrated circuit, it is also possible to obtain super high speed and capacity through a horizontal, high integrated circuit (multiple metal lines). In multilayer metal lines process technology, it is difficult to focus and impossible to form minute structures when the dielectric layer and metal line have rugged surfaces. Therefore, planarization processing was necessary to ensure lithographic depth of focus (DOF), which was considered to be the most important factor. A variety of planarization methods of high degree were indispensable in using a new material and transformation from two-dimensional flat structures to three-dimensional multilayer structures into a wide and high integrated ultra large scale integrated (ULSI) circuit device with a diameter from 200 mm to 300 mm of silicon wafer. By using preexisting borophosphosilicate glass (BPSG) deposition and planarization methods such as reflow, spin on glass (SOG), and spin coating, it may soften rugged surfaces to some degree during dielectric layering (Table 1.1). However, problems such as aggravation of formation, position precision, rugged surface device according to multilayer metal line, and three-dimensional structures would occur (Figure 1.1).

1 © 2009 by Taylor & Francis Group, LLC

2

Nanoparticle Engineering for Chemical-Mechanical Planarization

Table 1.1 Types and Features of Existing Planarization Types

Examples of Method

Features

Etching

Sputter, RIE, plasma etching

Easy process, difficult to control etching

Deposition

Bias sputter, Bias ECR, plasma chemical vapor deposition (CVD), RF plasma CVD

Damage concern, too much dust

Reflow floating

Reflow, SOG (spin on glass)

Easy to utilize, discontinuity, instability, establishment of migration

Selective growth

Selective CVD, selective epitaxial growth

Possible to fill only the required part (hole), low selective growth control, instability

(a)

Figure 1.1 Formation of planarization of semiconductor metal line.

(b) (c) (d)

To solve this problem, Kaufmann, from IBM, developed in the 1980s chemical–mechanical planarization (CMP), a new global planarization technique that combines mechanical polishing with chemical polishing into a manufacturing process. This was the origin of CMP process in the modern sense (Figure 1.2). CMP chemically or mechanically polishes the semiconductor’s surface for planarization. The chemical action affects productivity and polishing selectivity rate, whereas the mechanical action contributes to the smoothness of the surface. As in Figure 1.1c, the CMP process eliminated the rugged upper part of a surface in an orderly manner, regardless of the low area condition. CMP made global planarization possible without unevenness and solved the problem of existing techniques that caused deteriorated layers to form and lowered shape precision. For this reason, CMP technology became absolutely necessary for the production process for the next generation of semiconductors and it is used for production of device makers. Internationally, many businesses and lab organizations are actively making progress with research into a new process technology. This CMP propagation and active research progress may well be the first departure of shallow trench isolation (STI) CMP. STI CMP was introduced


3

Overview of CMP Technology

IMD CMP Metal CMP ILD CMP MESH Cap. (25k)

WIDNU, WIWNU, WTWNU

W CMP

WIWNU, Removal Rate, Defect

ILD CMP ILD CMP

Selectivity, Defect

80 nm DRAM Cell

ILD CMP ILD CMP STI CMP

WIWNU, Removal Rate, Defectivity Defect (scratch), Dishing

Poly CMP STI CMP

70 nm NAND Flash Memory Cell

Figure 1.2 Global planarization by CMP.

by replacing local oxidation of silicon (LOCOS) with STI by the splitting method for each transistor. For the process of complementary metal-oxide semiconductor (CMOS), each transistor used LOCOS because separation by electricity was needed to eliminate a short. Unfortunately, this LOCOS process caused a severe problem with device integration because its design rule entered under 0.5 μm, making a sharp edge called bird’s beak. To solve this problem, STI led to an increase in a very tiny active area and in device packing density. Despite the advantages of STI, it cannot be formed without the CMP process because to form STI, polishing must be stopped by eliminating gap filling oxide film at the Si3N4 layer. This process is only possible through STI CMP technology. Currently, manufactured semiconductor devices on the basis of CMOS are produced applying STI CMP.

1.2 The Key Factors of CMP Process The characteristics of CMP are material removal rate (MRR), thickness uniformity, and surface quality, and they are directly related to device characteristics and productivity. These characteristics are determined by each factor as per Figure 1.3. 1.2.1 CMP Polishing Machines Whereas wafer polishing machines polish dozens of micrometers (μm), CMP polishing machines polish 0.5 ~ 1.0 μm of target film. Uniformity is extremely important after polishing. The features of CMP polishing machines include automation, high precision, reproducibility, and control of process parameter. Polishing machines are largely divided into rotary type, orbital type, linear type, and fixed table type according to the movement of the wafer carrier and table (Table 1.2). A schematic diagram of the Mirra polisher, currently used in a device maker, is shown in Figure 1.4. In the cassette load, the sensor perceives the


4


Slurry Mix and Distribution Process Monitoring Wafers In Pad & Insert Technology

End Point Detection Polisher

Brush Scrubber

CMP Process

Megasonic Cleaning Conditioning Technique

Slurry Reclaim

Wafers Out

Metrology Defects and Thickness

Figure 1.3 The elements (factors) of CMP process.

Table 1.2 Motion of Wafer Carrier and Table by CMP Tool Type Motion Wafer Carrier

CMP Tool Type

Table (Platen)

Rotary

Rotate

Rotate

Orbital

Rotate

Orbital path

Linear

Linear path

Linear path

Fixed table

Orbital path

Stationary

wafer, and the FABS robot moves to the transfer station. CMP is transferred to the head clean load unload (HCLU) where CMP is actually formed after a long robot arm absorbs the wafer by using a void space. The FAB robot arm transfers the finished CMP processed wafer to the input station for cleaning in the HCLU. 1.2.2 Slurry for CMP As mentioned earlier, the core of CMP technology is slurry for CMP based on nanotechnology, even though the importance of CMP technology was highlighted before the introduction of a nano process for semiconductor processing. Slurry is composed of water, polishing particle, alkali, inorganic salts, and organic compound, and specific slurry is manufactured through appropriate selection of the components. Some of the most important characteristics of slurry are equal dispersion of polished particle caused scratch on the surface of wafers, minimizing of metal current, optional polishing characteristics, viscosity, and


5


3 Pads and 4 Heads LSS2

Robot Arm

LSS1 Holder

HSS

SC1 Cleaning (Lift off ) NH4OH:H2O2:H2O(1:5:50)

Cassette Drying (spin dry)

HF Cleaning (scrubber) SC1 Cleaning (scrubber) Cleaning System

3 Pads and 4 Heads LSS2

Robot Arm

LSS1 Holder

HSS

SC1 Cleaning (Lift off ) NH4OH:H2O2:H2O(1:5:50)

Cassette Drying (spin dry)

HF Cleaning (scrubber) SC1 Cleaning (scrubber) Cleaning System Figure 1.4 Mirra schematic.

storage safety that cause polysilicon abnormal resistance and metal line short. Commonly used solvent is highly pure, from which most of the impurities such as ion, small particles, microorganisms, and organic substance are eliminated, with a 5 ~ 18 MΩcm resistance rate. The appropriate slurry is applied according to objects to be polished. Table 1.3 summarizes the slurry required for various processes.


6


Table 1.3 CMP Slurry Type Polishing Objects SiO2 Interlayer dielectric

FSG BPSG

Purpose of Application Planarization, trend favoring introduction of processing below 0.35 μm

Low-k

Slurry Types Fumed silica is mainly used; tendency of switching to ceria

STI (shallow trench isolation)

Intra-semiconductor devices separation layer elimination; applied below 0.25 μm (128, 256M)

Ceria, fumed/colloidal silica

Polysilicon

Formation of trenchshaped capacitor, polysilicon is eliminated

Fumed/colloidal silica

W

Metal

Wire formation (W is eliminated)

Fumed silica is mainly used; alumina development phase

Al

Contact plug formation (Al elimination)

Fumed silica, alumina

Cu

Wiring and plug simultaneous formation (dual damascene: Cu is eliminated)

Fumed/colloidal silica, alumina, MnO2, and others

1.2.3 Pad Generally, polymer of polyurethane type is used for pads. Uniform surface roughness and porosity of pad influence the characteristics of WIWNU (within-wafer non-uniformity), WTWNU (wafer-to-wafer non-uniformity), and LTLNU (lot-to-lot non-uniformity). For this reason, chemical technology durability, hydrophilic, and viscoelastic features differ according to each required CMP process condition. Table 1.4 shows currently used pads types and the CMP process to which they are applied. 1.2.4 Slurry Supply Equipment and Filtering Equipment The CMP process has a higher possibility of defects than other processes because it uses abrasive in slurry. It especially causes scratches; therefore, controlling the defects is important. To repress scratches attributed to slurry, filter is generally placed at the supply system, circulation loop, and point of use (POU). These factors can be mixed diversely according to the polishing machine’s structure or processing condition selection. However, other materials are also influenced because of the correlation when a factor


7


Table 1.4 Typical Applications for Different Pad Types Type 1

Type 2

Type 3

Type 4

Structure

Felt fibers impregnated with polymeric binder

Porous film coated on a supporting substance

Microporous polymer sheet

Nonporous polymer sheet with surface macrotexture

Pad examples

PellonTM, SubaTM

PolytexTM, SurfinTM, UR100TM, WWP3000TM

IC1000TM, IC1010TM, IC1400TM, FX9TM, MHTM

OXP3000TM, IC2000TM

Typical applications

Si stock polish, tungsten CMP

Si final polish, tungsten CMP, post-CMP buff

Si stock, ILD CMP, STI, metal damascene CMP

ILD CMP, STI, metal dual damascene

changes. Therefore, each CMP process should be controlled appropriately because polishing target film and processing can be changed. All CMP processes applied to semiconductor manufacturing processes, including STI CMP, are formed around the CMP machine. The surface of the wafer and a pad are contacted by pressure of its own load of a head part. At this time, a pad attached to the polishing table makes a simple rotary movement, and a head makes a rotary movement and shaking movement at the same time (Figure 1.5). The wafer exerts a regular pressure on the polishing table. Consumables are liquid slurry, a pad, and a cleaner and others conformable to each target substance. At this point, abrasive of the inside of slurry and the wafer device flow into interface Insert Film

Carrier

Wafer Polishing Pad Platen

Slurry Figure 1.5 (See color insert) CMP process of manufacturing.


8


space to make contact at the overhang. Pressure is concentrated at this protuberant part. Therefore, it has a relatively higher speed of surface elimination than other parts. Also, the protuberant part is equally eliminated over the surface while processing is in progress. Except for STI CMP, 50 nm processing technology CMP can be divided into interlayer dielectric (ILD) CMP and metal CMP. Chapters 2 and 6, respectively, will discuss these two processes. The 50 nm CMP processing rate rapidly augments through multiple metal lines structure for high integrated circuits and is recognized as a necessary process for formation of various detail patterns. The existing CMP slurry is becoming limited to future applications because the device design rule is going below the 50 nm level, and new materials and structures are emerging. In addition, structures that can be embodied only through CMP processing are appearing. In the case of dynamic random access memory (DRAM), the top electrode used in capacitor for a device’s high speed raises the necessity of noble metals like ruthenium (Ru), platinum (Pt), and iridium (Ir), which have low electric resistance and are mechanically and thermally stable. These noble metals are also chemically very stable and it is not easy to form capacitors by the etch back process. That is why noble metal CMP is compulsory. However, Ru is divided during the CMP process as a consequence of poor adhesion of leakage of cap oxide, grain growth of Ru, and cap oxide. To protect this phenomenon, the application of new functional slurry is essential. NAND flash memory started to apply floating gate to increase the capacity of a device from 65 nano processing technology. After STI CMP processing in the gate formation area, silicon nitride is stripped. After Si is placed between the device manufacture areas using self-aligned poly (SAP) method, polysilicon floating gate is formed through CMP process. The poly gate isolation process using CMP raises many problems in applying the existing CMP slurry because of the soft characteristic of poly Si and polymeric reaction, despite simple processes like planarization after deposition. Manufacturing of smaller devices necessitates the introduction of new materials and processes. The role of CMP is expanding and its importance is also being augmented. As a result, slurry production companies and laboratories are actively processing developments and researching consumable and optimized processing.


2 Interlayer Dielectric CMP

2.1 Interlayer Dielectric (ILD) CMP Process In the deposition of the interlayer dielectric (ILD) film to break off relations wiring and wiring, step height is formed because the deposition aspect becomes different along the shape of the lower part pattern. Without removing induced step height in the wiring process, the limit of exposure is caused passing over the depth of focus (DOF) margin during the lithography process. Therefore, the global planarization process is essential after each layer is insulated, and this CMP process is designated as ILD CMP or intermetal dielectric (IMD) CMP. The ILD CMP process has been used to polish plasma-enhanced tetraethylorthosilicate (PETEOS) or high-density plasma chemical vapor deposition (HDPCVD) film on deposited silicon wafers. Figure 2.1 shows the ILD CMP process. As the manufacturing technique of the semiconductor device is developed, the number of levels in an interconnect technology is increased. To obtain the multilevel interconnection, the surface of wafer must be planarized to prevent topography roughness from growing with each level as shown in Table 2.1.

2.2 Rheological and Electrokinetic Behavior of Nano Fumed Silica Particle for ILD CMP In the ILD CMP process, the most important factor is the characteristics of nano fumed silica slurry. The chemical interactions and physical properties of nano ceramic particulates must be considered to planarize the surface of wafer successfully. The dispersion stability of nano fumed silica slurry is directly related to the polishing rate (removal rate), the surface scratch, and the uniformity (within-wafer non-uniformity) of wafer surface across the whole wafer. Controlling the dispersion stability of nano fumed silica slurry is a key parameter in the ILD CMP process. 9 © 2009 by Taylor & Francis Group, LLC

10


PETEO

2 Ti Al-0.5%Cu

PETEO

T

0.25 µm 0.75 µm 0.25 µm 0.8 µm

Si

PETEO

PETEO

CMP

Ti Al-0.5%Cu T

1.3 µm 0.25 µm 0.75 µm 0.25 µm 0.8 µm

Si

Before ILD CMP

After ILD CMP

Figure 2.1 (See color insert) Schematic of ILD CMP process.

2.2.1 The Unique Behavior of Concentrated Nano Fumed Silica Hydrosols Nanosize inorganic particles (i.e., below 100 nm) are gradually being incorporated into a broad range of advanced devices and applications. Some examples include silicon (Si) wafer polishing, planarization for semiconductor manufacturing (CMP process), electronic packages, ultrathin-film optical devices, advanced fuel cell catalysts, molecular conductors, and biochips. Recent evidence has indicated that classical colloid principles might not fully explain the complex behavior of concentrated nanosols. According to the Derjaguin–Landau–Verwey–Overbeek (DLVO) theory, a cornerstone of modern colloid science, two types of forces exist between colloidal particles suspended in a dielectric medium: (1) electrostatic forces, which result from unscreened surface charge on the particle; and (2) London–van der Waals attractive forces, which are universal in nature. The colloidal stability and rheology of oxide suspensions, in the absence of steric additives, can be largely understood by combining these two forces (assumption of additivity). There are several reports of the unique stability of nanosize silica hydrosols near the isoelectric point (IEP). The Canberra group experimentally discovered the existence of short-range forces that play an important role in the interaction process and must be added to those forces a1ready accounted for by the original DLVO theory. These short-range interactions Table 2.1 Roadmap for ILD CMP 2006

2007

2008

2009

2010

2011

DRAM ½ pitch (nm)

Year of Production

70

65

57

50

45

40

Flash ½ pitch (nm)

64

57

51

45

40

36

Dishing (A)

160

500:500:500

250:500:500

250:500:500

1:1:1

0.5:1.1

0.5:1:1

(cm–2)

≤0.17

≤0.17

≤0.17

(#/wafer)

≤0.16

≤120

≤115

Cu Polishing Rate (Å/min)

Polishing Rate (Å/min) Selectivity (Cu : Barrier : Low-k) Size (um)

Scratch (#/cm2)

0.1

1um 0.010

0.006

0.003

Cu Dishing (Å)

400

300

200

Cu Erosion (Å)

300

200

150

Figure 4.3 Cu CMP roadmap.


82


4.2 High Selectivity for Copper CMP Cu CMP slurries commonly use submicron-sized colloidal silica abrasive particles dispersed in aqueous solutions that contain an oxidizer, as well as an complexing agent and corrosion inhibiting agents and other chemicals. Most of the slurries described in the article by several researchers use H2O2 as the oxidizer and benzotriazole as the inhibitor, with various complexing agents such as organic polymer, alkaline agent, and organic amine in slurry. The pH value of the polishing slurry is one of the most important parameters influencing the polishing rate, surface roughness, and other performance characteristics of the Cu CMP process. In this section, the slurry’s pH and conductivity were adjusted to the range of pH 10 to 11 and conductivity of 8 to 10 (mS/cm) by adding an alkaline agent, including NH4OH and HCl solution. Figures 4.4 to 4.7 show the results obtained from an experiment conducted by varying the concentrations of complexing agent (alanine) and selectivity control agent (PAM) in aqueous slurry. Figure 4.4 shows the removal rate of Cu and TaN films versus the alanine concentration. The removal rate of Cu film increased with alanine concentrations. In addition, the removal rate of TaN film strongly suppressed and slightly increased with increasing alanine concentrations in aqueous suspension. As with the removal rate of Cu film, the removal rate of TaN film drastically decreased and was essentially saturated with a concentration of alanine beyond 0.5 wt%. 14000

2000 Cu removal rate TaN removal rate

1800 1600

10000

1400 1200

8000

1000

6000

800 600

4000

400

2000 0

TaN Removal Rate (Å/min)

Cu Removal Rate (Å/min)

12000

200 0

0.5 1 1.5 Alanine Concentration (wt%)

2

0

Figure 4.4 The removal rates of Cu and TaN films versus alanine concentration in slurry.


83

Copper CMP

Alanine could exist in aqueous solution in three different forms, namely, CH3 CH(NH3+)COOH (cation), CH3 CH(NH3+)COO– (zwitterions), and CH3 CH(NH2)COO– (anion). These species are denoted as H2L+, HL, and L–, respectively, for brevity. The equilibrium between these may be depicted, as Babu et al. (2005) previously reported, the dissolution and removal rate probability of the complexing agent, including phthalic acid, citric acid, glycine, oxalic acid, and carboxyl and/or amine functional group, which interact on the Cu film surface should strongly influence the removal rate.

(4.2)

Babu et al. explained that a complexing agent, such as amino group in glycine and hydrogen peroxide system, is protonated at pH 4.0 the amino group can chelate Cu2+ ion and cause the dissolution of the metal up to pH 10. However, alanine and H2O2–containing colloidal silica slurry exhibited an enhanced removal rate of Cu film at alkaline pH region. We thought that the alanine could be a very effective complexing agent with an increased removal rate of Cu film through a high dissolution rate of Cu2+ ion in alkaline pH region. The suppression of the removal rate of TaN film could not be fully explained through the electrochemical phenomena by chemical reaction between complexing agent and the TaN film surface. We thought that the TaN film loss and the Cu-to-TaN removal selectivity are directly related to the electrostatic interaction and electrokinetic behavior due to chemical adsorption and steric hindrance of adsorbed organic chemical. Figure 4.5 shows the electrokinetic behaviors of Cu film, TaN film, and colloidal silica slurries with alanine addition as a function of pH. The absolute surface zeta potential of the Cu film was slightly negatively charged above pH 5. The TaN film also exhibited a slightly negative charge at a pH above pH 5.3. Colloidal silica slurry with alanine exhibited a pHiep at pH 4.0. The surface potentials of the colloidal silica abrasive particles in the aqueous suspension with alanine were strongly negatively charged above


84


pH 4.0, while the TaN film’s surface potential was weakly negatively charged. The attraction behavior between the abrasive particles and the TaN film results from the different electrostatic potentials exhibited in certain pH regions. Therefore, we suggest that the selective adsorption of alanine added slurry on the abrasive particles and the TaN film surfaces correspond to the differing zeta potential charge. The removal rate of TaN film is drastically supressed, and increased slightly by this difference. By comparing the removal rate of Cu and TaN films, we can calculate the removal selectivity of Cu-to-TaN films (Figure 4.6). By increasing 20

Zeta-potential (mV)

10 0 –10 –20 Alanine 0.2 wt% 1.0 wt% 2.0 wt% Cu film TaN film

–30 –40 –50 –60

0

2

4

6 pH

8

10

12

Figure 4.5 Zeta potential of Cu, TaN films, and colloidal silica slurry with alanine as a function of pH.

Cu-to-TaN Removal Selectivity

35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0

0

0.5 1 1.5 Alanine Concentration (wt%)

2

Figure 4.6 Removal selectivity of Cu-to-TaN films versus alanine concentration in slurry.


85

Copper CMP

14000

2000

Cu Removal Rate (Å/min)

1600

10000

1400 1200

8000

1000

6000

800

4000 2000 0

Cu removal rate

600

TaN removal rate

400

TaN Removal Rate (Å/min)

1800

12000

200 0

0.3 0.5 PAM Concentration (wt%)

0.7

0

Figure 4.7 The removal rates of Cu and TaN films versus PAM concentration in slurry.

the alanine concentration, the removal selectivity drastically increased and essentially saturated from 5:1 to 32:1 with increasing alanine concentration. Figure 4.7 shows the removal rate of Cu and TaN films versus the PAM concentration. The removal rate of Cu film slightly decreased with PAM concentrations. Here, the removal rate of TaN film was strongly suppressed and saturated with increasing PAM concentrations in aqueous suspension as shown in Figure 4.7. To enhance the removal selectivity of Cu-to-TaN films with suppressing the removal rate of TaN film by selective adsorption, we also optionally added organic polymer (PAM) with the concentration of up to 0.7 wt%. The adsorption of PAM-added slurry on the abrasive particles and the film surfaces corresponds to the differing zeta potential charge. By this zeta potential difference, the removal rate of the Cu and TaN films was more suppressed, and the oxide-to-nitride removal selectivity increased with addition of PAM. Figure 4.8 shows the electrokinetic behaviors of Cu film, TaN film, and colloidal silica slurries with PAM addition as a function of pH. Adsorption of PAM on Cu and TaN film surfaces increases and reaches a strong suppressed point of approximately 0.3 wt%. In other words, PAM is more adsorbed on the Cu and TaN film surfaces. This is driven by the difference in zeta potential, which affects the interaction between PAM and each surface. In addition, above the isotropic point, the slightly negative-charged Cu oxide and TaN films surface can interact with the deprotonated between carboxyl groups of alanine, neutral –NH2 groups, and NH+ functional groups of PAM, which results in the formation of strong complexes with Cu and TaN films. However, with addition of PAM, the removal rate of


86


20 10

Zeta-potential (mV)

0 –10 –20 PAM 0.3 wt% 0.5 wt% 0.7 wt% Cu film TaN film

–30 –40 –50 –60

0

2

4

6 pH

8

10

12

Figure 4.8 Zeta potential of Cu, TaN films, and colloidal silica slurry with PAM as a function of pH.

Cu-to-TaN Removal Selectivity

200 160 120 80 40 0

0

0.3 0.5 PAM Concentration (wt%)

0.7

Figure 4.9 Removal selectivity of Cu-to-TaN films versus PAM concentration in slurry.

Cu and TaN film decreased. By increasing the PAM concentration, the removal selectivity drastically increased and essentially saturated from 30:1 to 130:1 (Figure 4.9). Potentiodynamic polarization studies were carried out to measure the corrosion current density and potential at various alanine and polyacrylamide concentrations with H2O2. Polarization plots for Cu film as a function of alanine concentration with H2O2 at pH 10 are presented in Figure 4.10a and b, respectively. The value of corrosion potential reduced gradually


87

Copper CMP

Ec vs. Ag/AgCl

0.5

0.0

–0.5

–1.0 –10

0.5

Ec vs. Ag/AgCl

0.5 wt% Alanine 1.0 wt% Alanine 1.5 wt% Alanine 2.0 wt% Alanine

–8

–6 –4 10x (A/cm2) (a)

–2

0

–2

0

1.5 wt% Alanine w/o PAM 1.5 wt% Alanine w/ PAM

0.0

–0.5

–1.0 –10

–8

–6 –4 10x (A/cm2) (b)

Figure 4.10 (See color insert) Potentiodynamic polarization: (a) various alanine concentration, (b) 1.5 wt% alanine with and without PAM.

with an increasing concentration of alanine (Figure 4.10a). As the alanine solution increases from 0.5 to 2.0, the fraction of carboxyl and amino functional group is more pronounced with increased anion fraction at alkaline pH. Since the bidentate (L–) is more reactive than the monodentate (HL), the increased dissolution rate of Cu+ or Cu2+ ions. The removal rate of Cu film increases with an increasing alanine concentration by low corrosion potential. On the other hand, corrosion potential showed no difference with addition of PAM solution (Figure 4.10b).


88


4.3 Copper CMP Pattern Dependence The use of copper as an interconnect material in multilevel scheme DRAM and NAND flash memory in design rules beyond 45 nm is being increasingly considered mainly due to copper’s low resistivity and high resistance to electromigration compared to the widely used aluminum (Al) alloys. As the device structure becomes more complicated and its dimensions shrink, the conductors on the chip must be thin enough to occupy less space. Such miniaturization of the conductor causes an increase in the RC delay, which is the product of the metal resistance (R) and the capacitance (C) of the interlevel dielectric. While the low resistivity of copper is expected to exhibit lower interconnect delay, high resistance to electromigration enhances the device reliability by increasing the mean time to device failure. In addition, in the manufacture of memory circuit devices with copper metallization, multilevel interconnects are formed using the damascene method, whereby copper is deposited by chemical vapor deposition (CVD) or electroplating into vias and trenches etched in the interlayer dielectric (ILD) over a diffusion barrier usually made from titanium (Ti), tantalum (Ta), or their nitrides. For the application of copper as interconnect material, the film surface within wafer must be made planar on a global scale. Inlaid metal patterns in multilevel chips could be obtained by CMP. The CMP is used to planarize the barrier metal, low-k, and copper layer following their deposition process. 4.3.1 Dishing Dependency on Feature Size and Pattern Density Dishing of copper lines is among the most important issues of copper CMP. Dishing reduces the final thickness of copper lines and degrades the planarity of the wafer’s surface, resulting in complications when adding multiple levels of metal. Understanding of dishing and its nature is helpful in process optimization and in understanding the process mechanism. Here, we present a thorough investigation of dishing in copper CMP. Along with studying the dependency of dishing on linewidth and pattern density, our investigation is focused on the effect of (over)polish time, oxidizer concentration in the slurry, and thickness of the as-deposited copper layer. As a result, a hypothesis of material removal mechanism for our type of slurry is presented. The test structures were fabricated as following. First, the interconnection grooves were etched in thermally grown silicon dioxide by RIE with the depth of 600 nm. The width of the trenches varies from 2 to 100 mm. Second, after depositing a 50-nm Ti layer by sputtering an adhesion promoter layer, an 800-nm Cu film was deposited also by sputtering without breaking the vacuum. An IC1000/Suba IV stacked-perforated pad from Rodel was applied. Prior to every run, pad conditioning was done using


Copper CMP

89

diamond tool. An alumina-based slurry (Al2O3 particles, median diameter 200 nm), which contains a complexing (carboxylic acid) agent and a stabilizer, was used throughout the investigation. Hydroperoxide (functions as oxidizer) was added to the slurry at three volume percentages: 7.5%, 10%, and 15%. After mixing, the pH of the slurry was measured to be around 4.0. Polishing runs were carried out using a Presi Mecapol E460 polishing tool. Optimum settings for uniformity were applied, which were found for our test pattern. The polishing pressure was 250 g/cm2. The rotation speed of platen/pad and that of the wafer holder were set at 50 rpm. The supply speed of the slurry was 125 ml/min. Due to practical limitations, we used a timed polish process. The nominal polish time was determined by the moment when the entire wafer surface is clear from excess metal. From then on, if the wafer polishing is continued, we consider it as overpolishing and the time is called overpolish time. In our study, four polish times were used, which are nominal, 5% (of nominal time) overpolish, and 10% and 20% overpolish. Figure 4.11 shows the dishing amount of copper lines at different linewidth and pattern density. The wafer was polished using slurry with 15% hydroperoxide and the polish time was nominal. As expected, the dishing amount strongly increases with the increment of linewidth (see Figure 4.11). The dependency is not a linear function of linewidth. At a linewidth above 50 mm, the dishing levels off. The pattern density only shows a minor effect on copper dishing. Unlike dishing data published for other material, such as tungsten, dishing of copper lines appears to be relatively large even at nominal polishing. As shown in Figure 4.11, the dishing amount of 100-mm wide copper lines is more than 100 nm. However, it is well known that the removal rate is higher at dense areas, thus when the entire wafer surface is clear, which we defined as nominal polishing, dense areas must have been overpolished. In addition, there is always a certain non-uniformity of removal rate over the wafer. Therefore, when the entire wafer surface is cleared there definitely are areas that have been overpolished. We assume that overpolishing with very high removal rate of copper (typical 600 nm/min), high selectivity between copper and ILD (typical larger than 90), and a too thin as-deposited copper layer are the reasons of the large amount of dishing. Overpolishing is needed to ensure good electrical properties of interconnection (no shorts between separate interconnect). However, overpolishing always results in an increasing amount of dishing and worsens the planarity of the wafer surface. Figure 4.12 shows the profiles of a test structure of 20-mm wide copper lines with a pattern density of 50% at nominal polish time and three overpolish times. The dishing increases dramatically with increasing overpolish time. As many authors have described, dishing as a result of the pad reaching into recess areas and removal of copper in the recess, there is a question raised if the dishing rate is the same at different linewidths. Therefore, we plotted the dishing


90


140 120

Dishing (nm)

100 80 60

PD = 20% PD = 33% PD = 50% PD = 66% PD = 83%

40 20 0

0

20

40

140

100

120

100 µm

120 Dishing (nm)

60 80 Line Width (µm) (a)

50 µm

100

20 µm

80 60

10 µm

40 5 µm

20 0

10

20

30

40 50 60 Pattern Density (%) (b)

70

80

90

Figure 4.11 Dishing versus (a) linewidth and (b) pattern density.

rates of different linewidths versus overpolishing time in Figure 4.13. The dishing rate of wide lines is higher than that of narrow ones. To explain this, we use the model proposed by Warnock saying that the pad reaches into recessed areas by bending and its roughness. The amount that the pad can reach into the recessed areas depends on the pad’s properties (e.g., hardness, surface roughness), linewidth, and applied pressure. Since all the other conditions remain the same in our case, linewidth is the only factor that can affect the amount of pad reaching. Therefore, it directly relates to the amount of dishing as well as to the dishing rate. The model is thus in accordance with the obtained dishing rate behavior seen in Figure 4.13, that is, the different slopes are explained.


91

Copper CMP

50 (LW = 20 µm – PD = 50%)

Height (nm)

0 –50

Nominal

–100

+5% OvP

+10% OvP

–150 –200

Cu

–250 –50

0

50

+20% OvP

SiO2 100 150 200 Scan Length (µm)

250

300

350

Figure 4.12 Surface profiles of a polished structure (20 μm linewidth, PD = 50%) at different polish times.

200

(PD = 20% – Ox. Conc. = 15%) tg (α4) = 3.96

Dishing (nm)

160

50 µm

120

tg (α2) = 2.78

20 µm

80 40 0

tg (α3) = 3.07

100 µm

tg (α1) = 1.57

10 µm –5

0

5 10 15 Percentage of Over Polishing

20

25

Figure 4.13 Dishing of different linewidths at different polish times.

Slurry chemistry has been reported to have a strong effect on polishing results. We also found a strong dependency of dishing on slurry chemistry. Figure 4.14 illustrates the dishing of 100-, 50-, and 20-mm wide lines (pattern density 20%) polished by slurries with different concentrations of hydroperoxide at nominal polish time. It can be seen that the dishing is reversely proportional to the concentration of oxidizer in the slurry. The explanation we propose for this phenomenon is that with higher oxidizer concentration in the slurry, a more effective passivation layer is formed on the copper surface (it will grow faster). This passivation layer slows the removal rate of copper in the recess areas and better protects the copper lines from dishing during the overpolish step. We have found that the


92


50 0

SiO2

–50 Dishing (nm)

20 µm

50 µm

100 µm

–100 –150 –200 –250

Cu

–300

7.5% H2O2

–350 500

10% H2O2

15% H2O2

1000 1500 Scan Length (µm)

2000

Figure 4.14 Surface profiles of a structure (PD = 20%) polished by slurry with different oxidizer concentrations. 160 140

Thin (Unfilled symbols)

Dishing (nm)

120 100

10 µm 20 µm 50 µm 100 µm 10 µm 20 µm 50 µm 100 µm

80 60

Thick (Filled symbols)

40 20 0

10

20

30

40

50 60 70 80 Pattern Density (%)

90 100 110 120

Figure 4.15 Dishing of as-deposited thin and thick copper layers at different linewidths and pattern densities.

thickness of the as-deposited copper layer also affects the amount of dishing of copper lines. Two copper thicknesses are used to study this dependency. The thin copper layers with a thickness of 800 nm was described earlier. The thick copper layer is 1.5 mm thick. Dishing data for both thicknesses at nominal polish times are shown in Figure 4.15. It is clear that the amount of dishing is smaller in all cases for the as-deposited thicker copper layers. Furthermore, the effect of thin versus thick copper layer on dishing appears to be even clearer at the large features, while only minor effects are observed for the small features. It is known that the removal rate of copper at dense areas is higher than that of field areas due to higher local pressure exerted on the features. Therefore, if the copper layer is too thin, the dense areas will be cleared first and experiences overpolishing


93

Copper CMP

before the field areas are cleared and global planarity is reached. This leads to severe dishing at the dense areas. The copper layer should be sufficiently thick to reach a globally planar surface with still excess of copper on all features (wide, small, densely and widely packed). This will minimize the dishing. In this way, we managed to reduce the maximum dishing for all investigated feature sizes to less than 100 nm for nominal polishing conditions. Figure 4.16 shows etch rates of copper in the slurry without abrasive particles at three investigated concentrations of oxidizer. We notice that the static etch rate of copper is very low (10 nm/min). On the other hand, the removal rate of copper during polishing is very high (more than 600 nm/ min is achieved). This is strong evidence of the forming of a passivation layer on the copper surface in the slurry. Further investigation of the chemistry of the slurry gave us the following hypothesis about the forming of the passivation layer on the copper surface and thereafter a proposal for the copper removal mechanism in copper CMP with our slurry. The oxidizer (H2O2) reacts with Cu in acidic slurry (pH 4) and Cu2+ ions are formed. The anions of the carboxylic acid react with Cu2+ ions (R(COO)2Cu). Carboxylates of metals other than the alkali metals generally are insoluble. Therefore, we suppose that R(COO)2Cu protects the copper underneath from etching. According to the Pourbaix diagram for the copper–H2O system, no copper oxide can be formed in our slurry (the pH of our slurry is about 4.0; at this pH, only two forms of Cu2+ or Cu are possible; see Figure 4.17). The concentration of H2O2 strongly influences the amount of Cu2+ ions and, therefore, the amount of R(COO)2Cu product. In other words, the effectiveness of the passivation layer is directly proportional to the H2O2 concentration in the slurry. This is consistent with our experimental results. 14

Etch Rate (nm/min)

12 10

StERCu = –0.22*[Ox] + 12.6 [nm/min] R2 = 0.995

8 6 4 2 0

6

8 10 12 14 Percentage of Oxidizer in Slurry (% Vol.)

16

Figure 4.16 Etch rate of copper in the slurry with different oxidizer concentrations.


94


Potential (V vs. SHE)

2

1

CuO

Cu++

CuO2 Cu2O

0 Cu

Slurry’s pH Range

–1 0

2

4

6

8 pH

10

12

14

16

Figure 4.17 Pourbaix diagram of the copper–H2O system.

The hypothesis for the copper removal mechanism using this slurry is proposed to be as follows. Copper on the surface is oxidized by H2O2 (in acidic environment) into copper cations. These cations then react with carboxylate anions to form the passivation layer that protects copper from etching. This layer is then removed at protruding levels by mechanical abrasion. Once removed from the surface, the “metallic soap” particles are swept away by the turbulent motion of the slurry. Further investigations of the passivation mechanism by varying the slurry chemistry are being conducted. The dishing behavior of copper lines has been extensively studied. Relationships between dishing and feature size, pattern density, overpolishing time, thickness of as-deposited copper layer, and slurry chemistry have been elucidated. While dishing strongly depends on linewidth, only a small effect of pattern density has been observed. As expected, dishing dramatically increases with the increment of overpolishing time. Furthermore, the dishing rate dependency of overpolish time is not the same for all feature sizes. The larger the linewidth, the higher the dishing rate is. Thick as-deposited copper layers yield less dishing than thinner ones. The oxidizer concentration in the slurry also has a strong impact on the amount of dishing. It was found that, within the investigation window, the dishing is inversely proportional to the oxidizer concentration. From the obtained results, a hypothesis for the passivation layer formation has been proposed and the mechanism of copper removal has been presented. 4.3.2 Pattern Effects on Planarization Efficiency of Cu Electropolishing Cu electropolishing technology has been explored as a replacement of the Cu CMP planarization process. Contolini et al. (1994) integrated Cu


Copper CMP

95

electropolishing with a wet etching technology in a novel electrochemical planarization (ECP) method for Cu multilevel interconnects, and Wang (2000) has designed a commercial tool for the electropolishing process. In addition, Cheung (1997) proposed a process of Cu electropolishing to enhance CMP throughput. Recently, groups at TSMC and SONY companies also applied Cu electropolishing in global planarization technologies. Traditional electropolishing is an important surface treatment technology, and can dissolve a metallic film uniformly and produce a smooth and bright surface. Furthermore, electropolishing has potential advantages in that it renders a reduced waste stream, is less consumable, and there is no applied pressure to the substrate, which is beneficial for future low-dielectric-constant-material integrated processes. In previous studies of Cu CMP, Steigerwald et al. (1997) found that Cu dishing is a strong function of linewidth but is only weakly dependent upon pattern density. At the same pattern density, the amount of dishing increased as the linewidth increased. In this work, pattern effects of Cu electropolishing were discussed. Anodic potentiodynamic polarization measurement was also employed to clarify the dissolution mechanism of Cu electropolishing. The patterned wafer used was composed of a 30-nm-thick ionized metal plasma (IMP)-TaN layer as the diffusion barrier, and a 200-nm-thick IMP-Cu film as the seed layer. The experiments on Cu electroplating and electropolishing were carried out in a tank of nonconducting material at room temperature. The counterelectrode was a platinum plate and the working electrode was a sliced wafer with a size of 2 × 3 cm2. In Cu electroplating, the electrolytes included CuSO4 ∙ 5H2O (30 g/L), H2SO4 (275 g/ L), chloride ions (50–100 ppm), polyethylene glycol (40–2000 ppm), and 2-aminobenzothiazole (10–100 ppm). The films were deposited under galvanostatic control. In Cu electropolishing, the electrolyte was phosphoric acid (H3PO4) and the films were polished under potentiostatic control. Potentiodynamic (PD) polarization measurement was performed on an EG&G potentiostat/galvanostat (model 273A) with a Pentium PC. In these analytical experiments, the counterelectrode was platinum and the working electrode was Cu with a constant surface area of 0.5 cm2. All potentials are reported relative to the Ag/AgCl electrode, which was used as the reference electrode. Cross-sectional profiles of Cu films were examined using a field emission scanning electron microscope (FESEM). Surface roughness was measured using an atomic force microscope (AFM). The sheet resistance of Cu deposits was measured by the four-point probe technique, and the resistivity measurements were carried out immediately after deposition. Cu planarization process using ECP of Cu by electropolishing followed by CMP is depicted in Figure 4.18. After Cu electroplating completely fills the trenches and vias, electropolishing planarizes the surface down to the barrier layer, and the remaining Cu and the barrier metal are removed


96


Figure 4.18 Basic process of Cu electrochemical planarization technology.

Cu Electroplating

Barrier Layer

Cu

Dielectric Layer

Substrate

Cu Electropolishing

Chemical Mechanical Polishing

by a single-step CMP process. Figure 4.19 shows the scanning electron microscope (SEM) cross-sectional profile of a 10-μm Cu line planarized by the ECP process. In this case, the defect-free filling was obtained by an acid cupric sulfate electrolyte containing chloride (Cl), polyethylene glycol (PEG), and 2-aminobenzothiazole (2ABT). Subsequently, a clean and scratch-free surface was produced by electropolishing using H3PO4 as the electrolyte. Finally, CMP removed the remaining Cu and the barrier metal. The final-step CMP process used the H2O2-based slurry, which has a higher removal rate of TaN than that of Cu. For Cu electroplating, the combined action of Cl–PEG–2ABT provided an inhibition gradient between the opening and the bottom of a feature to obtain an obviously selective deposition and to result in bottom-up filling. Tafel plots in Figure 4.20 reveal that the added 2ABT could enhance the charge transfer resistance to inhibit Cu deposition. The shifted overpotential, caused by the added PEG, was 61.7 mV relative to that of standard solution and the corresponding value for the combined action of PEG–2ABT was 77.2 mV.


97

Copper CMP

Figure 4.19 SEM cross-sectional profile of a 10-μm Cu line planarized by the ECP process. 100

E (mV vs. Ag/AgCl)

50 0

(1) (3)

–50 –100 –150 10–6

(1) (2) (3) (4)

Standard solution (1)+2ABT (1)+PEG (1)+PEG+2ABT 10–5

(2)

(4)

10–3 10–4 2 I (A/cm )

10–2

Figure 4.20 Tafel plots of Cu electroplating with various electrolytes.

The potentiodynamic curve of Cu electropolishing in the H3PO4 (85%) solution is shown in Figure 4.21. For anodic potentials in the AB range, the metal surface became active. When the anodic potential is higher than the B point to the BC range, a viscous sublayer may start to form on the anodic surface. In the CD range, called the plateau region, a wide passivation range existed; electropolishing occurred with negligible change in current density as the applied voltage increased. In this plateau operation


98


2.0

E Oxygen Formation

E (V vs. Ag/AgCl)

D 1.5

H3PO4: 85% (vol) Plateau Region (electropolishing)

1.0 C 0.5

Passivation Region

B A

0.00

Active Region 0.01

0.02

0.03

0.04

0.05

I (A/cm2) Figure 4.21 Potentiodynamic curve of Cu electropolishing. In addition, the optical microscope images (200×) show surface morphologies of Cu electropolished at different applied voltages.

region, a nearly constant current maintained a stable electropolishing process. Unlike the cathodic-limiting-current plateau in electrodeposition, which results from the depletion of metal ions in the diffusion layer near the electrode surface, the formation of anodic-limiting-current plateaus in electropolishing may be due to the presence of a viscous film on the anodic surface or the concentration barrier formed by accumulated dissolving metal ions. In the DE range of Figure 4.21, the electropolishing process occurred quickly because of the high applied voltage. An increase in current in this stage increased the rate of oxygen formation from the breakdown of water in the electrolyte with increasing potential. This oxygen formation reaction caused severe etch pits to be formed on the Cu surface. Optical microscope images in Figure 4.21 show that at applied voltages lower than point C, the polished surface was slightly etched; when the potential was in the plateau region (in the CD region), a smoother and scratch-free surface was obtained. Furthermore, when a high potential was applied (in the DE region), a greater amount of oxygen bubbles was generated and the working electrode surface was pitted. In the process of Cu electropolishing, the polishing rate was constant and determined by measuring the remaining Cu thickness of the blanket wafer with a 1-μm-thick Cu film. The polishing rates of electroplated Cu films were about 500 nm/min, 1000 nm/min, and 1500 nm/min for 85% (vol.), 70% (vol.), and 50% (vol.) of H3PO4 electrolytes, respectively, as calculated from the data in Figure 4.22. The fluctuation of polishing rates away from linear fitting may be due to non-uniform current distribution on the residual Cu film. After electropolishing, the average roughness (Ra) of the


99

Copper CMP

11000 10000

Applied Voltage: 1.3 V H3PO4: 85% H3PO4: 70% H3PO4: 50%

9000 Thickness (A0)

8000 7000 6000 5000 4000 3000 2000 1000 0

–10

0

10

20 30 40 50 Polishing Time (s)

60

70

80

Figure 4.22 Effects of acid concentration on polishing rates and surface morphologies (AFM images) for Cu electropolishing at applied voltage of 1.3 V (with respect to the Ag/ AgCl reference electrode).

films decreased with increasing acid concentration, as seen in Figure 4.22. Therefore, electropolishing is normally carried out in a limiting-current region and in a concentrated acid electrolyte; a higher acid concentration showed a higher leveling effect. Generally, conventional Cu electroplating will produce step on/between features. The traditional Cu CMP process includes step-height reduction of wiring metal and removal of overburden metal outside the features. Steigerwald et al. found that Cu dishing is a strong function of linewidth, but is only weakly dependent upon pattern density. At the same pattern density, the amount of dishing increased as the linewidth increased. In this study, we also encountered the same issue for Cu electropolishing. To measure the planarization efficiency (PE) of the CMP process, Steigerwald et al. defined the following equation:

PE = [1 –(Δdown/Δup)] *100%

(4.3)

where down and up are the thickness differences of the inside and outside of the feature respectively, as shown in Figure 4.23. In this article, we also applied Equation 4.3 is also applied to monitor PE of Cu electropolishing. A better planarization ability is noted when the PE value is higher. Ideally, PE is equal to 1. The following mechanism of electropolishing is suggested: the microleveling effect occurs because of selective dissolution. When current is applied, a passivation film covering the crevices of the surface—which has a high specific gravity, viscosity, and insulation—prevents dissolution; whereas the surface protuberances not covered by the passivation film—which receive greater current from the


100


Before Electropolishing

∆ Up

After Electropolishing

∆ Down

Figure 4.23 Diagram of PE measurements, where Δdown and Δup are the thickness differences inside and outside of the feature, respectively. 90 80 70

80

Pattern Density = 50%

60

PE (%)

PE (%)

90

Applied Voltage: 1.3 V in H3PO4 (85%) Solution

50

70 60

40 30

Applied Voltage: 1.3 V in H3PO4 (85%) Solution

50

20 0

10

20

30

40

50

40

1/4

1/2

1/1

2/1

Line Width (µm)

Line (µm)/Space (µm)

(a)

(b)

4/1

Figure 4.24 Evolution of PE values with (a) different linewidth and (b) different ratio of linewidth to space width.

cathode—dissolve more quickly. This phenomenon leads to a lower dissolution gradient in larger features such as in a blanket surface. Therefore, Figure 4.24a shows that PE decreased with increasing linewidths when pattern density [line/(line + space)] remained at 50%. By sputtering Cu into the filled features, starting profiles of filled features with greater step height manifest the pattern effect on planarization efficiency. The SEM images in Figure 4.25 indicate that the capability of step-height reduction in small patterns was higher than that in larger patterns. In these cases, the polishing time was 150 s. Table 4.1 summarizes the starting and final (after electropolishing) step heights of different features. Moreover, PE decreased more quickly for narrower lines than for wider lines. In addition to the linewidth dependence of PE, Figure 4.24b also


101

Copper CMP

Table 4.1 Starting and Final (after Electropolishing) Step Heights of Different Features Line/Space (μm)

Starting Step Height (nm)

Final Step Height (nm)

1/1

~850

~480

2/2

~730

~420

5/5

~720

~530

10/10

~720

~550

20/20

~720

~550

1/4

~1300

~700

1/2

~1300

~640

2/1

~850

~360

4/1

~760

~260

shows that PE decreased with an increase in space width when linewidth remained unchanged. We suggest that dissolution current density in a smaller space was higher than that in a larger space, thereby resulting in a higher polishing rate around the outside of the feature or leading to an enhancement of the dissolution gradient between the gap and spacing. However, the influence of space width on PE was lower than that of linewidth, as shown in Figure 4.24b. In these Cu electroplating experiments, only PEG and inhibitor were used, so there was no overplating but dishing occurred with about a 100 nm step height in a 10-μm Cu line. Cu electropolishing was capable of eliminating the step height of such an electroplated Cu line, as shown in Figure 4.19. However, overplating has recently been observed for a conventional bath with a brightener. Nevertheless, Cu electropolishing is still able to yield a planar surface due to a higher polishing rate for overplated protrusions with higher current density than that for blanket regions 1 µm

Before Polishing

After Polishing

Figure 4.25 SEM cross-sectional profiles.


5 µm

50 µm

102


3.0

16

2.8 2.6

12

2.4

10

2.2

8

2.0

6

1.8

4

1.6

Resistivity (µΨ-cm)

Ra (nm)

14

1.4

2

1.2

0 0

20

40

60

80

100

120

140

1.0

Polishing Time (s) Figure 4.26 Average roughness (Ra) and resistivity of blanket Cu films with various polishing times.

with lower current density. On the other hand, non-uniform current distribution is a challenge in the case of Cu electropolishing for global planarization of an entire wafer. Adding additives into polishing baths or introducing a multistep pulse current could improve the global uniformity within a wafer. Figure 4.26 reveals that the average roughness (Ra) of blanket Cu films decreased as polishing time increased. At the beginning of electropolishing, the microleveling effect was more obvious than at later times. The trend in this figure mainly followed from the fact that a point-discharge effect is more efficient for a rough surface than for a polished surface. After electropolishing for 130 s, Ra was approximately 1.1 nm, as compared to 13.2 nm before electropolishing. The resistivity of polished films was not obviously changed, as also shown in Figure 4.26. This result suggests that no H3PO4 electrolyte diffused into grain boundaries of Cu films, whereas some oxidants often cause such damage after CMP processes, thus degrading the electrical characteristics of polished Cu metals. 4.3.3 Cu Pad Size and Linewidth Affect Dishing Although the exposed Cu can immediately react with oxygen to form an oxide film, the film is porous and not of a self-protective nature. Therefore, a capping material, such as SiN, is necessary to prevent the corrosion of Cu. Unfortunately, the Cu corrosion depends on the delay time from the CMP polish of Cu to deposition of the protective layer. On the production line, the manufacture available time and efficiency are very hard to reach


103

Copper CMP

these stiff conditions. Hence, the prevention of Cu corrosion becomes the major challenge in production to improve the yield. On the other hand, the grains of Cu will enlarge during subsequent thermal processing. For instance, the heating during dielectric material deposition would induce the Cu grain growth and generate the voids in Cu due to the surface area diminution of grain boundary. This will result in poor thermal stability of Cu film. In the Cu CMP process, dishing and erosion are the other problems for the Cu line thickness control. The occurrence of dishing and erosion depends on the line width and density. Besides, the CMP parameters such as polishing down force, polish head rotation speed, polish pad elastic properties, slurry flow, polish time, and so forth affect dishing and erosion. Capping with a protective layer is the plausible way to avoid the dishing and erosion phenomena so as to improve the Cu thermal stability. This section investigated the dishing and erosion phenomena of Cu in the CMP process. The tantalum nitride (TaN) capping on the top of Cu surface is proposed to protect the Cu from corrosion and oxidation. The thermal property of Cu is also examined using stress migration to evaluate its stability. A three-metal-level Cu interconnect was performed. In metal 1, a single damascene structure was applied. Dual damascene structure of via 1, 2 and metal 2, 3 was applied. IMP sputtering of TaN was utilized for Cu barrier deposition and self-ionized plasma sputtering of Cu was applied for the seed layer deposition of electroplating Cu. Overburden Cu was polished in a linear system. A two-step polish (copper and barrier metal were separated polish) system was carried out for the Cu-CMP process. An aluminum oxide abrasive system was selected for both of the polishing steps. A TaN capping process was carried out after CMP polishing. The TaN of 30 nm in thickness was deposited and repolished away at the second step of Cu CMP (Figure 4.27). Because of the selectivity effect, there remained a very thin TaN layer on the Cu surface. The Tencor HRP20 microprofiler measured dishing and erosion. The thermal stability of Cu was evaluated in a furnace at 180ºC for 170 h. The resistance of metal, Rs, was measured based on a serpentine test structure and the resistance

ECP Cu Film

After ECP Plating

After Cu ECP Polish

30nm IMP-TaN Capping

Cu CMP TaN Re-polish

Figure 4.27 TaN capping process procedure. 30 nm TaN was capped after Cu CMP, and after TaN repolishing there remains a very thin TaN layer on the Cu surface.


104


of via, Rc, was measured based on via chain (totally 1798 via embedded with 2 mm in length and 1.5 mm in width) structure. A KLA-Tencor AIT-II was used to evaluate the defects induced by Cu corrosion. 4.3.3.1 Pattern Dependence of Dishing and Erosion Phenomena The influence of pattern density on dishing and erosion was characterized and the results are shown in Figure 4.28 and Figure 4.29, respectively. Figure 4.28 illustrates that the Cu pad size and linewidth affect the dishing. As the Cu pad size increases four times, the dishing increases 2250 2000

Dishing (A)

1750 1500 1250 1000 750 500 250 0

0

50

100 150 200 250 300 350 400 450 500 550 600 Cu Pad Size (um2)

EPD EPD + 10% OP EPD + 20% OP EPD + 30% OP EPD + 40% OP EPD + 50% OP EPD + 60% OP Figure 4.28 The effect of Cu pad size and linewidth on dishing.

900 800 Erosion (A)

700 600 500 400 300 200 100 0

0.1

0.12

0.14

0.16 0.18 0.2 Cu Line Width (um)

0.22

0.24

0.26

EPD EPD + 10% OP EPD + 20% OP EPD + 30% OP EPD + 40% OP EPD + 50% OP EPD + 60% OP Figure 4.29 The effect of Cu linewidth on erosion at fixed oxide pitch of 120 μm.


105

Copper CMP

Table 4.2 Selectivity of Different Cu Polish Modules CMP Polish Module 1st module for Cu polish 2nd module for TaN polish

Cu 115 1

TaN

FSG

Thermal Ox

4

0.7

1

5.8

3

2.3

to approximately two times. The erosion exhibits the same trend; it increases with the linewidth at a fixed oxide spacing of 120 mm, as shown in Figure 4.29. In Figure 4.28, the dishing increases in a very fast rate at the small sizes of Cu pad area ranging from 60 to 150 mm2. In small Cu pads, the oxide plays a very important role in antidishing. The higher the ratio of oxide area, the lesser the dishing observed. This results from the high selectivity of oxide in the Cu polishing module using the aluminum slurry system. The selectivity of different Cu CMP polishing modules is shown in Table 4.2. On the other hand, the percentage of Cu overpolish will worsen the result. As the percentages of overpolish increase, the total polish time increases. This, in turn, immerses the wafer in the slurry for longer times. The additional immersion time caused Cu corrosion by slurry chemical reaction. This explains why more overpolish causes a higher degree of dishing. For the Cu pads larger than 150 mm 2, the dishing increased at a nearly constant rate. In these cases, the CMP polish pad deformation dominated because the CMP polish pad is made of polyurethane that would be deformed during polishing and provide the CMP planarization. The limitation of polish pads deformation causes the constant increasing of dishing. As shown in Figure 4.29, the erosion also increases at a constant rate. Fixed densities of Cu lines and oxide pitch (120 mm) are the major cause of this phenomenon. Because the selectivity of Cu to oxide is approximately 200:1 (Table 4.2), the larger oxide area will reduce the erosion amount in small line width. The increase of erosion only depends on the Cu linewidth at fixed oxide pitch. Besides, the higher overpolish exhibited the same behavior, as observed in dishing experiments; the slurry chemistry effect is again dominant. 4.3.3.2 TaN Cap Process for Cu Corrosion Prevention and Thermal Stability Improvement The dishing and erosion generated by the Cu CMP process could be controlled by an appropriate Cu-to-oxide-area ratio. After Cu polishing, an IMP–TaN layer was sputtered onto the wafer surface. The overburden TaN


106


EDX Analysis TaN Cap

FSG

SiN

100 nm (a) EDX

500 Cu

400 Cu

Counts

300 Si Ta

200

100 Cu

0

Cu

0

5

Ta Ta

Ta

10 Energy (keV) (b)

Figure 4.30 (a) The cross-sectional view of the Cu surface capped with a very thin layer of TaN. (b) The EDX analysis of the circled area of (a).


107

Copper CMP

100.0% 90.0%

Cumulative %

80.0% 70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0%

0

0.01

0.02

0.03

0.04 0.05 0.06 Rs_M2 (ohm)

Cap TaN Rs (ohm)

0.07

0.08

0.09

0.1

No Cap Layer Rs (ohm)

Figure 4.31 The Rs of specimens with TaN and without TaN capping at 0.19 μm in width and 1400 μm in length.

above the Cu and dielectric was polished away by a TaN module and a cross-sectional view of such a composite structure is given in Figure 4.30a. The analysis of a capping layer using electron dispersive spectroscopy (EDX) is shown in Figure 4.30b. After TaN capping, Cu was isolated from oxidative ambient and its corrosion was thereby prevented. However, the TaN capping raised the resistance of Cu (Rs). Because the composite structure contains a high resistivity TaN layer (100 times higher than the Cu), the Rs of the Cu-containing TaN cap provides a 7.9% increment on resistance than that without TaN cap, as shown in Figure 4.31. On the other hand, the uniformity of Rs of composite metal is also lower than that without TaN capping. Furthermore, the Cu CMP repolish would worsen the non-uniformity of Rs. It is well known that Cu reacts easier with oxygen. The oxidation is a continuous reaction due to porous nature of Cu oxide and raises the resistivity of the Cu. The more Cu oxidation occurred, the less speed gain from the material changing from Al to Cu. In addition, the process reliability as well as the lifetime of products will shorten. The corrosion defect characterizations shown in Figure 4.32 and Figure 4.33 reveal that the corrosion defects dramatically increase in the specimens without TaN capping. As for the specimens capped with TaN, the defect level remained the same up to 128-h heating treatment at 180ºC. This observation evidenced that TaN capping could effectively isolate the Cu to prevent corrosion in an ambient environment. Thermal stability is another important issue for the utilization of Cu interconnection. Thermal stability of Cu was evaluated by the via resistance shift and the result is shown in Figure 4.34. After baking for 170 h in a furnace, the specimens capped with TaN exhibited a better thermal stability, as indicated by the Rc shift percentage characterization. During the following thermal process, grain growth of Cu occurred and


108


4500

Defect Counts (ea)

4000 3500 3000 2500 2000 1500 1000 500 0

0.5

1

2

4

8 16 Q-Time (hrs)

No TaN Cap Defect

32

64

128

TaN Cap Defect

Figure 4.32 The relationship between waiting time and defect counts scanned by KLAAIT-II. The defect counts increase with the waiting time.

10 20 30 40 50

10

20

30

40

(a)

50 (b)

Figure 4.33 (a) The corrosion defects observed after annealing for 8 h at 180°C. (b) The corrosion defects observed after annealing for 128 h at 180°C.

the voids appeared. The interface of via connecting to prelayer metal is the preferential site of void formation. Poor adhesion between oxide and metal interface was observed at the bottom of via sidewall (i.e., the shrank), as shown in Figure 4.35. These voids deteriorated the thermal stability after high-temperature baking. The TaN capping is able to enhance the thermal stability because it restricts the Cu surface from reacting with the oxidative ambient and provides a good adhesion on the next Cu barrier layer, which is also of TaN. In addition, the TaN cap restricts the Cu line and inhibits its expansion during subsequent dielectric deposition. The restriction provides a stable volume of Cu during further thermal processes and hence leads to a higher thermal stability of Cu.


109

Copper CMP

100.0% 90.0% 80.0%

Cum%

70.0% 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% –50

–40

–30

–20

–10 0 10 Rc Shift/0.19 um

No Cap Layer Rc shift %

20

30

40

50

TaN Cap Layer Rc shift %

Figure 4.34 The shift of Rc after 180°C baking for 170 h.

TaN/Cu Shrank

TaN/Cu Shrank and poor adhesion

TaN/Cu Shrank

TaN/Cu Shrank and poor adhesion

100 nm

Figure 4.35 The via bottom (i.e., the shrank) exhibited a poor adhesion after heat treatment.

The amount of Cu dishing and erosion after Cu CMP was found to increase with the increases of Cu pad size and overpolish time. By capping a thin TaN layer on Cu, the Cu surface was effectively isolated from the oxidative ambient and the corrosion is presented. Furthermore, there is no increase of defect density in the specimens incorporating with the TaN capping process. The TaN capping process also provided a better


110


thermal stability of Cu during subsequent thermal treatment. The only flaw of TaN capping is the increase of Rs, which will deteriorate the operation speed of devices. However, it could be overcome by design optimization of the circuits.


5 Nanotopography

5.1 What Is Nanotopography? The industry definition of nanotopography covers a spatial wavelength range of approximately 0.2 to 20 mm. This region essentially defines surface topography dimensions larger than roughness. Roughness is defined as the smaller size spatial features on the wafer (an analogy to grains of sand in the desert), and nanotopology defines wider features up to approximately a lithographic field site. Nanotopography defines the nanometerscale height variations that exist on lateral millimeter-scale wavelength on an unpatterned silicon wafer. The characteristics of the variation depend on the specific wafer manufacturing process used to generate a particular wafer. An illustration of wafer nanotopography is shown in Figure 5.1. The height variation is typically 100 nm with a lateral length scale between 1 and 20 mm. This is a parameter that measures the front-surface, free-state topology of an area that can range in size from fractions of a millimeter to tens of millimeters. Nanotopography is the surface topography of wafers placed on a flat stage without chucking or clamping. It has been known as the waviness visually represented with an optical tool called a magic mirror, which provides images that are qualitative pictures of topography variations on the frontside surface of wafers. It has a peak-to-valley height that is considered to vary between several nanometers and several hundred nanometers, and its spatial wavelength range is considered approximately up to 20 mm. In typical CMP machines, a front-side surface reference is employed, and the backside surface of a wafer touches soft carrier films or airbags, both of which absorb the topography variations of the backside surface. Thereby, wafers are in a condition without chucking or clamping in the CMP machines. Moreover, nanotopography differs from front-referenced site flatness in that for nanotopography the wafer is measured in a free state, while for flatness it is referenced to a flat chuck. A wafer may have perfect flatness (in the classical definition of flatness) yet still have nanotopography. If a wafer has surface irregularities on the front and backside 111 © 2009 by Taylor & Francis Group, LLC

112


+500 Å 20 to 80 (nm) Oxide Film 0.2 to 20 (mm)

Silicon

–500 Å Figure 5.1 (See color insert) Illustration of wafer nanotopography.

of the wafer, but front and back surfaces are parallel, the wafer has perfect flatness. However, the same wafer will exhibit nanotopography (Figure 5.2). Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency (Figure 5.3). As linewidth shrinks with non-uniform pattern density and with the use of hard pads for CMP, nanotopography may significantly degrade the dielectric film uniformity. Nanotopography is measured by two techniques: light scattering and interferometry. Light scattering tools typically employed for particle and surface-defect characterization can be used to measure the local slope change over the entire surface of the wafer. The local slope change may be integrated to yield height or topography information. Since the beam size can be on the order of fractions of a micron, nanotopography can be measured. Optical interference measurement is straightforward: A beam is split into two components—one component is reflected from the wafer surface and the second is reflected from a reference mirror. The interference of the combination of the two beams is a measurement of the topology of the wafer surface. With both techniques, signal filtering is used to separate the low-wavelength features (i.e., warp) so that only the Normal Wafer Surface

Backside Reference

Flatness Nanotopography

Good Poor

Good Good

Poor Poor

Figure 5.2 Nanotopography variations on the frontside and backside condition.


113

Nanotopography

PSD (log scale)

Wafer Touch Polishing Micro-roughness

Wafer Stock-removal Polishing

Haze

Nano-topography

1 um

100 um

10 um AFM AFM 10 um

100 nm Measurement LST haze Tools 1 um 5 um

5 um

1 mm

10 mm Wave Length

Nano-mapper 0.2 mm 20 mm Chapman

1 mm

PSD = Power Spectral Density LST = Light Scattering Topography (e.g. KLA-Tencor SP1) Figure 5.3 (See color insert) Topology map of wafer surface.

high-wavelength/low-frequency information, (i.e., the true surface nanotopography) is measured. The equipment used in measuring the nanotopography of the wafer will be introduced in Section 5.4.

5.2 Why Nanotopography Is Important Recently, the nanotopography of the surface of silicon wafers has become an important issue because it may seriously affect the post-CMP uniformity of thickness variation of dielectrics. Semiconductor device fabrication on silicon wafers comprises steps at which layers are deposited, subsequently planarized, and structured. Planarization is typically performed using a polishing step where the smoothing of the layer is due to chemical interaction with the polishing slurry as well as mechanical abrasion. Therefore, such processes are called chemical-mechanical polishing (CMP) and they have been implemented, for example, in silicon wafer manufacturing for more than 30 years. The homogeneity of a post-CMP layer is limited by fluctuations of the combination of layer deposition and CMP, as well as the frontside topography of the substrate. These two contributions to post-CMP layer thickness deviations of oxide film need to be quantified properly for identifying potentials that allow improvement of the efficiency of planarization for future devices. This is particularly necessary since excessively large-layer thickness variations after CMP may have a negative impact on device performance such as leakage and the pinhole effect, and the thickness of layers might even decrease with the ongoing reduction of critical dimensions.


114


Concern over local wafer site flatness for advanced lithography has led to new wafer surface topography requirements. These requirements are typically driven by CMP where film thickness variations can result in uneven surface topography. Control over local wafer site flatness becomes important for device geometries smaller than 0.25 μm.

5.3 Impact of Nanotopography on CMP 5.3.1 General Introduction The interaction of nanotopography upon film polishing uniformity in CMP has been under extensive investigation by Boning and co-workers and Tamura et al. (2000). The primary effect of oxide uniformity removal is due to the hardness of the CMP pad. The fundamental concept is very simple: soft polishing pads conform to local topology variations (i.e., nanotopography), whereas hard pads do not. Figure 5.4, adapted from Boning et al. (2000), illustrates this principle. Typically, a wafer has a characteristic nanotopography length (NL, shown in the top illustration of Figure 5.4). The soft pad will conform over the nanotopography and maintain a uniform film. The hard pad will not conform to the nanotopography and produce a non-uniform film with high spots on the wafer surface having a thinner film and low spots having a thicker film. Traditionally soft pads Oxide Silicon Nanotopography Length 2 mm (for example)

“Soft” Pad CMP Process

CMP

“Stiff” (“Hard”) Pad CMP Process

Pad

Pad

Pad conforms around nanotopography variations and polishes uniformly

Pad “bridges” across nanotopography down areas and preferentially thins surface films in raised nanotopography areas

Figure 5.4 (See color insert) Basic concepts of soft and hard polishing pads.


115

Nanotopography

have been used for film polishing in CMP. However, with the need for better planarization because of more layers, smaller critical dimension, and for multifunction logic devices that have several different areas of varying pattern densities, stiff pads are required. To some extent, the effect of nanotopography can be minimized by using polishing additives, such as ceria particles. Nonetheless, wafer nanotopography becomes increasingly important. To understand the influence of nanotopography in CMP film polishing uniformity, the concept of planarization length should be considered. The planarization length (PL; Figure 5.5) is the spatial length at which polishing cannot reduce the step height of a feature in the film thickness, as shown in Figure 5.5. The important aspect to consider is when PL is less than NL, the film uniformity is maintained; however, when PL is more than NL one could find non-uniform film polishing. Two typical examples are shown in Figure 5.4. The CMP process and the film uniformity specifications may be considered to determine the level of nanotopography required. Nanotopography of the silicon wafer is dictated to a large extent by the polishing process. For single-sided polished (SSP) wafers, the polishing process has been optimized to minimize nanotopography. In this process, to achieve good flatness, the wafer must be mounted or chucked against a flat reference block. Since the wafer backside is etched (not polished smooth), it has surface topology. Because of the fixing process used to mount the wafers (e.g., wax mounting or vacuum chucking), the topology of the backside of the wafer and the fixing surface or adhesive/ wax are transmitted to the front side and causes nanotopography. The other technique of mounting a wafer (the one that is normally used in CMP), namely, free mounting, does not cause nanotopography formation, but also does not guarantee the wafer is made flat. The best flatness and nanotopography is obtained when the wafers are double-sided polished (DSP). The true, planetary, free-floating DSP process polishes both sides of a silicon wafer simultaneously. Since the wafer is polished in a free state,

Step Height

Further polishing cannot decrease the step height over distances beyond the planarization length CMP

Oxide Oxide PL Planarization Length Figure 5.5 Basic concepts of soft (left) and hard (right) polishing pads.


116


Wax Mount

Wafer Mounting

Deformed Wafer

After Polish

Wafer Demount Wafer

Free Mount

Wax Free mounting pad

Wafer Mounting

After Polish Both sides of the wafer are polished while the wafer is in a nearly free state

Wafer Demount

Retaining ring Polish carrier

Wafer Polishing pad

Figure 5.6 (See color insert) A comparison of SSP and DSP mounting techniques and how these affect nanotopography and flatness.

nanotopography is minimized. Also, good flatness is achieved. Thus, both good flatness and nanotopography are produced. Figure 5.6 shows a comparison of SSP and DSP mounting techniques and how these affect nanotopography and flatness. Wafer manufacturing developed a planetary DSP process that provides wafers with leading-edge nanotopography and flatness characteristics that meet all of the increasing demands of CMP requirements. Although planetary DSP is technically the best method to achieve superior nanotopography and flatness, there are several barriers to practically applying this method in the fab. These barriers include cost of ownership for DSP, issues related to running both a polished backside DSP and an etched backside wafer in their lines at the same time, electrostatic chuck problems, and in-line sensor calibration. Wafer manufacturing companies are actively exploring both planetary DSP and SSP methods that promise to achieve a good balance between nanotopography and flatness results and cost of ownership. 5.3.2 Spectral Analysis of the Impact of Nanotopography on Oxide CMP and Fourier Transform Method In general, it is quite convenient to apply spectral analysis to research the impact of nanotopography on film thickness variation in CMP. The surface height changed as the nanotopography of wafers were measured by an ADE NanoMapper. Figure 5.7 shows an example of nanotopography of a wafer measured by ADE NanoMapper. The darker region in the map corresponds to a lower height and the brighter region to a higher height.


117

Nanotopography

1.E+14

pre CMP post CMP (soft) Nanotopo

1.E+12 1.E+10

Power Spectral Density (Å2 mm)

Power Spectral Density (Å2 mm)

Figure 5.7 (See color insert) Nanotopography map for a wafer.

Nanotopo

1.E+08 1.E+06

post CMP

1.E+04

pre CMP

1.E+02 1.E+00

1

10

100

1.E+14

pre CMP post CMP (hard) Nanotopo

1.E+12 1.E+10 1.E+08

Nanotopo

post CMP

1.E+06

pre CMP

1.E+04 1.E+02 1.E+00

1

10

Wave Length (mm)

Wave Length (mm)

(a) Soft Pad

(b) Hard Pad

100

Figure 5.8 Power spectral densities of nanotopography and pre-/post-CMP film thickness variation with different pads.

Figure 5.8 shows the power spectral densities (PSDs) of nanotopography and pre-/post-CMP film thickness variation. The higher the PSD number, the higher nanotopography in the surface of the wafer. To directly relate the nanotopography and the film thickness variation after CMP, we introduce a theory conducted by the professor J.G. Park, who used Fourier transform function to convert PSDs to a more understandable parameter called transfer function T(µ, t). Park and co-workers (2001) proposed a formula that describes the relationship between the nanotopography and the film thickness variations after CMP. The discussion is based on the concept of the planarization length of CMP, which is mentioned in Section of 5.3.1. Park et al. only deal with blanket (unpatterned, one material) wafers and the uniformity of the local polishing rate causing the fluctuations of surface height. The following formula is for one dimension:

h( x , t ) = w ( x ) + f ( x , t )


(5.1)

118


The height of the oxide surface at any time during polishing can be denoted as: x is position, t is time, h(x, t) is the height of the oxide surface, w(x) is the nanotopography of the silicon surface, and f(x, t) is the film thickness of the oxide. To simplify the formulation, the origin of the height axes for h(x, t), w(x), and f(x, t) can be arbitrary changed. The raised regions on the surface may cause the dynamical excess deformation of the polishing pad incurred during polishing. The deformation is propagated within a certain lateral range and it is a nonlocal phenomenon. It can be described by the spatial-convolution function in the real domain. The excess deformation of the polishing pad may affect the local removal rate. Supposing its effect is the linear correlation, the local polishing rate can be given by:

∂h( x , t ) =−( K 0 + K1 ⋅ CMP1 ⊗h( x , t )) ∂t

(5.2)

where K0 is the blanket polishing rate without considering nanotopography, K1 is the coefficient for the local excess-polishing rate caused by surface-height fluctuation, CMP1 (r) is the response function (r is the lateral distance from the origin) describing the nonlocal pad deformation and its affect on the polishing rate. The function CMP1 (r) is an even function and closely related to polishing parameters, such as the polishing-pad hardness, relative velocity between pad and wafer, polishing pressure, and so forth, through the planarization length that characterizes the lateral range over which the raised topography interacts. After integration of Equation 5.2 for time, h(x, t) is expressed as:

 h( x , t ) = h( x , 0) −  K 0 ⋅ t + K1  

∫

t 0

 CMP1 ⊗h( x , t )dt   

(5.3)

The unknown function h(x, t) is too complicated to solve analytically, so a simplification is applied below. When t = 0, if the film thickness f(x,0) is uniform enough for our analysis, the initial surface-height fluctuation can be denoted as follows using Equation 5.1 (Note: the origin of the height axis is variable).

h( x , 0) = w ( x )

(5.4)

The spatial profile of h(x, t) is continuously changing as the polishing is performed. However, supposing that the h(x, t) can be described as the convolution of h(x, 0) (as the initial profile) and another time-dependent proper response function CMP2 (r, t), the equation is given by:


119

Nanotopography

CMP1 ⊗h( x , t ) = CMP2 (t ) ⊗w( x )

(5.5)

Then, Equation 5.3 can be rewritten as: h( x , t ) = w ( x ) − K1

∫

 = w( x ) − K1 

t 0

∫

CMP2 (t ) ⊗w( x )dt t

0

 CMP2 (t )dt ) ⊗w( x ) 

(5.6)

≡w( x ) − CMP(t ) ⊗w( x )

where CMP (r, t) is a time-dependent spatial-convolution function, and the term of K0 in Equation 5.3 is omitted because it is x-independent. After Equations 5.1 and 5.6, the film thickness f(x, t) can be expressed as:

f ( x , t ) =−CMP(t ) ⊗w( x )

(5.7)

Next, the Fourier transformation of Equation 5.7 is denoted as:

F (λ , t ) =−FTCMP(λ , t ) ⋅W (λ )

(5.8)

where λ is the spatial wavelength, F(λ, t), W(λ), and FTCMP(t) are the Fourier transforms of f(x, t), w(x), and CMP(t), respectively. After Equation 5.8, the relationship between the power spectral densities of film thickness variation and the wafer nanotopography can be expressed as: 2

2

F (λ , t ) = T (λ , t ) ⋅ W (λ )

(5.9)

where T(λ, t) is |FTCMP(λ, t)|2 , and it is a time-dependent response function and should still have a characteristics length originating the planarization length, which depends on the CMP parameters mentioned earlier. This response function T(λ, t) can be regarded as the transfer function from the nanotopography spectrum to the film thickness variation spectrum. That is to say, if this transfer function has a large value in a certain wavelength region, the component of the nanotopography impacts severely on the film thickness variation after CMP. Figure 5.9 is an example of two calculated transfer functions with wavelength. As mentioned earlier, the larger value of transfer function in certain wavelengths means the stronger impact of nanotopography on film thickness variation.


120


Value of Transfer Function

10

1 hard Pad soft Pad

0.1

0.01

0.001

post CMP (soft) post CMP (hard) 1

10 Wave Length (mm)

100

Figure 5.9 Transfer function as the ratio of the oxide film thickness variation to that of nanotopography.

The more detailed analysis of the Fourier transform function of Equation 5.9 and the correlation between T(λ, t) and the nanotopography impact on the film thickness variation with different pad hardness will be discussed in the next section. 5.3.3 Impact of Nanotopography on Silicon Wafer on Oxide CMP 5.3.3.1 Wafering Method Dependency of Impact of Nanotopography on Oxide CMP In addition to CMP process optimization, better silicon wafers are required to solve the nanotopography problem. In general wafer manufacturing (wafering), chemical etching is applied to remove the mechanical damage induced during the preceding lapping process. This is followed by a polishing process to improve the parallelism of the wafer and create a very flat surface. The polishing process applied during wafering can be either DSP or SSP. For 8-inch wafers, device manufacturers generally require SSP because the frontside of the wafer is then distinct from the backside. To improve the nanotopography of SSP wafers, a combined chemical etching and SSP process that can be applied during wafering was developed, and the performance of the resulting wafers for oxide CMP was examined by the analysis method described earlier. Three chemical etching methods were applied: acid etching, alkali etching, and multietching (acid and alkali), which allowed us to obtain the benefits of both acid and alkali etching in a compatible process. To prepare the wafers to be tested, we used two polishing methods: conventional single-side polishing with wax mounting (SSP1) and improved single-side polishing (SSP2), in which the backside topography has little effect on


121

Nanotopography

the polishing of the front surface. Combining the three etching methods and the two polishing methods yielded six types of sample wafers. In this book, we will use a notation based on the letters and numbers given above to distinguish between wafer types, that is, A1 refers to a wafer that underwent acid chemical etching and wax mounted polishing (SSP1). Professor J.G. Park has produced a series of experiments to understand the effect of the different etching method and the different polishing method on film thickness variation after the CMP process. Figure 5.10 shows the height maps and line profiles of the six wafer types. Table 5.1 shows the parameters in this experiment of oxide CMP. (1)

(2)

Height (Å)

(a)

500 0 –500

500 0 –500

(b)

Height (Å)

+500 Å 500 0 –500

500 0 –500

Height (Å)

(c)

500 0 –500

500 0

–500 Å

–500

Figure 5.10 Nanotopography maps of wafers prepared using each process combination. Darker regions of the map correspond to a lower height and brighter regions to a greater height. The height profiles along the x-axis are shown.


122


Table 5.1 Standard Deviation of Height Profile (nm) SQM and NanoMapper

NanoMapper and DynaSearch

DynaSearch and SQM

Measurement 1

23.29

17.20

29.57

Measurement 2

13.00

13.21

18.23

Measurement 3

17.85

16.53

26.55

Measurement 4

12.15

11.57

19.95

Measurement 5

14.40

14.62

21.20

0

Nanotopo

–400 –300 pre-CMP –200 –100 0 post-CMP 100 200 –64 –48 –32 –16 0 16 32 48 Distance from Center (mm) (a)

–500

64

Inverse Film Thickness (Å)

500 0

Nanotopo

–400 –300 pre-CMP –200 –100 0 post-CMP 100 200 –64 –48 –32 –16 0 16 32 48 Distance from Center (mm) (b)

Nanotopography Height (Å)

500

–500


Inverse Film Thickness (Å)

As shown in Figure 5.10, the A1 wafer had the largest nanotopography, whereas the C2 wafer had the smallest. Comparing the polishing methods, we observe that SSP2 resulted in smaller height variation than SSP1. Figure 5.11 shows examples of the correlation between nanotopographic

64

Figure 5.11 Examples of the correlation between the nanotopography and inverse film thickness profiles before and after CMP for (a) A1 wafer and (b) C2 wafer.


123

Nanotopography

line profiles and film thickness variation before and after CMP. Figure 5.11a shows that for the A1 wafer and Figure 5.11b shows the C2 wafer. The peak and valley positions of the nanotopography coincided well with the film thickness variation after CMP, particularly for the A1 wafer. It can be observed that even the small nanotopography of the C2 wafer slightly influenced the film thickness variation. We attributed the fluctuations in the film thickness after CMP to the nanotopography. Note that the film thickness profiles are inversely plotted, which means that excess thinning occurred due to a pressure concentration at each local peak position of the nanotopography. In Figure 5.12, the standard deviation of the nanotopography and the film thickness variation after CMP are summarized for the six wafer types. Each value was calculated from the filtered profiles. For all types of etching, particularly acid etching, SSP2 more effectively reduced the nanotopography impact on the post-CMP film thickness variation. Wax mounting was

Nanotopography Rms (Å)

300

A) Acid

250

B) Alkali C) Acid & Alkali

200 150 100 50 0

1) SSP-1

2) SSP-2 (a)

Filtered Film THK Rms (Å)

50

A) Acid B) Alkali

40

C) Acid & Alkali

30 20 10 0

1) SSP-1

2) SSP-2 (b)

Figure 5.12 Standard deviations (Rms) of (a) the nanotopography and (b) the filtered film thickness after CMP.


124


used in SSP1 to hold the backside of the wafer on the flat ceramic plates. The backside waviness due to the chemical etching caused excessive height variation on the front surface through the internal stress distribution within the wafer. After stock removal polishing, the front surface became smooth, but once the wafer was removed from the ceramic plate, the internal stress was released and variation of the front surface height caused by the backside waviness appeared. This is probably the reason for the SSP1 wafers showing more nanotopographic variation than the SSP2 wafers. Among the different etching methods, acid etching resulted in the greatest nanotopographic variation, whereas the combined acid and alkali etching would account for the greater nanotopographic variation. Multietching can be optimized to reduce the waviness by balancing the acid and alkali factors. The variation that appears as waviness after the chemical etching leads to nanotopography due to the backside influence described above and/or residual waviness on the front side after polishing. The correlation between the standard deviations of the OTD (oxide thickness deviation) and the NH (nanotopography height) is plotted in Figure 5.13. The OTD is independent of the nanotopography before CMP. On the other hand, the OTD and NH after CMP show a clear, positive correlation. The slope of the fitting line for the post-CMP correlation in Figure 5.13 may vary, depending on the CMP process parameters. A small slope indicates that the nanotopography is less likely to have an impact on the effectiveness of the CMP process. We also calculated the PSDs of the NH and OTD. The PSDs for the A1 and C2 wafers are shown in Figure 5.14 as examples. This analysis quantitatively demonstrates that the C2 (multietching, SSP2) wafer had less nanotopography than the A1 wafer within the wavelength range from 2 to 100 50

pre-CMP post-CMP

Rms of OTD (Å)

40 30

y = 0.136x + 14.121 R2 = 0.948

20 10 0

y = –0.0001x + 2.9348 R2 = 0.0044 0

100 200 Rms of NH (Å)

300

Figure 5.13 Correlations between the Rms of the NH and that of the OTD.


125

Power Spectral Density (Å^2.mm)

Nanotopography

1.E+12

A1 C2

1.E+10 1.E+08 1.E+06 1.E+04 1.E+02

1

10 Wavelength (mm)

100

Power Spectrl Density (Å^2.mm)

(a) 1.E+10

A1 pre C2 pre A1 post C2 post

1.E+08

post-CMP

1.E+06

pre-CMP

1.E+04 1.E+02

1

10 Wavelength (mm)

100

(b) Figure 5.14 Power spectral densities of (a) height changes and (b) film thickness variations before and after CMP for the A1 and C2 wafers.

mm (Figure 5.12a). Regarding the film thickness variation (Figure 5.12b), the spectra before CMP were independent of the wafer nanotopography. On the other hand, the PSD of the OTD increased after CMP in accordance with the wafer nanotopography, which clearly demonstrates that the C2 wafer had a more uniform film thickness than the A1 wafer within the wavelength range from 2 to 30 mm. A clear and positive correlation between the standard deviation of the nanotopographic profile and that of the film thickness after CMP is evident. The PSD analysis of the CMP results quantitatively demonstrated the effect of the nanotopography of different wafers on the film thickness variation. Wafers prepared with the improved SSP technique had less film thickness variation after unpatterned oxide CMP than the wafers that underwent conventional SSP due to the impact of the nanotopography.


126


5.3.3.2 Slurry Characteristic Dependency of Impact of Nanotopography on Oxide CMP

0

–100

–500

0

–1000

100 –64 –48 –32 –16 0 16 32 48 64 Distance from Center (mm)

–1500

–1000

100 –64 –48 –32 –16 0 16 32 48 64 Distance from Center (mm)

–1500

(c)

Oxide Thickness Deviation (Å)

–500

0

–1000

100 –64 –48 –32 –16 0 16 32 48 Distance from Center (mm)



0

–100

–500

0

64

–1500

(b) 500

–200

0

–100

(a) –300

500

–200

–300

500

–200

0

–100

–500

0

–1000

100 –64 –48 –32 –16 0 16 32 48 Distance from Center (mm)

64

–1500


–200

–300


500


–300



To quantitatively analyze the impact of nanotopography on post-CMP oxide film thickness, we have introduced a spatial spectral method, and have used it to examine the effect of the pad type, removal depth, wafer manufacturing technique, and polishing method. However, the role of the slurry in controlling the impact of nanotopography on STI CMP is not yet clear. In this section, we discuss how the concentration of surfactant and abrasive size affect the impact of nanotopography. Four kinds of slurry with different sizes of abrasives, denoted as A, B, C, and D, were prepared through a mechanical treatment. Figure 5.15 shows the correlation between the lateral profiles of the NH and post-CMP OTD on a wafer for two surfactant concentrations. Figures 5.15a and b correspond to slurry A (largest abrasives) with surfactant concentrations of 0 and 0.80 wt%, respectively. Figure 5.15c and d correspond to slurry D (smallest abrasives), also with surfactant concentrations of 0 and 0.80 wt%, respectively. For each of the various surfactant concentrations, the peak and valley positions of the NH and post-CMP OTD coincide well with each other. Therefore, the fluctuations in the post-CMP OTD can be attributed to the wafer nanotopography. Whereas the magnitude of the OTD for slurry A is similar with or without surfactant, that for slurry D increased with the surfactant concentration.

(d)

Figure 5.15 Correlation between the NH and the post-CMP oxide thickness variation: (a) Slurry A, 0 wt%; (b) Slurry A, 0.8 wt%; (c) Slurry B, 0 wt%; (d) Slurry B, 0.8 wt%.


127

Nanotopography

50 40 30 20

m

(n

Siz e

0.00 Surf 0.05 acta nt C 0.10 0.20 once ntra 0.60 tion 0.80 (wt% )

72(D) 82(C) 148(B) 290(A)

ive

0

)

10

Ab ra s

Rms of Post-CMP OTD (A)

60

Figure 5.16 Standard deviation (Rms) of the post-CMP oxide thickness deviation.

The correlation between the abrasive size, the surfactant concentration, and the standard deviation of the OTD is shown in Figure 5.16. For slurries A and B, the standard deviation of the OTD is not influenced by the surfactant concentration. For slurry C, however, the standard deviation increases gradually with increasing surfactant concentration. For slurry D, it increases even more strongly with increasing surfactant concentration. Thus, when slurry with smaller abrasives is used, the magnitude of the OTD increases with increasing surfactant concentration. That is, the surfactant more strongly influences the nanotopography impact on OTD after CMP in the case of smaller abrasives. Though other factors, such as the selectivity of the removal rate between oxide and nitride films, must be taken into account when discussing the influence on the actual STI CMP process, these findings show that the nanotopography impact can be controlled by manipulating the slurry characteristics. Note that even if the ceria slurry generally used in STI CMP has high oxide-to-nitride removal selectivity, it basically avoids only excessive thinning of the nitride. It does not avoid incomplete clearing of the oxide as an influence on the nanotopography. The PSDs of the post-CMP OTD for three surfactant concentrations are shown in Figure 5.17. The PSD increased with increases in the surfactant concentration in the wavelength range up to 30 mm. This result suggests that the change in planarization efficiency (or nanotopography impact) as a result of adding the surfactant occurs even in a longer wavelength range up to around 30 mm. The mechanism for the impact of nanotopography on post-CMP OTD is directly related to the planarization of the oxide surface. That is, the local polishing rate of the protruding areas produced by nanotopography is greater than that of the valley areas, which causes excessive thinning of the oxide film at each nanotopography peak, as shown in Figure 5.18.



Power Spectral Density (Å^2.mm)

128

1.E+10

0.00 wt% 0.20 wt% 0.80 wt%

1.E+08 1.E+06 1.E+04 1.E+02

1

10 Wavelength (mm)

100

Figure 5.17 Power spectral densities of oxide thickness deviation after CMP.

Boning and Lee (2002) simulated this nanotopography impact through a contact mechanics model of the local contact pressure of the polishing pad on the wafer surface. However, an analysis that considers only the polishing pad and the film surface topography cannot explain the results of this study, as the role of the surfactant in planarization must also be taken into account. Nojo et al. (1996) proposed a useful model that contributes to our understanding of these results. They reported that adding a surfactant to ceria slurry can result in “self-stopping polishing,” in which the polishing rate drops automatically as planarization progresses. They attributed this to the protective layer formed on the surface of the film by the surfactant. We expanded this model to take account of the effect of the abrasive size, as shown in Figure 5.18a. The larger abrasives marked A and B in the figure can remove both protruding areas and valley areas, but the smaller abrasives marked C and D can remove only protruding areas due to the thicker surfactant layer when the surfactant is added to the slurry. Accordingly, for the smaller abrasives case (marked C and D), the surface of the post-CMP film in the slurry with surfactant becomes flatter than that in the slurry without surfactant. A flatter post-CMP film surface corresponds to a more severe impact of nanotopography on OTD, as shown in Figure 5.18b. As a result, this model can explain the results shown in Figure 5.16. In conclusion, the magnitude of film thickness variation after CMP was found to increase with the surfactant concentration in slurries with smaller abrasives but to be almost independent of the surfactant concentration in the slurry with the larger abrasive. This result can be explained with the model based on the passivation layer of the surfactant adsorbed on the oxide film surfaces during polishing.


129

Nanotopography

Larger Abrasives

Smaller Abrasives Polishing Pad

A

B

C

Surfactant Layer

D

SiO2 Film (a)

SiO2

Si (b)

–40 –30

100

Nanotopography

80 60

–20

40

–10

20

Experiment

0

0 –20

10

–40

20

–60

30 40 –64

–80

Simulation Result –48

–32

16

0

Nanotopography Height (nm)

Inverted Poly-silicon Thickness Variation (nm)

Figure 5.18 Proposed model for the nanotopography impact: (a) dependence of surface planarization efficiency on the abrasive size and surfactant and (b) relationship between film surface flatness and oxide thickness deviation after CMP.

16

32

48

–100 64

Wafer Position (nm) Figure 5.19 Correlation between simulated and experimental polysilicon thickness variation reduced by wafer nanotopography.



PV of Remaining Poly-silicon Film Thickness Variation After CMP (nm)

130

40 Experiment Fitted curve

30

20

10

0

0

20 40 60 80 100 PV of Wafer Nanotopography (nm)

120

Figure 5.20 PV of remaining polysilicon thickness after polysilicon CMP, depending on PV of wafer nanotopography in 10-mm scan.

5.3.3.3 Effect of Wafer Nanotopography on Remaining Polysilicon Thickness Variation after Polysilicon CMP Figure 5.19 shows the centerline profile for the wafer nanotopography (top line profile) and that for the remaining polysilicon thickness variation (middle profile line). The peak and valley positions of inverted thickness variation are well correlated with that of wafer nanotopography. This indicates that wafer nanotopography directly influences the thickness variation after polysilicon CMP. The bottom line in Figure 5.19 shows the simulated remaining polysilicon thickness variation induced by wafer nanotopography, based on the wear-contact model. It is obvious that the measured thickness variation (middle profile line) is well correlated with the simulated one (bottom line profile). This indicates that the polysilicon CMP mechanism using colloidal silica slurry follows Prestonian behavior rather than non-Prestonian behavior. Figure 5.20 shows the peak-to-valley (PV) value along the 10-mm radial scan of the remaining polysilicon thickness variation after polysilicon CMP as a function of the PV value along the 10-mm radial scan of wafer nanotopography. The PV value after polysilicon CMP exponentially increases with that of wafer nanotopography. Again, the wafer nanotopography strongly affects the remaining polysilicon thickness variation after polysilicon CMP, suggesting that the wafer nanotopography results in V T variation for a NAND-flash memory-cell fabricated with the self-alignment of polysilicon floating-gate via polysilicon CMP. This is because both the voltage coupling of the floating-gate and the floating-gate interference in the NAND-flash memory-cell are determined by the height of the polysilicon floating-gate, which is influenced by the remaining polysilicon thickness variation after polysilicon CMP.


131

Nanotopography

45 nm

(a)

Wafer Nanotopography PV

Poly-silicon Thickness PV

10 mm

30.1 nm

(b)

59.9 nm

(c)

Figure 5.21 (See color insert) Schematic structures of a 63-nm NAND-flash memorycell with different floating-gate heights, induced by the wafer nanotopography of 10-mmdiameter scanning: (a) 45-nm height (free of wafer nanotopography influence); (b) 30.1-nm height (at the top of wafer nanotopography influence); (c) 59.9-nm height (at the bottom of nanotopography influence).

5.3.3.4 Effect of VT Variation of Wafer Nanotopography on Remaining Polysilicon Thickness Variation after Polysilicon CMP A 63-nm NAND-flash memory-cell has a chip-side size of approximately 10 mm, as shown in Figure 5.21. We assumed that after polysilicon CMP the peak position of wafer nanotopography produces the smallest height of the polysilicon floating-gate (Figure 5.21b) and that the valley value of wafer nanotopography produced the largest height of polysilicon floating-gate (Figure 5.21c). To calculate the V T variation originating from the PV value of the remaining polysilicon thickness after polysilicon CMP induced by wafer nanotopography, we should extract the floating-gate voltage determined by the floating-gate voltage coupling ratio and the floating-gate interference effect. Figures 5.22a and b show a three-dimensional schematic drawing of NAND-flash memory-cells and top views of each cell. Here, it was assumed that memory cell No. 5 was programmed. The applied voltage on the control gate, VCG, at the selected word line was 18 V (Vpgm), while that at the unselected word line was 9 V (Vpass) for the 63-nm cell. The selected word-line bias was 16 V (Vpgm), and the unselected word-line bias was 8 V (Vpass). The applied voltage on the selected bit line was ground (GND), while that at the unselected bit line was 1.8 V (Vcc). Therefore, the channel-regions bias (Vch) of unselected bit-line cells was floating.


132


Vcc

Vcc Vpass Vpgm

#4

#7

GND

#8

#1

#2

#5

#6

#9

#3

Vpass

(a) BL1 #1

BL2 #2

F-gate

BL3 #3

C-gate WL1

CyFG2-yFG5 #4

F-gate

#5

CxFG4-xFG5 PGM cell CxFG5-xFG6

#6

CyFG5-yFG8 #7

#8

F-gate

F-gate

WL2 C-gate

#9

WL3

CFGCG : cap. between f-gate and c-gate (b)

Figure 5.22 (See color insert) Programming operation of a NAND-flash memory-cell, where the programming cell is No. 5: (a) voltage bias conditions for memory cells and (b) parasitic capacitances during No. 5 cell programming.

The device dimension for the 45-nm cell was extracted from the dimensional trend for 90-, 70-, and 63-nm technology nodes. According to this trend, the height, length, and width of the floating-gate are 32, 45, and 57 nm, respectively. For the 63-nm NAND cell, oxide–nitride–oxide (ONO) layer and tunneling oxide thicknesses (equivalent oxide thickness, EOT) were 14.5 and 6 nm; for the 45-nm one, they were 11.9 and 5.2 nm, respectively. Each of the parasitic capacitances was obtained using the equation C = εrε 0A/d, where εr, ε 0, A, and d are the dielectric constant for insulating film, dielectric constant for vacuum, capacitor area, and insulation film thickness, respectively. CxFG4-xFG5, CxFG5-xFG6, CyFG2-yFG5, and CyFG5-yFG8 are the parasitic capacitances between the floating-gates at cells 4 and 5, 5 and 6, 2 and 5, and 5 and 8, respectively. CyFG2-yCG5 and CyFG5-yCG8 are the


133

Nanotopography

parasitic capacitance between the floating-gate at cell 2 and control-gate at cell 5 and between the floating-gate at cell 5 and control-gate at cell 8, respectively. The other parasitic capacitances were neglected because their values are compared with those of the above-mentioned six parasitic capacitances. Since the ONO capacitance at the programmed memory-cell (CONO) depending on the height of floating-gate is related to the voltage coupling ratio, the calculation of CONO was performed with a device simulator (ATLAS, Silvaco Corp.) Using the results of two-dimensional Poisson equation solving, CONO was calculated by the formula

VFG =

CONO C V VCG → CONO = TUN FG CONO + CTUN VCG −VFG

(5.10)

where VFG and CTUN are the floating-gate voltage without considering the floating-gate interference effect and tunnel oxide capacitance. As shown in Figure 5.23, CONO for the 63- and 45-nm memory-cell linearly increases with increasing polysilicon floating-gate height determined by the PV of the remaining polysilicon thickness after polysilicon CMP. After the calculation of CONO, the floating-gate voltage, considering the floating-gate interference effect (VFG5), was calculated by

VFG 5 =

CONOVCG 5 + CxFG 4−xFG 5VFG 4 + CxFG 5−xFG 6VFG 6 + C yFG 2− yFG 5VFG 2 + C yFG 5− yFG 8VFG 8 + CFGCG (VCG 2 + VCG 8 ) CTUN + CONO + CxFG 4−xFG 5 + CxFG 5−xFG 6 + C yFG 2− yFG 5 + C yFG 5− yFG 8 + CFGCG

(5.11)

where VFG4,VFG6, VFG2, and VFG8 are the floating-gate voltage at cells 4, 6, 2, and 8, respectively, and VCG2 and VCG8 are the control-gate voltage at cells 0.028

63-nm NAND-flash Memory-cell

0.026 0.024 CONO (fF)

0.022 0.020

0.0225 fF

0.018 0.016 0.014 0.012

0.0108 fF

0.010 0.008 0.006

15


20 25 30 35 40 45 50 55 60 Poly-silicon Floating-gate Height (nm)

Figure 5.23 Calculated dependence of CONO on polysilicon floating-gate height.



45-nm 63-nm

Floating-gate Voltage (V)

8.5

9.5

8.0

9.0

7.5

8.5

7.0

0.54


0.52


0.50 0.48 0.46

8.0

10

Vpgm = 18 V @ 63-nm Vpgm = 16 V @ 45-nm

Voltage Coupling Ratio

134

0.44 0.42

20 30 40 50 60 Poly-silicon Floating-gate Height (nm)

Figure 5.24 Dependence of floating-gate voltage on floating-gate height with program voltage biasing.

2 and 8, respectively. For the 63-nm cell (63-nm gate length and 80-nm gate width), the distances between the floating-gates along the word line and bit line are 63 and 50 nm, respectively. For the 45-nm one (45-nm gate length and 57-nm gate width), they are 45 and 50 nm, respectively. Programming voltages were assumed to be 18 and 16 V for the 63- and 45-nm cells, and the pulse duration was 200 μsec. Figure 5.24 shows VFG5 as a function of polysilicon floating-gate height determined by the PV of the remaining polysilicon thickness after polysilicon CMP. VFG5 increases with polysilicon floating-gate height. The voltage coupling ratio for the 63-nm cell (at 45-nm floating-gate height) is approximately 2.2% larger than that for 45-nm one (at 32-nm floating-gate height). This indicates that the floating-gate voltage coupling becomes weaker as memory size becomes smaller because of the reduction of floating-gate voltage coupling and the enhancement of floating-gate interference. Fowler–Nordheim tunneling-current density, well known as the programming mechanism of a NAND-flash memory-cell, is represented by

32  *  −4 2m (qφox )  q2E 2 J= exp     16πφox 3qE  

(5.12)

where  is the conduction barrier height between SiO2 and silicon substrate and m* is the effective mass of electron. The size of the active area generating Fowler-Nordheim tunneling is W × L = 51.4 × 63 nm for the 63-nm NAND and 36.7 × 45 nm for the 45-nm NAND. The number of electrons can be approximately obtained because the current density is converted to charge when the pulse duration is 200 μsec, as assumed earlier.


135

Nanotopography

Number of Tunneling Electrons (EA)

1800 1600 1400 1200

Floating-gate Voltage (V) 9 10

8 7

8

9

TTUN = 6.0 nm @ 63-nm TTUN = 5.2 nm @ 45-nm Pulse Duration = 200 µsec

63-nm 45-nm

1000 63-nm NAND-flash Memory-cell

800 600 400 200


0 13 14 15 16 17 18 Electric Field on Tunneling Oxide at Cell No. 5 (MV/cm)

Figure 5.25 Number of tunneling electrons versus floating-gate voltage and electric field on tunneling oxide at cell No. 5.

The result is shown in Figure 5.25, where the x-axis is the voltage applied to the tunneling oxide and electric field, and the left y-axis is the number of tunneling electrons. Although, the number of tunneling electrons in the 63-nm NAND is larger than that of 45-nm NAND-flash memory-cell, V T variation of the latter is severe. This is because the tunneling oxide capacitance of the 63-nm NAND is 1.99 times bigger than that of 45-nm NAND, due to the large active silicon area. As VFG is changed with floating-gate height, the variation of V T defined by ΔV T is represented by ∆VT ,63nm =

∆QFN (= QFN ,45+α nm − QFN ,45−α nm ) CTUN ,63nm

∆VT ,45nm =

∆QFN (= QFN ,32+α nm − QFN ,32−α nm )

CTUN ,45nm

(5.13)

(5.14)

where α is the height of the changed floating-gate. For instance, if the height of the floating-gate has the variation of 10 nm, then α is 5 nm. Therefore, ΔQFN is QFN,50nm – QFN,40nm. The variation of V T classified by thickness, calculated earlier, is represented by the function of the PV of the polysilicon floating-gate height induced by wafer nanotopography, as shown in Figure 5.26. The final V T variation represents the difference in the variation between two cells that have different polysilicon floating-gate


136


0.7 0.6


VT Shift (V)

0.5 0.4 0.3 0.2


0.1 0.0

0

5 10 15 PV of Poly-silicon Floating-gate Height (nm)

20

Figure 5.26 Threshold voltage of NAND-flash cell shift due to film thickness variation.

heights. Thus, for both the 63- and 45-nm NAND-flash memory cells, V T variation linearly increased with the PV of the polysilicon floating-gate height induced by wafer nanotopography. However, the V T variation for the 45-nm cell is higher. The PV of the polysilicon floating-gate height and the PV of the wafer nanotopography are related, as shown in Figure 5.21c. Accordingly, the V T variation linearly increases with the PV of the wafer nanotopography, as shown in Figure 5.27. The impact of the V T variation for the 45-nm NAND is higher than that for 63-nm. This shows that the larger the direct influence of the wafer nanotopography, the larger the V T variation becomes. It is intuitive that the impact of the wafer nanotopography on the V T variation becomes larger as the memory-cell-device design rule (gate length) becomes smaller. Thus, optimizing silicon-wafer fabrication processes to reduce the PV of wafer nanotopography, and thereby minimize the V T variation, is key to improving device yield.

5.4 Equipment in Measuring the Nanotopography Three kinds of instruments for the characterization of nanotopography, namely, SQM, NanoMapper, and DynaSearch are reviewed and compared. The calibration result using identical samples is also shown. 5.4.1 Introduction to General Equipment Used in the Measurement of Nanotopography How is nanotopography inspected and sorted?


137

Nanotopography

0.40 45-nm NAND-flash Memory-cell

0.35

VT Shift (V)

0.30

29 nm

0.25 0.20 0.15

49 nm

0.10


0.05 0.00

0

10 20 30 40 50 60 70 PV of Wafer Nanotopography (nm)

80

Figure 5.27 NAND-flash cell threshold voltage shift resulting from wafer nanotopography. X Deflection

Incident Laser Beam

Partial Mirrors

Y Deflection

PMT Slit to Filter Distorted Light PMT

Sum Quad Cell Detector

Reflected Laser Beam PMT Wafer Surface Figure 5.28 Optical schematic of SQM.

Spot Centered

Figure 5.29 Quantitative measurement of surface slope.


Spot Offset

138


Figure 5.30 Slope magnitude map of nanotopography of polished 200 mm wafer.

5.4.1.1 SQMTM (Surface Quality Monitor), from ADE, USA A. Laser beam reflectance-based bright channel technology (quad cell)

1. AWIS-SQM: It is viewed as a next-generation multifunctional inspection tool; can be used in a 200 mm or 300 mm wafer; has multifunctional inspection capability; and is mainly used in measurement of particle, haze, and nanotopography.

2. CR83-SQM: Currently used as the standard wafer substrate inspection tool worldwide. The WIS CR83-SQM provides wafer manufacturers the required nanotopography measurement capability for design rules down to 0.18 micron and better. It is the production tool for nanotopography inspection, sorting and surface mapping. Utilizing ADE’s Quad Cell technology, the WIS CR83 provides height maps based on slope measurements and has a dynamic range from 0.5 mm to 10 mm. Its versatile software allows users to define four unique nanotopography bins for automated sorting by specifying a designated height change (nm) over a specified distance (spatial wavelength). It also allows users to view height maps at five selectable view scales. With these capabilities the WIS CR83 enables wafer manufacturers to simultaneously inspect for nanotopography features and monitor their production processes.

B. SQMTM Technology: Bright Field Quad Cell • Surface nanometer scale topography height variation and location over whole wafer surface • Automated sort on user-defined parameters


Nanotopography

• • • • •

139

Change in reflected angle = 2 × Change in surface slope Change in spot location = Focal length × Reflected angel Quad cell circuit converts spot location to voltage Extract surface slope distribution within a wafer Height map is calculated from the integration of the slope

5.4.1.2 NanoMapper, from ADE Phase Shift, USA A. NanoMapper®: NanoMapper is a nanoscale science and engineering (NSE) knowledge mapping system developed by the Artificial Intelligence Lab at the University of Arizona. NanoMapper enables users to search for patents (1976/1978–2006) or grants (1991–2006) by patent or grant number, keywords, and other data fields. NanoMapper also provides analysis tools. The National Science Foundation supported this research project. NanoMapper is an automated, precision surface mapping system available for research, analytical, and process control applications for 200 mm and 300 mm wafers. Using proprietary, optical interferometry from ADE Phase Shift, the system characterizes polished wafer surfaces by providing whole wafer topology measurements.

1. Product highlights −− Wafer nanotopography measurement −− Measurement features: −− Able to accurately repeat measurements −− Measures 200 and/or 300 mm wafers, based on configuration −− User editable recipes −− Software features: −− Measures nanotopography to the edge of the wafer −− User editable recipes

B. NanoMapper® FA (Figure 5.31): NanoMapper FA has all the analysis options of its R & D brother, but features full factory automation, including FOUP, SMIF, and open cassette capabilities. With NanoMapper FA, you can have: full edge-grip capability, enhanced chuck performance, and additional SECS-GEM functionality. NanoMapper FA is an automated, precision surface mapping system available for research, analytical, and process control applications for 200 mm and 300 mm wafers. Using proprietary, optical interferometry from ADE Phase Shift, the system characterizes polished wafer surfaces by providing whole wafer topology measurements.


140


Figure 5.31 NanoMapper FA.

1. Product highlights −− Automated wafer nanotopography measurement −− Measurement features: −− Able to accurately repeat measurements −− Subnanometer height resolution −− Software features: −− Measure nanotography to the edge of the wafer −− Single-statistic pass/fail threshold curve analysis −− User editable recipes

C. Summary

1. Unfiltered height data typically includes ~10 microns of topography for quality prime wafers.

2. Spatial filtering removes the high amplitude long wavelength shape information to reveal nanotopography. −− Spatial filter cutoff wavelength should be approximately twice the CMP length. −− Nanotopography directly impacts post-CMP film thickness variation.

Measuring surface height directly, NanoMapper provides the subnanometer sensitivity necessary to address the process development needs


Nanotopography

141

for leading edge semiconductor device design rules down to 0.1 micron. Interactive 3-D graphics and powerful analysis software allow rapid visualization and quantification of polishing process effects. These effects include nanotopology defects that ultimately limit wafer usability during semiconductor device fabrication. The result is faster process development and precision process control during production, with reduced wafer scrap costs. 5.4.1.3 DynaSearch, from Raytex, Japan DynaSearch (Figure 5.32) is an optical measurement system for evaluating the flatness of 200 mm and 300 mm wafers based on a unique, proprietary image processing algorithm. It views the entire surface of the wafer and gives real-time image data to derive the wafer topography from the angular components of the skewed surface. The system is capable of evaluating both the wafer flatness and nanotopography (Figure 5.33). Using Raytex’s proprietary optical method, the DynaSearch performs scientific wafer topography measurement and inspection to quantify wafer flatness and topography. This one unit handles both the wafer flatness and the nanotopography measurements necessary to evaluate wafer-manufacturing quality. The Raytex’s EdgeScan edge inspection, BackScan backside inspection, and flatness and topography measurement performed by the Raytex DynaSearch are a winning product combination that enables users to create a total shipping inspection line.

1. Features: • Performs high-resolution high-accuracy wafer topography measurement using Raytex’s proprietary optical measurement system

Figure 5.32 (a) DynaSearch N4-800, (b) DynaSearch N4-1200.


142


Figure 5.33 (a) Flatness measurement, (b) nanotopography measurement.

• Minimal impact due to vibration or other equipment environmental conditions unavoidable using conventional interferometry • Employs a stepper-type chuck for measurement to reproduce lithography flatness conditions in measurement


Nanotopography

143

2. Measurement items: • Flatness measurement • Nanotopography measurement 3. Applications: • Outgoing/acceptance inspection of mirror and epitaxial wafers • Wafer shape evaluation before and after film deposition and epitaxial processes • Yield improvement of photolithographic process • Conditioning of grinding, polishing, diffusion, and epitaxial growth

5.4.1.4 Line Profile Comparison among Three Instruments The line profiles of height change along the x-axis of the wafer measured by SQM, NanoMapper, and DynaSearch are superimposed on Figures 5.34a–e. Each of five measurements is done for different wafers. The filters applied to raw profiles are “Standard Filter” for SQM and “Gaussian Filter” for NanoMapper and DynaSearch. The cutoff length is set to 20 mm for all methods. From the overview of the profiles, the positions of local peak and valley almost coincide for the three tools. However, SQM gives somewhat different profiles from the other two methods. 5.4.1.5 Calibration among the Standard Deviations of Height Change Measured by Three Kinds of Instruments Figures 5.35a–c is the calibration among the standard deviations of height change profiles. As for the standard deviation, SQM gave smaller values and variations than NanoMapper or DynaSearch (see also Table 5.1).


144


Figure 5.34 Sensitivity comparisons of SQM, NanoMapper, and DynaSearch: (a) Measurement #1, (b) Measurement #2, (c) Measurement #3, (d) Measurement #4, (e) Measurement #5.

Height Change (nm)

100

Measurement #1 SQM Nanomapper DynaSearch

0

–100 –100

–50 0 50 Distance from Center (mm)

100

A

Height Change (nm)

100


0

–100 –100

–50 0 50 Distance from Center (mm) B


100

145

Nanotopography

Height Change (nm)

100


0

–100 –100


100

C

Height Change (nm)

100


0

–100 –100


100

D

Height Change (nm)

100


0

–100 –100

–50 0 50 Distance from Center (mm) E


100

146


Figure 5.35 Standard deviation comparison of SQM, NanoMapper, and DynaSearch: (a) SQM and NanoMapper, (b) NanoMapper and DynaSearch, and (c) DynaSearch and SQM. STDEV Correlation: SQM vs Nanomapper

30

Nanomapper STDEV (nm)

25

y = 1.7758x – 9.8358 R2 = 0.8203

20 15 10 5 0

0

5

10 15 20 SQM STDEV (nm)

25

30

A STDEV Correlation: Nanomapper vs DynaSearch

30

DynaSearch STDEV (nm)

25 20 15

y = 1.0058x – 6.8686 R2 = 0.9206

10 5 0

0

5

10 15 20 Nanomapper STDEV (nm) B


25

30

147

Nanotopography

STDEV Correlation: DynaSearch vs SQM

30

SQM STDEV (nm)

25 20

y = 0.4362x + 4.5493 R2 = 0.8039

15 10 5 0

0

5

10 15 20 DynaSearch STDEV (nm) C


25

30

6 Novel CMP for Next-Generation Devices

6.1 The Progress of Semiconductor Devices upon Current Demand Chapters 2 through 5 describe CMP process technology for semiconductor device makers. This chapter will describe CMP planarization technology for emerging devices and materials. From the point of view of the researcher whose specialty is detailed (or accurate) processing, the advent of CMP technology has diverse meaning. Silicon wafers on devices are an unapproachable part to the mechanic processing technician. Because of complex factors, the structure of a device’s circuit is becoming highly integrated and super miniature. As a result, the degree of rugged processing surface falls under nano scale because device processing and machine processing have very different materials of processing. Devices are shrinking to under 60 nm; therefore, new material and structure processing are appearing. To adapt to this condition, more progressive CMP processing is required and new structures and materials will arrive successively only through CMP processing. The memory industry is led by metal-oxide semiconductor (MOS) memory, which is largely divided into volatile and non-volatile memory (Figure 6.1). The example of volatile memory is dynamic random access memory (DRAM), whereas non-volatile memory is representative of flash memory. DRAM and flash memory developed rapidly due to the demands for high speed and high capacity devices such as computers, digital cameras, mobile phones, and MP3s (Figure 6.2). New structures and materials were used for improving the performance of these devices. CMP processing has faced a new challenge as well. Even though the integration of DRAM and flash memory is increasing during this brilliant growth, it is expected that it will hits its limits. To overcome its limit, instead of MOS memory, the latest non-volatile memory research includes phase-change random access memory (PRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), and resistance random access memory (ReRAM). But similar to MOS memory, these new non-volatile memory systems cannot increase integration and 149 © 2009 by Taylor & Francis Group, LLC

150


form multilayer without planarization processing. This chapter introduces DRAM under 60 nm of MOS memory, CMP processing applied to NAND flash, and CMP processing for next-generation memory producing. MOS Memories

Volatile

Nonvolatile

Read Only Memory (ROM)

Random Access Memory (RAM) Writable Static RAM (SRAM) 1970 by Intel

Dynamic RAM (DRAM) 1970 by Intel

Fixed

Programmable ROM (PROM) UV Erase Elec. Erase EPROM 1971 by Intel

Mask ROM 1970 by Intel

EEPROM Bit-wise Block

Conventional

Flash

1979 by Intel

1984 by Toshiba

Figure 6.1 Classification of MOS memories.

Year of Production

2005

2006

2007

2008

2009

2010

2011

2012

DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (Ml) ½ Pitch (nm)

80

70

65

57

50

45

40

36

2013 32

90

78

68

59

52

45

40

36

32

MPU Physical Gate Length (nm)

32

28

25

23

20

18

16

14

13

DRAM Product Table Cell area factor [a]

IS

Cell area [Ca = af2] (µm2)

Cell array area at production (% of chip size)

8

8

8

6

6

6

6

6

6

0.051

0.041

0.032

0.019

0.015

0.012

0.0096

0.0077

0.0061 56.08%

63.00%

63.00%

63.00%

56.08%

56.08%

56.08%

56.08%

56.08%

Generation at produciton

1G

2G

2G

2G

4G

4G

4G

8G

8G

Functions per chip (Gbits)

1.07

2.15

2.15

2.15

4.29

4.29

4.29

8.59

8.59

Chip size at production (mm2) Gbits/cm2 at production

88

139

110

74

117

93

74

117

93

1.22

1.54

1.94

2.91

3.66

4.62

5.82

7.33

9.23

75.7

63.6

56.7

50.5

45.0

40.1

35.7

31.8

28.3

4.0

4.0

4.0

4.0

4.0

4.0

4.0

4.0

4.0

Cell area [Ca = af 2] (µm2)

0.023

0.016

0.013

0.010

0.008

0.006

0.005

0.004

0.003

Cell array area at production (% of chip size)

Flash Product Table Flash ½ Pitch (nm) (un-contacted Poly)(f ) Cell area factor [a]

IS

IS IS

67.5%

67.5%

67.5%

67.5%

67.5%

67.5%

67.5%

67.5%

67.5%

Generation at production SLC

4G

4G

4G

8G

8G

8G

16G

16G

16G

Generation at production MLC

8G

8G

8G

16G

16G

16G

32G

32G

32G

Functions per chip (Gbits) SLC

4.29

4.29

4.29

8.59

8.59

8.59

17.18

17.18

17.18

Functions per chip (Gbits) MLC

8.59

8.59

8.59

17.18

17.18

17.18

34.36

34.36

34.36

Chip size at production (mm2) SLC Chip size at production (mm2) MLC

144

101.8

80.8

128.3

101.8

80.8

128.3

101.8

80.8

144

101.8

80.8

128.3

101.8

80.8

128.3

101.8

80.8

Bits/cm2 at production SLC

3.0E+09

4.2E+09

5.3E+09

6.7E+09

8.4E+09

1.1E+10

1.3E+10

1.7E+10

2.1E+10

Bits/cm2 at production MLC

6.0E+09

8.4E+09

1.1E+10

1.3E+10

1.7E+10

2.1E+10

2.7E+10

3.4E+10

4.3E+10

Figure 6.2 Technical roadmap for DRAM and NAND flash memory.


151

Novel CMP for Next-Generation Devices

6.2 Complementary Metal-Oxide Semiconductor (CMOS) Memory Memory semiconductors should be of high capacity through high-integrated circuits. DRAM cell factor evolved from 8F2 into 6F2. Along with expectations of 45 nm in 2010 to 32 nm in 2013, there is an anticipation that capacity per chip will increase fourfold like 2.15 Gbit to 8.59 Gbit. Flash memory keeps the design rule of 4F2 and when future technology passes through 56.7 nm to 28.3 nm, the capacity per chip will increase rapidly from 8 G to 32 G. Fulfilling multilayer and miniature structures of memory devices led to the introduction of new materials and structures. For the structure, the design rule decreases less than 70 nm and the short channel effect (SCE) phenomenon appears to have a bad influence on the device drive if existing planar transistor (TR) is applied. To solve this problem, studies are in progress to apply recessed channel array TR and three-dimensional structured FinFET in DRAM and floating gate, twin SONOS, and FinFET SONOS in flash memory (Figure 6.3). New materials are applied to maximize the capacity of device. To increase the capacitance of cap used in DRAM, studies about high-k dielectric material are in process. Flash memory uses a gate material with polysilicon by reason of high speed and stable storage. To reduce semiconductor device RC delay, Cu metal lines and low-k are being introduced. This section represents the concept of CMP processing being introduced to DRAM and NAND flash devices.

DRAM Planar Transistor

Year

2005

D/R(nm) 90

Recessed Channel Array Transistor

Partial Insulated FET

Body Tied FinFET

Multi Bridge Channel MOSFET

2006

2007

2008

2009

2010

2011

80

70

60

50

45

40

NAND Flash

Planar Transistor

Floating Gate CMP

Twin SONOS

Fin FET SONOS

Figure 6.3 Roadmap for transistor structures of DRAM and NANA flash memory.


152


A RCAT structure of three-dimensional recess channel array transistor was developed for the device memory to solve the problem of short channel effect, a demand of integration. The surface of device procession reduces and channel makes recess to lengthen the valid length. As a result, short channel effect can be reduced. Future technology under 60 nm will anticipate the partly insulation FET (PiFET) structure to the part of channel. PiFET that are drawn to the concept of body-tied SOI limits the junction depth by dielectric layer to easily form ultra shallow junction. It also has a small amount of leakage current and it has a merit of SOI that short channel effect is almost nonexistent. This is a device to diminish the production cost. DRAM of future technology under 45 nm is anticipated to have a MBCFET device structure of metal-oxide semiconductor field-effect transistor (MOSFET), which has multichannels by passing through FinFET. This device makes driving current larger and has a great advantage of current resistance capability of a gate because it has a gate all-around (GAA) structure. The self-aligned STI processing, which is a method of formation of floating gate into a device less than 60 nm, enlarges the surface of the floating gate. Therefore, it can increase coupling ratio. To avoid the coupling phenomenon, floating gates to the active area are aligned correctly; that is self-aligned poly Si floating gates fabricated by the CMP process are necessary to overcome the misalignment between the active area and the floating gate in cell arrays. 6.2.1 Noble Metal CMP for DRAM Existing SiO2 used in gate dielectric faces its limit because thickness of thin film becomes thinner by the integration of the semiconductor device. Indeed, power dissipation exceeds the standard rate because of the leakage current by tunneling of carrier by electric field is increased. Consequently, it has the same EOT electronically. High-k dielectric makes possible the embodiment of thickness of thin film without tunneling, is physically interested. With using high-k dielectric film, simplifying the cell structure and formation process is the most efficient method to ensure sufficient capacitance for the high-integrated capacitor’s role in narrow surfaces like miniaturizing the next generation of DRAM. Previously used dielectric film in low-k materials are NO of Si3N4/SiO2 and ONO of SiO2/Si3N4/SiOX. For the next-generation capacitor, the high-k materials mainly used are Al2O3, HfO2, ZrO2, Ta2O5, BST, and STO, as well as other materials such as HfSiOX and ZrSiOX. In semiconductor industry, high-k thin films form film by chemical vapor deposition (CVD). In relation to this, the study and developments of CVD precursors are as follows. Capacitor using HfO2 base dielectric film, applies TiN by top/bottom electrode. However, capacitor technology under 50 nm needs to develop new dielectric material and electrode material. So, noble metals, such as


153


1600

Ox. 2 Ox. 1 Ox. 5

1200

Ox. 3 Ox. 6

800 400 0 –400

Strong Passivation State (H2RuO5) Ox. 4

Weak Passivation State (RuO2H2O)

Metal State 0

2

4

Ru R/R Increase

Corrosion Potential (mV)

Ru, Pt, and Ir, are being researched as new electrode materials. In the case of the noble metal, which is a stable material, it is not easy to form a capacitor by using etch back or CMP processing. Noble metal CMP processing, including Ru, should oxidize the surface of polishing target film for the polishing process like other metal CMP. In Ru CMP, polishing stops when oxide, dielectric between electrodes, exposures while Ru is polished. The removal rate of Ru is under the control of an oxidizer added into slurry. The Pourbaix diagram of Ru shows that RuO2 and Ru2O5 exist when Ru oxidizes, and the removal rate of noble metal CMP depends on the degree of oxidization (Figure 6.4). However, in the real situation, there is no oxidizer that can secure the safety of slurry and strongly oxidize noble metal at the same time. Moreover, for successful Ru CMP, polishing selectivity of Ru:oxide should be considered with STI CMP processing. In this difficult situation, the reason for applying noble metal CMP is closely related to the electronic characteristics of a device. For example, Ru CMP makes it possible to produce a capacitor to have a higher capacitance than with dry etching because it loses less than dry etching and it has a clear pattern formation as in Figure 6.5. That is, the electronic characteristic can be improved when Ru CMP applies to a device process. In fact,

Ox. 7 6

8 pH

10

12

14

Figure 6.4 Electrochemical characterization of various oxidizers in Pourbaix diagram of Ru, obtained from Tafel plots and pH of the slurries.

(a)

(b)

Figure 6.5 SEM images after (a) Ru CMP and (b) Ru dry etching process.


154

Leakage Current (A)


1.E–08 1.E–09 1.E–10 1.E–11 1.E–12 1.E–13 1.E–14 1.E–15 1.E–16 1.E–17 1.E–18 1.E–19 –4

CMP Dry etching

–2

0 Voltage (V)

2

4

Leakage Current (fA)

Figure 6.6 Comparison of leakage current of RIR capacitors node separated by Ru CMP and Ru dry etching. 10 9 8 7 6 5 4 3 2 1 0

Positive leakage current Negative leakage current

CMP #1

CMP #2

CMP #3

D/E #1

D/E #2

D/E #3

Figure 6.7 Positive and negative leakage current of RIR capacitor at 1V and –1V.

when processing by dry etching, the leakage current is 6.537 fA at 1V. As shown in Figure 6.6 and Figure 6.7, the value is remarkably low when a device is processed by CMP. In addition, cell capacitance is 13.4 fF/cell; the CMP process makes it possible to get a much higher value than dry etching, which is 8.4 fF/cell. 6.2.2 Poly Si CMP for NAND Flash Memory 8 G NAND flash memory connects 32 cells in a sequence without source and drain contact each cell. Two transistors of SSL (source select line) and GSL (ground select line) are connected in a series between bit-line contact and CSL (common source line). Floating gate and control gate exist in each cell and is formed channel by controlling the voltage of control gate (Figure 6.8a). Electron that transfers this channel becomes tunneling to be accumulated at the control gate to be a role of memory. The state of stored electron at the floating gate through F-N tunneling is the program state.


155


100 nm

CG

ONO FG

Active Silicon

STI

200 nm

(a)

CG

FG

45 nm

Active Silicon

ONO

SA-STI 50 nm (b)

Figure 6.8 (a) Cross-sectional SEM image of a 90-nm NAND-flash memory-cell without CMP. (b) Cross-sectional TEM image of a sub-60 nm structure with interpoly ONO dielectrics.

Missing electron state is the erase. Programming and erasing are formed according to the size of Vth of cell transistor. So, the Vth of a device rises at programming time. The state of program/ erase can be confirmed through the difference of Vth. The augmentation of integration is easily achieved because the simplicity of the structure of NAND flash memory and scaling down are easy. Recently, the emergence of multilevel cell (MLC) makes to have a higher integration. This reduction of design rule might make it possible to be at least 40 nm. Because of the diminution of charge loss tolerance based on scaling down by word-line applied voltage with the decreasing of coupling ratio, interference of floating gate becomes a severe problem. Coupling ratio suddenly decreases at the 60 nm level. Formation processing of the existing floating gate and self-aligned CMP process, like Figure 6.8(b), are brought in because there is no space to increase the size of floating gate that can enlarge the coupling ratio.


156


With a method of forming floating gate into a 60-nm level device, when polysilicon CMP is used in connection with self-aligned STI process, the surface of floating gate can be extended like in Figure 6.8b. This leads to an increased coupling ratio. Polysilicon CMP is an absolutely necessary process for improving the capacity of flash memory. When slurry, which has high removal selectivity to polysilicon and oxide, makes progress CMP processing, polysilicon recess is occurred by dishing, which is CMP’s characteristics. Or electrical characteristics inside cells, including Vth, can become worse by thickness distribution of floating gate, which occurs by CMP non-uniformity. The voltage of floating gate is capacitance based on ONO (oxide–nitride–oxide) between control and floating gate. CTot(= CONO + CTunnel) is capacitance based on Tox and capacitance based on ONO is decided according to the voltage of control gate. To obtain a high coupling ratio, the value of ONO capacitance should be increased. Capacitance needs to maximize the selective surface above floating gate. But the width of floating gate, which is a factor for deciding a selective surface, is determined when the design rule was set. The height of the floating gate will be a key factor to determine the coupling ratio in the end. Furthermore, stored electron at the floating gate rapidly decreases in accordance with the decreasing of design rules. In case of SLC (single-level cell), electron loss less than 20% is allowed within the same range. In case of MLC, each program state has to have the same Vth range. To reduce the tolerance limit of electron loss per each state, control gate and capacitance of floating gate should be increased; however, scaling down of interpoly ONO ends its limit. Another problem is that the gap between cells becomes narrow according to the increasing of cell integration, and an interference phenomenon will arrive by capacitive coupling between floating gates. The transition of cell Vth by interference of floating gate brings up the Vth transition of around cell. So, when Vth changed in the phase of programmed one cell, Vth is changed due to the coupling phenomenon in which electrode is accumulated in floating gate by writing to the next cell. This change of Vth becomes a severe problem at the MLC action, which should keep the Vth gap between cells. Voltage of floating gate is influenced by control gate of around cell and floating gate, and is not only influenced by the voltage of control gate of the corresponding cell. As described earlier, by increasing integration, coupling ratio of floating gate, permitted possible charge loss, and Vth shift by capacitive coupling of intercells become problems. Especially, due to narrowing the space between bit line and word line, Vth shift of cell dramatically increases around 0.2 V to make higher Vth distribution through interference of floating gate between cells. To decrease this interference, the space between cells fills with low-k material or reduces the height of floating gate. At the same time, exact thickness control of floating gate should be needed.


157


Especially, the height of floating gate should be controlled through the CMP process because that greatly influences word-line and bit-line cells. To achieve the isolated poly floating gate, the polishing should be stopped at the oxide film. Therefore, the poly-to-oxide removal selectivity is the most important factor for the poly isolation CMP process. Poly isolation CMP without selectivity induces dishing and rugged topography on surfaces, which result in deterioration in the quality of interlayers in the device. The two steps of poly Si CMP are shown in Figure 6.9. The first step is to remove Si, then polishing at oxidize film is to be stopped in the second step. The polishing of Si needs an addition for accelaration polishing because it should be progressed over 2000 Å per minute. This additive is mainly a chemical compound that has an amine group and abrasives polish the Si film by the complex formation of Si surface and amine group. For the last step, lower the polishing rate of oxidized film to less than 100 Å/min for stopping polishing. The difference of hydrophobicity between poly Si and oxide film is the key factor to achieving the high removal selectivity in the poly isolation CMP process. As oxide film is more hydrophilic than silicon film, hydrophilic polymer is preferred to be adsorbed on the hydrophilic oxide film. By utilizing selective adsorption of hydrophilic polymer, the passivation layer formed on oxide film can prevent the direct contact of abrasive particles, which results in suppression of the removal rate of oxide film during poly isolation CMP process (Figure 6.10).

1

Oxide Deposition

4

Oxide Nitride Pad Oxide

Amorphous Si Deposition

in-situ PH3 doping, dose:1.5 × 1010 eal?

0.3 um

Amorphous-Si Deposition

150–200 nm 10–15 nm 0.5 um

Gap Fill Oxide

Si Substrate

Si Substrate

2

STI CMP Nitride Pad Oxide

5

Poly Isolation CMP

150–200 nm 10–15 nm

Gap Fill Oxide

Si Substrate

Nitride Strip with Phosphoric Acid

6

Forming of Poly Si by Annealing 910°C

Gap Fill Oxide

65 nm

Gap Fill Oxide

Si Substrate

3

300 nm

Gap Fill Oxide

Nitride Strip

Si Substrate

Pad Oxide

RTA: 15 sec N2

Floating Gate Gap Fill Oxide

85 nm

Si Substrate

Figure 6.9 (See color insert) Schematic process flow of the poly isolation CMP process.


158



300 nm

Gap Fill Oxide Si Substrate

85 nm


Figure 6.10 (See color insert) Mechanism for the poly isolation CMP process.

Intensity

Si 2p

108

106

104 102 100 Binding Energy (eV) (a)

98

96

Intensity

Si 2p

108

106

104 102 Binding Energy (eV) (b)

Figure 6.11 XPS spectrum of poly Si and oxide film at pH 10.


100

98


159

To investigate the surface structures of poly Si and the plasma-enhanced tetraethylorthosilicate (PETEOS) films, Si 2p XPS analysis for each film was conducted as shown in Figure 6.11. The Si2p spectra of poly Si film in Figure 6.11a shows two symmetrical profiles, of which binding energies correspond to 98.7 eV for Si and 102.5 eV for SiOH. Compared with the intensity of Si peak, that of SiOH is considerably low, which mean the surface structure of poly Si film consists of Si structure for the most part. On the other hand, as shown in Figure 6.11b, the spectrum observed from the PETEOS film was mainly separated into two symmetrical profiles. The binding energies observed from this result are 102.50 and 103.30 eV, which correspond to SiOH and SiO, respectively. The intensities of the two peaks are almost similar and this observation indicates that a respectable amount of siloxane group is present on the surface of PETEOS film. The difference originated from hydrophilic and hydrophobic characteristics is confirmed from contact angles of deionized (DI) water on each surface. The contact angle of DI water on poly Si film was 61.2° in the Kruss contact angle measurement system. On the other hand, DI water drop exhibited a low contact angle below 10°, thus spread out on the oxide wafer as shown in Figure 6.12. This result is coincided with the XPS result; that is, the surface of SiO2 is more hydrophilic than that of poly Si due to siloxane (≡Si–O–Si≡) bonding. Figure 6.13 shows the adsorption isotherms for PAM on poly Si and SiO2 as a function of PAM concentration. Adsorption of PAM on oxide surfaces increases and reaches a plateau level of approximately 0.23 mg/m2. However, PAM is scarcely adsorbed on poly Si surfaces. This is driven by the difference in hydrophobicity, which affects the interaction between PAM and each surface. At high pH, the negative site MO – of metal oxide (MO) surface bonds with the weakly acidic NH2 function. Therefore, the interaction between SiO – of SiO2 surface and NH2 group of PAM led to the selective adsorption of PAM on SiO2. 61.2°

8.71°

Figure 6.12 Contact angle of poly Si and oxide film at pH 10.


160


Adsorbed Amount of PAM (m2/g)

0.30 0.25 0.20 0.15

SiO2 poly Si

0.10 0.05 0.00

0.0

0.1

0.2 0.3 0.4 Residual Concentration (g/dL)

0.5

Figure 6.13 Adsorption isotherms of PAM on poly Si and oxide at pH 10.

Adhesive forces were measured to analyze the interaction between Si atomic force microscope (AFM) tips and the deposited films from the force-distance measurement with the AFM. The force-distance curve is expected to elucidate the adsorption behavior of PAM on the deposited films. In the force-distance measurement, there is no interaction until the tip is close enough to be attracted to the surface. As the tip approaches to the surface, it contacts with the surface. After the contact, the tip is retracted from the surface, the cantilever is bent, and a repulsive force (positive) is measured. When the tip is being retracted, an attractive force is measured (negative). When the critical force is reached, the tip is separate from the surface and this point is called the pull-off point. Therefore, the pull-off point, which corresponds to the point of the critical force, is determined by the degree of the adhesive force between the tip and the surface. The higher the adhesive force between the tips and the films, the lower the pull-off point. Figure 6.14a shows the force–distance curves of the tips and poly Si film at pH 10 as a function of the PAM concentration. In the absence of the absorbed PAM molecule, an adhesive force was observed at approximately 20 nm of separation distance. It is of interest that there is no significant difference between the surface forces of the tip and poly Si film even with the presence of PAM. This result is almost the same for all samples, irrespective of the concentration, which means that PAM is scarcely adsorbed on poly Si film. On the other hand, Figure 6.14b shows the force–distance curves of the tips and the oxide film at pH 10 as a function of the PAM concentration. In the absence of the absorbed PAM molecule, an adhesive force was observed at approximately 30 nm of separation distance. However, it was found that the adhesive force disappeared by the addition of PAM due


161


50 Poly Si at pH 10 in 10–4 M NaNO3 w/o PAM 0.005 wt% 0.01 wt% 0.06 wt%

40

Force (nN)

30 20 10 0 –10 –20 –30

20

0

40 Separation Distance (nm)

60

80

(a) 50 45

PETEOS at pH 10 in 10–4 M NaNO3 w/o PAM 0.005 wt% 0.01 wt% 0.06 wt%

40 35 Force (nN)

30 25 20 15 10 5 0 –5 –10

0

20

40 60 Separation Distance (nm)

80

100

(b) Figure 6.14 Force-distance curve between the AFM tip and the surface of wafer: (a) poly Si, (b) oxide.

to the interaction between the siloxane bonding of the oxide film and the amine group of PAM at pH 10. This result is more clearly observed as the concentration of PAM increases. Therefore, it is expected that the presence of PAM causes the suppressed removal rate of the PETEOS film by the formation of the passivation layer on the oxide film and the increase in the concentration of PAM leads to the decrease in the oxide removal rate.


162


3000 Poly Si PETEOS

Removal Rate (Å/min)

2500 2000 1500 100 80 60 40 20 0

0

0.005 0.01 PAM Concentration (%)

0.06

Figure 6.15 Removal rate of poly Si and oxide film.

The results of the CMP performance as a function of the concentration of PAM are shown in Figure 6.15. As the concentration of PAM in poly isolation CMP slurry increased, the slurry for poly isolation CMP process had a higher removal rate for the PETEOS film, reduced from 82 Å/min without PAM to 12 Å/min with 0.06 wt% of PAM. It is considered that this decrease in the removal rate of the PETEOS film as a function of the concentration of the PETEOS film is due to the formation of the polymercoated layer on the PETEOS film caused by the high affinity of PAM to the PETEOS film. From the adsorption isotherms shown in Figure 6.13, the PETEOS film has high affinity to PAM, which induces PAM to adsorb on the surface of the PETEOS film. The PAM layer formed on the PETEOS layer reduces the possibility of the penetration of the abrasive particles to the PETEOS film and also decrease the friction force between abrasive particles and the PETEOS film. On the other hand, the removal rate for poly Si film remained at 2190 Å/min without PAM and 2178 Å/min with 0.06 wt% of PAM. Compared with the decrease of the removal rate for the PETEOS film, the change of the removal rate for poly Si film is small enough to ignore. It is expected that PAM scarcely adsorbs on poly Si film due to the low affinity between them as shown in Figure 6.13. Therefore, the PAM layer on poly Si is not thick enough to prevent the penetration of the abrasive particles to poly Si film even though the concentration of PAM is increased. Therefore, it is expected that poly Si film is directly exposed to the mechanical polishing during the poly isolation CMP process and it results in the small change of the removal rate of poly Si film with addition of PAM. As a result, the difference in the removal mechanism of each film achieves the drastic improvement in poly-Si-to-oxide selectivity values from 26.7 to 181.8 as the concentration of PAM increases


163


from 0 to 0.06 wt%. Consequently, the formation of a polymer-coated layer by the selective adsorption of PAM on the PETEOS film plays a dominant role to improve poly-Si-to-oxide selectivity in poly isolation CMP. One can conclude that the control of selective adsorption of polymer regarding the characteristics of target films is a key technique to achieve poly-Si-tooxide selectivity in the poly isolation CMP process.

6.3 Novel CMP for New Memory Recently, flash memory—used in mobile phones, MP3s, digital cameras, and USBs—is a non-volatile memory device that solved a weak point of DRAM device of volatile movement. NAND flash memory in business today is possible up to 2 gigabyte in integrated diagram. It has a characteristic of action at high supply voltage of 10 to 15V. Flash memory device applies threshold voltage transition of transistor with memory motion theory to floating gate made by polysilicon through the accumulating or discharge of electric charge. With the interaction of flash memory device structures, unbalanced polysilicon grain-size distribution increases threshold voltage distribution. The movement above 10 V voltage generated from devices is increasing. The technical limit of integration is known as 16 gigabit level. Therefore, there is a need for the next-generation non-volatile memory devices that are several integrations over 64 gigabit with tens of nanosecond write/erase time (Figure 6.16). Research has progressed in the areas of phase-change random access memory (PRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), and so on (Figure 6.17). 6.3.1 GST CMP for PRAM Phase-change random access memory (PRAM) has been intensively studied as one of the candidates of a non-volatile memory to challenge conventional memories such as DRAM and flash memory, due to its fast Non-volatile

Flash

New Memory

Density Speed

SRAM

DRAM

Non-volatile High Speed High Density Low Power Consumption CMOS FET Compatibility

Figure 6.16 (See color insert) Comparison of new memory and conventional memory.


164


Baseline 2004 Technologies

PRAM

NFGM

PoRAM

ReRAM

Storage Mechanism

First Availability Device Types

2004 DRAM

2004 NOR Flash

~2006

>2006

>2010

~2010

OUM

Engineered Tunnel Barrier or Nanocrystal

Bistable Switch

MIM

Cell Elements

1T1C

1T

1T1R

1T

1T

1T1R

F Value

90 nm

90 nm

100 nm

80 nm

45 nm

65 nm

Cell Size

8F2 0.065 µm2

12.5F2 0.101 µm2

~6F2 0.06 µm2

~6F2 0.038 µm2

4F2 ~0.008 µm2[I]

6F2 0.025 µm2[C]

Write/Erase Time

50 ns

1us/1ms

1 year

>1 year

E/W Cycles

Infinite

>1E5

>1E13

>1E6

>1E15

>1E3

Figure 6.17 Classification of memory.

switching speed, good endurance, and compatibility with CMOS logic process. PRAM stores data according to the resistance change of chalcogenide (GeSbTe, GST) materials that is basically caused by the phase change of chalcogenide materials, and the phase change is followed by heat flux from the bottom electrode (BE) to contact dimension. Chalcogenide materials exhibit at least two states. The states are the amorphous and crystalline states, and transitions between these states may be selectively initiated. The amorphous state generally exhibits higher resistivity than the crystalline state. The phase change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter in response to temperature changes. In effect, each memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states. The phase change may be induced by resistive heating. As shown in Figure 6.18, PRAM manufacturing applies the CMP Ideal GST CMP Concept Key issue : Bulk GST removal rate = > 500A Process : Polish stop on oxide Selectivity : GST to Oxide = > 50 : 1

GST Oxide GST

Be

Be

CMP

Oxide

GST

Lower dishing/erosion Require a polisher having good uniformity Surface defect and scratch

Figure 6.18 Schematic drawing of GST CMP process for on-axis confined structure in PRAM device.



165

technique to planarize the GST layers deposited on the front surfaces of wafers. In particular, to scale down PRAM beyond 256 Mbit (design rule less than 100 nm), achieving the writing current level of several hundred uA is an essential parameter. Therefore, GST was on-axis confined within a small pore, which may result in high planarity of GST surface. The SiO2 film acts to isolate the adjacent cell with GST materials, and as a barrier that stops the polishing process immediately after complete removal of the GST materials. Besides, in the fabrication of PRAM beyond 256 Mb, the ring-shaped contact structure for small BEC formation is very important to process technologies. The writing current flows through the perimeter of the ring-shaped contact instead of the whole body of the contact. Obviously, the effective contact area of the ring-shaped contact has less dependency on the contact diameter because it is linearly proportional to the diameter of the defined contact. Thus the ring-shaped contact structure has robustness against the contact size variations. The CMP slurry needs to perform a high selectivity (>50:1) of polishing rate between GST and SiO2 films. CMP slurry is composed of colloidal silica abrasive, surfactant, organic chemical, alkaline agent, titrant, and deionized water to control the removal selectivity of GST-to-SiO2 films and TiN-to-SiO2. For CMP evaluation, 8-inch silicon wafers with a multilevel structure of NGST/SiO2/Si were used. The as-deposited NGST film had an amorphous structure. The NGST film was deposited using a metal organic precursor under a nitrogen atmosphere at 350°C, giving a composition of approximately 25:23:52 (Ge:Sb:Te) by atomic percentage, as shown by the cross-sectional TEM energy-dispersive x-ray spectroscopy (EDS) analysis results listed in Figure 6.19. The bottom oxide film was deposited by the PETEOS method at 720°C. The thicknesses of the as-deposited NGST and oxide films were 200 and 100 nm, respectively. The films were polished on a CMP system (6EC, Strasbaugh, USA.) with a single polishing head and a polishing platen. We used an industry-standard CMP polishing pad (IC1000/Suba IV, Rohm and Haas Electronic Materials, USA.). The thickness variation of the NGST films on the wafers before and after CMP was

Figure 6.19 TEM energy-dispersive x-ray spectroscopy (EDS) analysis results.


166


measured with a spectroscopic phase-modulated ellipsometer (UVISEL, HORIBA Jobin Yvon, Japan). The oxide film thickness before and after CMP was estimated with a tabletop film analysis system (Nanospec 180, Nanometrics, USA). The contact angle was measured with a contact angle meter (DIGIDROP, GBX, France). The chemical bonding characteristics of the NGST film surface after dipping in the slurry were characterized by x-ray photoelectron spectroscopy (XPS) using an ESCA 2000 (V.G. Microtech, UK) system with a monochromatic Al Kα x-ray monochromatic source (linewidths = 0.85 eV, energy = 1487 eV). Figure 6.20a shows the polishing rate of NGST film as a function of the tetramethylammonium hydroxide (TMAH) concentration. Without TMAH in the slurry, the polishing rate was 6 nm/min. With the TMAH addition, however, the NGST polishing rate drastically increased up to 242 nm/ min at a TMAH concentration of 0.12 wt%. This striking difference in the polishing rates with and without TMAH resulted from the chemical reactions between the NGST film and the TMAH, which we explain later in detail. Beyond a TMAH concentration of 0.12 wt%, however, the polishing rate of NGST slightly decreased. This behavior was related to the way that TMAH effectively influences chemical reactions at the NGST film surface, such as hydrophobic or hydrophilic interactions. The characteristics of the reaction of TMAH with the NGST film surface can be estimated from the surface tension by measuring the contact angle. In general, wettability can be quantitatively evaluated in terms of the spreading coefficient, which is the energy difference between the solid substrate and the contacting liquid phase. The interaction of the interfacial tensions at the liquid–vapor– solid junction is described by the Young equation as follows: cosθ =

rSV − rSL rLV

(6.1)

where θ is contact angle (θ > 0°), and rSV, rSL, and rLV are the effective interfacial tensions. After dipping the NGST film in the slurry for 1 min at 45°C, the contact angle of the NGST film surface was measured as a function of the TMAH concentration, as shown in Figure 6.20b. The contact angle decreased drastically with increasing TMAH concentration up to 0.12 wt% and then gradually increased. The contact angle results shown in Figure 6.20b coincided with the inverse of the NGST film polishing rate curve in Figure 6.20a. The hydrophilicity indicated by a small contact angle means that adhesion of TMAH molecules on the NGST film surface, more so than cohesion, plays a dominant role in enhancing the impact probability of molecules for the chemical reaction to etch the oxidized surface of the NGST film. The enhanced impact probability results in an accelerating chemical and mechanical reaction speed between the colloidal silica abrasives and



167

(a)

(b) Figure 6.20 (a) Polishing rate of NGST film as a function of the TMAH concentration, (b) contact angle of the NGST film surface.

the NGST film surface during CMP. As a result, a slurry with enhanced hydrophilicity initially produces a higher polishing rate. Note that TMAH molecules initially etch off the oxidized surface of the as-deposited NGST film, and the exposed, unoxidized NGST surface is then chemically oxidized, resulting in a hydrophilic surface. The hydrophilicity of the NGST film surface, however, becomes progressively lower once the TMAH concentration exceeds a specific value (0~0.12 wt% in this experiment). This


168


is probably associated with the formation of a polymer layer enhanced by excessive TMAH molecules on the NGST film surface, making the surface less hydrophilic and suppressing the direct mechanical contact between the colloidal silica abrasives and the unoxidized NGST film surface. As a result, the polishing rate of NGST film decreases with increasing contact angle. These results for NGST film CMP—namely, the relation between the polishing rate and contact angle—are the same as those that we previously reported for polysilicon CMP. Therefore, this study has provided key information on using TMAH in colloidal silica slurry to obtain a high polishing rate of NGST film during CMP. We conducted an additional dipping test to confirm the validity of the contact-angle mechanism of NGST film CMP. The as-deposited NGST film was dipped into the slurry for one minute at 45°C. After dipping, the chemical composition of the NGST film surface was characterized by XPS, which is one of the best ways to examine the chemical binding characteristics of film surfaces and further explore the chemical reaction between TMAH and the NGST surface. Figure 6.21a shows the XPS spectra for Ge 2p. Before dipping, there was a strong GeO2 peak at 1219.8 eV; after dipping, this peak was weakened. Thus, TMAH is a strong etchant of GeO2 on the NGST film surface. Figure 6.21b shows the XPS spectra for Sb 3d. The Sb 3d3/2 peaks for Sb2O5 and metallic Sb bonding occurred at 539.8 eV and 537–538 eV, respectively. The Sb 3d5/2 peaks for Sb2O5 and metallic Sb bonding occurred at 530.4 eV and 529–530 eV, respectively. Here, Sb metallic bonding refers to Sb–Te or Sb–Ge bonds and the formation of Sb clusters in the film. Before dipping, the peak position for Sb was between the Sb homopolar and metallic bonds, so there could be equivalent numbers of Sb homopolar and Sb–Te or Sb–Ge bonds in the amorphous NGST film. After dipping, the intensities of the Sb 3d3/2 and Sb 3d5/2 peaks for Sb2O5 decreased significantly. This indicates that Sb2O5 was easily etched by the TMAH-based slurry. In the case of tellurium oxide, the Te 3d5/2 peaks for Te metallic bonding and Te oxide bonding occurred at 572.5–574 eV and 576–577 eV, respectively. The Te 3d3/2 peaks for Te metallic bonding and Te oxide bonding occurred at 583–584 eV and 586–587 eV, respectively. As shown in Figure 6.21c, there was no significant difference in the XPS spectra for the Te 3d peaks before and after dipping. This indicates that Te oxide bonding is stronger than the oxide bonding of Ge and Sb. The results suggest a possible CMP mechanism for NGST film. The TMAH initially etches off the oxidized film surface (particularly GeO2 and Sb2O5), and the colloidal silica abrasives then directly contact the unoxidized NGST film surface to perform mechanical polishing. In addition, hardness measurement of the NGST film showed that its hardness (3.2 GPa) was approximately three times smaller than that of SiO2 film (9 GPa). As a result, the colloidal silica abrasives in the TMAH-based slurry significantly enhance the polishing rate of NGST film by etching off the oxidized surface and applying direct mechanical polishing to the soft NGST film surface.


169


7000

Intensity (a.u.)

6000

Before dipping After dipping

5000 4000 3000 2000 1000 0 1225

1220

1215

1210

Binding energy (eV) (a)

7000

Intensity (a.u.)

6000 5000 4000 3000 2000 1000 0 545

540

535

530

525

Binding energy (eV) (b)

7000

Intensity (a.u.)

6000 5000 4000 3000 2000 1000 0 595

590

585

580

575

570

565

Binding energy (eV) (c)

Figure 6.21 The XPS spectra of NGST film for (a) Ge 2p, (b) Sb 3d, and (c) Te 3d.


170


Figure 6.22 The structure of ReRAM.

6.3.2 Novel CMP for ReRAM ReRAM can produce a device by 1T/1R or 1R structure (Figure 6.22). In the case of producing by 1T1R structure, after deposition of a resistance change material except for CMP for STI, the CMP process is considered. ReRam is not sure about its effect regarding contact-area dimension like PRAM. If it is not produced by extremely confined structure, the use of CMP process depends on the processing choice. Recently, in the new ReRAM non-volatile memory, a nickel oxide film with titanium (Ti:NiO) was doped to increase voltage for memory erasures. Operations required only 5 ns, about 10,000 times faster than before, and with resistance fluctuations reduced to 1/10 that of conventional ReRAMs. Optimizing the voltage applied to a transistor reduced the current need to erase memory to ≤100 μA. The prototype ReRAM device offers low fluctuation of resistance value even during high-speed operation. The ReRAM technology “is amenable to miniaturization and can be manufactured inexpensively,” so it is seen as an alternative to flash, the company explained. “If further minute non-volatile memory can be realized using ReRAM, there is potential for higher performance of mobile devices.”


Insert Film

Carrier

Wafer Polishing Pad Platen

Slurry Figure 1.5 CMP process of manufacturing.

PETEO

PETEO

2 Ti Al-0.5%Cu T

0.25 µm 0.75 µm 0.25 µm 0.8 µm

Si

PETEO

CMP

Before ILD CMP

PETEO

Ti Al-0.5%Cu T

1.3 µm 0.25 µm 0.75 µm 0.25 µm 0.8 µm

Si After ILD CMP

Figure 2.1 Schematic of ILD CMP process.

Figure 2.7 Analysis of remaining silica particles (particle size > 0.189µm) on silicon wafers after post CMP cleaning: (left) modified slurry, (right) nonmodified slurry.


ILD Thickness (Normalized)

1.1 1.05 1 0.95

ER

AF W

0.9

FL

AT

0.85 0.8 40

30 Y

20 10 0

0

10

20

30

40

X

Figure 2.16 Wafer level variation for tool A.


1.1 1.05 1 0.95 0.9 0.85 0.8 40

30 Y

20 10 0

Figure 2.17 Wafer level variation for tool B.


0

LAT ER F WAF 20 X 10

30

40


0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4

20

15 Y

10

5

0

0

5

10

X

15

20

25

Figure 2.18 Die variation for tool A.


0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4

20

15 Y

10

5

Figure 2.19 Die variation for tool B.


0

0

5

10

15 X

20

25

~0.8 mm

PETEOS or HDP

PETEOS or HDP

150–200 nm 10–15 nm 0.5 mm

10–15 nm

Si WAFER

Si WAFER

STI CMP

Nitride Thickness e.g. 100±10 nm

Nitride Target

SiO2

Oxide Thickness e.g. 400±40 nm

Oxide

Si

Si Active

Active

Isolation

Isolation

Figure 3.1 STI CMP process.

Gate Source

Drain

Leff

Leff

Reduction

Id

Vth

Vth

Figure 3.2 The effect of overpolishing on the characteristics of the device: (top) the decrease of gate length by overpolishing; (bottom) the shift of threshold voltage in the device.


Cubic 200

A

111

A

022

Cubic 111 200 022

30 nm 100 nm Cubic B

220

B

111

Hexagonal 110

30 nm

001

100 nm Cubic C

002 111

C

220

Hexagonal 1–10

30 nm 001

100 nm

Figure 3.6 TEM images and nano beam diffraction.


1–15

1 um

205 nm

658 nm

1 um 173 nm

626 nm

(b) Slurry A_large (Mw 30K)

(a) Before CMP

1 um

1 um

193 nm

204 nm

646 nm

(c) Slurry B_large (Mw 50K)

657 nm

(d) Slurry C_large (Mw 90K)

1 um

137 nm

590 nm

(e) Slurry D_small (Mw 30K) Figure 3.28 Pre- and post-CMP cross-sectional SEM micrographs: (a) pre-CMP, (b) slurry A_large (Mw 30K), (c) slurry B_large (Mw 50K), (c) slurry C_large (Mw 90K), and (d) slurry D_small (Mw 30K).


nm 4

nm 4 nm 4 3 2 1 0

3

RMS 0.280 nm

3

750

2

2 500

nm

1

250 250

0 0

0

500 nm

750

1000

RMS 0.334 nm

nm 4 3 2 1 0 750 500 nm

1

0 0

0

(a) Slurry A_large (Mw 30K) nm 4

3

2

3

2 500

nm

250 250

0 0

0

750

1000

nm 4

750

1

250

500 nm

(b) Slurry B_large (Mw 50K)

RMS 0.355 nm

nm 4 3 2 1 0

250

500 nm

750

750 500

1000 1

0

(c) Slurry C_large (Mw 90K)

RMS 0.288 nm

nm 4 3 2 1 0

nm

250 0 0

250

500 nm

750

1000

(d) Slurry D_small (Mw 30K)

Figure 3.30 Post-CMP three-dimensional AFM micrographs of patterned wafers: (a) slurry A_large (Mw 30K), (b) slurry B_large (Mw 50K), (c) slurry C_large (Mw 90K), and (d) slurry D_small (Mw 30K).

1st Step Key action : bulk Cu planarization/removal Process : polish stop on barrier Selectivity : Cu to Ta/TaN > 100:1 Cu polishing rate > 10000 [Å/min]

Cu Ta or TaN

Ta or TaN

SiO2 /low-k 1st Step CMP Cu SiO2 /low-k

2nd Step Key action : barier metal removal & dielectric polishing Process : barrier/dielectric polished with same removal rate Selectivity : Cu : TaN : Low-k = ~ 1 : 1 : 1 (500–1000 [Å/min] from Memory Makers)

2nd Step CMP Ta or TaN

Cu SiO2/ low-k

1. Lower dishing/erosion 2. Require a polisher having good uniformity 3. Less low-k damage

Figure 4.2 Two-step process of Cu CMP.


Ec vs. Ag/AgCl

0.5

0.0

–0.5

–1.0 –10

0.5

Ec vs. Ag/AgCl

0.5 wt% Alanine 1.0 wt% Alanine 1.5 wt% Alanine 2.0 wt% Alanine

–8

–6 –4 10x (A/cm2) (a)

–2

0

–2

0

1.5 wt% Alanine w/o PAM 1.5 wt% Alanine w/ PAM

0.0

–0.5

–1.0 –10

–8

–6 –4 10x (A/cm2) (b)

Figure 4.10 Potentiodynamic polarization: (a) various alanine concentration, (b) 1.5 wt% alanine with and without PAM.


+500 Å 20 to 80 (nm) Oxide Film 0.2 to 20 (mm)

Silicon

–500 Å Figure 5.1 Illustration of wafer nanotopography.

PSD (log scale)

Wafer Touch Polishing Micro-roughness

Wafer Stock-removal Polishing

Haze

Nano-topography

1 um

100 um

10 um AFM AFM 10 um

100 nm Measurement LST haze Tools 1 um 5 um

5 um

1 mm

10 mm Wave Length

Nano-mapper 0.2 mm 20 mm Chapman

1 mm

PSD = Power Spectral Density LST = Light Scattering Topography (e.g. KLA-Tencor SP1) Figure 5.3 Topology map of wafer surface.


Oxide Silicon Nanotopography Length 2 mm (for example)

“Soft” Pad CMP Process

CMP

“Stiff” (“Hard”) Pad CMP Process

Pad

Pad

Pad conforms around nanotopography variations and polishes uniformly

Pad “bridges” across nanotopography down areas and preferentially thins surface films in raised nanotopography areas

Figure 5.4 Basic concepts of soft and hard polishing pads.

Wax Mount

Wafer Mounting

Deformed Wafer

After Polish

Wafer Demount Wafer

Free Mount

Wax Free mounting pad

Wafer Mounting

After Polish Both sides of the wafer are polished while the wafer is in a nearly free state

Wafer Demount

Retaining ring Polish carrier

Wafer Polishing pad

Figure 5.6 A comparison of SSP and DSP mounting techniques and how these affect nanotopography and flatness.


Figure 5.7 Nanotopography map for a wafer.

45 nm

(a)

Wafer Nanotopography PV

Poly-silicon Thickness PV

10 mm

30.1 nm

(b)

59.9 nm

(c)

Figure 5.21 Schematic structures of a 63-nm NAND-flash memory-cell with different floating-gate heights, induced by the wafer nanotopography of 10-mm-diameter scanning: (a) 45-nm height (free of wafer nanotopography influence); (b) 30.1-nm height (at the top of wafer nanotopography influence); (c) 59.9-nm height (at the bottom of nanotopography influence).


Vcc

Vcc Vpass Vpgm

#4

#7

GND

#8

#1

#2

#5

#6

#3

Vpass

#9

(a)

BL1 #1

BL2 #2

F-gate

BL3 #3

C-gate WL1

CyFG2-yFG5 #4

F-gate

#5

CxFG4-xFG5 PGM cell CxFG5-xFG6

#6

CyFG5-yFG8 #7

#8

F-gate

F-gate

WL2 C-gate

#9

WL3

CFGCG : cap. between f-gate and c-gate (b) Figure 5.22 Programming operation of a NAND-flash memory-cell, where the programming cell is No. 5: (a) voltage bias conditions for memory cells and (b) parasitic capacitances during No. 5 cell programming.


1

Oxide Deposition

4

Oxide


in-situ PH3 doping, dose:1.5 × 1010 eal?

0.3 um

Nitride Pad Oxide

Amorphous-Si Deposition

150–200 nm 10–15 nm 0.5 um

Gap Fill Oxide

Si Substrate

Si Substrate

2

STI CMP

5

Nitride Pad Oxide

Poly Isolation CMP

150–200 nm 10–15 nm

Gap Fill Oxide

Si Substrate

Nitride Strip with Phosphoric Acid

6

Forming of Poly Si by Annealing 910°C

Gap Fill Oxide

65 nm

Gap Fill Oxide

Si Substrate

3

300 nm

Gap Fill Oxide

RTA: 15 sec N2

Nitride Strip

Floating Gate Gap Fill Oxide

Pad Oxide

85 nm

Si Substrate

Si Substrate

Figure 6.9 Schematic process flow of the poly isolation CMP process.

Amorphous Si Deposition Gap Fill Oxide Si Substrate

300 nm


Figure 6.10 Mechanism for the poly isolation CMP process.


85 nm

Non-volatile

Flash

New Memory

Density Speed

SRAM

DRAM

Non-volatile High Speed High Density Low Power Consumption CMOS FET Compatibility

Figure 6.16 Comparison of new memory and conventional memory.


References Ali, I., et al., Solid-State Technol., October 1994. America, W. G., and S. V. Babu, Electrochem. Solid-Atate Lett., 7, G327, 2004. Baraban, P., V. V. Bulavinov, and P. P. Konorov, Electronics of SiO2 Layers on Silicon, Izd. LGU, Leningrad, 1988. Basim, G. B., and B. M. Boudgil, J. Colloid Interface Sci., 256, 137, 2002. Beecroft, L., and C. K. Ober, Chem. Mater., 9, 1302, 1997. Billmeyer, F. W., Textbook of Polymer Science, Wiley Interscience, New York, 1984, p. 7. Bohmer, M. R., O. A. Evers, and J. M. H. M. Scheutjens, Macromolecules, 23, 2288, 1990. Boning, D., MRS Bull. B., 27, 761, 2002. Boning, D., and B. Lee, MRS Bull., 27, 761, 2002. Boning, D., B. Lee, W. Baylies, N. Poduje, P. Hester, J. Valley, and C. Koliopoulos, International CMP Symposium, Tokyo, 2000. Boning, D., B. Lee, C. Oji, D. Ouma, T. Park, T. Smith, and T. Tugbawa, Pattern dependent modeling for CMP optimization and control, Proc. Symposium P: Chemical Mechanical Polishing (MRS Spring Meeting), San Francisco, CA, 1999, p. 761. Boning, D. S., and O. Ouma, Chemical mechanical polishing in silicon processing, in Semiconductors and Semimetals, Vol. 63, Academic Press, 2000, chap. 4, p. 108. Bonner, B. A., A. Iyer, D. Kumar, T. H. Osterheld, A. S. Nickles, and D. Flynn, Development of a direct polish process for shallow trench isolation modules, CMP-MIC Spring Meeting, Proc. Symposium: Chemical Mechanical Planarization for ULSI Multilevel Interconnection, 2001, p. 572. Boyd, J. M., and J. P. Ellul, J. Electrochem. Soc., 143, 3718, 1996. Burke, P., VMIC, pp. 379–384, 1991. Cardinaud, C. H., G. Lemperiere, M. C. Peignon, and P. Y. Jouan, App. Surf. Sci., 68, 595, 1993. Carter, P. W., and T. P. Johns, Electrochem. Solid-State Lett., 8, G221, 2005. Chang, E., et al., IEDM Tech. Digest, pp. 499–502, 1995. Chekina, G., and L. M. Keer, J. Electrochem. Soc., 145, 2100, 1998. Cheng, J. Y., T. F. Lei, T. S. Chao, D. L. W. Yen, B. J. Jin, and C. J. Lin, J. Electrochem. Soc., 144, 315, 1997. Cheng, J. Y., T. F. Lei, and T. S. Chao, Jpn. J. Appl. Phys., 36, 1319, 1997. Cho, C. W., S. K. Kim, U. Paik, J. G. Park, and W. M. Sigmund, J. Mater. Res., 21, 473, 2006. Choibowski, S., and M. Wisniewska, Colloids Surf. A, 208, 131, 2002. Clark, M. G., Proc. of IEE Circuits Devices Syst., 141, 3, 1994. Clear, S. C., and P. F. Nealey, J. Colloid Interf. Sci., 213, 238, 1999. Contolini, R. J., Bernhardt, A. F, and Mayer, S. T. J. Electrochem. Soc., 141, 2503, 1994. Cook, L. M., J. Non-Cryst. Solids, 120, 152, 1990. Cooperman, S. S., A. I. Nasr, and G. J. Grula, J. Electrochem. Soc., 142, 3180, 1995.

171 © 2009 by Taylor & Francis Group, LLC

172

References

Coppetta, J., C. Rogers, A. Phillipossian, and F. Kaufman, Proc. 2nd CMP-MIC, 307, 1997. Cross, L. E., Ferroelectrics, 76, 241, 1987. De Angelis, C., Rizzo, S. Contarini, and S. P. Howlett, App. Surf. Sci., 51, 177, 1991. Depasse, J., and A. Watillon, J. Colloid and Interface. Sci., 33, 430, 1970. Divecha, R., et al., Proc. of the 1st IEEE International Workshop on Statistical Metrology, June 1996. Djuricic, B., S. Pickering, J. Eur. Ceram. Soc., 19, 1925, 1999. Fierro, J. L. G., S. Mendioroz, and A. M. Olivan, J. Colloid Interface Sci., 100, 303, 1984. Fukuda, T., Y. Shimizu, M. Yoshise, M. Hashimoto, and T. Kumagai, Proc. 3rd Int. Symp. Advanced Science and Technology of Silicon Materials, The Japan Society for the Promotion of Science, 2000, p. 382, Kona, Hawaii. Gorantla, V. R. K., Babel, A., Pandija, S., and Babu, S. V. Electrochem. Solid-State Lett., 8, G131, 2005. Hackley, V. A., J. Am. Ceram. Soc., 80, 2315, 1997. Hackley, V. A., and S. G. Malghan, J. Mater. Sci., 29, 4420, 1994. Healy, T. W., in The Colloid Chemistry of Silica, H. E. Bergna, Ed., American Chemical Society, Washington, DC, 1994, p. 147. Hernandez, J., P. Wrschka, Y. Hsu, T.-S. Kuan, G. S. Oehrlein, H. J. Sun, D. A. Hansen, J. King, and M. A. Fury, J. Electochem. Soc., 146(12), 4647, 1999. Hetherington, D., et al., CMP-MIC, pp. 74–81, 1996. Hiemenz, P. C., and R. Rajagopalan, Principles of Colloid and Surface Chemistry, Marcel Dekker, New York, 1997, chap. 13, pp. 585–592. Hirai, K., H. Ohtsuki, T. Ashizawa, and Y. Kurata, High performance CMP slurry for STI, Hitachi Chemical Tech. Report No. 35, 17, 2000. Hisamune, Y. S., K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, IEDM Tech. Dig., 19, 1993. Homma, Y., T. Furusawa, H. Morishima, and H. Sato, Solid-State Electron., 41, 1005, 1997. Horiike, Y., H. Sakaue, H. Shindo, and S. Shingubara, JKPS, 26, S75, 1993. Horn, R. G., J. Am. Ceram. Soc., 73, 1117, 1990. Hoshino, T., Y. Kurata, Y. Terasaki, and K. Susa, J. Non-Cryst. Solids, 283, 129, 2001. Hu, Y. Z., R. J. Gutmann, and T. P. Chow, J. Electrochem. Soc., 145, 3919, 1998. Hunter, R. J., Introduction to Modern Colloid Science, Oxford University Press, New York, 1993, chap. 1, p. 204. Hussein, G. A. M., J. Anal. Appl. Pyrolysis, 37, 111, 1996. Iler, R. K., The Chemistry of Silica, John Wiley & Sons, New York, 1979. Itoh, A., M. Imai, and Y. Arimoto, Jpn. J. Appl. Phys., 37, 1697, 1998. Israelachvili, J. N., Intermolecular and Surface Forces, Academic Press, San Diego, CA, 1987. Kang, H. G., T. Katoh, W. M. Lee, U. Paik, and J. G. Park, Jpn. J. App. Phys., 43, L1, 2004. Kang, H. G., T. Katoh, H. S. Park, U. Paik, and J. G. Park, Jpn. J. App. Phys., 43, L365, 2004. Kang, H. G., T. Katoh, H. S. Park, U. Paik, and J. G. Park, Jpn. J. App. Phys., 44, 4752, 2006. Katoh, T., H. G. Kang, U. Paik, and J. G. Park, Jpn. J. App. Phys., 42, 1150, 2003. Katoh, T., M. S. Kim, U. Paik, and J. G. Park, Jpn. J. Appl. Phys., 43, L217, 2004. Katoh, T., S. J. Kim, U. Paik, and J. G. Park, Jpn. J. Appl. Phys., 42, 5430, 2003.


References

173

Katoh, T., B. G. Ko, J. H. Park, H. C. Yoo, J. G. Park, and U. G. Paik, J. Korean Phys. Soc., 40, 180, 2002. Katoh, T., J. G. Park, W. M. Lee, H. Jeon, U. Paik, and H. Suga, Jpn. J. Appl. Phys., 41, L443, 2002. Kaufman, F. B., D. B. Thomson, R. E. Broadie, M. A. Jaso, W. L. Guthriem, D. J. Pearson, and M. B. Small, J. Electrochem. Soc., 138(11), 3460, 1991. Kim, D. C., W. C. Shin, J. D. Lee, J. H. Shin, J. H. Lee, S. H. Hur, I. H. Baik, et al., IEDM Tech. Dig., 919, 2002. Kim, D. H., H. G. Kang, S. K. Kim, U. Paik, and J. G. Park, Jpn. J. App. Phys., 45, 4893, 2006. Kim, J. P., Y. S. Jung, J. G. Yeo, U. Paik, J. G. Park, and V. A. Hackley, J. Kor. Phys. Soc., 39, 197, 2001. Kim, J. P., U. Paik, Y. G. Jung, T. Katoh, and J.-G. Park, Jpn. J. Appl. Phys., 41, 4509, 2002. Kim, J. Y., S. K. Kim, U. Paik, T. Katoh, and J. G. Park, J. Korean Phys. Soc., 41, 413, 2002. Kim, K., IEDM Tech. Dig., 13.5, 2005. Kim, S. D., I. S. Hwang, and H. M. Park, J. Vac. Sci. Technol. B, 20, 918, 2002. Kim, S. K., S. Lee, U. Paik, T. Katoh, and J. G. Park, J. Mater. Res., 18, 2163, 2003. Kim, S. K., S. Lee, U. Paik, T. Katoh, and J. G. Park, Jpn. J. App. Phys., 43, 7427, 2004. Kim, S. K., U. Paik, S. G. Oh, T. Katoh, and J. G. Park, Jpn. J. Appl. Phys., 42, 1227, 2003. Kim, T., J. Kim, and J. Om, JKPS, 35, S861, 1999. Koh, C.-G., I.-S. Yeo, S.-H. Pyi, and S.-K. Lee, JKPS, 35, S1038, 1999. Kubo, N., in Handotai heitanka CMP gijyutsu (CMP technology for semiconductor planarization), T. Doi, T. Kasai, T. Nakagawa, Eds., Kougyo-chosakai, Tokyo, 1998, p. 124. Laparra, O., and M. Weling, Proc. Int. Symp. Chemical Mechanical Planarization II, San Diego, 1998, Electrochemical Society, Pennington, 1998, p. 98. Lee, B., Impact of Nanotopography on STI CMP in Future Technologies, PhD thesis, Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts, 2002. Lee, B., D. Boning, W. Baylies, N. Poduje, P. Hester, Y. Xia, J. Valley, et al., Materials Research Society (MRS) Spring Meeting, San Francisco, CA, April 2001. Lee, B., T. Gan, D. Boning, P. Hester, N. Poduje, and W. Baylies, in Advanced Semiconductor Manufacturing Conference, Boston, MA, Sept. 2000, p. 425. Lee, J. D., S. H. Hur, and J. D. Choi, IEEE Electron Device Lett., 23, 5, 2002. Lee, L. T., and P. Somasundaran, Langmuir, 5, 854, 1989. Lee, S. H., Z. Lu, S.V. Babu, and E. Matijevi, J. Mater. Res., 17, 2744, 2002. Lenzlinger, M., and E. H. Snow, J. Appl. Phys., 40, 278, 1969. Lewis, J. A., J. Am. Ceram. Soc., 83, 2341, 2000. Li, S. H., and R. O. Miller, Chemical Mechanical Polishing in Silicon Processing, Academic Press, New York, 2000, p. 142. Lin, C. F., W. T. Tseng, and M. S. Feng, J. Electrochem. Soc., 146(5), 1984, 1999. Lin, C. F., W. T. Tseng, M. S. Feng, and Y. L. Wang, Thin Solid Films, 347, 248, 1999. Luo, J., and D. A. Dornfeld, IEEE Trans. Semiconductor Manufacturing, 16, 469, 2003. Maca, K., M. Trunec, and J. Cihlar, Ceram. Int., 28, 337, 2002. Mahanty, J., and B.W. Ninham, Dispersion Forces, Academic Press, New York, 1979. McCormick, P. G., T. Tsuzuki, J. S. Robinson, and J. Ding, Adv. Mater., 13, 1008, 2001. Milonijic, S. K., Colloids Surf., 63, 113, 1992.


174

References

Muller, T., R. Kumpe, H. A. Gerber, R. Schmolke, F. Passek, and P. Wagner, Microelectronic Eng., 56, 123, 2001. Nojo, H., M. Kodera, and K. Nakata, IEEE, 96, 349, 1996. Otsuga, K., H. Kurata, S. Node, Y. Sasago, T. Arigane, T. Kawamura, and T. Kobayashi, IEICE Trans. Electron., E90-C 4, 2007. Ouma, D., C. Oji, D. Boning and J. Chung, Proc. CMP-MIC Conf. IMIC, 1998, p. 20. Oya, A., F. Beguin, K. Fujita, and R. Benoit, J. Mater. Sci., 31, 4609, 1996. Paik, U., V. A. Hackley, S. C. Choi, and Y. G. Jung, Coll. Surf., A135, 77, 1998. Paik, U., V. A. Hackley, J. Lee, and S. Lee, J. Mater. Res., 18, 1266, 2005. Paik, U., V. A. Hackley, and H. W. Lee, J. Am. Ceram. Soc., 82, 833, 1999. Paik, U., J. P. Kim, T. W. Lee, Y. G. Jung, J. G. Park, and V. A. Hackley, J. Kor. Phys. Soc., 39, 201, 2001. Palla, B. J., and D. O. Shah, IEEE/CPMT Intl. Electronics Manufacturing Technology Symposium, 1999. Palla, B. J., and D. O. Shah, J. Coll. Inter. Sci., 223, 102, 2000. Park, H. S., K. B. Kim, C. K. Hong, U. I. Chung, and M. Y. Lee, Jpn. J. Appl. Phys., 37, 5849, 1998. Park, J. G., T. Katoh, W. M. Lee, H. Jeon, and U. Paik, Jpn. J. Appl. Phys., 42, 5420, 2003. Park, J. G., T. Katoh, H. C. Yoo, D. H. Lee, and U. Paik, Jpn. J. App. Phys., 41, L17, 2002. Park, J. G., T. Katoh, H. C. Yoo, and U. G. Paik, Proc. 5th Int. Symp. Chemical Mechanical Polishing (201st Meeting of the Electrochemical Society, Philadelphia, PA), 2002, p. 202. Park, J. G., T. Katoh, H. C. Yoo and J. H. Park, Jpn. J. Appl. Phys., 40, L857, 2001. Park, J. G., T. Katoh, H. C. Yoo, and J. H. Park, Jpn. J. Appl. Phys., 40, L857, 2001. Park, J. H., S. H. Hur, J. H. Lee, J. T. Park, J. S. Sel, J. W. Kim, S. B. Song, et al., IEDM Tech. Dig., 873, 2004. Pavan, P., R. Bez, P. Olivo, and E. Zanoni, Proc. of IEEE, 85, 1248, 1997. Philipossian, A., and M. Hanazono, Tribology and fluid dynamics characterization of cerium oxide slurries, www.innovative-planarization.com, 2001. Preston, F. W., J. Soc. Glass Technol., 120, 214, 1927. Pye, J. T., H. W. Fry, and W. J. Schaffer, Solid State Tech., December, 65, 1995. Quirk, M., and J. Serda, Semiconductor Manufacturing Technology, Prentice Hall, New Jersey, 2001, chap. 9, p. 199. Raghavan, S. R., H. J. Walls, and S. A. Khan, Langmuir, 16, 7920, 2000. Rajan, K., R. Singh, J. Adler, U. Mahajan, Y. Rabinovich, B. Moudgil, Thin Solid Films, 308-309, 529, 1997. Ravi, K. V., Wafer flatness requirements for future technology, Future Fab International, Summer 1999. Reed, J. S., Principles of Ceramics Processing, 2nd ed., Wiley Interscience, New York, 1995, chap. 17, p. 323. Rozman, M., and M. Drofenik, J. Am. Ceram. Soc., 81, 1757, 1998. Russel, W. B., J. Rheol., 24, 287, 1980. Scheutjens, J. M., and G. J. Fleer, J. Phys. Chem., 83, 1619, 1979. SEMI Document M43: Guide for Reporting Wafer Nanotopography, 2001. SEMI Draft Document 3089: A Guide for Reporting Wafer Nanotopography, 1999. Semiconductor Industry Association. Front end processes in international technology roadmap for semiconductor, p. 4. Semiconductor Industry Association. Process integration, devices, and structures in international technology roadmap for semiconductor, p. 23, 2006.


References

175

Seo, Y. J., and W. S. Lee, J. Korean Phys. Soc., 48, 1651, 2006. Seo, Y. J., S. W. Park, C. B. Kim, S. Y. Kim, W. S. Lee and J. S. Park, J. Korean Phys. Soc., 42, 421, 2003. Shen, Q., D. Mu, L. W. Yu, and L. Chen, J. Col. Inter. Sci., 275, 30, 2004. Singh, R. K., S.-M. Lee, K.-S. Choi, G. B. Basim, W. Choi, Z. Chen, and B. M. Moudgil, J. Mater. Res. Bull., 27, 752, 2002. Sivaram, S., H. Bath, R. Legegett, A. Maury, K. Monning, and R. Tolles, Solid State Tech., 35-5, 87, 1992. Sivaram, S., H. Bath, R. Legegett, A. Maury, K. Monning, and R. Tolles, Solid State Tech, 97, May 1992. Sjöberg, S., J. Non-crystalline Solids, 196, 51, 1996. Smekaiin, K., Solid State Tech., 40, 187, 1997. Steigerwald, J. M., S. P. Murarka, and R. J. Gutmann, Chemical Mechanical Planarization of Microelectronic Materials, Wiley Interscience, New Jersey, 1997, p. 141. Steigerwald, J. M., R. Zirpoli, S. P. Muraka, and R. J. Gutmann, J. Electrochem. Soc., 142(10), 2841, Oct. 1994. Stine, B., D. S. Boning, J. E. Chung, IEEE Trans. Semiconductor Manuf., 10, 24, 1997. Stine, B., D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherrington, I. Ali, et al., A closed-form analytic model for ILD thickness variation in CMP processes, Proc. CMP-MIC Conf., Santa Clara, CA, Feb. 1997. Sze, S. M., and K. Ng, Physics of Semiconductor Devices, 3rd ed., Wiley Interscience, Hoboken, NJ, 2007. Tamura, N., Niwa, H., Hatanaka, M., Kase, M., and Fukuda, T. 197t h ECS Meeting, Toronto, Ontario, Canada, May, 2000. Togrul, H., and N. Arslan, Carbohydrate Polymers, 54, 63, 2003. Tsukruk, V. V., and V. N. Bliznyuk, Langmuir, 14, 446, 1998. Tung, T.-L., A method for die-scale simulation for CMP planarization, Proc. of SISPAD Conf., Cambridge, MA, Sept. 1997. Vedula, R. R. and Spencer, H. G. Colloids Surf., 58, 99, 1991. Wagner, D., J. Vac. Sci. Technol., 15, 518, 1978. Wang, L., W. M. Sigmund, and F. Aldinger, J. Am. Ceram. Soc., 83, 697, 2000. Wolf, S., Silicon Processing for the VLSI Era Process Integration, Vol. 2, Lattice Press, Sunset Beach, CA, 1990, chap. 13, p. 24. Wolf, S., Silicon Processing for the VLSI Era, Vol. 4, Lattice Press, Sunset Beach, CA, 2002, chap. 8, pp. 375–390. Wrschka, P., J. Hernandez, G. S. Oehrlein, and J. King, J. Electrochem. Soc., 147(2), 706, 2000. Xia, B., I. W. Lenggoro, and K. Okuyama, Chem. Mater., 14, 2623, 2002. Xu, C. S., E. Zhao, R. Jairath, and W. Krusell, J. Electrochem. Solid-State Lett., 1, 4, 1998. Yang, J., S. Mei, and J. M. F. Ferreira, J. Am. Ceram. Soc., 83, 1361, 2000. Yim, Y. S., K. S. Shin, S. H. Hur, J. D. Lee, I. H. Baik, H. S. Kim, S. J. Chai, et al., IEDM Tech. Dig., 34.1.1, 2003. Yu, C., P. C. Fazan, V. K. Mathews, and T. T. Doan, Appl. Phys. Lett., 61, 1344, 1992. Zaman, A. A., B. M. Moudgil, A. L. Fricke, and H. El-Shall, J. Rheol., 40, 1191, 1996. Zhou, Z., P. J. Scales, and D. V. Boger, Chem. Eng. Sci., 56, 1290, 2001.


Nanoparticle Engineering for Chemical-Mechanical Planarization: Fabrication of Next-Generation Nanodevices

Optical Fibers for Nanodevices

Fabrication and Welding Engineering

Photomask Fabrication Technology (Professional Engineering)

Mechanical Alloying for Fabrication of Advanced Engineering Materials

The Science and Engineering of Microelectronic Fabrication

Optical Properties of Nanoparticle Systems

Ceramic Fabrication Technology (Materials Engineering, 20)

Plasma Processes for Semiconductor Fabrication

Plasma processes for semiconductor fabrication

Plasma Processes for Semiconductor Fabrication

Plasma Processes for Semiconductor Fabrication

Actinide Nanoparticle Research

Bionanotechnology: Proteins to Nanodevices

Nanoparticle Technology Handbook

Chemical Mechanical Planarization of Microelectronic Materials

Fundamentals of semiconductor fabrication

Fabrication of GaAs Devices

Handbook of Composite Fabrication

Tribology In Chemical-Mechanical Planarization

Microelectronic applications of chemical mechanical planarization

Microelectronic Applications of Chemical Mechanical Planarization

Chemical Mechanical Planarization of Microelectronic Materials

Microchip Fabrication

Nanoparticle Technology for Drug Delivery (Drugs and the Pharmaceutical Sciences)

The Art of Gear Fabrication

Micro Process Engineering: Fundamentals, Devices, Fabrication, and Applications

Nanoparticles and Nanodevices in Biological Applications 3540709436

Nanoelectronics: Nanowires, Molecular Electronics, and Nanodevices

Nanoparticle Engineering for Chemical-Mechanical Planarization: Fabrication of Next-Generation Nanodevices

Optical Fibers for Nanodevices

Fabrication and Welding Engineering

Photomask Fabrication Technology (Professional Engineering)

Mechanical Alloying for Fabrication of Advanced Engineering Materials

The Science and Engineering of Microelectronic Fabrication

Optical Properties of Nanoparticle Systems

Ceramic Fabrication Technology (Materials Engineering, 20)

Plasma Processes for Semiconductor Fabrication

Plasma processes for semiconductor fabrication

Plasma Processes for Semiconductor Fabrication

Plasma Processes for Semiconductor Fabrication

Actinide Nanoparticle Research

Bionanotechnology: Proteins to Nanodevices

Nanoparticle Technology Handbook

Chemical Mechanical Planarization of Microelectronic Materials

Fundamentals of semiconductor fabrication

Fabrication of GaAs Devices

Handbook of Composite Fabrication

Tribology In Chemical-Mechanical Planarization

Microelectronic applications of chemical mechanical planarization

Microelectronic Applications of Chemical Mechanical Planarization

Chemical Mechanical Planarization of Microelectronic Materials

Microchip Fabrication

Nanoparticle Technology for Drug Delivery (Drugs and the Pharmaceutical Sciences)

The Art of Gear Fabrication

Micro Process Engineering: Fundamentals, Devices, Fabrication, and Applications

Nanoparticles and Nanodevices in Biological Applications 3540709436

Nanoelectronics: Nanowires, Molecular Electronics, and Nanodevices

Recommend Documents