Microvias: For Low Cost, High Density Interconnects

Source: Microvias Chapter 1 Introduction to Microvia and WLCSP Technologies 1.1 Semiconductor Industry Update The se...

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Source: Microvias

Chapter

1 Introduction to Microvia and WLCSP Technologies

1.1 Semiconductor Industry Update The semiconductor industry is firing on all cylinders. Worldwide semiconductor sales are predicted to grow by a combined annual growth rate (CAGR) of 16.2 percent from 2000 to 2004, reaching $316.2 billion as shown in Fig. 1.1. Sales remain strong across all product segments, including digital signal processors (DSPs), standard-cell applicationspecific integrated circuits (ASICs), dynamic random access memories (DRAMs), microprocessors, and flash and telecom analog chips. The applications driving booming chip demand are personal computers, networking equipment, and wireless communications. The networking hardware market will grow to $104 billion by 2004, while the worldwide number of broadband subscribers will climb to $61 billion during the same time frame. The wireless communications market will reach $132 billion by 2004, while the total number of cellular handsets (cell phones) shipped will soar to 1.4 billion units. The region of fastest growing equipment consumption is the Asia Pacific region, led by Taiwan and South Korea, which have consumed $6.8 billion and $3.4 billion worth of equipment, respectively, in 2000. The Asia Pacific region will surpass the Americas as the largest equipment consumer by 2001, while Europe and Japan will both approach the $10 billion mark by 2002. There are almost forty 12-in. semiconductor fabrications (FABs) in the world. Two-thirds of these FABs are located in the Asia Pacific region, led by Taiwan, Japan, and South Korea.

1

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Introduction to Microvia and WLCSP Technologies

2

Chapter One

Figure 1.1

Worldwide semiconductor revenue growth.

1.2 System-on-a-Chip (SOC) One of the 12-in. FABs’ future semiconductor integrated circuit (IC) products is system-on-a-chip (SOC), which contains diverse functions on a single, large, and complex chip. These chip designs and build cycles usually are long and require multiple design passes to complete. The advantages of SOC are performance, small system form factor, and potentially low system cost. The challenges of SOC are: (1) to deal with the cost of large ICs, the slowdown in the reduction of cost per transistor as a result of very low IC yields, and the very high wafer FAB costs that are estimated to be in the range of $3 to 5 billion; (2) to integrate the intellectual property from multiple, possibly independent sources, with attendant interoperability, integration, and liability hurdles; and (3) to meet the mixed-signal requirements of future products, mixed technology systems, design issues, and limitation of on-chip performance that the industry faces for the first time. 1.3 System-on-a-Package (SOP) Based on the trends in the semiconductor industry, IC packaging1–12 can look forward to solid growth in the next few years, as shown in Table 1.1. It can be seen that chip scale packages (CSPs) have the largest percentage of CAGR, followed by the ball grid array (BGA) and the direct chip attach (DCA). Although there is no way to determine the exact




TABLE 1.1

3

IC Package Forecast by Package Family

Package units (M)

1999

2000

2001

2002

DIP

9,413

8,880

8,838

7,974

2003 8,126

2004 8,165

−2.80%

CAGR

SO

40,163

43,803

49,167

52,123

58,793

63,477

9.59%

CC

3,430

3,570

3,851

3,890

4,092

4,276

4.51%

QFP

6,371

7,241

8,138

8,939

9,794

10,912

11.36%

PGA

244

268

294

333

397

428

11.90%

BGA

1,742

2,491

3,311

4,244

5,237

6,205

28.92%

CSP

1,180

2,402

3,762

5,395

7,516

9,908

53.04%

DCA

5,588

6,257

7,099

7,999

9,201

10,311

13.04%

Total

68,130

74,914

84,461

90,898

103,157

113,683

10.78%

total revenue of IC packaging, 10 percent of the total semiconductor revenue is a reasonable guess for the total IC packaging revenue. In that case, the total revenue of IC packaging should be $32 billion by 2004. For very high-volume and simple applications, SOC is particularly appropriate. However, for mixed technologies, lower volumes, and the integration of passives, SOP is the most appropriate. SOP is an attractive alternative to SOC design complexity and uses a lower-risk approach that permits the use of mature semiconductor and packaging technologies and standard chip-to-package attach methods. In the case of printed circuit board (PCB) design of multiple packaging technologies such as wire bonding, DCA, CSP, and BGA, it is often clear that designing and manufacturing a PCB containing all these diverse technologies can be expensive and time consuming. Moreover, in these designs, clusters of functionally related components can be identified as ideal candidates for functional subassemblies—a microprocessor and its buffer memory, an input/output (I/O) processor and interface chips. Packaging technology has now progressed to the point where these “systems” (subsystems) can be contained on an independent package called a few-chip module (FCM). This package can be assembled and tested separately, often resulting in saving of PCB space and cost, simplication of the substrate carrier (either organic or ceramic), and lower overall packaging costs. Electrical performance is enhanced through shorter interconnections of chip on SOP. The use of reference planes allows isolation of critical nets. Impedance/coupling levels can be controlled. Current design ground rules allow regions of very dense wiring to permit interconnection of high chip pin counts. Using glass-ceramic or organic materials offers the fastest propagation speeds and lowest line resis-



4

Chapter One

tances. The close physical proximity of the components mounted on SOP can minimize operating temperature deltas and permit thermal tracking, improving system performance. Use of an FCM allows designers to optimize that set of components for performance through functional subsystem testing prior to PCB assembly, allowing simplification of board test. The compacting of several electrical functions into SOP usually leads to some thermal challenges. Unless power and airflow levels are such that no heat management is necessary, the package components will have their own unique solutions. On simple two (or three)-chip SOPs, separate heat spreaders can be attached to each chip, depending on its power level. If space permits, an advanced thermal compound can be dispensed onto each component and a full module cap can be used. The differing expansion rates of each element in the SOP demand mechanical isolation for thermal management. Often, common heat sinking approaches can be used with SOP to minimize the number and handing of individual thermal solutions. Both direct lid attachment (DLA) and thermal paste solutions can be used when components are closely spaced; individual applications will require differing solutions. 1.4 Microvia and Wafer-Level Chip-Scale Package (WLCSP) As mentioned earlier, CSP will have the largest percentage of CAGR in the future of IC packaging. WLCSP is not only one of the CSPs, but the real CSP. Also, WLCSP is considered potentially the most cost-effective and reliable package. There are more than 30 different types of WLCSP reported in the literature, and their advantages and disadvantages have already been discussed.1–4 Just like many other new technologies, however, WLCSP still faces many critical issues (only solder-bumped WLCSP will be considered13–30): ■

The infrastructure of WLCSP is not well established.

■

The standard of WLCSP is not well established.

■

WLCSP expertise is not commonly available.

■

Bare wafer is not commonly available.

■

Bare wafer handling is delicate.

■

The Cost for poor-yield IC wafers is high.

■

Wafer bumping is still too costly.

■

There is a high cost for low wafer-bumping yield, especially for highcost dies.




5

■

Wafer-level redistribution is still too costly.

■

There is a high cost for low wafer-level redistribution yield, especially for high-cost dies.

■

Troubles can occur with system makers if the die shrinks.

■

Test at speed and burn-in at high temperature on a wafer are difficult.

■

Single-point touch-up on the wafer is difficult.

■

PCB assembly of WLCSP is difficult.

■

Solder joint reliability is critical.

■

Microvia build-up PCB affects WLCSP solder joint reliability.

■

Alpha particle emission occurs through the lead-bearing solder on WLCSP.

■

Lead-free solder regulations have an impact on WLCSP.

■

Who should do the WLCSP? IC foundries or bump houses?

■

What are the cost-effective and reliable WLCSPs and for what IC devices?

■

How large is the WLCSP market?

■

What is the life cycle of WLCSP?

One of the unique features of most WLCSPs is the use of a metal layer to redistribute the very fine-pitch peripheral-arrayed pads on the chip to much larger-pitch area-arrayed pads with much taller solder joints on the PCB or substrate, as shown in Figs. 1.2 through 1.5. Figure 1.2 shows the wafer-level redistribution. Figure 1.3 shows a cross section of the redistribution. Figure 1.4 shows a typical cross section of the WLCSP assembled on a PCB, and Fig. 1.5 shows the cross section of the WLCSP-PCB assembly in more detail. In this book a few new solder-bumped flip-chip WLCSPs will be discussed in Chap. 10. Also, solder developments for the next-generation high-density interconnects will be presented in Chap. 9. In general, with WLCSPs, the underfill encapsulant may not be necessary (as shown in Fig. 1.4) and the demands on the PCB or substrate are relaxed. Since there is no underfill for most of the WLCSP assemblies, solder joint reliability becomes one of the most critical issues. Chapter 12 will address the solder joint reliability issues. A few new and high-throughput processes for assembling WLCSPs on PCB or substrate will be discussed in Chap. 11. For solder-bumped flip chip on low-cost substrate or PCB applications, even with wafer-level pad redistribution (from peripheral array to area array) to relax the pressure on PCB or substrate, in many cases



6

Chapter One

Figure 1.2

Wafer-level redistribution on a peripheral-arrayed

chip.

one to two or even three to four build-up layers with microvias are needed to fan out the circuitry. Chapters 3 through 7 will present, respectively, five different methods of forming the microvias, namely mechanical numerical control (NC) drilling, laser drilling, photo defining, etching, and conductive-material fill. A few very special and novel microvia build-up substrates for solder-bumped flip chip in packages are discussed in Chap. 8. Some necessary fundamental knowledge for making the conventional PCB or substrate is presented in Chap. 2. In this chapter, microvia build-up PCBs or substrates will be briefly discussed. However, since packaging cost is the most important issue, the WLCSP costs will be discussed first.

A typical cross section of the wafer-level redistributed chip.

Figure 1.3




Figure 1.4

7

PCB assembly of the WLCSP.

1.5 WLCSP Costs Since 100 percent perfect wafers cannot be made at high volume today, the true IC chip yield YT plays the most important role in cost analysis. Also, the physical possible number of undamaged chips Nc stepped from a wafer is needed for cost analysis, since (YTNc) is the number of truly good dies on a wafer. Nc is given by1, 2, 16

Figure 1.5

PCB assembly of the WLCSP (enlarged view).



8

Chapter One

[φ − (1 + θ)兹A/θ 苶]2 Nc = π ᎏᎏᎏ 4A

(1.1)

A = xy

(1.2)

x θ=ᎏ ≥1 y

(1.3)

where

and

In Eq. (1.1) through (1.3), x and y are the dimensions of a rectangular chip (in mm), with x no less than y; θ is the ratio between x and y; φ is the wafer diameter (mm); and A is the area of the chip (in mm2). For example, for a 200-mm wafer with A = 10 × 10 = 100 mm2, then Nc ∼ 255 chips. 1.5.1 Wafer redistribution costs

Wafer-level redistribution is the heart of the WLCSPs, since only a handful of companies have the area-arrayed IC technology. The cost of wafer-level redistribution is affected by the true yield YT of the IC chip, the wafer-level redistribution yield YR , and the good die cost CD. The actual wafer-level redistribution cost per wafer CR is CR = CWR + (1 − YR)YTNcCD

(1.4)

where CWR is the wafer-level redistribution cost per wafer (ranging from $50 to $200), YR is the wafer-level redistribution yield per wafer, CD is the good die cost, Nc is given in Eq. (1.1), and YT is the true IC chip yield after at-speed/burn-in system tests. Again, it can be seen that the actual wafer-level redistribution cost per wafer depends not only on the wafer-level redistribution cost per wafer but also on the true IC chip yield per wafer, wafer-level redistribution yield per wafer, and good die cost. Wafer-level redistribution yield YR plays a very important role in WLCSP. The wafer-level redistribution yield loss (1 − YR) could be due to: 1. More process steps 2. Wafer breakage 3. Wafer warping




9

4. Process defects such as spots of contamination or irregularities on the wafer surface 5. Mask defects such as spots, holes, inclusions, protrusions, breaks, and bridges 6. Feature size distortions 7. Pattern misregistration 8. Lack of resist adhesion 9. Overetching 10. Undercutting 11. Incomplete etching 12. Wrong materials It should be noted that rework of wafer-level redistribution is very difficult if not impossible. It has to be right the first time; otherwise, someone has to pay for it! The uses of Eq. (1.1) and (1.4) are shown in the following examples. If the die size of a 200-mm wafer is 100 mm2, true IC chip yield per wafer is 80 percent (since the importance of YT has been shown in Refs. 1, 2, and 28, only one value of YT will be considered in this study), wafer-level redistribution yield per wafer is 90 percent, wafer-level redistribution cost per wafer is $100, and die cost is $100 (e.g., microprocessors), then from Eq. (1.1), Nc = 255, and from Eq. (1.4), the actual wafer-level redistribution cost per wafer is $2140. For the same size of wafer, if the die cost is $5 (e.g., memory devices), then the actual waferlevel redistribution cost per wafer is $202. It is noted that for both cases the actual wafer-level redistribution cost per wafer is much higher than the wafer-level redistribution cost (CWR = $100)! On the other hand, if the wafer-level redistribution yield is increased from 90 percent to 99 percent, then the actual cost for redistributing the microprocessor wafer is reduced from $2140 to $304 and for redistributing the memory wafer it is reduced from $202 to $110.2 (Table 1.2). Thus, wafer-level redistribution yield plays an important role in the cost of wafer-level redistribution and the wafer-level redistribution houses should strive to make YR > 99 percent, especially for expensive good dies. 1.5.2 Wafer bumping costs

Wafer bumping is the heart of solder-bumped WLCSPs. The cost of wafer bumping is affected by YT, CD, YR and the wafer-bumping yield YB. The actual wafer-bumping cost per wafer CB is CB = CWB + (1 − YB)YRYTNcCD

(1.5)


99%

90%

90%

90%

$1956

$4096

$3876

$20.08

Wafer-level bumping yield

Actual wafer-level bumping cost

Total actual cost of WLCSP per wafer

Hidden cost of WLCSP per wafer

Actual cost of WLCSP per good die

$11.98

$2223.60

$2443.60

$303.60

90%

90%

$11.98

$2223.60

$2443.60

$2139.60

$304

$3.07

$405.96

$625.96

$321.96

$2.03

$193.80

$413.80

$211.80

$202

$1.62

$111.18

$1.62

$111.18

$331.18

90% $220.98

99%

$331.18

99%

99%

$1.18

$20.30

$240.30

$130.10

$110.20

$129.18

Number of physically possible dies on wafer

$2140

255

255

Wafer-level bumping cost

Actual wafer-level redistribution cost

$120

$120

Wafer-level redistribution cost

Wafer-level redistribution yield

80% $100

80% $100

IC chip yield

99%

$5

$100

Good die cost

99%

Memory device

Item

WLCSP Cost Analysis Microprocessor device

TABLE 1.2



10



11

where CWB is the wafer-bumping cost per wafer (ranging from $25 to $250), YB is the wafer-bumping yield per wafer, YR is the wafer-level redistribution yield per wafer, CD is the good die cost, Nc is given in Eq. (1.1), and YT is the true IC chip yield after at-speed/burn-in system tests. Again, it can be seen that the actual wafer-bumping cost per wafer depends not only on the wafer-bumping cost per wafer but also on the true IC chip yield per wafer, wafer-bumping yield per wafer, good die cost, and wafer-level redistribution yield per wafer. Just like YR, wafer-bumping yield YB plays a very important role in WLCSP. The wafer-bumping yield loss (1 − YB) could be due to: 1. Wrong process 2. Different materials 3. Too tall or short of a bump height 4. Not enough shear strength 5. Uneven shear strength 6. Broken wafers or dies 7. Solder bridging 8. Damaged bumps 9. Missing bumps 10. Scratching of the wafer For the previous example, if the wafer-bumping yield per wafer is 90 percent and wafer-bumping cost per wafer is $120, then the actual wafer-bumping costs per (microprocessor) wafer are, respectively, $1956 if YR = 90 percent and $2139.60 if YR = 99 percent, and the actual wafer bumping costs per (the memory) wafer are, respectively, $211.80 if YR = 90 percent and $220.98 if YR = 99 percent (Table 1.2). Again, it should be noted that the actual wafer-bumping cost per wafer is much higher than the wafer-bumping cost (CWB = $120). On the other hand, if the wafer-bumping yield is increased from 90 percent to 99 percent, then the actual costs for bumping the microprocessors wafer are, respectively, $303.60 if YR = 90 percent and $321.96 if YR = 99 percent, and the actual costs for bumping the memory wafer are, respectively, $129.18 if YR = 90 percent and $130.10 if YR = 99 percent. Thus, wafer-bumping yield plays an important role in the cost of wafer bumping and the wafer-bumping houses should stride to make YBYR > 99 percent, especially for expensive good dies. If there is no wafer-level redistribution, then there is no wafer redistribution yield loss, i.e., YR = 1, and Eq. (1.5) degenerates to that shown in Refs. 1 and 2.



12

Chapter One

1.5.3 Wafer redistribution and wafer-bumping costs

Based on the foregoing discussions, the total actual cost for solderbumping and wafer-level redistribution CBR becomes CBR = CWBR + (1 − YRYB)YTNcCD

(1.6)

CWBR = CWR + CWB

(1.7)

where

is the sum of wafer-level redistribution cost and wafer-bumping cost CWBR usually charged by the wafer-bumping houses. For our example, the total actual costs of the microprocessor WLCSP are: CBR = $4096 if YR = YB = 90 percent; CBR = $2443.60 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR = $625.96 if YR = YB = 99 percent. The total actual costs of the memory WLCSP are: CBR = $413.80 if YR = YB = 90 percent; CBR = $331.18 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR = $240.30 if YR = YB = 99 percent (Table 1.2). Thus (1) for both devices, the actual WLCSP costs are higher than the cost ($100 + $120 = $220) charged by the redistribution-bumping houses; (2) this is even more so for the more expensive dies; and (3) YR and YB play very important roles in WLCSP and YRYB > 99 percent is a must for WLCSP to be competitive. 1.5.4 WLCSP hidden costs

The hidden cost per wafer is defined as the difference between the actual wafer-bumping and wafer-level redistribution cost, and the waferbumping and wafer-level redistribution cost charged by the waferbumping houses. From Eq. (1.6), the hidden cost per wafer for solder-bumped WLCSP CH is given as CH = CBR − CWBR

(1.8)

CH = (1 − YRYB)YTNcCD

(1.9)

or

It can be seen that, if YR = YB = 1, then there is no hidden cost (CH = 0) in solder-bumped WLCSP, meaning the wafer-bumping houses are perfect in doing the wafer-level redistribution and wafer bumping. Unfortunately, they cannot and never will be perfect, which is what makes the costs of wafer-level redistribution and wafer bumping so expensive, especially for expensive good dies.




13

For our example, the hidden costs of the microprocessor WLCSP are: CH = $3876 if YR = YB = 90 percent; CH = $2223.60 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CH = $405.96 if YR = YB = 99 percent. The hidden costs of the memory WLCSP are: CH = $193.80 if YR = YB = 90 percent; CH = $111.18 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CH = $20.30 if YR = YB = 99 percent (Table 1.2). The fact that someone has to pay for (or share) the hidden costs is one of the major reasons why solder-bumped WLCSP is not very popular today. 1.5.5 WLCSP cost per good die

The actual wafer-bumping and wafer-level redistribution cost per good die CBR/D can be determined by CBR/D = CBR/YTNc

(1.10)

CBR/D = CWBR/YTNc + (1 − YBYR)CD

(1.11)

or

For our example, the actual WLCSP costs per the good microprocessor die are: CBR/D = $20.08 if YR = YB = 90 percent; CBR/D = $11.98 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR/D = $3.07 if YR = YB = 99 percent. The total actual WLCSP costs per the good memory die are: CBR/D = $2.03 if YR = YB = 90 percent; CBR/D = $1.62 if YR = 90 percent and YB = 99 percent or YR = 99 percent and YB = 90 percent; and CBR/D = $1.18 if YR = YB = 99 percent (Table 1.2). Comparing with the wire bonding technology, these costs are much too high for solder-bumped WLCSP to be competitive, unless it is compensated for by performance, density, and form factor. Thus, again, YRYB >> 99 percent is a must for WLCSP to be popular. 1.5.6 Wafer-level underfill costs

For some special applications, such as portable electronic products under drop (shock) and vibration kinds of operation conditions, underfills are needed for ensuring the solder joint reliability of WLCSPs. Recently, in order to increase throughput and reduce production time, the research in wafer-level underfill materials and process has been very active.20 For WLCSP, in this process, the underfill is deposited on the entire solder-bumped wafer prior to dicing. During surface-mount technology (SMT) assemblies, the singulated chip is processed as in standard flip chip reflow operations. The key difference is that the pre-underfilled (with build-in flux) solder-bumped chip will be reflowed and cured concurrently between the chip and the organic substrate.



14

Chapter One

The actual wafer-level underfill cost per wafer CU can be determined by CU = CWU + (1 − YU)YBYRYTNcCD

(1.12)

where CWU is the wafer-level underfill cost per wafer and YU is the wafer-level underfill yield per wafer. The wafer-level underfill yield loss (1 − YU) could be due to: 1. More wafer process steps 2. Wrong process 3. Wrong materials 4. Dicing 5. Nonuniformity 6. Incompletely cured underfill 7. Damage to solder bumps 8. Breaking of the wafer 9. Scratching of the wafer 10. Too high a thermal expansion coefficient 11. Too low a modulus The actual wafer-level underfill cost per good die CU/D can be determined by CU/D = CWU/YTNc + (1 − YU)YBYRCD

(1.13)

Thus, from the cost point of view, wafer-level underfill is not a good idea and makes solder-bumped WLCSP even more expensive. It can be seen from the first term of the right side of Eq. (1.13) that the underfill costs of the good dies are increased because some of the expensive underfills are wasted on the bad dies. Also, the hidden cost of wafer-level underfill per good die is high and is shown in the second term of Eq. (1.13). It should be pointed out that, in most of the conventional solderbumped flip chip on low-cost substrate applications, the underfill operation is usually applied to the individual dies after the system test of the assemblies.1–5 The reasons are: (1) it is easy to rework; (2) underfill is needed for only the good dies; and (3) there is no chance to damage the very expensive wafer. Also, from the process point of view, waferlevel underfill will reduce the self-alignment characteristic (which is so unique) of solder-bumped flip chip technology.




15

If there is no wafer-level pad redistribution operation, then the actual wafer-level underfill cost per wafer can be determined by CU = CWU + (1 − YU)YBYTNcCD

(1.14)

Also, the actual wafer-level underfill cost per good die CU/D without wafer-level pad redistribution can be determined by CU/D = CWU/YTNc + (1 − YU)YBCD

(1.15)

Again, from both cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates. 1.5.7 Summary

More than 20 different critical issues regarding WLCSP have been mentioned. The most important issue of WLCSP (cost) has been analyzed in terms of the true IC chip yield, wafer-level redistribution yield, wafer-bumping yield, wafer-level underfill yield, and die size and cost. Also, useful equations in terms of these parameters have been presented and demonstrated through examples. Some important results are summarized as follows. ■

IC chip yield YT plays the most important role in WLCSP. If YT is low for a particular IC device, then it is not cost effective to house the IC with WLCSP, unless it is compensated for by performance, density, and form factor.

■

Wafer-level redistribution yield YR plays the second most important role in WLCSP. Since this is the first postwafer processing after the IC FAB, the wafer-level redistribution houses should strive to make YR > 99 percent (99.9 percent is preferred). Otherwise, the subsequent steps will be made very expensive by wasting of the material and process on the damaged dies.

■

Wafer-bumping yield YB plays the third most important role in WLCSP. The wafer-bumping house should strive to make YRYB > 99 percent (99.9 percent is preferred) to minimize the hidden cost, since they cannot afford to damage the already redistributed good dies.

■

Based on cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates.

1.6 Microvia Microvias are the keys to making low-cost and high-density PCBs and substrates. In order to make cost-effective PCB and substrates, the



16

Chapter One

sequential buildup (SBU) fabrication technique is a must. This is done by adding a minimum of one layer of dielectric to the double-sided or multilayer core. Non-through-hole microvias are selectively formed to reclaim real estate and are used to accommodate the fine I/O pitch and redistribute circuits from the chip to the internal layers of the PCB, reduce PCB layer count and size, and enhance electrical performance. By IPC’s definition, holes of 6 mils (0.15 mm) or less on PCBs and substrates are called microvias. There are many advantages of microvia:31–78 (1) it requires a much smaller pad, which saves the board size and weight; (2) more chips can be placed in less space or a smaller PCB, which results in a low cost; and (3) electrical performance improves as well, since the parasitic capacitance is increased due to the smaller via length and diameter and the inductance is reduced due to the shorter pathway created by the microvia compared to the plated through-hole (PTH).31–37 According to a recent study by TechSearch International, the market for microvia substrates will reach $1.6 billion this year. That number is expected to grow to $8.6 billion by 2005. Currently, 75 companies around the world are producing microvia substrates. Japan is the world leader, with more than 50 percent of the world’s microvia production. Europe and the Asia Pacific region come in second in microvia production. Most of the products that use microvia technology are mobile phones (Fig. 1.6), notebook computers, and other handheld products. The U.S. will not have high volume production until after 2000. The reason is that most U.S. companies are currently focusing on high-value applications like workstations, servers, and network systems. Table 1.3 shows the usage of microvias in different business sectors. It can be seen that the largest market is in personal communications such as the mobile phone (Fig. 1.6). Figures 1.7 through 1.10 show a few examples (by Intel and Mitsubishi) of using the microvia build-up substrates for solder-bumped flip chips, usually microprocessors and ASIC applications. Figure 1.11 shows a microvia build-up PCB with two thinfilm metal layers by X-LAM, which will be discussed in Chap. 8. 1.6.1 Categories of vias

Typical via hole diameters range from 50 to 300 µm and are divided into three categories. Blind vias. Blind vias are located on the outer layer of the top and bottom of the circuit board and are formed to a depth at which they make contact with the first inner layer. The depth of this hole usually does not exceed 1 aspect ratio (hole diameter).




17

Figure 1.6 Mobile phone with microvia build-up PCB. (Courtesy of Samsung)

Buried vias. Buried vias are holes that are plated within the core of the circuit board without access to the surface on either side of the board. These holes are formed before the board is laminated. The innerlayer material has the holes created by a through-hole processing method. The inner layers may be stacked several layers high during this hole formation process. Through-hole vias. Through-hole vias are formed through the entire thickness of the board. These vias are used as interconnect or as mounting locations for components. Basically, there are five major processes for microvia formation: (1) NC drilling; (2) laser via fabrication including CO2 laser, yttrium aluminum garnet (YAG) laser, and Excimer laser, (3) photo-defined vias, wet or dry; (4) etch via fabrications, including chemical (wet) etching and plasma (dry) etching; and (5) conductive-ink-filled vias, wet or dry. In general, even though photo-defining and chemical and plasma etching processes can make microvias in very high throughput, laser drills can make finer vias. 1.6.2 Microvias made by mechanical NC drilling

Currently, NC drilling is the most common process for generating holes on the PCB. However, NC drilling is technically limited to hole sizes of


Cisco, Lucent, Alcatel, Nortel, Sun, Ericsson, NEC, Schlumberger, Agilent, HP

Mainly North American and some European, with limited opportunity in Asia Pacific

Accelerating growth in largearea boards as multiple highleadcount ASICs drop to 1-mm pitch and below.

Players

Geography

Direction

Very rapid growth driven by both demand and conversion to CSP/microvia by majors. Cellphones will become smaller due to baseband and RF integration and despite multimode function.

Mainly Japan and Southeast Asia; now rapidly becoming global with Europe and U.S.

Samsung and all Japanese cellphone makers (Panasonic, NEC, Sharp, Fujitsu, Kyocera, etc.); Motorola, Nokia, and Ericsson (combined 67% of market and rapidly converting to microvia— 104 million units 1997)

$180 million → $970 million


Market size

Personal communications Cellphones, pagers, personal communications, handheld global positioning systems (GPSs), satellite phones

Workstations, servers, processor modules, transmission, switching, router boards, test equipment

Computing and data communications

Usage of Microvias in Different Business Sectors

Products

TABLE 1.3

Digital imaging

Steady growth in camcorders and cost reduction through integration. Digital cameras going from 2 million units to 8 million units per year in 2002, and converting from ceramic to microvia.

Mainly Japan, with Japan remaining dominant

JVC Victor, Sony, Panasonic, Kodak (9 million camcorders and 2 million digital cameras in 1997)


Camcorders, digital cameras, digital receivers



18



19

Figure 1.7 Intel’s microprocessor supported by a microvia build-up substrate.

Figure 1.8

Schematic of Intel’s microvia build-up substrate.

Figure 1.9

Mitsubishi’s microvia build-up substrate.



20

Chapter One

Mitsubishi’s solder-bumped flip chip plastic ball grid array (PBGA) package with microvias.

Figure 1.10

Figure 1.11

Schematic of X-LAM’s thin-film metal layer substrate.




21

200 µm and up (not microvias). Although smaller holes may be possible, these would come at the cost of significant productivity (such as minimal stack height). In addition, the blind vias are virtually impossible where typical dielectric thickness is 50 µm or less.38 In general, mechanical drilling cannot make microvias. However, it should be pointed out that some special machines are being designed to drill very small vias. For example, Excellon Automation have been developing drilling machines that can drill vias as small as 4 mils (100 µm) in diameter. For more information on mechanical NC drilling, please read Chap. 3. 1.6.3 Microvias made by laser drilling

Laser drilling can be a single or multiple via generation process that replaces the existing mechanical drilling process. Laser drilling differs from mechanical drilling in that the focused beam used to create the holes can produce smaller holes than those produced by conventional drilling. One of the most important advantages of laser drilling is that it is compatible with many copper-clad or unclad dielectrics and reinforced or nonreinforced PCBs. Laser drilling can be used to create both blind vias and holes. The process follows standard multilayer and is capable of resolving smaller features. Low productivity is one of the weaknesses of laser drilling; that is, one beam produces one blind via at a time.31 Laserdrilled microvias have been reported by several authors,39–51 and a typical PCB including a blind via is shown in Fig. 1.12. Several laser processes have been developed to generate small via holes; these are categorized as Excimer laser, YAG laser, and CO2 laser. The CO2 lasers have significantly higher productivity for holes larger than 70 µm in diameter. They can ablate more than 15,000 (100 µm diameter) holes through 50-µm-thick dielectric in 1 min. In general,

Figure 1.12

laser.

Via (75 µm) on 45-µm resin by UV:YAG



22

Chapter One

carbon dioxide laser is used to drill holes on the dielectric layer and not to drill holes on copper, because the visible wavelength (1060 nm) of CO2 is too large to have enough energy to penetrate the copper at high speed. Today, the companies that supply the CO2 laser drilling machines are Hitachi, Lumonics, Panasonic (Matsushita), Mitsubishi, and Sumitomo. On the other hand, the ultraviolet (UV):YAG laser, with smaller wavelengths (365 to 255 nm) and much higher energy, is used to drill holes on the copper and dielectric (the so-called imaging method) at a much lower speed. UV:YAG lasers have demonstrated great productivity through both dielectric and copper layers, but for both processes ablation time is proportional to hole diameter and neither process is therefore competitive above 100 µm diameter. Today, ESI, Excellon, Exotech, Hitachi, and Sumitomo supply the UV/Nd:YAG laser machines. Also, Hitachi and Lumonics of Canada now offer a combination of Nd:YAG/CO2 laser machines. The excimer laser has a wavelength of 248 nm with krypton fluoride (KrF) and of 193 nm with argon fluoride (ArF). Excimer lasers can generate holes smaller than 50 µm in diameter through dielectric or copper layers. Controlled-depth drilling is also possible, thus allowing blind vias to be created. The slow etch rate, however, makes this process impractical for microvia formation. Today, Litel, JPSA, and Tamarack supply UV:excimer machines, to which JPSA can add either T-CO2 or diamond CO2 laser heads. For more information about laser-drilled microvias, please read Chap. 4. 1.6.4 Photo-defined vias

In 1990, IBM at Yasu, Japan, commercially produced microvias using a modified liquid photoimageable dielectric (PID). Modern PID is either a liquid or dry film. For photovias with liquid photodielectric, the dielectric is curtain-coated and cured, microvias are exposed, and the dielectric is developed. Panel plating follows with patterning to create signal traces. For photovias with dry-film photodielectric, the dielectric is laminated, microvias are exposed, and the dielectric is developed. Panel plating follows with patterning to create signal traces.55 The equipment needed for photo-defined via technology includes exposure unit, developer, and wet process. The suppliers of exposure unit are Bacher, Byers, Colight, Csun, Dupont, Dynachem, Gyrex, HiTech, Mirmir, Morton, Olec, Optical Radiation, ORC, Peak Measuring, Tamarac, and Theimer. The suppliers of developer are Advanced Chemill Systems, ASI, Chemcut, Ciba-Geigy, Circuit Services, Danippon Screen, Glenbrook, James River, Lantronic, Microplate, Quan-




23

tum, Rexham Graphics, and Technifax. The suppliers of wet process (develop-etch-strip) are ASI, Chemcut, Hollmuller, Lantronic, and Schmid. For more information about photo-defined microvias, please read Chap. 5. 1.6.5 Chemical (wet)- and plasma (dry)-etched vias

Microvias can be formed by various etching techniques. The most common etching technique is to use a microwave-gas plasma, which is a dry etching process. Wet etching by hot KOH has been used for polyimide films. Both methods are isotropic such that they etch inward while they etch down. On the positive side, these formation techniques involve mass via generation in that they form all vias at the same time without regard to number or diameter. Plasma etching and chemical etching can be extremely cost effective for generating high volumes of small holes in dielectric layers. The principle in this case is to create a mask, which defines the position and size of the holes. This may be achieved by using dry film to image and then etch a hole pattern in a copper layer, or simply by using the dry film as the etch mask by imaging and developing. In either case the process cost is derived by the number of holes in a given working area. All the holes are generated simultaneously, and the process time is dependent on how long it takes to erode or dissolve the unmasked dielectric. Plasma etching has the added benefit of removing organic contaminants, and with careful conditioning, the amount of slope (undercut) created in the hole can be minimized. Chemical etching is the lowest-cost process for generating small holes on dielectrics. Both plasma and chemical etching processes can create blind vias, usually using the target pad as a means of defining the bottom of the blind via.57–58 The dry etching process needs extra processes like plasma etching and copper thinning (etch-back) processes. Micro Via Hole (MVH) formation by gas-microwave plasma (GMP) has been promoted by Dyconex of Switzerland. Dyconex has sixteen licensees worldwide because it sells a basic plasma drill for $55,000, compared to a laser drill that costs from $500,000 and up or to a photoimaging facility that requires around $300,000. The plasma equipment can be found from Advanced Plasma Systems, Inc. or Plasma Etch Inc. For more information about etched microvias, please read Chap. 6. 1.6.6 Conductive-ink-filled vias

Conductive ink describes a single-layer dielectric with microvias formed by laser, photoimaging, or insulation displacement. A conduc-



24

Chapter One

tive paste (or film) is used to fill the microvias and act as the conductive path between layers. Surface metallization may be accomplished either by laminating copper foil onto the dielectric surface or by chemical deposition. For more information about conductive-ink-filled microvias, please read Chap. 7. 1.6.7 Microvia production in Japan

Since more than half of the world’s microvia PCBs and substrates are made in Japan, it is interesting to note the status of some key manufacturers in this area. These are reported as follows. (See Table 1.4 for additional details.) Fujitsu Limited. Fujitsu’s FLD (Fujitsu Laminate and Deposit) buildup process is currently in production and utilizing photoimaging system. FLLD (Fujitsu Laminate with Laser via and Deposit) process is under development and utilizes a laser drilling system. The technology is capable of producing 50-µm copper lines with 50-µm spaces and 100-µm-diameter vias for packaging substrates. Fujitsu is changing from photovia to laser via for its next generation packaging substrates. Highly Accelerated Stress Test (HAST) and reliability test results are presented in Ref. 64. Hitachi Chemical Co. Hitachi has developed two types of PCBs, namely, HITAVIA Type 1 and Type 3 using metal clad B-stage insulation resin film (MCF). Type 1 is used for motherboards and liquid crystal display drivers; Type 3 is used for semiconductor packages such as PBGA. The interstitial via holes (IVHs) are formed using mechanically predrilled metal-clad film. A CO2 laser is used to etch the microvias. The technology is capable of producing 100-µm copper lines with 100-µm spaces for Type 1 and 50-µm lines with 50-µm spaces for Type 3. The size of vias can be 250 µm on 500-µm pads for both types. All passed the qualification tests.65 Ibiden. Ibiden has developed a double-sided four-layer build-up board using fully additive copper plating and photosensitive epoxy. This technology is capable of producing 75-µm lines with 75-µm spaces for motherboards and 35-µm copper lines with 35-µm spaces for packages. Using the photovia process, it is possible to make 150-µm-diameter via on 250-µm lands for motherboards and 80-µm-diameter via holes on 125-µm lands for packages.66 IBM at Yasu. The IBM (at Yasu) Surface Laminar Circuit (SLC) also uses liquid-dispensed photoimaged epoxy in the build-up layers on FR-4 or bismaleimide triazine (BT) substrates. The photo-sensitive epoxy




TABLE 1.4

25

Microvia Build-up PCB and Substrate Suppliers

Company Amitec

Via formation method Thin film

Via/pad diameter (µm)

Line/space (µm)

Maximum number of multilayers

25/50

15/15

2–4

ASTI

Laser

25/125

35/35

16

Canon

Laser

150/300

75/75

3+core+3

Compaq

Laser

75/195

75/30

10

Daisho Denshi

Laser

100/300

75/75

8

D. T. Circuit

B2it

200/400

75/75

4+core+4

Fujitsu

Photovia Laser

80/130 50/100

40/40 35/35

6 3+core+3

Hitachi Cable

Laser

50/80

25/25

2

Hitachi Chemical

Laser

100/125

50/50

10

Ibiden (IBSS)

Photovia Laser

85/125 150/250

40/40 75/75

4-2-4 10

IBM (HPCC)

Laser

50/100

28/33

9

IBM (SLC)

Photovia

100/150

50/50

3+core+3

JCI

Laser

100/160

40/40

8

JVC

Laser

150/250

60/60

2+core+2

K&S (X-Lam)

Thin film

25/54

18/14

2-4

Kyocera/JME

Photovia

50/100

30/30

4-8-4

Matsushita

Laser

100/125

50/50

4+core+4

Mitsubishi

Laser

75/125

30/30

3+core+3

Multek

Photovia

75/150

75/75

8

NEC

Photovia

40/60

20/20

3+core+3

NTK

Photovia Laser

90/130 50/130

35/35 40/40

3+core+3 9

Samsung

Photovia with laser

150/200

50/50

3+core+3

Sheldahl

Laser

25/140

50/37.5

Shinko

Laser

50/110

45/45

3+core+3

2

SMI

Photovia

95/135

37/37

2+core+2

STP

Photovia

100/200

75/75

1+8+1

Toppan

Photovia Laser

80/130 100–125/300

40/40 75/75

3+core+3 —

W. L. Gore

Laser

50/87

25/25

9

The number before and after the core is the number of build-up layers.



26

Chapter One

resin is exposed and developed to form the via hole. The via diameter can be 100 µm and the land diameter can also be 100 µm. The line width and space can be 38 µm. The flip chip attached on SLC board has passed reliability tests with 100°C delta temperature cycling and temperature/humidity/bias test.67–70 JVC. The Victor Company of Japan (JVC) has produced the Variously Interconnected Layers (VIL) type of build-up PCB by applying thermosetting material to insulation and by the laser processing of via holes through the mask imaging method. Lines and spaces of 100 µm have been produced. JVC has succeeded in making a skip via hole as small as 280 µm in diameter.71 Matsushita. Matsushita has developed a unique stacked type of substrate technology called ALIVH, which is discussed in Sec. 7.3.30–33 Laser ablation (currently CO2 laser) and Cu paste are used for buried holes. It is reported that Matsushita’s share of the Japanese cellular phone market has risen to 60 percent with the introduction of ALIVH substrates. The company’s conductor line and space resolution are 50 µm and 50 µm, respectively.72 Reliability data for ALIVH-CSP have been shown in Ref. 63. NEC. NEC Toyama has developed a high-density microvia (µV) PCB for advanced microelectronic packaging application. The more advanced technology can produce 50-µm copper lines with 50-µm spaces. The via diameter can be 50 µm and land diameter can be 150 µm. The via is formed by laser processing. Most of the samples pass reliability tests, although there are less than 3 percent fails on the interconnection reliability test, MIL-STD-107G (−65°C for 30 min to +125°C for 30 min) after 500 cycles.73 Toshiba. Toshiba has introduced a unique Buried Bump Interconnection Technology (B2it). Silver paste is used to form conductive bumps on copper foil. Conically shaped bumps can penetrate the insulator and form a conductive path through the prepreg. The conductive lines and spaces, currently 75 µm in width each, are being formed by subtractive processing using photoresist. The “via” (bump) diameter is 200 µm and the land diameter is 400 µm. These are now under mass production.74 Recently, Toshiba and Dai Nippon Printing Co., Ltd formed a new start-up company called D. T. Circuit Technology Co., Ltd for making the B2it PCB and substrate. A summary of the line width and space width capabilities of these eight Japanese microvia manufacturers is shown in Fig. 1.13. It can be seen that Ibiden can make the finest lines and spaces. Figure 1.14 is a




Figure 1.13

27

Line/space width technologies for some Japanese companies.

summary of the microvia and pad diameter capabilities of the eight Japanese microvia manufacturers. The smallest via and pad can be manufactured by NEC Toyama Corporation. It should be pointed out that five (Hitachi, Ibiden, JVC, Matsushita, and Toshiba) of the eight Japanese companies have developed their own new materials for the microvia process and formation. Four

Figure 1.14

Via/pad diameter technologies for some Japanese companies.



28

Chapter One

(Hitachi, JVC, Matsushita, and NEC) use laser drilling. Two (Ibiden and IBM-Yasu) use photoimaging, and Fujitsu is changing from photoimaging to laser drilling. Toshiba (D. T. Circuit) has changed from the conventional (drilling and plating) process to a new process. 1.6.8 Summary

In general, laser drilling can create the smallest holes. Photo-defined via technology has highest productivity. Laser drilling technology gains 70 percent of the microvia market because of its straightforward nature and compatibility with all kinds of materials (including clad laminates, copper-coated foil, and dielectrics). The photoimaging method is the second most popular technology used in making microvias. Japan is the leader in making microvias, and the U.S. is very well back. However, some U.S. companies are catching up. For example, Johnson Matthey is the largest supplier of microvias in North America. It has 10 laser drills (4 YAG to ablate copper for RCC processing and 6 CO2 units to remove dielectric). Johnson Matthey’s electronic materials division was sold to Allied Signal Electronic Materials unit in August 1999. Allied Signal sold its laminate systems business to Rutgers AG, based in Essen, Germany, in order to enter higher-margin specialty segments. 1.7 A Note on High-Speed and High-Density Interconnects In Ref. 77, IPC-2141 gives the equations for estimating the characteristic impedance for some very simple circuits. Since these are approximate formulas, very often they lead to great errors, especially for high-speed and high-density interconnects. For example, for the simplest case (surface microstrip) shown in Fig. 1.15, with T = 35 µm, H = 794 µm, W = 3300 µm, εr = 4.2, IPC-2141’s equation underpredicts the characteristic impedance by almost 30 percent. In this book, some useful design charts for the surface microstrip, differential edge-coupled surface microstrip, embedded microstrip, differential microstrip, embedded stripline, differential symmetrical broadside-coupled stripline, differential symmetrical edge-couple centered-embedded stripline, and surface microstrips are shown in Figs. 1.15 through 1.26. It should be noted that all the data to make the curves are determined (with εr = 4.2) from numerical simulations of the Maxwell equations and checked randomly with some well-known solutions such as those given in Ref. 78. In these charts, Z0 is the characteristic impedance and Zdiff ⬵ 2 × Z0o, where Z0o is the odd-mode impedance.




Figure 1.15

29

Characteristic impedance of a surface microstrip (εr = 4.2).

Figure 1.16 Differential impedance of a differential edge-coupled surface microstrip (εr = 4.2).



30

Chapter One

Figure 1.17 Differential impedance of a differential edge-coupled surface microstrip (εr = 4.2).

Figure 1.18

Characteristic impedance of a embedded microstrip (εr = 4.2).




31

Figure 1.19 Differential impedance of a differential centered-embedded microstrip (εr = 4.2).

Differential impedance of a differential centered edge-coupled embedded microstrip (εr = 4.2).

Figure 1.20



32

Chapter One

Figure 1.21

Characteristic impedance of an embedded stripline (εr = 4.2).

Figure 1.22 Differential impedance of a differential symmetrical broadsidecouple stripline (εr = 4.2).




33

Figure 1.23 Differential impedance of a differential symmetrical embeddedcentered stripline (εr = 4.2).

Differential impedance of a differential symmetrical embeddedcentered stripline (εr = 4.2).

Figure 1.24



34

Chapter One

Figure 1.25

Capacitance of surface microstrips (εr = 4.2).

Figure 1.26

Inductance of surface microstrips (εr = 4.2).




35

1.8 References 1. Lau, J. H., Low-Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, 2000. 2. Lau, J. H., and S.W.R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999. 3. Lau, J. H., C. Wong, J. L. Prince, and W. Nakayama, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998. 4. Lau, J. H., and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, 1997. 5. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, 1996. 6. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, 1995. 7. Lau, J. H., Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, 1994. 8. Lau, J. H., Handbook of Fine Pitch Surface Mount Technology, Van Nostrand Reinhold, New York, 1994. 9. Frear, D., H. Morgan, S. Burchett, and J. Lau, The Mechanics of Solder Alloy, Van Nostrand Reinhold, New York, 1994. 10. Lau, J. H., Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993. 11. Lau, J. H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, 1992. 12. Lau, J. H., Solder Joint Reliability, Theory and Applications, Van Nostrand Reinhold, New York, 1991. 13. Garrou, P., “Wafer Level Chip Scale Packaging (WL-CSP): An Overview,” IEEE Trans. Adv. Packaging, 23(2): 198–205, May 2000. 14. Nguyen, L., N. Kelkar, and H. Takiar, “A Manufacturing Perspective of Wafer Level CSP,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 97–100, Las Vegas, NV, May 2000. 15. Topper, M., J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jager, D. Petter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, and H. Reichl, “Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 74–80, Las Vegas, NV, May 2000. 16. Ahn, M., D. Lee, and S. Kang, “Optimal Structure of Wafer Level Package for the Electrical Performance,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 530–534, Las Vegas, NV, May 2000. 17. Mirza, A. R., “One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 676–680, Las Vegas, NV, May 2000. 18. Simon, J., and H. Reichl, “Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S3),” IEEE Proceedings of Electronic Components & Technology Conference, pp. 81–86, Las Vegas, NV, May 2000. 19. Teutsch, T., T. Oppert, E. Zakel, E. Klusmann, H. Meyer, R. Schulz, and J. Schulze, “Wafer Level CSP using Low Cost Electroless Redistribution Layer,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 107–113, Las Vegas, NV, May 2000. 20. Tong, Q., B. Ma, E. Zhang, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, and C. P. Wong, “Recent Advances on a Wafer-Level Flip Chip Packaging Process,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 101–106, Las Vegas, NV, May 2000. 21. Lau, J. H., C. Chang, and S. W. Lee, “Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 1360–1368, Las Vegas, NV, May 2000. 22. Lau, J. H., S. Pan, and C. Chang, “Nonlinear Fracture Mechanics Analysis of WaferLevel Chip Scale Package Solder Joints with Cracks,” Proceedings of IMAPS Microelectronics Conference, pp. 857–865, Boston, MA, September 2000.



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Chapter One

23. Lau, J. H., T. Chung, S. W. Lee, C. Chang, and C. Chen, “A Novel and Reliable WaferLevel Chip Scale Package (WLCSP),” Proceedings of SEMI Chip Scale International, pp. H 1–8, San Jose, CA, September 1999. 24. Jim, K. L., G. Faulkner, D. O’Brien, D. Edwards, and J. H. Lau, “Fabrication of Wafer Level Chip Scale Packaging for Optoelectronic Devices,” IEEE Proceedings of Electronic Components & Technology Conference, pp. 1145–1147, Las Vegas, NV, June 1999. 25. Lau, J. H., S. W. Lee, and C. Chang, “Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” ASME Trans., J. Electronic Packaging, 122(4): 311–316, December 2000. 26. Lau, J. H., “Cost Analysis: Solder Bumped Flip Chip Versus Wire Bonding,” IEEE Trans. Electronics Packaging Mfg., (23): 4–11, March 2000. 27. Lau, J. H., and C. Chang, “Overview of Microvia Technologies,” Circuit World, 26(2): 22–23, January 2000. 28. Lau, J. H., “Critical Issues of Wafer-Level Chip-Scale Package (WLCSP) with Emphasis on Cost Analysis and Solder Joint Reliability,” IEEE Proceedings of International Electronic Manufacturing Technology Symposium, pp. 33–46, San Jose, CA, October 2000. 29. Lau, J. H., S. Pan, and C. Chang, “Creep Analysis of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia BuildUp Printed Circuit Board,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, pp. 79–89, November 2000. 30. Lau, J. H., S. Pan, and C. Chang, “A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints,” in Packaging of Electronic and Photonic Devices, ASME Book No. HO1217, pp. 91–101, November 2000. 31. Gonzalez, C. G., R. A. Wessel, and S. A. Padlewski, “Epoxy-Based Aqueous Processable Photo Dielectric Dry Film and Conductive ViaPlug for PCB Build-Up and IC Packaging,” IEEE Trans. Adv. Packaging, 22(3):385–390, August 1999. 32. Singer, A. T., “Microvia Cost Modeling,” Proceedings from IPC Works, p. S-14-2, Washington, DC, October 1997. 33. Burgess, L. W., and P. D. Madden, “Blind Vias in SMD Pads,” Printed Circuit Fabrication, 21(1): 28–29, January 1998. 34. Castro, A., “Chip Carrier Package Constructions Made Easier with Dry Film Photo Dielectric,” Proceedings from IPC Works, p. S01-5-1, Washington, DC, October 1997. 35. Thorne, J., “Using New Interconnection Technologies to Reduce Substrate Cost,” IPC EXPO ’98, p. S-10, Long Beach, CA, April 1998. 36. Nargi-Toth, K., and P. Gandhi, “Manufacturing Methodologies for High Density Interconnect Structures (HDIS),” CSI Technical Symposium, pp. 63–70, San Jose, CA, September 1998. 37. Nargi-Toth, K., “ITRI Microvia Technology Roadshow,” IPC EXPO ’99, p. S17-1, Long Beach, CA, March 1999. 38. Numakura, D. K., S. E. Dean, D. J. McKenney, and J. A. DiPalermo, “Micro Hole Generation Processes for HDI Flex Circuit,” HDI EXPO ’99, pp. 443–450, Mesa, AZ, August 1999. 39. Noddin, D. B., E. Swenson, and Y. Sun, “Solid State UV-LASER Technology for the Manufacture of High Performance Organic Modules,” Proceedings of 48th Electronic Components and Technology Conference, pp. 822–827, Seattle, WA, May 1998. 40. Cable, A., “Improvements in High Speed Microvia Formation Using Solid State Nd:YAG UV Lasers,” IPC EXPO ’97, p. S-2, San Jose, CA, March 1997. 41. Owen, M., “Production Experiences with CO2 and UV YAG Drilling,” IPC EXPO ’97, p. S7-3, San Jose, CA, March 1997. 42. Tessier, T. G. and J. Aday, “Casting Light on Recent Advancements in Laser Based MCM-L Processing,” Proceedings 1995 International Conference on Multichip Modules, pp. 6–13, Denver, CO, April 1995. 43. Illyefalvi-Vitez, Z., M. Ruszinko, and J. Pinkola, “Recent Advancements in MCM-L Imaging and Via Generation by Laser Direct Writing,” Proceedings of 48th Electronic Components and Technology Conference, pp. 144–150, Seattle, WA, May 1998. 44. Moser, D, “Sights Set on Small Holes? How to Get There with Lasers,” Printed Circuit Fabrication, 20–22, February 1997.




37

45. Owen, M., E. Roelants, and J. Van Puymbroeck, “Laser Drilling of Blind Holes in FR4/Glass,” Circuit World, 24(1): 45–49, 1997. 46. Contini, H. S., “Machining Lasers Find Niches by Solving Very Small Problems,” Photonics Spectra, 116–118, November 1997. 47. Illyefalvi-Vitez, Z. and J. Pinkola, “Application of Laser Engraving for the Fabrication of Fine Resolution Printed Wiring Laminates for MCM-Ls,” Proceedings of 47th Electronic Components and Technology Conference, pp. 502–510, San Jose, CA, May 1997. 48. Kobayashi, K., N. Katagiri, and S. Koyama, “Development of a Build Up Package with High Density of Circuits for High Pin Count Flip Chip Application,” IPC Expo 99, pp. S01–4, Long Beach, CA, March 1999. 49. Burgess, L. W., and F. Pauri, “Optimizing BGA to PCB Interconnections Using MultiDepth Laser Drilled Blind Vias-in-Pad,” Circuit World, 25(2): 31–34, 1999. 50. Raman, S., J. H. Jeong, S. J. Kim, B. Sun, and K. Park, “Laser (UV) Microvia Application in Cellular Technology,” IPC EXPO ’99, p. S17-6, Long Beach, CA, March 1999. 51. Schaeffer, R. D., “Laser Microvia Drilling: Recent Advances,” CircuiTree, 12, 38–44, 1998. 52. Petefish, W. G., D. B. Noddin, and D. A. Hanson, “High Density Organic Flip Chip Package Substrate Technology,” Proceedings of 48th Electronic Components and Technology Conference, pp. 1089–1097, Seattle, WA, May 1998. 53. Young, T. and F. Polakovic, “Thermal Reliability of Laser Ablated Microvias and Standard Through-Hole Technologies,” IPC Expo 99, pp. S17–2, Long Beach, CA, March 1999. 54. Gaku, M., H. Kimbara, N. Ikeguchi, and Y. Kato, “CO2 Laser Drilling Technology for Glass Fabrics Base Copper Clad Laminate,” IPC Expo 99, pp. S17–3, Long Beach, CA, March 1999. 55. Estes, W. E., T. R. Overcash, S. Padlewski, B. D. Neve, E. B. Murray, R. E. Anderson, R. C. Mason, and J. P. Lonneville, W. L. Hamilton and M. Periyasamy, “Photodielectric Dry Films for Ultra High Density Packaging,” SMI Proceedings, pp. 47–53, San Jose, CA, September 1997. 56. McDermott, B. J., and S. Tryzbiak, “The Practical Application of Photo-Defined Micro-Via Technology,” SMI Proceedings, pp. 199–207, San Jose, CA, September 1997. 57. Reboredo, L., “Microvias: A Challenge for Wet Processes,” IPC Expo 99, pp. S12–1, Long Beach, CA, March 1999. 58. Schmidt, W., “High Performance Microvia PWB and MCM Applications,” IPC Expo 99, pp. S17–5, Long Beach, CA, March 1999. 59. Ho, I., “What’s Up with SBU Technology?” Printed Circuit Fabrication, 64–68, March 1997. 60. Felten, J. J., and S. A. Padlewski, “Electrically Conductive Via Plug Material for PWB Applications,” IPC EXPO ’97, p. S6-6, San Jose, CA, March 1997. 61. Wessel, R. A., J. F. Henderson, J. J. Felten, S. Padlewski, M. A. Saltzberg, P. Charest, J. L. Parker, and P. T. Miscikowski, “A New Approach to Fill Conductive Vias in PCBs,” Printed Circuit Fabrication, 42–45, November 1997. 62. Nishii, T., S. Nakamura, T. Takenaka, and S. Nakatani, “Performance of Any Layer IVH Structure Multi-Layered Printed Wiring Board,” Proceedings of 1995 Japan IEMT Symposium, pp. 93–96, Omiya, Japan, December 1995. 63. Itagaki, M., K. Amami, Y. Tomura, S. Yuhaku, Y. Ishimaru, Y. Bessho, K. Eda, and T. Ishida, “Packaging Properties of ALIVH-CSP using SBB Flip-Chip Bonding Technology,” IEEE Trans. Adv. Packaging, 22(3): 366–371, August 1999. 64. Miyazawa, Y., T. Shirotsuki, H. Sugai, and Y. Yoneda, “Highly Accelerated Stress Test and Reliability Analysis for Build-up Circuits,” 1998 International Symposium on Microelectronics, pp. 430–434, San Diego, CA, November 1998. 65. Arike, S, K. Otsuka, N. Urasaki, A. Nakaso, K. Shibata, K. Kobayashi, K. Tsuyama, K. Suzuki, and H. Nakayama, “PWB using Mechanically Pre-drilled Metal Clad Film for IVH and Build-up PWB with Laser Via Hole for Semiconductor Package Substrate,” 1998 International Symposium on Microelectronics, pp. 425–429, San Diego, CA, November 1998.



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66. Enomoto, R., M. Asai, and N. Hirose, “High Density MLB using Additive and Buildup Process,” 1998 International Symposium on Microelectronics, pp. 399–404, San Diego, CA, November 1998. 67. Tsukada, Y., and S. Tsuchida, “Surface Laminar Circuit, a Low Cost High Density Printed Circuit Board,” Proc. Surface Mount Int., 1: 537–542, August 1992. 68. Tsukada, Y., Y. Mashimoto, T. Nishio, and N. Mii, “Reliability and Stress Analysis of Encapsulated Flip Chip Joint on Epoxy Base Printed Circuit Board,” Proceedings of ASME/JSME Joint Conference on Electronic Packaging, vol. 2, pp. 827–835, San Jose, CA, September 1992. 69. Tsukada, Y., Y. Maeda, and K. Yamanaka, “A Novel Solution for MCM-L Utilizing Surface Laminar Circuit and Flip Chip Attach Technology,” Proceedings of 2nd International Conference on Multichip Modules,” pp. 252–259, Denver, CO, April 1993. 70. Tsukada, Y., “Solder Bumped Flip Chip Attach on SLC Board and Multichip Module,” in Chip on Board, Lau, J. H., ed., van Nostrand Reinhold, New York, pp. 410–443, 1994. 71. Segawa, K., “Build-Up PWB with Laser-Processed Via Holes ‘VIL’,” 1998 International Symposium on Microelectronics, 419–424, San Diego, CA, November 1998. 72. Kohl, P. A., C. S. Patel, and K. Martin, “Wafer-Level Batch Packaging and the Interface Between ICs and PWBs,” Chip Scale International 99, p. B-1, San Jose, CA, September 1999. 73. Maniwa, R., “Finer Micro-Via PWB by Laser and Additive Process,” 1998 International Symposium on Microelectronics, 413–418, San Diego, CA, November 1998. 74. Fukuoka, Y., T. Oguma, and Y. Tahara, “New High Density Substrates with Buried Bump Interconnection Technology (B2it)—Design Features of Electrical and Thermal Performances with the Actual Applications,” 1998 International Symposium on Microelectronics, pp. 405–412, San Diego, CA, November 1998. 75. Jimarez, M., L. Li, C. Tytran, C. Loveland, and J. Obrzut, “Technical Evaluation of a Near Chip Scale Size Flip Chip/Plastic Ball Grid Array Package,” Proceeding of IEEE ECTC, pp. 495–502, Seattle, WA, June 1998. 76. Mawer, A., K. Simmons, T. Burnette, and B. Oyler, “Assembly and Interconnect Reliability of BGA Assembled onto Blind Micro and Through-Hole Drilled Via in Pad,” Proceedings of SMI Conference, pp. 21–28, San Jose, CA, August 1998. 77. IPC-2141, Controlled Impedance Circuit Boards and High-Speed Logic Design, April 1996. 78. Wadel, B., Transmission Line Design Handbook, Artech House, 1991.


Source: Microvias

Chapter

2 Conventional Printed Circuit Board Technologies

2.1 Introduction Modern electronic packaging has become very complex. Interconnections are pushed more into lower levels of packaging. The choice of which packaging technology to use is governed by many factors: cost, electrical requirements, thermal requirements, density requirements, and so on. Material also plays a very important role. All things considered, PCBs play very important roles in electronic packaging.1 Since the invention of printed circuit technology by Dr. Paul Eisner in 1936, several methods and processes have been developed for manufacturing PCBs of various types. Most of these have not changed significantly over the years. However, some specific trends continue to exert major influences on the types of PCBs required and the processes that create them: 1. Computers and portable telecommunications equipment require higher-frequency circuits, boards, and materials, and also use more functional components that generate considerable amounts of heat that need to be extracted. 2. Consumer products have incorporated digital products into their design, requiring more functionality at ever lower total cost. 3. Products for all uses continue to get smaller and more functional, driving the total circuit package itself to become more dense, causing the PCBs to evolve to meet these needs.

39


Conventional Printed Circuit Board Technologies

40

Chapter Two

These will be discussed in this chapter, along with the traditional board structures and processes. The terms printed circuit board, PCB, and board will be used synonymously. Also, the words laminate, substrate, and panel will be used interchangeably.

2.2 Types of Printed Circuit Boards 2.2.1 Basic PCB classifications

PCBs may be classified in many different ways according to their various attributes. One fundamental structure common to all of them is that they must provide electrical conductor paths that interconnect components to be mounted on them. There are two basic ways to form these conductors: 1. Subtractive. In the subtractive process, the unwanted portion of the copper foil on the base substrate is etched away, leaving the desired conductor pattern in place. 2. Additive. In the additive process, formation of the conductor pattern is accomplished by adding copper to a bare (no copper foil) substrate in the pattern and places desired. This can be done by plating copper, screening conductive paste, or laying down insulating wire onto the substrate on the predetermined conductor paths. The PCB classifications given in Fig. 2.1 take into consideration all these factors, i.e., fabrication processes as well as substrate materials. The use of Fig. 2.1 is as follows: ■

Column 1 shows the classification of PCBs by the nature of the substrate.

■

Column 2 shows the classification of PCBs by the way the conductor pattern is imaged.

■

Column 3 shows the classification of PCBs by their physical nature.

■

Column 4 shows the classification of PCBs by the method of conductor formation.

■

Column 5 shows the classification of PCBs by the number of conductor layers.

■

Column 6 shows the classification of PCBs by the existence or absence of PTHs.

■

Column 7 shows the classification of PCBs by production method.




Figure 2.1

41

Classification of printed circuit boards.

2.2.2 Other classifications of PCBs

One of the major issues that has arisen with the ever higher speed and functionality of components used in computers and telecommunications is the availability of materials for the PCB substrate that are compatible with these product and process needs. This includes the stresses on substrate material created by more and longer exposure to soldering temperatures during the assembly process, as well as the need to match the coefficient of thermal expansion for components and substrate. The resultant search has found new materials, both organic and nonorganic based.



42

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Organic substrates consist of layers of paper impregnated with phenolic resin or layers of woven or nonwoven glass cloth impregnated with epoxy resin, polyimide, cyanate ester, BT resin, etc. The usage of these substrates depends on the physical characteristics required by the application of the PCB, such as operating temperature, frequency, or mechanical strength. Nonorganic substrates consist mainly of ceramic and metallic materials such as aluminum, soft iron, and copperinvar-copper. The usage of these substrates is usually dictated by the need for heat dissipation, except for the case of soft iron, which provides the flux path for flexible disk motor drives. PCBs may be classified into two other categories, graphical and discrete-wire boards, based on the way they are manufactured. A graphical PCB is the standard PCB and the type that is usually thought of when PCBs are discussed. In this case, the image of the master circuit pattern is formed photographically on a photosensitive material, such as treated glass plate or plastic film. The image is then transferred to the circuit board by screening or photoprinting the artwork generated from the master. Due to the speed and economy of making master artwork by laser plotters, this master can also be the working artwork. Discrete-wire boards do not involve an imaging process for the formation of signal conductors. Rather, conductors are formed directly onto the wiring board with insulated copper wire. Wire-wrap® and Multiwire® are the best known discrete-wire interconnection technologies. Because of the allowance of wire crossings, a single layer of wiring can match multiple conductor layers in the graphically produced boards, thus offering very high wiring density. However, the wiring process is sequential in nature and the productivity of discrete-wiring technology is not suitable for mass production. Despite this weakness, discrete-wiring boards are in use for some very high-density packaging applications. Another class of boards is made up of the rigid and flexible PCBs. Whereas boards are made of a variety of materials, flexible boards generally are made of polyester and polyimide bases. RigiFlex boards, a combination of rigid and flexible boards bonded together, have gained wide use in electronic packaging (see Fig. 2.2). Most RigiFlex boards are three-dimensional structures that have flexible parts connecting the rigid boards, which usually support components; this packaging is thus volumetrically efficient. 2.2.3 Graphically produced boards

The majority of boards produced in the world are graphically produced. There are three alternative types: single-sided boards, double-sided boards, and multilayer boards.




Figure 2.2

43

RigiFlex printed circuit board.

2.2.3.1 Single-sided boards (SSBs). Single-sided boards have circuitry on only one side of the board and are often referred to as print-and-etch boards because the etch resist is usually printed on by screen-printing techniques and the conductor pattern is then formed by chemically etching the exposed, and unwanted, copper foil. This method of board fabrication is generally used for low-cost, highvolume, and relatively low-functionality boards. In the Far East, for example, the majority of SSBs are made of paper-based substrates for lowest cost, with the most popular grade of paper-based laminate being



44

Chapter Two

XPC-FR, which is a flame-retardant phenolic material that is also highly punchable. In Europe, FR-2 grade paper laminate is the most popular substrate for SSBs because it emits less odor than XPC-FR when placed in high-voltage, high-temperature environments, such as inside a television set chassis. In the United States, CEM-1 material, which is a composite of paper and glass impregnated with epoxy resin, is the most popular substrate for SSBs. While not as low-cost as XPC-FR or FR-2, CEM-1 has gained popularity because of its mechanical strength and also because of the relative unavailability of paper phenolic laminates. 2.2.3.2 Double-sided boards (DBs). By definition, double-sided boards have circuitry on both sides. They can be classified into two categories: with and without through-hole metallization. The category of throughhole metallization can be further broken into two types: plated throughhole (PTH) and silver through-hole (STH).2 Metallization of holes by copper plating has been practiced since the mid-1950s. Because PCB substrate is an insulating material, and therefore nonconductive, holes must be metallized first before subsequent copper plating can take place. The usual metallization procedure is to catalyze the holes with palladium catalyst followed by electroless copper plating. Then, thicker plating is done by means of galvanic plating. Alternately, electroless plating can be used to plate all the way to the desired thickness, which is called additive plating. The biggest change in the manufacturing process of double-sided PTH boards, and also of multilayer boards (MLBs), is the use of direct metallization technologies. In this case the electroless copper process is eliminated. The hole wall is made conductive by palladium catalyst, carbon, or polymer conductive film, and then copper is deposited by galvanic plating. The elimination of electroless copper, in turn, allows the elimination of environmentally hazardous chemicals, such as formaldehyde and EDTA, which are two main components of electroless copper-plating solutions. STH boards are usually made of paper phenolic materials or composite epoxy paper and glass materials, such as CE-1 or CE-3. After double-sided copper-clad materials are etched to form conductor patterns on both sides of the panel, holes are formed by drilling. Then the panel is screened with silver-filled conductive paste. (Instead of silver, copper paste can also be used.) Since STH boards have a relatively high electrical resistance compared with PTH boards, the application of STH boards is limited. However, because of their economic advantage (the cost of STH boards is usually one-half to two-thirds that of functionally equivalent PTH boards), their application has spread to high-volume, low-cost products such as audio equipment, floppy disk controllers, car radios, remote controls, etc.




45

2.2.3.3 Multilayer boards (MLBs). By definition, MLBs have three or more circuit layers (see Fig. 2.3). Main applications of MLBs used to be confined to sophisticated industrial electronic products. Now, however, they are the mainstream of all electronic devices, including consumer products such as portable video cameras, cellular phones, and audio discs. As personal computers and workstations become more powerful, mainframe computers and supercomputers are being replaced in many applications by these smaller machines. As a result, the use of highly sophisticated MLBs, which have layer counts over 70, is being reduced, but the technology to produce them is proven. At the other end of the layer-count spectrum, thin and high-density MLBs with layer counts between four and eight are mainstream. The drive toward thinner MLBs will continue and is made possible by the continuing concurrent advancement of materials and equipment to handle thin core materials. As PCBs have had to address the issues of higher speed, higher density, and the rise of surface-mount components that use both sides, the need to communicate between layers has increased dramatically. At the same time, the space available for vias has decreased, causing a continuing trend toward smaller holes, more holes on the board, and the decline of the use of holes that penetrate the entire board, which use space on all layers. As a result, the use of buried and blind vias has become a standard part of multilayer board technology, driven by the need for this increased package density (Fig. 2.3). One of the immediate issues that arise from these trends is the problems of drilling and the associated cost of this fabrication step. Printed circuit boards, which once were stacked three high on a drilling machine, must be drilled individually, and the number of holes per board has risen to accommodate the need for vias. This has caused a major problem for fabricators, who find that a lack of drilling capacity is creating a big demand on funds for additional machines, while

Figure 2.3

Cross section of multilayer board with buried via

holes.



46

Chapter Two

the cost of drilling continues to increase dramatically. Therefore, alternate methods for creating vias are being developed. These pressures will be ongoing, and therefore the process listed here, or some equivalent, will undoubtedly become more important as the drive toward miniaturization continues and drilling individual holes becomes less and less practical.

2.3 Base Materials 2.3.1 Copper-clad laminates

It is important to understand the types of copper-clad laminates that are available, how they are made, where they are used, and the advantages and disadvantages of each before selecting the material most suitable for the intended application. Many types of copper-clad materials are available (see Fig. 2.4). The copper-clad laminates most widely used in the manufacture of printed circuit boards, however, are FR-2, CEM-1, CEM-3, FR-4, FR-5, and GI. These are the materials that are primarily discussed in this section. The FR-2 laminates are composed of multiple plies of paper that have been impregnated with a flame-retardant phenolic resin. The major advantages of FR-2 laminates are their relative low cost and their good electrical and punching qualities. FR-2 is typically used in

Figure 2.4

PCB designations and materials.




47

applications where tight dimensional stability is not required, such as in radios, calculators, toys, and television games. FR-3, the other all-paper-base laminate, is also made of multiple plies of paper that have been impregnated with an epoxy-resin binder. The FR-3 laminate has electrical and physical properties that are higher than those of the FR-2 but lower than those of epoxy laminates that have woven glass cloth as a reinforcement. FR-3 is used to manufacture printed circuits used in consumer products, computers, television sets, and communication equipment. CEM-1 is a composite material that has a paper core impregnated with epoxy resin. Woven glass cloth impregnated with the same resin covers the two surfaces. This construction allows the material to have punching properties similar to those of FR-2 and FR-3, with electrical and physical properties approaching those of FR-4. CEM-1 is used in smoke detectors, television sets, calculators, and automobiles as well as in industrial electronics. CEM-3, a composite of dissimilar core material, uses an epoxy-resinimpregnated nonwoven fiberglass core with epoxy-resin-impregnated woven glass cloth surface sheets. It is higher in cost than CEM-1, but it is more suitable for plated through-holes. CEM-3 is used in applications such as home computers, automobiles, and home entertainment products. FR-4 laminates are constructed on multiple plies of epoxy-resinimpregnated woven glass cloth. It is the most widely used material in the printed circuit board industry because its properties satisfy the electrical and mechanical needs of most applications. Its excellent electrical, physical, and thermal properties make it a well-suited material for high-technology applications. It is used in aerospace, communications, computers and peripherals, industrial controls, and automotive applications. FR-5 laminates are composed of multiple plies of woven glass cloth impregnated with mostly polyfunctional epoxy resin. The glass transition temperature Tg is typically 150 to 160°C, as compared with FR-4, which has a glass transition temperature of 125 to 135°C. FR-5 is used where higher heat resistance is needed than is attainable with FR-4, but not where the very high thermal properties of GI-type materials are needed. GI-type materials are composed of multiple plies of woven glass cloth impregnated with a polyimide resin. The materials have a glass transition temperature in excess of 200°C, which virtually eliminates “drill smear” caused by heat during the drilling process. It also exhibits excellent mechanical properties and z-axis dimensional stability at high temperatures. GI materials have a lower interlaminar bond strength



48

Chapter Two

than the epoxy systems; therefore, care should be taken during drilling and routing. 2.3.2 Considerations in glass transition temperature Tg

Tg has become a measure of how well a laminate resin system resists softening from heat. When the Tg temperature is reached, the resin changes from its “glassy” state and causes changes in the laminate’s properties. Tg is not a measure of the resin’s melting point, but rather a point at which molecular bonds begin to weaken enough to cause a change in physical properties (dimensional stability, flexural strength, etc.). Its value is determined by the intersection of the two slopes of the temperature-property-change curve (Fig. 2.5a). FR-4 epoxy exhibits a Tg of 125 to 135°C and polyimide 260 to 300°C. Although the Tg value is a measure of the toughness of a material under heating, it is not meant for comparison purposes once the Tg

TE21

Property change

Tg Temperature

(a)

Property change

Resin x Resin y Tg(x)

Tg(y)

Temperature

(b)

(a) Determination of glass transition temperature Tg. (b) General features of Tg. Figure 2.5




49

is exceeded. For example, materials with a higher Tg are desirable because they maintain their stability over a wider temperature range up to the Tg. However, once the Tg is exceeded, the material properties of a high-Tg resin could change much more rapidly than those of a material with a low Tg. At a higher temperature, the lower-Tg material may often exhibit superior properties (Fig. 2.5b). 2.3.3 Lamination process 2.3.3.1 Material preparation. The base raw material—paper, glass matte, woven glass cloth, quartz, or Kevlar®—is impregnated or coated with resin. The resin is then polymerized to a point suitable for storage and final pressing. A machine called a treater or coater is used for treating the material. First the material passes through a dip pan of resin, where it is impregnated, and then through a set of metering rollers (squeeze rollers) and a drying oven. The oven is air-circulating or infrared and can be up to 120 ft long. Most of the volatiles such as solvents in the resin are driven off in the oven, and the resin is polymerized to what is called a B-stage. This semicured material is also known as prepreg. The prepreg is dry and nontacky. The treater illustrated in Fig. 2.6 is a vertical treater that runs principally woven glass cloth; horizontal treaters impregnate mainly paper and glass matte. Rigid process control is applied during treating so that the ratio of resin to base material, the final thickness of the prepreg, and the degree of resin polymerization can be monitored. Beta-ray gauges may compare the raw material with the final semicured product and automatically adjust the metering rollers above the resin dip pan so that the proper

Figure 2.6

Features of the vertical tower processing system.



50

Chapter Two

ratio of resin to base material is maintained. The degree of polymerization of the resin is controlled by the treater air temperature, the air velocity, and the speed at which the material passes through the treater. The prepreg material is usually stored in an area where the temperature and humidity are controlled below 21°C and 35 percent relative humidity (RH), respectively, until the time of the pressing operation. Each roll or stack of prepreg is tagged with the processing date and the test results for resin content, gel time, resin flow, cured thickness, and volatile content. 2.3.3.2 Copper inspection. Besides the base material and resin, the other principal component of copper-clad laminates is copper foil. Today, almost all copper is electrodeposited rather than rolled. Each roll of copper is inspected by the laminator for visual surface quality and pinholes, and a sample is taken for trial pressing. The trial pressing sample is tested for copper peel strength, solder blister resistance, copper oxidation after heat exposure, and general surface quality. The side of the foil to be pressed against the prepreg is treated with an alloy to improve adhesion of the copper to the laminate. The alloy is a proprietary coating, usually of zinc or brass, in a controlled ratio to enhance the chemical bond between the copper and the resin. 2.3.3.3 Laminate buildup. Most laminators build up their sheets in clean room facilities with filtered air-conditioned systems to control the temperature and humidity as well as to keep dust particles away from the copper and prepreg during buildup. Electrostatic attraction of dust particles to the treated material and copper before pressing is a source of contamination in the laminate and a source of pits and dents on the copper surface of the finished laminate. During the buildup operation, the copper foil is first laid against a large polished stainless steel press plate. Then a number of sheets of prepreg are laid on top of the copper. The number of layers depends on the desired thickness of the laminate and the characteristics of the prepreg material. Some of the art of laminating comes in balancing all of these variables to produce a final dense material to relatively close tolerances. The final sheet of copper foil is placed on top of the prepreg if the material is to have copper on both sides. If copper is desired on only one side of the laminate, a release film such as Tedlar® replaces one of the sheets of copper. 2.3.3.4 Laminate pressing. The press plates, with the material, are removed from the buildup room and stacked in a large, multiopening press. Several sheets are pressed into each press opening, with typical presses being capable of molding 80 sheets 36 × 48 in. to 250 sheets 48 × 144 in., 1⁄16 in. thick. The presses, which are hydraulic, are capable of developing pressure in excess of 1000 lb/in2. Steam is a typical heat source. It is released into the press platens until the platens reach the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.



51

uniform laminating temperature. The packs or books of material are then loaded into the press, and the desired pressure is applied so that the material is cured into a final homogeneous sheet. To ensure that all of the sheets in the pack or book receive the desired state of cure, thermocouples are placed in several sheets in the press. A timer automatically records time against a preset cure cycle. When the desired stage of cure is achieved, the steam is automatically cut off and cold water is pumped through the press platens until the material reaches approximately 27°C. The material is then removed from the press, and the edges are trimmed from the sheet to remove irregular resin flow areas. 2.3.3.5 Laminating quality control system. Statistical process control methods are used to verify that each step in the manufacturing process is controlled. Figure 2.7 outlines laminate traceability. Each press load is tested according to the appropriate sampling plan to ensure that the material will meet customer requirements. Each sheet is then identified as to manufacturer, appropriate specification, and load or lot number. Most manufacturers retain samples of material from each load for at least 1 year to enable them to effectively check any processing problems or questions that may result from the use of that lot in the field. Periodically, laminators are required to run a complete set of physical and electrical tests as set forth by the National Electrical Manufacturers Association (NEMA) or MIL-P-13949. 2.3.4 Grades and specifications

The grades and specifications of some standard laminates are presented in Tables 2.1 to 2.3. The most common method of designating copper-clad materials is described in MIL-P-13949 and illustrated in Fig. 2.8. As an example, GFN-0620-CN/CI-A-2-A means no coloring in flame-retardant glass-epoxy laminate, 0.062 in thick, 1⁄2-oz/ft2 copper, drum side out, on one side, and 1-oz/ft2 copper, drum side out, on the other side, Grade A pits and dents, Class 2 thickness tolerance, and Class A warp and twist.

Figure 2.7

Flow chart for laminate quality control.


GP

GH

GI

FR-5

None

None

FR-6

G-11

None

CEM-3

GE

None

CEM-1

GF

PX

FR-3

FR-4

None

FR-2

G-10

None

XXXPC

Polyimide

Epoxy

Epoxy

Epoxy

Epoxy

Polyester

Epoxy

Epoxy

Epoxy

Phenolic

Phenolic

Glass

Glass

Glass

Glass

Glass

Glass matte

Glass matte

Paper-glass composite

Paper

Paper

Paper

Base

Military designation MIL-P-13949F

NEMA grade

Resin system

Standard Materials for Printed Circuit Boards

TABLE 2.1

Color

Translucent dark brown

Translucent

Translucent

Translucent

Translucent

Opaque white

Translucent

Opaque tan

Opaque cream

Opaque brown

Opaque brown

Description

Polyimide resin, glass laminate with high continuous operating temperature and high property retention at temperature, low z-dimensional expansion

High-temperature epoxy-glass with flame-resistant resin system with strength and electrical retention at elevated temperatures

High-temperature epoxy-glass with strength and electrical retention at elevated temperatures

Epoxy-glass with self-extinguishing resin system

Epoxy-glass, general purpose

Polyester, random glass fiber, flame-resistant, designed for low-capacitance or high-impact applications

Epoxy resin nonwoven glass core with woven glass surfaces, self-extinguishing, punchable with properties similar to FR-4

Epoxy resin paper core with glass on the laminate surface, self-extinguishing, economic fabrication of paper base, mechanical characteristics of glass

Epoxy resin, paper base with flame-resistant resin system, cold punching, and high insulation resistance

Phenolic paper, punchable, with flame-resistant (self-extinguishing) resin system

Phenolic paper with punchability at or above room temperature Conventional Printed Circuit Board Technologies


52



TABLE 2.2

53

Materials for High-Frequency Applications

NEMA grade

Military Designation MIL-P13949

GT

GX

Resin system

Base

Color

Description

GT

TFE

Glass

Opaque brown

Glass fabric base, PTFE (Teflon) resin, controlled dielectric constant

GX

TFE

Glass

Opaque brown

Glass fabric base, PTFE (Teflon) resin dielectric constant with closer controlled limits than GT

Polystyrene

Glass

Opaque white

Polystyrene cast-resin base for low-dissipation-factor applications

Cross-linked polystyrene

Glass

Opaque white

Polyethylene cast base, radiation cross-linked for low dissipation factor

The conditioning designations used to describe the environment in which tests were run are as follows: ■

Condition A. As received; no special conditioning

■

Condition C. Humidity conditioning

■

Condition D. Immersion conditioning in distilled water

■

Condition E. Temperature conditioning

■

Condition T. Test conditioning

Conditioning procedures are designated in accordance with the following: ■

First, a capital letter indicating the general condition of the specimen to be tested, i.e., as received or conditioned to humidity, immersion, or temperature.

■

A number indicating the duration of the conditioning, in hours, follows.

2.3.5 Mechanical properties of laminates

The principal characteristics usually required in the mechanical design of printed boards are outlined here. If a specific test is required, the test is listed under a particular heading. Whenever they are available, the minimum standards set forth in MIL-P-13949 or NEMA standards for industrial laminates are used.


Military designation MIL-P-13949

None None None None

None None None None None

None

None None None

None

XXXPC FR-2 FR-3 FR-4

XXXPC FR-2 FR-3 FR-4 CEM-1

CEM-3

FR-2 FR-3 FR-4

FR-4

Epoxy

Phenolic Phenolic Epoxy

Epoxy

Phenolic Phenolic Phenolic Epoxy Epoxy

Phenolic Phenolic Phenolic Epoxy

Resin system Base

Color

Opaque brown Opaque brown Opaque brown Translucent

Adhesives

Glass

Translucent

Swell and etch

Paper Paper Glass, glasspaper composite

Sacrificial aluminum-clad

Opaque brown Opaque brown Opaque brown Translucent Opaque tan, blue, white Translucent

Seeded and coated Paper Paper Paper Glass Paper-glass composite Glass-matte composite

Paper Paper Paper Glass

Materials for Additive Circuit Processing

NEMA grade

TABLE 2.3

This laminate is used in the commercially available swell-and-etch additive process. The epoxy-glass laminate has a 0.0015-in.thick resin-rich surface and a specially designed surface for swell-and-etch chemicals.

These laminates are the patented sacrificial additive process. They are clad on two sides with a specially anodized aluminum foil. The sacrificial aluminum cladding makes the laminate surface acceptable for the additive process.

These laminates are used in the patented seeded and coated processes. They are seeded with a small percentage of the catalytic seeding agent dispersed throughout the resin system and are coated with a catalyzed adhesive.

These laminates are designed for use with additive processes using adhesive bonding techniques.

Description



54



Figure 2.8

55

Designation of Cu-clad laminates.

2.3.5.1 Thickness tolerance. Nominal thicknesses and tolerances should be specified per MIL-P-13949. At least 90 percent of the area of a sheet should be within the tolerance given, and at no point should the thickness vary from the nominal by a value greater than 125 percent of the specified tolerance. Cut sheets less than 18 × 18 in. should meet the applicable thickness tolerance in 100 percent of the area of the sheet. Class of tolerance is as specified in the type designation. For nominal thicknesses not shown in this table, the tolerance for the next greater thickness shown applies. The nominal thicknesses include metal foil except in the case of microwave materials, which are without foil. (See Table 2.4.) 2.3.5.2

Flexural strength. Method: ASTM D 790. Unit of value: lb/in2.

This test is measure of the load that a beam will stand without fracture when supported at the ends and loaded in the center, as shown in Fig. 2.9. (See Table 2.5.) 2.3.5.3 Coefficient of thermal expansion (CTE). Method: ASTM D 696 (at 130°F). Unit of value: in./in./°F. The coefficient of thermal expansion (Table 2.6) is the change in length per unit of length per degree change in temperature. The coefficient may vary in different temperature ranges, so the temperature range must be specified.

TABLE 2.4

Nominal Thickness and Tolerance for Laminates (MIL-P-13949F) Class 1

Thickness (in. × 10−3)

PX paper base only

Glassreinforced

Class 2 glassreinforced

Class 3 glassreinforced

Class 4 for microwave application

0010 to 0045 0046 to 0065 0066 to 0120 0121 to 0199 0200 to 0309 0310 to 0409 0410 to 0659 0660 to 1009 1010 to 1409 1410 to 2400

— — — — — ⫾0045 ⫾0060 ⫾0075 ⫾0090 ⫾0120

⫾0010 ⫾0015 ⫾0020 ⫾0025 ⫾0030 ⫾0065 ⫾0075 ⫾0090 ⫾0120 ⫾0220

⫾00075 ⫾0010 ⫾0015 ⫾0020 ⫾0025 ⫾0040 ⫾0050 ⫾0070 ⫾0090 ⫾0120

⫾0005 ⫾00075 ⫾0010 ⫾0015 ⫾0020 ⫾0030 ⫾0030 ⫾0040 ⫾0050 ⫾0060

— — — — — ⫾002 ⫾002 ⫾002 ⫾0035 ⫾0040



56

Chapter Two

Figure 2.9

Flexural strength test.

2.3.5.4 Water absorption. Unit of value: Percent water absorption is the ratio of weight of water absorbed by the material to the weight of the dry material. (See Table 2.7.) 2.3.5.5 Flammability. According to Underwriters Laboratories, materials tested for flammability are classified 94V-0, 94V-1, and 94V-2. For material flame ratings, see Table 2.8. Definitions of those classifications, as tested by the Underwriters Laboratories flammability procedure, are outlined as follows. ■

94V-0. Specimens must extinguish within 10 s after each flame application and a total combustion of less than 50 s after 10 flame applications. No samples are to drip flaming particles or have glowing combustion lasting beyond 30 s after the second flame test.

■

94V-1. Specimens must extinguish within 30 s after each flame application and a total combustion of less than 250 s after 10 flame applications. No samples are to drip flaming particles or have glowing combustion lasting beyond 60 s after the second flame test.

■

94V-2. Specimens must extinguish within 30 s after each flame application and a total combustion of less than 250 s after 10 flame applications. Samples may drip flame particles, burning briefly, and no specimen will have glowing combustion beyond 60 s after the second flame test.

TABLE 2.5

Flexural Strength (Condition A, Minimum Average psi) Material

Lengthwise

Crosswise

XXXPC FR-2 FR-3 FR-4 FR-5 FR-6 G-10 G-11 CEM-1 CEM-3 GT GX GI

12,000 12,000 20,000 60,000 60,000 15,000 60,000 60,000 35,000 40,000 15,000 15,000 50,000

10,500 10,500 16,000 50,000 50,000 15,000 50,000 50,000 28,000 32,000 10,000 10,000 40,000




TABLE 2.6

57

Coefficient of Thermal Expansion

(CTE) Coefficient, × 10−5 Material

Lengthwise

Crosswise

Ordinary applications XXXP XXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

1.2 1.2 1.2 1.3 1.1 1.0 1.0 1.0 1.0 1.0 1.0 1.0

1.7 1.7 2.5 2.5 1.7 1.5 1.0 1.5 1.5 1.5 1.5 1.2

High-frequency applications GT GX Polystyrene Cross-linked polystyrene

TABLE 2.7

1.0 1.0 7.0 5.7

2.5 2.5 7.0 5.7

Water Absorption (Condition D 24/23)

Material

⁄32 in.

1

⁄16 in.

1

⁄32 in.

3

Ordinary applications XXXP XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

1.3 1.3 1.3 1.0 0.50 0.50 0.50 0.50 0.50 0.50

1.0 0.75 0.75 0.65 0.30 0.25 0.40 0.25 0.25 0.25 0.25 1.0

0.85 0.65 0.65 0.60 0.25 0.20

0.10 0.10 0.05 0.01

0.09 0.09

0.20 0.20 0.20 0.20


0.20 0.20



58

Chapter Two

TABLE 2.8

Grade XXXPC FR-2 FR-3 CEM-1 CEM-3

■

Flammability Classifications UL classification

Grade

UL classification

94HB 94V-1 94V-0 94V-0 94V-0

G-10 FR-4 G-11 FR-5 FR-6

94HB 94V-0 94HB 94V-0 94V-0

94HB. Specimens are to be horizontal and have a burning rate less than 1.5 in./min over a 3.0-in. span. Sample must cease to burn before the flame reaches the 4-in. mark.

2.3.6 Electrical properties of laminates 2.3.6.1 Surface resistivity. The effect of humidity on the surface resistance of glass-epoxy was measured by using the American Society for Testing Materials (ASTM) three-electrode circular pattern, starting with 97.5 percent RH at 40°C and decreasing the humidity to 64 percent. The results, shown in Fig. 2.10, indicate that the surface resistivity decreases logarithmically with an increase in humidity at approximately the rate of 1 decade per 20 percent humidity change. 2.3.6.2 Dielectric strength. (Perpendicular to the laminations at 23°C.) Method: ASTM D 149. Unit of value: V/mil. Dielectric strength is the ability of an insulation material to resist the passage of a disruptive discharge produced by an electric stress.3 A disruptive discharge is measured by applying 60-Hz voltage through the thickness of the laminate, as shown in Fig. 2.11. All the tests are run under oil. In the shorttime test the applied voltage is increased at a uniform rate of 0.5 kV/s. In the step-by-step test, the initial voltage is 50 percent of the shorttime breakdown voltage; thus, the voltage is increased in increments according to a predetermined schedule of 1-min intervals. The test val-

Figure 2.10

Surface resistivity vs. relative humidity.




Figure 2.11

59

Dielectric strength test.

ues for dielectric strength vary with the thickness of the material, the form and size of electrodes, the time of application of the voltage, the temperature, the frequency and wave shape of the voltage, and the surrounding medium. Step-by-step data for 1⁄16-in.-thick material are as shown in Table 2.9. 2.3.6.3 Dielectric breakdown. (Parallel to the laminations at 23°C.) Method: ASTM D 149. Unit of value: kV. Condition D 48/50. Dielectric breakdown is the disruptive discharge measured between two electrodes (Pratt and Whitney No. 3 taper pins) inserted in the laminate on 1-in. centers perpendicular to the laminations.4 All tests are run under oil. The short-time and step-by-step tests are performed as in the test for dielectric strength perpendicular to laminations. Step-by-step data on 1⁄16-in.-thick material are given in Table 2.10. 2.3.6.4 Dielectric constant (permitivity). Method: ASTM D 150. Unit of value: dimensionless. Dielectric constant is the ratio of the capacitance of a capacitor with a given dielectric to the capacitance of the same capacitor with air as a dielectric, as illustrated in Fig. 2.12. The dielectric constant is a measure of the ability of an insulating material to store electrostatic energy. It is calculated from the capacitance as read TABLE 2.9

Material XXXP FR-2 FR-3 CEM-1 CEM-3

TABLE 2.10

Dielectric Strength Data V/mil

Material

V/mil

740 740 550 500 500

G-10 G-11 FR-4 FR-5 GI

510 600 500 500 750

Dielectric Breakdown Data

Material

kV

Material

kV

XXXPC FR-2 FR-3 FR-6 CEM-1 CEM-3

15 15 30 30 40 40

G-10 FR-4 G-11 FR-5 GT GX

40 40 40 40 20 20



60

Chapter Two

Dielectric constant test.

Figure 2.12

on a capacitance bridge, the thickness of the specimen, and the area of the electrodes. It varies with temperature, humidity, and frequency. (See Table 2.11.) 2.3.6.5 Dissipation factor. (Average at 1 MHz.) Method: ASTM D 150. (See Fig. 2.13.) Unit of value: dimensionless. In an insulating material, the dissipation factor is the ratio of the total power loss, in watts, in the material to the product of the voltage and current in a capacitor in which the material is a dielectric. It varies over a frequency range. (See Tables 2.12 and 2.13.)

2.4 Imaging/Drilling/Plating/Etching 2.4.1 Imaging processes

The imaging process comprises several sequential steps that together allow for the metal interconnect pattern to be formed on a bare substrate. The steps themselves are interactive and it is a balance between them that allows for the reproduction of a master pattern into a metal TABLE 2.11

Materials

Permittivity Permittivity at 1 MHz (Condition D 24/23)

Ordinary applications XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

4.1 4.5 4.3 4.4 4.6 4.1 4.6 4.6 4.5 4.3 4.8 High-frequency applications

GT GX Polystyrene Cross-linked polystyrene

2.8 2.8 2.5 2.6




Figure 2.13

61

Dissipation factor test.

pattern with high fidelity. The success of the steps in the sequence is dependent on the materials or chemicals used, but also to a large extent on the equipment utilized. Thus, again there is a balance of various factors needed in order to obtain a stable, reproducible, and highyield/low-cost process. The details of the chemistry and the equipment used to perform it will be outlined, and as often as possible the tradeoffs of various choices will be highlighted so that both the inexperienced process engineers and the designers and procurers of PCBs who need an overview of the process considerations will be able to proceed in their work to obtain a manufacturable product. The process sequence for imaging is given in Fig. 2.14, where the resulting pattern is used for either subtractive or additive metal pattern transfer. The details of these processes are given in the subsequent chapters. In a generic sense the process involves the coating of a polymeric material onto the substrate of interest, patterning the TABLE 2.12

Dissipation Factors Dissipation factor at 1 MHz

Materials

Condition A

Condition D 24/23

Ordinary applications XXXP XXXPC FR-2 FR-3 CEM-1 CEM-3 FR-6 G-10 FR-4 G-11 FR-5 GI

0.028 0.028 0.024 0.024 0.027 0.020 0.020 0.018 0.018 0.019 0.019 0.020

0.03 0.03 0.026 0.026 0.028 0.022 0.028 0.019 0.020 0.020 0.028 0.030


0.005 0.002 0.00012–0.00025* 0.0004–0.0005†

0.006 0.002 0.00012–0.00066* 0.0005

* Condition A, 10 MHz. † Condition A, 10 GHz.



62

Chapter Two

TABLE 2.13

Permittivity and Dissipation Factors of FR-4 (Condition D 24/23) Frequency

Dielectric constant

Dissipation factor

100 Hz 1,000 Hz 10,000 Hz 100,000 Hz 1 MHz 10 MHz 100 MHz 1,000 MHz 10,000 MHz

4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40

0.009 0.012 0.015 0.018 0.020 0.022 0.024 0.025 0.025

material either by depositing the initial layer in a patterned fashion (screen printing) or by the use of a master of the pattern desired and a photographic sequence of exposing and developing for copying the master to the polymer coating. The choice between these patterning sequences is governed by the feature size desired. Larger features (8 mil and greater) can be very economically formed by screen printing. Feature sizes smaller than 8 mil are formed using a photolithographic process.

Clean Surface

Apply Photoresist

Expose Photoresist

Develop Photoresist Image

Pattern Transfer Image (plating or etching)

Strip Photoresist Process flow chart of photolithography.

Figure 2.14




63

2.4.1.1 Photosensitive materials. The photosensitive polymeric systems used in the PCB industry are used either as liquids directly or as dry films of an initial liquid solution. Both types of materials are used widely and are excellent solutions for a variety of processing requirements. In addition, these materials may function in a photographic sense in a positive or negative tone. The difference is illustrated in Fig. 2.15 and arises from the distinct chemical compositions and in the photoinitiated reaction within the film itself. The key factor to the functioning of these materials is that their solubility in the developing solution changes on exposure to light. In the case of the common negative-acting systems, the photoreaction provides a polymer network that is less soluble in the developing solution by promoting cross-linking between one or more of the components in the polymeric matrix. The resulting molecular weight change in the exposed region of the film reduces the material’s solubility, and it is these regions that remain after development of the image. In the positive-acting systems, the chemistry is very often that of the novalac resin-based materials utilized by the semiconductor industry. Upon irradiation, the material becomes more soluble than the original, and it is these exposed regions that are removed in the developer solution. There are many reports of the inherent differences in product yield associated with either positive- or negative-acting material. Positive-acting materials are often considered to provide for a higher-yield process. This could be due to the division of lines and spaces on the phototool; spaces are a greater area than lines. For a positive-acting material, the spaces are clear and these large areas are less sensitive to defect-causing debris. In contrast, for negative phototools, a small size and amount of contaminant will be reproduced as an open in the conductor. It is unfortunate that there are few materials that don’t have some other obvious attribute such as thickness, coating method, etc., which will alter the yield other than their photographic tone. There is a large variety of materials commercially available, but how does one determine which is likely to perform best for a given application? There are several key factors to consider—several technical and many economic, the latter of which are unique to each manufacturing facility. The technical decision sequence is summarized in Fig. 2.16. The foremost consideration is the end use of the pattern; the material must have chemical compatibility with the subsequent pattern transfer steps. The chemical nature of these steps, especially the solution pH, must be distinct from the photoresist’s unique solubility. Only then can the photoresist perform as an accurate mask for pattern transfer. Another key factor is the nature of the substrate itself in terms of topography and surface features; i.e., is the mask required to cover or tent plated through-holes or tooling features, and must it conform to



64

Chapter Two

Figure 2.15 Procedures for positive and negative tone photoresists.

existing circuitry? This consideration will dictate whether dry film or liquid material is appropriate and, in some instances, the required tone of the photoresist material. Equally important is the required product feature dimension and allowable variation. This is usually specified in terms of line width and spacing with a given allowable variation on the nominal. Since these product parameters are for the final conductor features, some estimate of the photoresist processing contribution to this value must be established. Each material has its inherent contrast or ability to switch from exposed to unexposed. This, along with the resist thickness, phototool, and light source used for exposure, governs the feature dimensions that can be defined with a given material. For the materials used in the PCB industry, the following rule usually holds: the minimum line width definable in production is usually 0.5 to 1.0 mil greater than the photoresist thickness. New process sequences have demonstrated improvements beyond this traditional barrier.5 Of a more practical nature, the material chosen must have adhesion to the underlying substrate. There are many approaches to promoting adhesion between dissimilar materials, but there must be an inherent compatibility.




Figure 2.16

65

Selection criteria for photoresist materials.

2.4.1.2 Equipment alternatives. The process steps for obtaining a usable image are all interactive and, therefore, the equipment plays a very large role in the success of the overall process. For each step there are numerous options. The choice between options is governed by the product specifications with respect to layer thickness and feature size and, in some instances, by the chosen photoresist, in addition to the economic factors that are unique to each installation. The alternative equipment for each process step will be described with criteria by which to compare them. Cleanliness considerations. Cleanliness is of concern for the entire photolithography process. This includes yellow room contamination level



66

Chapter Two

(cleanliness class), solution filtration, equipment cleanliness class, and product handling. The relative importance of each of these must be established for the product feature dimensions. The sensitivity of the photolithographic sequence to the size and location of contamination can be determined, and then the appropriate level of cleanliness can be instituted and maintained.6–8 In addition, equipment to remove contamination from flat surfaces—either panels or equipment—can be used throughout the processing sequence. These sticky rollers are available as freestanding equipment and as handheld items. Preclean. This step provides the foundation for all the others since only an appropriately cleaned substrate allows for good adhesion between the photoresist and the substrate and for the remainder of the process to be successful.9 All laminates arrive at the imaging area dirty and, depending on the type of contamination, the exact process sequence is chosen. Contamination—epoxy dust—from trimming and processing the laminate itself is removed by mechanical cleaning. The surface copper is either foil or foil with electroless or electroplated copper. The foil is treated with an antitarnishing agent of chromium and zinc, which is removed for reproducible imaging results. Not only are contaminants removed, but also the texture or surface roughness of the copper is altered to promote mechanical adhesion between the base copper and the photoresist. The extent of this texturing is measured by the usual parameters for surface roughness where the height and spacing of the topography is quantified by profilometer measurements (see Fig. 2.17). Chemical cleanliness can be determined in a variety of ways. Wetting is often tested using a water break test or more analytically in terms of contact angle where a low value is desirable. In addition, analytical techniques can be used to evaluate the chemical composition of the surface (Auger and x-ray photoelectron spectroscopy [XPS]) (Table 2.14). Photoresist apply. The numerous choices for applying the photoresist are tied in most instances to the photoresist choice. The discussion here will be divided between liquid and dry film methods. Irrespective of the method chosen, the cleanliness of the operation—both the equipment and the clean room—and the handling of the product are important. It is also advisable to minimize the handling at this stage with the use of automated operation. Specifically, in-line equipment, with the preclean step and automatic loading and unloading, is advised. Expose. In this key step for image formation, the master pattern is aligned to and exposed in the product so that the relief image can be subsequently developed. The elements of the process are the phototool, the registration of the phototool to the panel, and the light source used for exposure. The choices for phototools (film or glass) differ as to sharp-




Figure 2.17

67

Surface roughness parameters.

ness of the transition from opaque to clear, the pattern’s dimensional stability, and the substrate absorption of the exposing light. The panel is aligned either mechanically with pins holding the phototool with respect to the product or optically with alignment features dictating the movement of the phototool and product. The alignment requirements are interrelated with those achieved at composite lamination and drilling. The registration scheme is contained within the exposure equipment. The light source alternatives include contact printing with either a collimated or uncollimated light source, proximity printing, projection printing, and laser direct imaging.10 The latter three methods separate the phototool from the substrate and are expected to have an increased product yield due to reduced contamination. No phototool is used in laser direct imaging since the laser beam exposes the image based on the design data. TABLE 2.14

Sample Initial Preclean 1 Preclean 2

Copper Surface Chemical Composition as Measured by XPS % Cu

%O

%C

12 6

46 19 10

24 68 70

%N

% Zn

% Cr

16

12

14



68

Chapter Two

Develop. In this process step, the solubility difference between the exposed and unexposed portions of the photoresist is realized. Immersion in an appropriate solvent results in a relief image of the master pattern. The process conditions are adjusted to alter the clearing time for dissolving the unexposed or negative materials or exposed or positive ones. The total dwell time is set to approximately double the time to clear, commonly called a 50 percent breakpoint. Additional variables include the solution temperature, agitation, and concentration. The resulting photoresist images should be distinct with vertical sidewalls. Failure to accomplish this is an indication that the previous process step setpoints require adjustment. Images larger than the phototool dimension result from incomplete development, overexposure, or poor contact at expose. If the images are smaller than expected, then the exposure dose is too low or development is too aggressive. Distorted images can be caused by problems with precleaning, application, or exposure. The common equipment for developing is spray conveyorized, either horizontally or vertically. Additives to the developer solution are required in many instances to prevent foaming. The solution is filtered to remove resist particles and either replenished with fresh solution to maintain a consistent dissolved resist value and solution concentration or operated continuously for a certain amount of product and replaced. Waste developer solution is treated (aqueous and semiaqueous) or distilled and reused (solvent). Rinsing is also important to stop the dissolution reaction. In addition, water with a high mineral content often improves the aqueous photoresist resist image and the conductor yield. Tank systems can also be used, especially for materials with a wide process latitude. Often, ultrasonic agitation is used to aid in the dissolution. There are additional steps that improve the resist removal in the line channels and the conductor formation yield. Plasma treatment has been used effectively to improve product yield, especially with respect to shorts in a print-and-etch process. In addition, for some aqueousdevelopable dry films, a heat treatment after exposure improves the space definition, and spaces equal to or smaller than the resist height have been resolved.5 Thus, these process steps ensure that tight resolution requirements can be met. Strip. The photoresist is removed from the substrate after it has functioned in the pattern transfer step. The equipment used for this process step is identical to that used for developing. The removal is accomplished by swelling and dissolving the material. Some materials are removed in sheets or as small particles and, depending on the equipment design, can be accommodated. Often brushes and ultrasonic




69

agitation are added to aid in the resist removal. As with developing, filtration is important to keep fresh solution reaching the part and the nozzles of a spray tool clean. For stripper chemistries that oxidize the copper, an antitarnishing agent is often added to either the stripping or rinsing solution. 2.4.1.3 Design for manufacturing. A high-yield conductor formation process can be enhanced by the optimization of several design features. These concern the conductor dimensions and the process used to form them. Specifically, these are the process sequence to be used (etched or plated metal), the division of conductor pitch between line and spacing, and the PTH capture land size and shape. Process sequence: etch vs. plate considerations. For a given product conductor dimension, there is often a question of the appropriate process sequence. Although the capabilities of imaging and the pattern transfer step dictate the overall limitations, the decision depends on the unique capabilities of the manufacturing line to be used. Some general considerations can clarify the true issues for most production situations. The photoresist patterns for plating and etching are very distinct. For etching, a thin photoresist is desirable to maximize the etchants’ attack in the line channel. Thus, the resolution of the photoresist does not limit the process, since very small spaces can be resolved in liquidcoated materials. The challenge for conductor formation resides with the etching. Depending on the metal thickness and the etching equipment, it can be very difficult to remove the copper in tight spaces. Therefore, the key criterion defining the capabilities of the print-andetch process is the minimum spacing cleared as constrained by the final conductor height and the etchant chemistry and equipment. For plated products, the photoresist thickness must be greater than or equal to the final thickness of the conductor wire and it must be possible to clear a photoresist space equal to the final conductor width. These fine spaces are challenging when the conductor height increases. The photoresist resolution is on the order of its thickness, so that for 1-mil-thick plating, it would be difficult to resolve a photoresist space smaller than 1.5 mil, irrespective of the final conductor spacing. Thus, the challenge for plating is to resolve the fine spaces in thicker photoresist materials and then to ensure that the plating solution wets the bottom of the narrow photoresist channels. Thus, in choosing the conductor formation process, the thickness of the conductor and the line width and spacing are the key parameters. A generalized relationship between them is found in Fig. 2.18. It is important that this type of plot is known for the production area before the process sequence is determined.



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2

1.8

1.6

Cu Thickness (mils)

1.4 1.2

1 0.8

0.6 0.4

0.2 0 2

4

5

9

10

Line / Space Pitch (mils)

Figure 2.18

Typical manufacturing line process capability to aid in sequence decisions.

Line and space division for a fixed pitch. It is common for product designs to have a fixed pitch, whether it refers to the I/Os for direct chip or packaging attachment or to the spacing between PTHs. This space is often divided equally between conductors and spacing. As mentioned previously, for either additive or subtractive processing, the photoresist and pattern transfer process yield can be enhanced by avoiding the resolution limitations of each sequence. In subtractive conductor formation, an etch factor is used to obtain straighter sidewalls and improved line width control. If lines and spaces are equally allocated, then the photoresist must resolve a smaller space than a line. This is difficult, except when very thin coatings are used in conjunction with one of the enhancement schemes.5 Thus, it is a higher-yielding process to have larger spaces than lines. For additive processing, the spacing in the photoresist is the limiting factor. After pattern transfer, this will become the line. In this instance, equal lines and spaces are more acceptable, but based on the photoresist concerns, a wider final line than space is preferred. At the same time, it is desirable to increase the spacing for reduced incidence of line shorting, which translates to a wider “line” in the photoresist. The former is usually more important. Therefore, for both process sequences there is preferably balance between line width and spacing. PTH capture pad size and shape for optimum line formation. Just as the conductor line and spacing can be optimized, the PTH capture pad shape and size can be altered to further increase the yield. The absolute




71

dimension of the feature is dictated by the placement accuracy of the drilling process and the overall dimensional stability of the product. The feature is sized to ensure that the PTH and conductor are connected. There are varying specifications as to the extent of capture that is required. Depending on the direction and magnitude of the dimensional stability and the drill wander and accuracy, the shape required to capture the PTH can be changed. This would reduce the size of this feature in at least one direction. In consequence, the spacing between the line and pad increases. Since this location is a change to the nominal line-to-line spacing, the narrowing of the channel results in shorting between the features in both print-and-etch and additive processes. In the former case, it is more difficult to clear the space, and in the latter, the narrower resist width is often underplated. Thus, when possible, an elongated pad will benefit the final conductor yield. 2.4.2 Drilling processes

The purpose of drilling printed circuit boards is twofold: (1) to produce an opening through the board that will permit a subsequent process to form an electrical connection between top, bottom, and sometimes intermediate conductor pathways; and (2) to permit through-theboard component mounting with structural integrity and precision of location. The quality of a drilled hole through a printed circuit board is measured by its interface with the following processes: plating, soldering, and forming a high-reliability nondegrading electrical and mechanical connection. It is possible to drill holes meeting these requirements with high productivity, consistency, and yield. The elements of this process are materials, such as laminates, drill entry, and backup, and drills; processes including machine parameters, techniques, and operating personnel; and control evaluation of hole quality, drills, and process machinery. When all these elements are properly developed and implemented, high-quality printed circuit board holes are a natural result. Such holes can be plated directly, eliminating remedial processes of deburring, desmearing, and etchback, and resulting in process simplification, higher yields, and lower costs. The interaction and practice of elements shown in Fig. 2.19 can optimize the drilling process for the fabrication of printed circuit boards. While all of the elements shown are interdependent, it is hole quality and location accuracy that ultimately steer decisions on feeds and speeds, material choices, and productivity.



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Figure 2.19

Essential elements of successful PCB drilling.

2.4.2.1 Drills. Drills for making holes in printed circuit boards are usually made of tungsten carbide. This is due to interrelated needs of cost, wear properties, machinability, and handling properties. No other material has proved to be as suitable. The design of a drill is just as important as the materials used. The design and the wear of the drill affect its drilling temperature, ability to remove chips, tendency to create entry and exit burrs, and smoothness of the hole wall (all directly related to hole quality). Figure 2.20 shows a typical drill bit geometry. The point angle is usually between 90° and 110° for paper-base materials and between 115° and 130° for glass-base materials. By far the most common point angle

Figure 2.20

Typical drill bit geometry.




73

used in drilling is 130°. The flute or helix angle determines the drill’s ability to remove chips from the hole. Helix angles vary from 20° to 50°. A 20° angle provides fast chip removal with poor cutting efficiency. A high helix angle (50°) creates a smaller material plastic zone but yields slower chip removal, as shown in Fig. 2.21, angle A. A helix angle of 30° is a good compromise between a small plastic zone and quick chip removal. This compromise minimizes drilling temperature. Figure 2.20 also shows an important characteristic of highperformance drills described as a relieved land. Increases in temperature during drilling can also be caused by the amount of drill surface area in direct contact with the hole wall. To minimize this surface area, most manufacturers remove material just behind the margin or cutting area to reduce friction and thus lower the temperature of drilling. Other geometries being equal, the narrower the margin, the cooler the drilling temperature. The length of the margin relieved area also affects the drilling temperature. Figure 2.22 shows the relief area in a (a) partially relieved, (b) fully relieved, and (c) spade-head drill. A drill design with a larger relief area will drill cooler because of the smaller drill surface area in contact with the hole wall. Other factors being equal, the partially relieved design will drill hotter than the fully relieved design and the spade head design will drill cooler than the fully relieved design. The surface finish of the drill is important; that is, the smoother the surface, the cooler the drilling. Surface finishes lower than 4 µin. should be used. The volume of empty space in the drill flutes is another important design consideration. The greater the open volume, the higher the capacity of the drill to remove chips efficiently. Conversely, greater volume (thinner center web) implies a weaker drill that is more prone to breakage. Figure 2.23 shows (a) a standard microdrill and (b) a step design that strengthens the drill without increasing the web thickness by adding a step in the diameter reduction between the drill shank and the fluted area. The added step strengthens the drill bit by

Schematic diagram for the cutting process of drill bit.

Figure 2.21



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Figure 2.22 Drill bit flute designs. (a) Partially relieved. (b) Fully relieved. (c) Spade-head.

reducing the abruptness of the transition between the flute and the shank of the drill bit. In general, the best drill designs are those that drill with the lowest drill temperature. Drills that drill cooler have a good surface finish, thin webs, no geometrical defects or chips, sharp cutting edges, and durable carbide. In addition, the best operating parameters for drills are those that also minimize drill temperatures. Finally, as drills wear, they drill hotter and hole quality decreases. Run length must be carefully determined. It should not be assumed that all manufactured drills are of equal quality. Differences in design, manufacturing processes, surface finish, raw materials, and consistency vary widely and should be evaluated prior to the purchase of production quantities of drills. 2.4.2.2 Laminates. All laminates are manufactured to specifications that take into account electrical and physical properties. Ease of drilling ordinarily is not considered by laminate engineers. It is left up to the printed circuit board fabricator to develop the correct parameters to drill laminates for the best hole quality. The various types of laminates are formed from several resins and supporting materials. These vary from common to exotic types that differ in the ease with which they may be drilled. From easiest to most difficult to drill, some commonly available laminates are G-10 epoxy-glass, FR-4 epoxy-glass, multifunctional epoxy, polyimide-glass, phenolic-paper, Teflon-glass, polyimide-quartz, and exotics.




Figure 2.23

75

Geometry of microdrill bits. (a) Standard design. (b) Step

design.

Where cloth is used, the weave and fiber thickness affect drill wander. The finer the fiber, the less drill wander. In addition, laminate is produced with various thicknesses of copper, either in double-sided laminates or in multilayers. The ratio of the copper thickness to total thickness of the laminate changes the optimum drilling parameters so that feeds and speeds should be adjusted based on the ratio of copper to substrate. Dimensional stability, warping, bow, and twist specifica-



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tions are important to the drilling operations. For example, laminates that are not flat drill with high burrs. The thickness of the laminate to be drilled is controlled by the smallest drill diameter to be used. The controlling factor is 10 times the drill diameter. For example, the maximum material thickness for a 0.020-in.diameter drill is 0.200 in. As drill depth increases, the drill’s deviation from true center increases. For minimum-sized drills, the deviation increases by 0.001 in. for each 0.0625 in. of laminate thickness. For example, a 0.020-in.-diameter drill drilling through 0.200-in. laminate provides deviations of 0.005 in. If this is unacceptable, laminate thickness must be reduced. Good multilayers and double-sided laminates should not require prebaking before drilling to fully cure the laminate. Uncured laminate is unacceptable from the supplier. Prebaking is often practiced to stress-relieve the laminate. Edges of laminate panels for drilling should be free of burrs so that stacking can occur with good interlaminate contact. To produce quality holes for each series or type of laminate, the following generalities can be stated: ■

The higher the Tg of the laminate, the better.

■

The laminate should be flat, uniform in thickness, and smooth, and it should exhibit high copper peel strength.

■

Prebaking the laminate before drilling helps dimensional stability but does not “correct” uncured resin.

■

The storage of laminate under controlled conditions of temperature and humidity is necessary. These conditions should be the same as the ambient conditions surrounding the drilling machine.

■

The more glass cloth layers and the higher the glass-to-resin ratio, the more drill wear is obtained per hole drilled.

■

The thicker the glass cloth diameter, the greater the drill wander.

■

Laminates that are not flat will cause interlaminate entry and exit burring.

■

The more abrasive the supporting fibers (quartz, for example), the greater the drill wear and the shorter the drilling run per drill.

■

Harder and thicker copper shortens the life of the drill.

Laminate panels are normally stacked three high between entry and backup materials for 0.062-in.-thick double-sided laminates and one or two high for multilayers. They are placed in a pinning machine that drills a minimum of two holes and inserts tooling pins to hold the stack firmly.




77

Foreign materials and burrs on the laminate must be removed. This is true for entry and backup materials as well. The stack must be tight. Loose pinning causes burrs and poor registration. Poor pin alignment can cause bowed stacks. Pins and bushings should be checked for wear, and drilling machine operators should be instructed on the importance of cleanliness when handling laminates and entry and backup materials. 2.4.2.3 Drilling machines. Drilling machine types vary over a wide range, from single-spindle, manually operated, bottom-drilling types, using templates for locating holes, to multiple-drill-station, computer numerically controlled (CNC), automatic machines that accept stacks of laminate, eject laminate, and change tools automatically. Machines are designed to accept laminate panels of various sizes, up to 24 × 24 in. Costs range from $10,000 at the low end to $500,000 for the largest and most automated machines. The type of machine needed depends on production capacity and the type of process design. Whatever the type, it is important to prepare and design the machine’s environment. Machines should be located in temperature- and humiditycontrolled, dust-free environments. Floors should be adequately designed to carry the machine weight. Machines should be isolated from any external vibrations. Isolated electrical power and grounding are necessary. Rigorous and well-planned maintenance programs are important. The items in the following list are most important, but the list is not inclusive.

1. The actual revolutions per minute and feed rate of the machine should be determined by an independent method. Do not rely on the machine readout. 2. Vacuum systems should be maintained at high flow rates and full efficiency. It is better to overdesign this function. Filters should be replaced regularly. 3. Spindle cooling systems, coolant, and heat exhangers should be checked and kept clean so that they work efficiently. 4. Spindles and collets should be kept clean at all times, using noncorrosive cleaners that keep thin protective films on the metallic parts. 5. Spindle runout should be kept to less than 0.0005 in. for heart of the range drilling and to less than 0.0002 in. for small hole drilling. 6. Drill bars, springs, and air-pressure seals should be carefully checked and maintained. 7. Pressure foot pressures should remain as high as the laminate will allow. 8. The z-axis alignment should be checked often.



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Machine manufacturers’ instructions regarding warmup before use should be followed carefully. Machines should be kept scrupulously clean. Dirt, chips, and debris left on machine tables should be removed with a vacuum cleaner. Never blow surfaces with compressed air to remove dirt. There are two aspects to drill wander: precision and accuracy. Only accuracy is affected by machine performance. The machine accuracy can be checked by drilling a square matrix of holes. The lines of holes can be defined in the x and y directions by comparing the mean lines to reference holes via regression analysis. These best-fit lines are compared with the desired lines the machine was instructed to place. From the slopes, the orthogonality of the machine can also be determined. Precision of drilling is dependent on many factors. One of these is spindle runout. The less the spindle runout, the greater the precision of drilling. With good spindles and a well-maintained machine, precision and accuracy are about equal for 0.0135-in.-diameter drills. These calculations are based on drilling 0.100 in. of laminate. Precision is also affected by chip load, roughness of laminate surface, entry material roughness, entry material construction, drill bit diameter, glass weave, glass thickness, drill design, and drill concentricity. 2.4.2.4 Accuracy and precision. It is important to understand how to produce not only high hole quality but also accurate, precisely drilled holes. Accuracy can be defined as how well the hole location agrees with the correct or target value. Precision is defined as how reproducible the hole location is. Accuracy problems are usually due to drilling machine problems. Machine problems are due to mechanical wear, loss of computer data, and electromechanical error. Precision problems are due to poor entry material, laminate thicknesses that are too great for the drill diameter, excessive chip loads, drill resonance, and excessive spindle runout. 2.4.3 Plating processes

A major part of manufacturing printed circuit boards involves wet process chemistry. The plating aspects of wet chemistry include deposition of metals by electroless (metallization) and electrolytic (electroplating) processes. Topics to be described here are electroless copper, electroplating of copper and resist metals, nickel and gold for edge connector (tips), tin-lead plating, and alternative coatings. Specific operating conditions, process controls, and problems in each area will be reviewed in this section. (See printed circuit plating flowchart in Fig. 2.24.) Two driving forces have had major influence on plating practices: the precise technical requirements of electronic products and the demands




79

Plating flowchart for printed circuit board manufacturing.

Figure 2.24

of environmental and safety compliance. Recent technical achievements in plating are evident in the capability to produce complex, highresolution multilayer boards. These boards show narrow lines (3 to 6 mil), small holes (12 mil), surface-mount density, and high reliability. In plating, such precision has been made possible by the use of improved automatic, computer-controlled plating machines, instrumental techniques for analysis of organic and metallic additives, and the availability of controllable chemical processes. Mil-spec-quality boards are produced when the procedures given here are closely followed. 2.4.3.1 Electroless copper plating.11–15 This series of chemical steps (after smear removal) is used to make panel side-to-side and innerlayer connections by metallizing with copper. The process steps needed include racking, cleaning, copper microetching, hole and surface catalyzing with palladium, and electroless copper. Typical steps are as follows:

1. Cleaner-conditioner. Alkaline cleaning is used to remove soils and condition holes.



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2. Microetch. This slow acid etching is used for removal of copper surface pretreatments, oxidation, and presentation of uniformly active copper. Persulfates and sulfuric acid–hydrogen peroxide solutions are commonly used. 3. Sulfuric acid. Used for removal of persulfate residues. 4. Predip. Used to maintain balance of the next step. 5. Catalyst (activator). Neutral or acid solutions of palladium and tin are used to deposit a thin layer of surface-active palladium in the holes and on the surface. 6. Accelerator (postactivator). Used for the removal of colloidal tin on board surfaces and holes. 7. Electroless copper. Alkaline-chelated copper reducing solution that deposits thin copper in the holes (20 to 100 µin.) and on surfaces. 8. Antitarnish. A neutral solution that prevents oxidation of active copper surfaces by forming a copper conversion coating. Selection from several types available depends on the type of image transfer desired. Operation and control of three bath types and the function of constituents are given in Tables 2.15 and 2.16. The following outline presents the typical steps in an electroless copper process: 1. Rack 2. Clean and condition 3. Water rinse 4. Surface copper etch (microtech) TABLE 2.15

Operation and Control of Electroless Cu Processes Low deposition

Medium deposition

Heavy deposition

Copper HCHO NaOH Temperature Air agitation Filtration Tank design

3 g/l 6–9 g/l 6–9 g/l 65–85°F Mild Periodic Static

Heater Panel loading Replenish mode

Teflon 0.25–1.5 ft2/gal Manual

2.0 g/l 3.3 g/l 8 g/l 115 ⫾ 5°F Moderate Continuous Overflow, separate sump Teflon 0.1–2.0 ft2/gal Automatic

Idle time, control Deposition time Thickness

70–85% 20 min 20 µin.

2.8 g/l 3.5 g/l 10–11 g/l 115 ⫾ 5°F Mild/moderate Continuous Overflow, separate sump Teflon 0.1–2.0 ft2/gal Manual or continuous Turn off heat 20 min 40–60 µin.

Turn off heat 20–30 min 60–100 µin.




TABLE 2.16

81

Function of Constituents for Electroless Cu Plating Constituent

Copper salt Reducing agent Complexer pH controller Additives

CuSO4 ⋅ 5 H2O HCHO EDTA, tartrates, Rochelle salts NaOH NaCN, metals, S, N, CN organics

Function Supplies copper Cu+2 + 2e → Cu0 Holds Cu+2 in solution at high pH; controls rate Controls pH (rate) 11.5–12.5 optimum for HCHO reduction Stabilize, brighten, speed rate, strengthen

5. Water rinse 6. Sulfuric acid (optional) 7. Water rinse 8. Preactivator 9. Activator (catalyst) 10. Water rinse 11. Postactivator (accelerator) 12. Water rinse 13. Electroless copper 14. Rinse 15. Sulfuric acid or antitarnish 16. Rinse 17. Scrub (optional) 18. Rinse 19. Copper flash plate (optional) 20. Dry 21. Release to image transfer 2.4.3.2 Copper electroplating. Because of its high electrical conductivity, strength, ductility, and low cost, copper is the most commonly used metal for the structure of a printed circuit board. In addition, copper is readily plated from simple solutions and is easily etched. MIL-STD275 states that electrode-posited copper shall be in accordance with MIL-C-104550, and shall have a minimum purity of 99.5 percent as determined by ASTM E 53. The minimum thickness shall be 0.001 in. (1 mil). Requirements for good soldering also indicate the need for 1 mil of copper and smooth holes.30 Copper plating is generally regarded as the slow step in manufacturing PCBs. New methods that cut plating



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times by as much as 50 percent include high-speed additives, pulse plating, and rapid solution-impingement machines.16–24 Key factors for uniform plating. To have day-to-day control and to achieve ductile, strong deposits and uniform copper thickness, the following controls are required:25–27

1. Maintain equipment following best practices, such as uniform air agitation in the tank, equal anode-cathode distances, rectifier connection on both ends of tank, and low resistance between rack and cathode bar. 2. Maintain narrow range control of all chemical constituents, including organic additives and contaminants. 3. Conduct batch carbon treatment regularly. 4. Control temperature at 70°F to 85°F. 5. Eliminate contaminants in tank from preplate cleaners, microetchants, and impure chemicals. 6. Plate at one-eighth to one-half of the conventional cathode current density when using thick boards (0.100 in.) with small holes (0.015 in.) and fine lines (6 to 8 mil). Acid copper sulfate. The preferred industrial process uses an acid copper sulfate solution containing copper sulfate, sulfuric acid, chloride ion, and organic additives. Using the proper additives, the resultant copper is fine-grained with tensile strengths of 50,000 lb/in2 (345 MPa), a minimum of 10 percent elongation, and a surface-to-hole thickness ratio of 1.2. (See Table 2.17.) Copper pyrophosphate. Once the standard of the industry, pyrocopper has been almost entirely replaced by acid copper, except in military and special applications. Pyrocopper continues to be used because of its resistance to cracking, high throwing power, and purity of deposits. The use of organic additives with pyrocopper is optional,28–30 but it is preferred because such additives provide wider tolerance of cracking control and improve deposit quality.31–34 The additive PY-61H, identified as dimercaptothiadiazole, is effectively controlled in production by CVS. (See Table 2.18.)

2.4.3.3 Solder (Sn-Pb) electroplating. Solder plate (Sn60-Pb40) is widely used as a finish plate on printed circuit boards. This process features excellent etch resistance to alkaline ammonia, good solderability after storage, and good corrosion resistance. Tin-lead plating is used for several types of boards, including tin-lead/copper, tin-lead/tin-nickel/copper, solder mask on bare copper (SMOBC), and surface-mount (SM). Fusing




TABLE 2.17

83

Operation and Control of Acid Cu Sulfate Conventional

Operating variables Copper Copper sulfate Sulfuric acid Chloride Additives Temperature Cathode current density Anodes† Type Composition Bags Hooks Length Anode current density Properties Composition Elongation Tensile strength

2–3 oz/gal 8–12 oz/gal 22–28 oz/gal 40–80 ppm As required 70–85°F 20–40 A/ft2*

High-speed 3–4.5 oz/gal 12–18 oz/gal 24–36 oz/gal 40–80 ppm As required 75–100°F 40–150 A/ft2

Bars or baskets Phosphorized 0.04–0.06% P Closed-napped polypropylene Titanium or Monel Rack length minus 2 in. 10–20 A/ft2 conventional; 25–50 A/ft2 high speed 99.8% (99.5% min, ASTM E 53) 10–25% (6% min, ASTM E8 or E 345) 40–50 kpsi (36 kpsi min, ASTM E 8 or E 345)

* A/ft2 refers to amperes per square foot and is sometimes expressed as ASF. † Operating anodes should have a thin, brown or black, easily removed film.

TABLE 2.18

Operation and Control of Cu Pyrophosphate

Operating conditions pH Copper Pyrophosphate Orthophosphate Ammonia (NH3) Ratio (pyro/Cu) Temperature Cathode current density Aqua ammonia PY 61-H* Anodes† Type Composition Bags Current density Hooks Length

8.1–8.5 copper 2.7–3.5 oz/gal 19.4–26.3 oz/gal 8 oz/gal max 0.2–0.3 oz/gal 7.5–8.0/L 115–125°F 20–35 A/ft2 As needed; about 1–2 qt/day 0.25–0.75 ml/(Ah) Control with CVS Bars or baskets OFHC copper Optional, none required 20–30 A/ft2 Titanium Rack length minus 2 in

* Product of M&T Chemicals, Rahway, N.J. † Operating anodes should have a thin golden or light tan film.



84

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is required on all tin-lead-plated surfaces. Thickness minimums are not specified. The preferred composition contains a minimum of 55 percent and a maximum of 70 percent tin. This alloy is near the tin-lead eutectic, which fuses at a temperature lower than the melting point of either tin or lead, and thus makes it easy to reflow (fuse) and solder. (The composition of the eutectic is 63 percent tin, 37 percent lead with a melting point of 361°F.) Fusing processes include infrared (IR), hot oil, vapor phase, and hot-air leveling for SMOBC. Plating solutions currently available include the widely used high-concentration fluoboric acidpeptone system, as well as low-fluoboric, nonpeptone, and a nonfluoboric organic aryl sulfonic acid process. These processes are formulated to have high throwing power and give uniform alloy composition.35 The sulfonic acid process has the advantage of using ball-shaped lead-tin anodes but is difficult to operate. Table 2.19 gives details of operation and control of two high-throw tin-lead (solder) baths. 2.4.3.4 Tin electroplating. Tin is used extensively for plating electronic components and PCBs due to its solderability, corrosion resistance, and metal etch-resist properties. The current MIL-STD-275 does not include tin plating, although earlier versions stated a required thickness of 0.0003 in. Specifications covering tin plating are MIL-T-10727 and MILP-38510, which say that tin must be fused on component leads. Acid tin sulfate is the most widely used system. Among the many processes available, some produce bright deposits for appearance and TABLE 2.19

Operation and Control of Sn-Pb Fluoborate High HBF4 /peptone

Lead Stannous tin (Sn+2) Free fluoboric acid Boric acid Additive Temperature Cathode current density Agitation Anodes Type Composition Purity Bags Hooks Length Current density

Low HBF4 /proprietary

1.07–1.88 oz/gal 1.61–2.68 oz/gal 47–67 oz/gal Hang bag in tank Use as needed by Hull cell and Ah usage 60–80°F 15–18 A/ft2

1.4–2.0 oz/gal 2.8–4.0 oz/gal 15–25 oz/gal Same

Solution circulation

Mechanical and solution circulation

70–85°F 10–30 A/ft2

Bar Sn60-Pb40 Federal Specification QQ-S-571 Polypro Monel Rack length minus 2 in. 10–20 A/ft2




85

corrosion resistance; others give matte deposits that can be fused as well as soldered after long-term heating. Tin sulfate baths are somewhat difficult to control, especially after prolonged use.36 Operation and control are given in Table 2.20. Nickel electroplating. Nickel plating is used as an undercoat for precious and nonprecious metals. For surfaces such as contacts or tips that normally receive heavy wear, the use of nickel under a gold or rhodium plate will greatly increase wear resistance. When used as a barrier layer, nickel is effective in preventing diffusion between copper and other plated metals. Nickel-gold combinations are frequently used as metal etch resists. Nickel alone will function as an etch resist against the ammoniacal etchants.37 MIL-STD-275 calls for a low-stress nickel with a minimum thickness of 0.0002 in. Low-stress nickel deposits are generally obtained using nickel sulfamate baths in conjunction with wetting (antipit) agents. Additives are also used to reduce stress and to improve surface appearance. Nickel sulfamate is commonly used both as undercoat for throughhole plating and on tips. Conditions given in Table 2.21 are applicable for through-hole and full-board plating. Nickel sulfate is typically plated with an automatic edge connector (tip) plating machine. Table 2.22 gives the operating conditions that apply to these systems. Nickel anodes are preferred in tip machines because the pH and the metal content remain stable. The pH will decrease rapidly when insoluble anodes are used. The pH should be maintained at 1.5 or higher with additions of nickel carbonate. Stress values are higher than in sulfamate baths with values of about 20 kpsi.

2.4.3.5

TABLE 2.20

Operation and Control of Acid Sn Sulfate

Operating conditions Tin Sulfuric acid Carrier, additives Temperature Cathode current density Current efficiency Solution color Plating rate Anodes Type Composition Bags Length Hooks Current density

2 oz/gal 10–12% by volume Replenish by Ah usage and spectrophotometry 55–65°F preferred 65–85°F hazy 20–35 A/ft2 100% Milky, white 0.3 mil @ 25 A/ft2 for 10 min Bars Pure tin Polypropylene Rack length minus 2 in. Monel or titanium 5–20 A/ft2



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TABLE 2.21

Operation and Control of Ni Sulfamate

Operating conditions pH Nickel As nickel sulfamate Nickel chloride Boric acid Additives Antipit Temperature Cathode current density Anodes Type Composition Purity Hooks, baskets Bags Length

3.5–4.5 (3.8) 10–12 oz/gal 43 oz/gal 4 oz/gal 4–6 oz/gal As required As required 130 ⫾ 5°F 20–40 ASF Bars or chunks Nickel Rolled depolarized, cast, or electrolytic; SD chips in titanium basket Titanium Polypro, Dynel, or cotton Rack length minus 2 in.

Early printed circuit board technology used gold extensively. In addition to being an excellent resist for etching, gold has good electrical conductivity, tarnish resistance, and solderability after storage. Gold can produce contact surfaces with low electrical resistance. Despite its continued advantages, the high cost of gold has restricted its major application to edge connectors (tips) and selected areas, with occasional plating on pads, holes, and traces (body gold). Both hard alloy and soft, pure gold are currently used. Plating solutions are acid (pH 3.5 to 5.0) and neutral (pH 6 to 8.5). Automatic plating machines for edge connectors and manual lines are in use. 2.4.3.6

Gold electroplating.38

Acid hard gold. To a large extent, acid golds are used for compliance to MIL-STD-275, which states that gold shall be in accordance with MILG-45204, Type II, Class 1. The minimum thickness shall be 0.000050 TABLE 2.22

Operation and Control of Ni Sulfate

Operating conditions pH Nickel Nickel chloride Boric acid Stress reducer Antipit Temperature Cathode current density Current efficiency

1.5–4.5 15–17 oz/gal 2–4 oz/gal (with soluble anodes) 3–4 oz/gal As required As required 130 ⫾ 5°F 100–600 A/ft2 65%

Anodes Composition

Nickel or platinized titanium




87

in. (50 µin.); the maximum shall be 0.000100 in. in areas that are to be soldered. A low-stress nickel shall be used between gold overplating and copper. Nonmilitary applications require 25 to 50 µin. Type II hard gold is not suited for wire bonding. These systems use potassium gold cyanide in an organic acid electrolyte. Deposit hardness and wear resistance are made possible by adding complexes of cobalt, nickel, or iron to the bath makeup. Automatic plating machines are being used increasingly because of the enhanced thickness (distribution) control, efficient gold usage, productivity, and quality. A comparison of automatic versus manual plating methods for edge connectors is given in Table 2.23. Pure 24-karat gold. High-purity 99.99 percent gold processes are used for boards designed for semiconductor chip (die) attachment, wire bonding, and plating solder (leaded) glass devices due to their solderability and weldability. These qualities comply with Types I and III of MIL-G-45204. The processes are neutral (pH 6 to 8.5) or acid (pH 3 to 6). Pulse plating is frequently used. Table 2.24 gives typical conditions for a neutral bath. Alkaline, noncyanide gold. Various processes for alloy and pure gold deposits are available. Solutions are based on sulfite-gold complexes

TABLE 2.23

Operation and Control of Acid Au-Co Alloy Manual

Gold content, troy oz/gal pH Cobalt content Temperature Solution density Replenishment per troy oz gold Current efficiency Agitation Anode-to-cathode distance Anodes, composition Cathode current density Thickness Deposition rate for 40 µin. Deposition composition Hardness

Automatic

0.9–1.1 4.2–4.6 800–1000 ppm 90–110°F 8–15 Be 8 Ah 50% 5 gal/min 2–3 in. Platinized titanium 1–10 A/ft2 40 ⫾ 10 µin. 3–6 min Au99.8-Co0.2 150 Knoop

1–3 4.5–5.0 800–1200 ppm 100–125°F 12–18 Be 6.5 Ah 60% 50 gal/min 1 ⁄4 in. Platinized titanium 50–100 A/ft2 40 ⫾ 2 µin. 0.3–0.6 min Au99.8-Co0.2 150 Knoop

Gold solution contaminants Metal Lead Silver Chromium Copper

Maximum ppm

Metal

Maximum ppm

10 5 5 50

Iron Tin Nickel

100 300 300–3000

Organics: tape residues, mold growth, and cyanide breakdowns.



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TABLE 2.24

Operation and Control of Neutral Pure Au

Gold content pH Temperature Agitation Solution density Replenishment Current efficiency Cathode current density Deposition rate for 100 µin., 5 A/ft2 Deposit composition Hardness

0.9–1.5 troy oz/gal 6.0–7.0 150°F Vigorous 12–15 Be 4 Ah/troy oz 90–95% 1–10 A/ft2 8 min Au99.99 60–90 Knoop

and arsenic additives and operate at a pH of 8.5 to 10.0. A decision to use this process is based primarily on the need for uniformity (leveling), hardness (180 Knoop), purity, reflectivity, and ductility. PCB use is limited to body plating, since the wear characteristics of sulfite-gold are not suitable for edge connector applications. The microelectronics industry uses these processes for reasons of safety and gold purity. Semiconductor chip attachment, wire bonding, and gold plating on semiconductors are possible applications and are enhanced by using pulse plating without metallic additives. 2.4.3.7 Silver electroplating. Silver is not widely used in the PC industry, although it finds applications in optical devices and switch contacts. Thicknesses of 0.0001 to 0.0002 in. (0.1 to 0.2 mil) in conjunction with a thin overlay of precious metal are specified. Silver plating should not be used when boards are to meet military specification. The reason for this is that, under certain conditions of electrical potential and humidity, silver will migrate along the surface of the deposit and through the body of insulation to produce low-resistance leakage paths. Tarnishing of silver-gold in moist sulfide atmospheres also produces electrical problems on contact surfaces due to diffusion of the silver to the surface. Another reason for the lack of acceptance of silver is that silver is plated from an alkaline cyanide bath, which is highly toxic. Bright plating solutions produce deposits with improved tarnish and corrosion resistance, relative freedom from porosity, and greater hardness. Plating troubles are usually related to black anodes and are due chiefly to solution imbalance, impurities in anodes, or solution roughness and pitting. Most metals to be plated, particularly the less noble metals, require a silver strike prior to silver plating to ensure deposit adhesion. 2.4.3.8 Immersion and electroless plating. Interest in these methods has increased due to their ability to produce coplanar (flat and even pad-to-




89

pad) surfaces required for fine-pitch, surface-mount devices (SMDs). In effect, these systems offer alternatives to hot-air solder leveling and tinlead alloy plate fusing. These processes are nonelectrolytic. Immersion tin. Immersion tin remains in widespread use to clean boards after etching, to cover copper trace edges with tin, and to act as a soldering aid. Self-limiting by nature, immersion tin processes work by displacement of the copper substrate. Deposits are thin—about 30 µin.—and must be processed immediately for effective results. Aging and thermal excursions cause the growth of the copper-tin intermetallics, which degrades solderability. In addition, tin readily forms a thick oxide when exposed to high temperatures and humidity. Electroless nickel. Electroless nickel (EN) followed by immersion or electroless gold also provides coplanar pad surfaces for SMDs. Electroless nickel is an autocatalytic process that utilizes a reducing agent such as hypophosphite or borohydride. Hypophosphite is the preferred choice for printed circuits. Deposition rate from a bath at pH 4.4 to 5.2 is 1⁄2 to 1 mil/h. The deposit contains 9 to 13 percent phosphorus. EN provides wear resistance, hardness, and excellent uniformity. Thicknesses of 50 to 250 µin. are specified when EN is used as a diffusion barrier between gold and copper. Immersion gold. Immersion gold systems deposit a maximum of 4 to 12 µin. of gold over nickel. Additional gold thickness must be applied by an electroless gold system.

Processes are reported that are capable of depositing 0.5 to 4 mil gold on immersion gold and gold-isolated circuitry by true electroless (autocatalytic) means. These systems contain organic amine boranes and borohydride reducing agents and cyanides and operate at a high pH and temperature. Deposition rate is 80 µin./h. Deposits meet the requirements of MIL-G-45204, Type III, Grade A with 99.9 percent purity and hardnesses of 90 KHN. They are suitable for edge connectors, semiconductor wire bonding, and die attachment. Electroless gold.39

Organic solderability preservatives (OSPs). The OSP processes (also known as prefluxes) are applied to bare copper surfaces after solder mask. Generally, these flat surfaces provide reliable solderability after thermal excursions such as adhesive curing, solder past reflow, and wave soldering, and provided they are adequately protected from oxidation. The OSP must be thermally stable and provide corrosion protection. Options for OSP systems include chemistry based on substituted azoles and rosin/resin bases. The coatings can generally be applied in immersion, spray, or flood mode. The coatings must bind to copper, preventing humidity and high temperatures from degrading solderabil-



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ity, and must be compatible with no-clean assembly fluxes. Proper surface preparation of the boards is required for OSP coatings to be effective. An alternative to this process is the use of benzotrizole. However, this is an extremely thin coating that gives very limited protection against oxidation and moisture. Improved protection can be achieved by following the benzotrizole step with posttreatment of a preflux. The preflux will prevent moisture penetration.40 Both solvent-based and water-based prefluxes are available. The following points should be considered when deciding on alternative coatings previously described. 1. Ease of assembly. Fine-pitch technology may require immersion tin or other electroless plating systems. Mixed-technology boards may be better suited for OSP coatings. 2. Rework and handling. OSP coatings are the easiest to rework but are the most fragile compared to metallic systems. OSPs can be removed with organic solvents or with 5 percent hydrochloric acid if the OSP is a water-based structure. 3. Shelf life. The shelf life of immersion, electroless-plated, and OSP coatings is not as long as that of leveled or fused solder surfaces. Storage time should be kept to a minimum for alternative coatings. 2.4.4 Etching processes

One of the major steps in the chemical processing of subtractive printed boards is etching (removal of copper) to achieve the desired circuit patterns. Etching is also used for surface preparation with minimal metal removal (microetching) during inner-layer oxide coating and electroless or electrolytic plating. Technical, economic, and environmental needs for practical process control have brought about major improvements in etching techniques. Batch-type operations, with their variable etching rates and long downtimes, have been replaced with continuous, constant-etch-rate processes. In addition, the need for continuous processing has led to extensive automation along with complete, integrated systems. The most common etching systems are based on alkaline ammonia, hydrogen peroxide–sulfuric acid, and cupric chloride. Other systems include persulfates, ferric chloride, and chromic-sulfuric acids. Process steps include resist stripping, precleaning, etching, neutralizing, water rinsing, and drying. This chapter describes the technology for etching high-quality, fine-line (0.004 to 0.006 in.) circuits in high volume at a lower cost, as well as closed-loop continuous processing, constant etch rates, control at high dissolved copper capacities, regenerationrecovery, less pollution, and increased safety. Problems of waste dis-




91

posal and pollution control have been minimized by adapting these principles. Typical procedures are given for etching organic (i.e., dry film) and metal-resist boards, and for inner layers. Strippers and procedures for resist removal are described based on resist selection, cost, and pollution problems. The properties of available etchants are also described in terms of finish plate compatibility, control methods, ease of control, and equipment maintenance. Other considerations include chemical and etchant effects on dielectric laminates, etching of thin-clad copper and semiadditive boards, SMOBC, equipment selection techniques, production capabilities, quality attained, and facilities. 2.4.4.1 General etching considerations and procedures. Good etching results depend on proper image transfer in both organic inner layer print-and-etch and plated-metal etch resists. Etch personnel must be familiar with screened, photosensitive, and plated resists commonly used. The etching of printed boards must begin with suitable cleaning, inspection, and pre-etch steps to ensure acceptable products. Plated boards also require careful and complete resist removal. The steps after etching are important because they are necessary to remove surface contamination and yield sound surfaces. This discussion considers the various types of resists and outlines typical procedures used to etch printed boards using organic and plated resist patterns. Screened resists. Screen printing is a common method for producing standard copper-printed circuitry on metal-clad dielectric and other substrates. The etch resist material is printed with a positive pattern (circuitry only) for copper etch-only boards or with a negative image (field only) when plated through-holes and metal resist are present. The type of resist material used must meet the requirements for proper image transfer demanded by the printer. From the metal etcher’s point of view, the material needs to provide good adhesion and etch solution resistance; be free of pinholes, oil, or resin bleed-out; and be readily removable without damage to substrate or circuitry. Typical problems are excessive undercutting, slivers, unetched areas, and inner-layer shorts in multilayer boards. In addition, conductor line lifting may occur when the copper-to-laminate peel strength is below specification. Hole plugging. Plugged-hole, copper-only boards use alkaline-soluble screen resists in a unique manner. The technique, called hole plugging, makes the SMOBC board possible. UV-cured screen resists. Ultraviolet-cured solventless systems are available for print-and-etch and plating applications. These products are resistant to commonly used acidic plating and etching solutions. Stripping must be evaluated carefully.



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Photoresists. Dry film and liquid photoresist materials are capable of yielding fine-line (0.004 to 0.006 in.) circuits needed for production of surface-mount circuit boards. Like screened resists, photosensitive resists can be used to print either negative or positive patterns on the metal-clad laminate. Although dry film and liquid materials differ in both physical and chemical properties, they will be considered together for our purpose. In general, both positive- and negative-acting resists offer better protection in acidic rather than alkaline solutions; however, negative-acting types are more tolerant of alkaline solutions. Negative resists, once exposed and developed, are no longer light-sensitive and can be processed and stored in normal white light. The positive resists remain light-sensitive even after developing and must therefore be protected from white light. Liquid photoresists, although less durable, are capable of finer line definition and resolution. Positive-acting resists are subject to the same problems as are negative-acting resists, although they are easier to remove cleanly, after exposure, from areas to be etched or plated. Plated etch resists. At present, the most extensive use of metal-plated resists is found in the production of double-sided and multilayer plated through-hole circuit boards. The most commonly used resists are solder plate (Sn60-Pb40), tin, nickel, tin-nickel, and gold. Silver is used to some extent for light-emitting and liquid crystal applications. Etching of the metal-resist-plated boards begins with removal of the resist using commercial solvents and strippers. Gold, solder, and tin resists must be handled carefully because they scratch very easily. Tinnickel alloy and nickel plate, however, are very hard and resistant to abrasion. The procedure after etching includes thorough water rinsing and acid neutralizing to ensure removal of etchant residues on the board surface and under the traces. Alkaline etchants are followed by treatment with proprietary ammonium chloride acidic solutions, ferric and cupric chloride with solutions of hydrochloric or oxalic acid, and ammonium persulfate with sulfuric acid. Alkaline cleaning is used for tinlead boards etched in chromic-sulfuric acid. Etchant residues not removed before drying or reflow result in lowered electrical resistance of the dielectric substrate and in poor electrical contact and soldering on the conductive surfaces.

Resist removal. The method used for resist stripping is important when a resist is selected. The effect on board materials, cost and production requirements, and compliance with safety and pollution standards must be taken into account. Both aqueous and solvent stripping systems are widely used.

2.4.4.2




93

Screen resist removal. Alkali-soluble resist inks are generally preferred. Stripping in the case of thermal and UV-curable resists is accomplished in 2 percent sodium hydroxide or in proprietary solutions. The resist is loosened and rinsed off with a water spray. Adequate safety precautions must be taken, since caustics are harmful. Conveyorized resist-stripping and etching machines use highpressure pumping systems that spray hot alkaline solutions on both sides of the boards. Single-sided boards and certain laminate materials such as the polyimides may be attached by alkaline strippers. Measling, staining, or other degradation is noted when strippers attack epoxy or other substrates. Screened vinyl-based resists are removed by a dissolving action in solutions of chlorinated, petroleum, or glycol ether solvents. Methylene chloride and toluene are used extensively in cold stripper formulations.41 Commercial cold strippers are classified according to their pH in a 10 percent stripper-water mixture. The most common strippers are acidic formulations that contain copper brighteners and swelling, dissolution, and water-rinsing agents. The usual procedure for static tank stripping involves soaking the coated boards in at least two tanks of stripper. Excessive time in strippers is to be avoided because of attack on the “butter” (top epoxy) coat, especially on print-and-etch or singlesided boards. Water is a contaminant in most cold strippers. Solvent stripping machines are commercially available. High-volume users save costs by using conveyorized systems equipped with reclamation and pollution-control facilities. Distillable cold strippers generally contain methylene chloride or trichloroethylene (TCE). Some heating may be used, but only in closed systems because of health and fire hazards. In all cases, proper safety, ventilation, pollution control, and certified waste disposal must be provided. Methylene chloride, toluene, and TCE are priority pollutants (TTO) regulated by the Environmental Protection Agency (EPA). Alternatives to methylene chloride are available as glycol ethers. Photoresist removal. Dry-film resists have been formulated for ease of removal in both aqueous-alkaline and solvent solutions. Strippers of each type are available for both static tank and conveyorized systems. Cold stripper solvent-type formulations are similar to those used on vinyl screen inks in which the primary solvent is methylene chloride.42 Aqueous-alkaline stripping results in undissolved residues of softened resist films. These residues can be captured in a filter system and disposed of in accordance with waste disposal requirements. Negative-acting, liquid-applied photoresist can be readily removed from printed boards that have not been baked excessively. Baking is critical to removal because it relates to the degree of polymerization.



94

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Since overbaking is also damaging to the insulating substrates, processes should stress minimal baking—only enough to withstand the operations involved. The negative-acting resists are removed by using solvents and commercial strippers. In this case, the resist does not dissolve; instead, it softens and swells, breaking the adhesive bond to the substrate. Once this has taken place over the entire coated area, a water spray is used to flush away the film. Positive-acting photoresists are removed by dissolving in acetone, ketone, cellusolve acetate, or other organic solvents. Commercial organic and inorganic strippers are suitable if baking has not been excessive. Removal by exposure to UV light and subsequent dipping in sodium hydroxide, trisodium phosphate (TSP), or other strong alkaline solutions is also effective. Overbaking also makes removal difficult. Machine stripping is done in a solution of 0.5 N sodium hydroxide, nonionic surfactants, and defoamers. 2.4.4.3 Etching solutions. This section is a survey of the technology and chemistry of the copper etching systems in common use. Changes from batch-type operation to continuous constant-rate systems with increased process automation represent major innovations in etching practices. Problems encountered in the control of equipment and etchant solutions are frequently difficult to separate. Often, the utmost in performance and life of the etchant is not attained. A current understanding is needed in the areas of fine-line production, regeneration and recycling of materials, and pollution control. Alkaline ammonia. Alkaline etching with ammonium hydroxide complexing is increasingly used because of its continuous operation, compatibility with most metallic and organic resists, minimum undercut, high capacity for dissolved copper, and fast etch rates. Both batch and continuous (closed-loop) spray machine systems are in use. Continuous operation provides constant etch rates, high work output, ease of control and replenishment, and improved pollution control. However, costs are relatively high, neutralization after etching is critical, and the ammonium ion introduced into the rinses presents a difficult waste treatment problem. Complete regeneration with chemical recycling is not routinely practiced. Sulfuric acid–hydrogen peroxide. Sulfuric-peroxide systems are used extensively for copper surface preparation (microetching), i.e., for oxide coating of inner layers, and for electroless and electrolytic copper plating. The reasons for this wide acceptance are the ease of replenishment, simple waste treatment needed, closed-loop copper recovery, and optimum surface texture of the copper. In addition to these advantages, the compatibility of these systems with most organic and metallic resists,




95

their steady etch rates, and the optimum undercut they provide make them especially suited to be used as final etch step. Both tank immersion and etching systems are commercially available. Continuous processing equipment is also available for the electroplating-throughetching operations. Cupric chloride. Cupric chloride systems are typical of the innovations to achieve closed-loop regeneration, lower costs, and a constant, predictable etch rate. Steady-state etching with acidic cupric chloride permits high throughput, material recovery, and reduced pollution. Regeneration in this case is somewhat complex but is readily maintained. Dissolved copper capacity is high compared with that of batch operation. Cupric chloride solutions are used mainly for fineline multilayer inner details and print-and-etch boards.43 Resists are screened inks, dry film, gold, and tin-nickel. Solder and tin boards are not compatible with cupric chloride etchant. Persulfates. Ammonium, sodium, and potassium persulfates modified by certain catalysts have been adopted for the etching of copper in PC manufacturing. Continuous regenerative systems and a batch system using ammonium persulfate are common. Wide use is made of persulfates as a microetch for inner-layer oxide coating and copper electroless and plating processes. Persulfate solutions allow all common types of resists on boards, including solder, tin, tin-nickel, screened inks, and photosensitive films. Persulfate solutions are not suitable etchants for gold because of excess undercut and low etch factors. Formulations of ammonium persulfate catalyzed with mercuric chloride have etch rates comparable to those of the chloride etchants and are preferred for solder, print-and-etch, and tin-nickel boards. Formulations with proprietary additives other than mercury catalysts are available and have been improved to give good etch factors. Regenerative systems have made possible higher copper capacities and constant etch rates. In general, persulfate etchants are unstable and will exhibit decomposition, lower etch rates versus copper content, and lower useful copper capacity. The use of persulfate etching systems has declined recently because of high costs and other improvements in alkaline ammonia etchants. Ferric chloride. Ferric chloride solutions are used as etchants for copper, copper alloys, Ni-Fe alloys, and steel in PC applications, electronics, photoengraving arts, and metal finishing. Ferric chloride is used with screen inks, photoresist, and gold patterns, but it cannot be used on tin-lead or tin-plated boards. However, ferric chloride is an attractive spray etchant because of its low cost and its high holding capacity for copper.



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The composition of the etchant is mainly ferric chloride in water, with concentrations ranging from 28 percent to 42 percent by weight (see Table 2.25). Free acid is present because of the hydrolysis reaction. This HCl is usually supplemented by additional amounts of HCl (up to 5 percent) to hold back the formation of insoluble precipitates of ferric hydroxide. Commercial formulations also contain wetting and antifoam agents. The effects of ferric chloride concentration, dissolved copper content, temperature, and agitation on the rate and quality of etching have been reported in the literature.41 Commercial availability includes lump FeCl3⋅6H2O and aqueous solutions with and without additives. Ferric chloride with additives has the advantage of low foaming (reduced odor and fuming), fast and even etching (due partly to added strong oxidizers and surface-wetting properties), and reduced iron hydroxide precipitate formation, owing to the slight acidity and to the chelating additives. The useful life of ferric chloride etchants and the uniformity of etching rates have been greatly improved by the manufacturers of proprietary solutions. Chromic-sulfuric acids. These etchants for solder- and tin-plated boards were preferred for many years. More recently, their use has been limited drastically because of the difficulty in regeneration, the inconsistent etch rate, the low limit of dissolved copper (4 to 6 oz/gal), and especially the pollution concerns. Chromic acid etchant is suitable for use with solder, tin-nickel, gold, screened vinyl lacquer, and dry or liquid film photoresists. Although chromic acid etchants are strong oxidizing agents, they do not attack the solder, since insoluble lead sulfate is formed. Undercut is seen less with solder-plated patterns than with gold and organic resists. Nitric acid. Etchant systems based on nitric acid have not found extensive application in PC manufacture. Copper etching is very exothermic, which may lead to violent runaway reactions. Problems with this system include solution control, attack on resists and substrates, and toxic gas fuming. However, nitric acid has certain advanTABLE 2.25

Composition of FeCl3 Solutions Low strength

Percent by weight Specific gravity Baumé lb/gal g/L Molarity

28 1.275 31.5 3.07 365 2.25

Optimum 34 1.353 38 3.9 452 2.79

38 1.402 42 4.45 530 3.27

High strength 42 1.450 45 5.11 608 3.75

Data taken at 68–77°F (20–25°C). Photoengraving FeCl3 42° Baumé has 0.2–0.4% free HCl. Proprietary etchants contain up to 5% HCl.




97

tages. These include rapid etching, high dissolved copper capacity, high solubility of nonsludging products, easy availability, and low cost. 2.4.4.4 Equipment and techniques. Etching techniques and the equipment used today have evolved from four basic etching methods: immersion, bubble, splash (paddle), and spray etching. Spray etching is the most common method, since it is fast, well suited to high production, and capable of very fine line definition. Spray techniques include single- and double-sided etching with either horizontal or vertical positioning of the boards. These techniques yield high etch factors and short etching times, due in part to high solution controls and to the introduction of high quantities of air. As in all etching procedures, however, the highest definition (fine-line patterns) or the use of thicker copper foils requires control of the undercutting by careful selection of equipment and etchants. Spray-etching machines have evolved simultaneously with the availability of chemical-resistant metals and plastics essential to their construction (polyvinyl chloride [PVC] and titanium alloys). Titanium is suitable for constant use in all common etchants except sulfuric acid–hydrogen peroxide, which requires stainless steel materials. Polycarbonate, polypropylene, and Hastelloy C alloys are also used. Automatic vertical etching. This type of machine is designed for higher production rates. A mechanism carries a loaded rack through the etch chamber, where it is sprayed on one or both sides by oscillating banks of spray nozzles. The rack goes through water (spray-rinse) and neutralizing chambers. Cooling coils are available for sulfuric-peroxide etchants. Control of pressure to each bank of spray nozzles and on-off valves provide additional versatility. The etchant sump has a larger volume of etchant than drawer-type vertical etchers, as well as a capability for continuous replenishment. Fine-line etching is attainable when spray nozzles, pressure, speed, and other variables are working optimally. Horizontal etching. Double-sided horizontal etchers are generally preferred in PC manufacturing, since the majority of the boards are twosided. The etcher is available with a drawer-type holding rack and also has a built-in sink at the left of the chamber. The etch operation proceeds and automatically pushes the rack into the rinse area after a timed cycle. Etching is done via independently controlled spray-nozzle banks at the top and bottom. Automatic horizontal etching machines. Made for high-volume production, these machines incorporate the features previously listed for horizontal machines, plus the advantages of conveyorized loading and han-



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dling of boards up to 36 in. wide and of indefinite length, as well as built-in rinsing and neutralizing. In operation, machines are loaded by laying boards flat on an open horizontal conveyor belt that carries them progressively through the etch chamber and subsequent rinses. Rollers on conveyor belts are spaced so as to allow the bottom spray to reach the board. Automatic equipment is available for flow-through solution replenishment, which gives constant etch rates. 2.5 Solder Resist Materials and Processes IPC-T-50b defines a solder resist (mask) as “a coating material used to mask or to protect selected areas of a printed circuit board (PCB) from the action of an etchant, solder, or plating.” A somewhat more useful working definition for a solder resist is as follows: a coating that masks off a printed circuit board surface and prevents those areas from accepting any solder during reflow or wave soldering processing (see Fig. 2.25). The prime function of a solder resist is to restrict the molten solder pickup or flow in those areas of the PCB, holes, pads, and conductor lines that are not covered by the solder resist. PCB designers, however, often expect more functionality out of the solder resist than just a means to restrict the solder pickup. Table 2.26 lists the functions of a solder resist. 2.5.1 Design considerations for solder resists

The design goals for the selection and application of a solder resist should be carefully considered. As with all design goals, one should try to achieve maximum design flexibility, reliability, and functionality at a cost consistent with the required level of system performance. The system’s performance and reliability requirements are the keys in determining the selection process for a solder resist. Critical life-support systems will require different materials and standards than a less critical system such as a video cassette recorder (VCR).

Figure 2.25

Major features of solder resist on a PCB.




TABLE 2.26

99

Functions of Solder Resists

Reduce solder bridging and electrical shorts Reduce the volume of solder pickup to obtain cost and weight savings Reduce solder pot contamination (copper and gold) Protect printed circuit board (PCB) circuitry from handling damage, i.e., dirt, finger prints, etc. Provide an environmental barrier Fill space between conductor lines and pads with material of known dielectric characteristics Provide an electromigration barrier for dendritic growth Provide an insulation or dielectric barrier between electrical components and conductor lines or via interconnections when components are mounted directly on top of the conductor lines

Table 2.27 outlines some of the factors to consider in the design process when selecting a solder resist. It is not very likely that a single solder resist material or application technique will satisfy all the design considerations that are viewed as necessary. It should also be noted that not all the design factors listed in Table 2.27 carry the same weight or value, so the designer needs to prioritize those design factors, analyze the necessary trade-offs, and then specify the solder resist material and process that gives the best balance of properties or characteristics. 2.5.2 Solder resist selection

The solder resists available are broadly divided into two categories, i.e., permanent and temporary. The breakdown of the solder resist types is shown in Fig. 2.26. The permanent solder resist materials are classiTABLE 2.27

Design Factors for Solder Resists

Criticality of system’s performance and reliability Physical size of PCB Metallization on PCB, i.e., SnPb, copper, etc. Line and space (density) of PCB Average height of conductor line (amount and uniformity of the metallization) Size and number of drilled PTHs Annual ring tolerance for PTHs Placement of components on one or both sides of PCB Need to have components mounted directly on top of conductor line Need to tent via holes in order to keep molten solder out of selected holes Need to prevent flow of solder up via holes, which may have components sitting on top of them Likelihood of field repair or replacement of components Need for solder resist to be thick enough to contain the volume of solder needed to make good solder connections Choice of specifications and performance class that will give the solder resist properties that are necessary to achieve design goals



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Figure 2.26

Solder resist selection considerations.

fied by the means used to image the solder resist, i.e., screen printing or photoprint. In addition, the screen-printed resists are further classified by the curing technique, i.e., thermal or UV curing. The photoprint solder resists are distinguished from each other by whether they are in the form of liquid or dry film. The temporary resist materials are classified by chemistry or means of development. 2.5.2.1 Temporary resists. A distinction is made between permanent and temporary solder resists. The temporary resists are usually applied to a selected or limited area of a PCB to protect certain holes or features such as connector fingers from accepting solder. The temporary resist keeps solder out of the selected holes and thus allows for certain process- or temperature-sensitive components to be added manually at a later time. The temporary solder resists usually consist of a latex rubber material or any of a variety of adhesive tapes. These materials can be applied by an automatic or manual dispenser. Some of the temporary mask materials dissolve in the solvents or cleaning processes that are used to clean off the soldering flux residues. This is really a benefit, since it eliminates the need for a separate manual removal and/or cleaning step for the temporary resist. 2.5.2.2 Permanent resists. Permanent solder resists are not removed and thus become an integral part of the PCB. The demand for permanent solder resist coatings on PCBs has greatly increased as the trend toward surface mounting and higher circuit density has increased. When the conductor line density was low, there was little concern about solder bridging, but as the density increased, the number and complexity of the components increased. At the same time, the incidence of soldering defects, such as line and component shorts, greatly increased. Inspection, testing, and rework costs accelerated as effort went into locating and repairing the offending solder defects. The additional cost of the solder resist on one or both sides of the PCB was viewed as a cost-effective means to offset the higher inspection, testing, and rework costs. The




101

addition of a solder resist also had the added value for the designer of providing an environmental barrier on the PCB. This feature was important and dictated that the materials considered for a permanent solder resist should have similar physical, thermal, electrical, and environmental performance properties to the laminate material. See Table 2.28 for a comparison of properties for permanent solder resist types. 2.5.2.3

Selection factors

General considerations ■

Reliability and performance data on the solder resist material

■

Cost effectiveness

■

Past experience

■

Vendor reliability and technical support

■

Number of panels required

■

Appearance and cosmetics of solder resist

■

Number of sources for application and supply Material considerations

■

IPC-SM-840 class designation callout

■

Cost and availability of materials

TABLE 2.28

Permanent Solder Resist Selection Guide Screen print

Feature Soldering performance Ease of application Operator skill level Turnaround time Inspectability Feature resolution Adhesion to SnPb Adhesion to laminate Thickness over conduct or lines Bleed or residues on pads Tenting or plugging of selected holes Handling of large panel size with good accuracy Meeting of IPC-SM-840 Class 3 specification Two-sided application Capital equipment cost

Dry film

Thermal

UV

Aqueous

Solvent

Liquid photoresist

1 1 2 2–3 2–3 3 1 1 3–4

1 1 2 2–3 2–3 3 3 1–2 3–4

1 2 2 2 3 1 1–2 1 1–2

1 2 2 2 3 1 1–2 1 1–2

1 2 2 2 3 1 1 1 2

3–4 4

3 4

1 1

1 1

1 4

3

3

1

1

1

3–4

3–4

1–2

1

1

4 4

4 4

1 1–2

1 1–2

3–4 1

1 = good or high; 2 = moderate; 3 = fair; 4 = poor or low.



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■

Lot-to-lot consistency record

■

Setup and cleanup times

■

Working time and shelf life of solder resist

■

Safety concern for release of noxious or toxic fumes during processing or curing steps

■

Degree of workability Process considerations

■

Operator skill level requirement

■

Need for special applications or curing equipment

■

Cleaning requirements for PCB before and after application

■

Size of PCB

■

Need for solder resist on one or both sides of PCB

■

Number of panels to be processed

■

Turnaround time required

■

Machinability

■

Need to tent selected holes

■

Touchup or rework limitations

■

Inspectability and conformance to specification Performance considerations

■

Testing to IPC-SM-840 specification requirements

■

Adhesion after soldering and cleaning

■

Bleed-out of resist onto pads or PTHs

■

Solvent resistance to flux and flux cleaners

■

Ionic contamination levels

■

Integrity of resist after soldering and thermal cycling

2.5.3 Solder mask over bare copper (SMOBC)

SMOBC is a major solder resist application technology. A problem for conventional copper-tin-lead electroplated PCBs is the flow of tin-lead solder under the solder resist during the wave or vapor phase or infrared soldering. This flow of molten metal underneath the resist can prevent the resist from adhering to metal or laminate. If the resist fractures because of this hydraulic force, the surface integrity is lost and the effectiveness of the resist as an environmental or dielectric barrier can be severely impaired. In fact, such breaks in the resist can actually




103

trap moisture, dirt, and soldering flux and serve as a conduit to direct liquids down to the resist-laminate interface. This solder resist situation could lead to serious reliability and/or performance concerns. The SMOBC process addresses the tin-lead flow problem by eliminating the use of tin-lead electroplating on the conductor lines under the solder resist. An all-copper PTH printed circuit board is often produced by a tent-and-etch process. This process is one in which the PCB is drilled and plated with electroless copper, which is immediately followed by copper panel plating with the full-thickness copper required for the PTHs. A dry-film resist process is often used with a negative phototool (clear conductor lines and pads) to polymerize the resist in only those clear areas of the phototool. This polymerized resist will now protect the lines and PTHs during a copper-etching process that will remove all the unwanted background copper. The photoresist is then stripped off, and the solder resist material is applied and processed through curing. Tin-lead is next added to the open component pads and PTHs by the hot-air leveling process. An alternative process uses conventional procedures to create a pattern-plated board. After etching, however, the metal etch resist is removed chemically, leaving the underlying copper bare. Subsequent process steps are the same as for SMOBC. The primary function of tin-lead in the PTHs and on the component pads is to improve solderability and appearance. It is important to demonstrate the solderability of the holes and pads on the SMOBC panel. This is accomplished by a hot-air leveling process that places a thin coating of molten tin-lead on only those copper areas of the PTH that have not been covered by the solder resist. This hot-air leveling process improves the ability of the copper surface to be soldered and also improves the appearance and solderability after longer-term storage of the PTHs and pad surfaces. Since there is no flowable metal under the solder resist during the hot-air leveling step or later during component soldering, the resist maintains its adhesion and integrity. The lower metallization height of the conductor lines allows the use of a thinner dry-film resist and also makes the liquid and screen-printing application somewhat easier. One variation on the basic SMOBC process is to make the PCB by the conventional pattern-plate copper and tin-lead process followed by etching of the background copper. Then another photoresist step is used to tent the holes and pads so that the tin-lead can be selectively stripped from the conductor lines. This is followed by infrared or oil reflow, cleaning, and application of solder resist. A second process variation strips off the tin-lead plating completely and is followed by cleaning, solder resist application, and hot-air leveling. There are still other PCB fabricators that do not like either of these processes and are opt-



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ing to use a nonflowable, copper-etchant-resistant metal like tin-nickel under the solder resist. The major shortcoming of tin-nickel is that it is considered more difficult to solder with low-activity soldering fluxes. 2.5.4 Cleaning and PCB preparation prior to solder resist application

Optimum solder resist performance and effectiveness can be obtained only if the PCB surfaces are properly prepared prior to the application of the resist. Surface preparation usually consists of a mechanical brush scrubbing for the non-tin-lead PCBs followed by an oven-drying step. The tin-lead PCBs should not be scrubbed and require less aggressive cleaning procedures. The cleaning options prior to solder resist application are shown in Table 2.29. Dry-film and liquid-photopolymer resists applied to meet the IPCSM-840 Class 3 requirements are particularly sensitive to the cleaning processes and baking step used to remove volatiles prior to the application of the resist. Tin-lead-coated PCBs should not be mechanically brush-scrubbed because of the smearing potential of such a malleable metal as tinlead. Scrubbing can cause a thin smear of the metal to be wiped across the substrate, leaving a potentially conductive path or, at a minimum, a decrease in the insulation resistance between the conductor lines. Pumice scrubbing is also unacceptable for tin-lead circuitry, since the pumice particles may become embedded in the soft metal, which can lead to poor soldering performance. Solvent degreasing with Freon or 1,1,1-trichloroethane cleaners is necessary with tin-lead PCBs in order to remove the light process oils from the solder reflow step, dirt, and fingerprints that are usually found on the PCB at the solder resist step. Solvent degreasing will not remove metal oxides or contaminates that are not soluble in the degreasing media. The last step prior to the application of a solder resist to the PCB should be an oven-drying step in which absorbed surface moisture and low-boiling volatiles are removed. This drying step should immediately precede the resist application step in order to minimize the reabsorption of moisture. TABLE 2.29

Preparation for Solder Resists Panel metallization

Operation

Cu

Sn-Pb

Others

Mechanical brush Pumice Solvent degrease Chemical cleaning Oven drying

Yes Yes Yes Yes Yes

No No Yes Yes Yes

Yes Yes Yes Yes Yes




105

The most stringent performance specifications will in turn require the most stringent cleaning procedures prior to the resist application. Not all resists and performance specifications require the same degree of cleaning. In certain cases, where performance requirements are less stringent, some screen-printed resists may be used successfully without any particular cleaning or oven-drying steps. 2.5.5 Solder resist applications

Permanent solder resists may be applied to the PCB by any of several techniques or pieces of equipment. Screen printing of liquid solder resists (ink) is the most common; with regard to photoprint solder resists, the dry-film solder resists are applied to one or both sides of the PCB by a special vacuum laminator, and the liquid-photoprint solder resists are applied by curtain coating, roll coating, or blank-screenprinting techniques. 2.5.5.1 Screen printing. Screen printing is typically carried out in manual or semiautomatic screen-printing machines using polyester or stainless steel mesh for the screen material. If solder resist is required on two sides, the first side is coated and cured or partially cured and then recycled to apply the solder resist on the second side using the screen pattern for that side, and then the entire PCB is fully cured. 2.5.5.2 Liquid photoprint. For some liquid-photoprint solder resists, a screen-printing technique is used to apply the resist in a controlled manner to the surface of the PCB. The screen has no image and serves only to control the thickness and waste of the liquid solder resist. There is no registration of the screen, since there is no image. The actual solder resist image will be obtained by exposing the coated PCB using ultraviolet light energy and the appropriate phototool image. The unexposed solder resist areas defined by the phototool are washed away during the development step. Some liquid-photoprint solder resists require a highly mechanized process (roller or curtain coating) and therefore, because of the equipment costs and the setup, cleanup, and changeover costs, are best suited to high-volume production. The liquid solder resists do not tent holes as effectively as the dry-film solder resist materials. 2.5.5.3 Dry film. Dry-film solder resists are best applied using the vacuum laminators that have been designed for that purpose. The equipment removes the air from a chamber in which the PCB has been placed. The solder resist film is held out of contact from the PCB surface until atmospheric pressure is used to force the film onto one or both sides of the PCB.



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The roll laminators that apply the dry-film resists for plating or etching are usually found to be unacceptable for solder resist application. The roll laminators were designed to apply a resist to a smooth, flat surface such as copper foil, and not to a three-dimensional surface such as an etched and plated PCB. Air is usually trapped adjacent to the conductor lines as the lamination roll crosses over a conductor line running parallel to the lamination roll. Entrapped air next to the conductor lines can cause wicking of liquids, which in turn causes reliability and/or performance concerns. The dry-film resist thickness, as supplied, is usually 0.003 or 0.004 in. and will meet the requirement of the Class 3 specification for a 0.001-in. minimum thickness of solder resist on top of the conductor lines. The resist thickness chosen depends on the expected thickness of the copper circuitry to be covered, allowing for filling of the spaces between circuit traces with resist. 2.5.6 Curing

Once the solder mask has been applied to the PCB, it must be cured according to the manufacturer’s recommendations. Typically, curing processes include thermal curing by oven baking or infrared heating, UV curing, or a combination of the two processes. The general objective of the curing process is to remove any volatiles (if present) and to chemically cross-link and/or polymerize the solder resist. This curing toughens the resist to help ensure that it will maintain its integrity during the chemical, thermal, electrical, and physical exposure the PCB will see during its service life. Undercuring, or an out-of-control curing process, is usually the prime cause for solder resist failure. The second leading cause for failure is inadequate cleaning prior to solder resist application. All PCBs should be carefully inspected for defects prior to curing. Once a solder resist has been cured, it is usually impossible or impractical to strip the resist for rework without seriously damaging the PCB. 2.5.7 Liquid photoimageable solder resist (LPISR)

With the advent of SMT in the early 1980s, the requirements for tighter registration of solder mask to circuit features have become ever more demanding. As the lead pitch of SMT components became finer, as illustrated in Table 2.30, conventional thermal and UV-curable screen resists could no longer satisfy the requirements to deposit material completely and consistently between the board features, such as adjacent traces or traces and pads. Although dry-film solder resist (DFSR) is able to satisfy many of these tighter tolerance requirements, it is expensive and sometimes it has difficulty in coverage of spacings




TABLE 2.30

107

Standard Design Rules for Surface Mount Device Pads (mm) Pad

Kind of SMD

Number of pins

Pitch

SOP (PLCC)

8–28

1.27

QFP

64 80 100 48 224 300

1.0 0.8 0.65 0.5 0.4 0.3

Solder mask

Width

Space

Clearance

Width

0.5–0.6

0.77–0.67

0.1–0.15

0.37–0.57

0.6–0.7

0.67–0.57

0.1–0.15

0.27–0.47

0.6 0.5 0.35 0.3 0.22 0.15

0.4 0.3 0.3 0.2 0.18 0.15

0.135 0.085 0.085 0.05 0.05 0.04

0.2 0.13 0.13 0.1 0.08 0.07

PLCC: plastic leaded chip carrier. SOURCE: NEC Corporation.

between tightly formed fine-line conductors at their base area, leaving small air pockets that tend to erupt during the soldering operation. Therefore, the use of DFSR has declined as SMT has proliferated and LPISR has gained acceptance. The usage of DFSR seems to be confined to some special cases when requirements such as hole tenting, small lot size, and thicker mask (3 mil or more) are present. When Ciba-Geigy introduced the Probimer 52 LPISR system in 1978, SMT was not yet in place and most of the PCB manufacturers were reluctant to adopt it because the cost of the Probimer system was expensive compared to what they were then using. However, some PCB manufacturers catering to the telecommunication industry started to adopt it because of its excellent corrosion resistance; then, as SMT started to gain momentum in the mid-1980s, other solder resist ink makers saw the value of LPISR and followed Ciba-Geigy into the marketplace. Today, there are a great number of LPISR manufacturers offering material and process alternatives, and nearly all SMT boards are coated with LPISR. 2.5.7.1 Panel preparation. Before proceeding with the topic of coating methods, a discussion of panel preparation is appropriate because it is the starting point of all processes. When cleaning copper circuitry for solder mask application, it is important to remove all intermetallic compounds, oxides, and organic and ionic contaminants. A typical cleaning process may consist of the following steps: ■

Acid spray rinse (5 percent hydrochloric acid, for example)

■

Water spray rinse



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■

Mechanical abrasion (jet scrub, pumice scrub, brush scrub, etc.)

■

High-pressure water and deionized water rinse

■

Dry and optional bake at about 160 to 180°F for 30 min

Mechanical abrasion ensures better adhesion of solder resist to copper and helps resist ink to flow into spacings more naturally by removing sharp conductor edges that sometimes block the smooth flow of resist ink. 2.5.7.2 Screen coating. Open screen coating is the simplest entrylevel method for most PCB manufacturers, although screen coating can be very sophisticated when the process is to be automated. Single-sided screen coating. On a worldwide basis, the most popular coating method by far is single-sided open screen coating because it is relatively easy to do successfully and has a low entry cost. By its nature, however, screen coating tends to remove resist ink at the conductor edge that makes the first contact with the squeegee and leave spacings between densely spaced conductors uncovered, whether it is single-sided or the simultaneous double-sided coating to be explained in the next subsection. (Figure 2.27 shows this weakness.) To overcome this weakness, the users of the screen-coating method normally screen the panel twice or even three times to ensure sufficient coverage at conductor edges and spacings, particularly at their bottom area. Users of PCBs usually demand that the thickness of the solder resist be about 0.6 mil (or 0.15 mm) at the edges of the conductors. Simultaneous double-sided screen coating. This method was conceived by a Japanese PCB manufacturer, Satosen, and the hardware implementation was made by another Japanese company, Toshin Kogyo. Depending on the models, double-sided screening equipment can coat between 120 and 180 panels per hour. These screening machines are equipped with back-side scrapers to prevent resist ink from falling into holes.

Figure 2.27

“Skipping” problem associated with screen coating.




109

There is another maker of double-sided screening equipment: Circuit Automation. The equipment made by this company is essentially the same as the Japanese machine. However, the Circuit Automation machine, sold under the trade name of DP series, avoids ink getting into holes by moving the screen slightly and changing the skew angle of the squeegee on the second screening. Double-sided screen coating advantages/disadvantages. One major advantage of the double-sided simultaneous screening method is that the panel receives tack-free curing only once, and therefore the degree of cure on both sides of the panel is equal. Single-sided screening makes the first side cure more than the second side, and, in some extreme cases, the colors of the two sides may become different. Double-sided screen coating has one weakness in that it is difficult to screen thin panels. To overcome this problem, the makers of such equipment provide a special frame on which to mount thin panels, which gives tension to the panel and makes screening possible. However, the throughput by the thin-panel version is somewhat reduced due to the more intricate panel-mounting scheme.

2.5.7.3 Curtain coating. Ciba-Geigy introduced the first curtain coating system, the Probimer 52, in 1978. Coates Circuit Products of the United Kingdom followed. Years later, Maas of Germany started to offer curtain-coating equipment, but no resist ink. Figure 2.28 shows a typical fully automated configuration of a curtain-coater line.

Dryer

Coater

Turn-over device (not shown)

Cart

Dryer

vel Tra yor e v n Co

Coater

Cart

Figure 2.28

Typical fully automated configuration of a curtain-coater line.



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The speed of the belt conveyor under the curtain of resist ink determines the thickness of the coating. One pass is sufficient to secure the required coating thickness. The quality of coverage by curtain coating is excellent. Curtain coating can accommodate mixed panel sizes of different thicknesses without any setup change, but it can coat only one side of the panel at a time. Because of the nature of coating, the entire panel surface gets coated. To provide room for tooling holes and test coupons, 15 to 25 percent of the panel area is used as trimming, and resist ink coated on this trimming area is wasted in curtain coating. That is, “useful” ink utilization in curtain coating is usually between 75 and 85 percent. However, the newer curtain coaters have the provisions to block two edges of the panel from being coated, thus improving resist ink utilization. In the early days of curtain coaters, it was difficult to coat thin panels since the leading edge of a thin panel tends to droop down at the end of the fast conveyor belt under the curtain. However, this problem is overcome by a flipping mechanism provided at the end of the conveyor belt. To avoid the “lap-around” effect of resist ink at the leading edge of the panel, the panel is usually fed into the curtain at a slightly skewed angle. Curtain coating can process typically 180 panels per hour; a high-productivity model can handle in excess of 300 panels per hour. The process after coating is more or less the same as in screen coating. Newer types of tack-free curing ovens are made much shorter than the original one, and the entire length of a fully automated line with two curtain coaters in series is no more than 60 to 70 ft. 2.5.7.4

Spray coating

When it comes to the arrangement of spray guns (atomizers), there are also a few variations. In one variation, a single gun sways sideways back and forth, perpendicular to the direction of panel travel. In a second single-gun system, the gun is stationary. In other coaters, two stationary guns are arranged in staggered position. Each one of these gun arrangements has its strength and weaknesses. In electrostatic spray systems, effective grounding is essential for good results. Also, it is important to keep a distance of about half an inch between adjacent panels. If the adjacent panels get closer than this clearance, sparks may be induced at the edges of these panels, leaving uncoated spots. In such a system, the typical coating speed is about 240 panels per hour. Vertical spray systems.

Horizontal spray systems. All horizontal systems coat one side at a time. In most such systems, the panel is tack-free cured before being coated




111

on the second side. In some systems, however, the panel is carried on a V belt. After the first side is coated, the panel is flipped and the other side gets coated. In this case, tack-free curing is done only once, but it is difficult to process thin panels in such a system. Thin panels are usually spray coated vertically. Overspray. Unlike screen and curtain coating, spray coating creates an overspray. There are various ways to treat oversprayed ink. In one system, a roll of paper 800 to 1000 yards long is used to absorb oversprayed ink. When the entire length of paper is used up, it is removed and treated for waste disposal. In other systems, a container tank is provided underneath the carrying belt to collect oversprayed ink. When the tank gets filled to a certain level (about once every two to three months), chemicals are added to coagulate the ink, and the coagulated ink is carted away for waste disposal. Curtain-coating and spray-coating methods can process panels of different sizes and shapes without special setup, which is an advantage in dealing with small lot sizes. On the other hand, when panels of mixed sizes are passed through a spray coater, ink utilization can be very poor—as low as 40 percent. Some resist ink manufacturers claim oversprayed ink can be used again by adding solvent, but in reality, reutilization of oversprayed ink is not done because such solvents are not a part of ink formulation and are not compatible with the main ingredients. Spray coating gives the best conformal coverage on the peaks and valleys of the panel surface. Because of this, however, spray coating can create skips in subsequent legend screening when valleys are too low, as illustrated in Fig. 2.29. After years of struggle, ink makers have now corrected this “skipping” problem by formulating spray inks to fill the valleys high.

2.5.8 Tenting holes

All coating methods described so far have one problem in common. None of the methods can effectively and reliably tent holes. Closely

Figure 2.29 Spray coating can create good conformity with circuits, which, however, may cause skipping problems in legend screening.



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placed feed-through holes can cause bridging at the time of soldering. Flux can be entrapped in small holes. Therefore, some users of PCBs demand that the holes be tented or filled with solder mask. Dry-film solder mask can provide tenting, but it is usually expensive and often fails to fill the narrow valleys between tightly spaced conductors. To overcome this difficulty, DuPont came up with a solution with the VALU system, in which the panel is first coated thinly with LPISR and then dry-film solder mask is laminated on top of it. When hole tenting is required in conjunction with screen, curtain, or spray coating, holes are filled with epoxy-based ink by screening after the panel is coated with LPISR. Some PCB manufacturers fill the holes first before coating with LPISR. Such processes add extra cost, but there seems to be no better alternative way to accomplish hole tenting. 2.5.9 Electroless Ni/Au plating issues for solder resists

Hot-air solder leveling (HASL) is the most popular surface finish for SMT. As the density of SMT boards becomes higher, first-pass assembly yields tend to be poorer and repair is very costly and error prone. In recent years, electroless nickel-gold finish has been gaining popularity as an alternative finish to HASL. MLBs for cellular telephone applications and a large portion of Personal Computer Memory Card International Association (PCMCIA) cards (now called PC cards) are finished with electroless Ni-Au plating, which provides excellent protection against oxidation before the soldering operation. Boards with Ni-Au finish can withstand a few soldering cycles without oxidation. Initially, some LPISRs could not withstand the electroless Ni-Au plating operation. Improvements have been made on most LPISRs available in the market to accommodate electroless Ni-Au plating. If a given LPISR is not suitable for electroless Ni-Au plating, LPISR makers offer versions of their resist inks that can satisfy the plating requirement. 2.6 Machining and Routing Laminate machining consists of the mechanical processes by which circuit boards are prepared for the vital chemical processes of image transfer, plating, and etching. Such processes as cutting to size, drilling holes, and shaping have major effects on the final quality of the printed board. This section will review the basic mechanical processes that are essential to producing the finished board. 2.6.1 Punching holes (piercing) 2.6.1.1 Design of the die. It is possible to pierce holes down to one-half the thickness of XXXPC and FR-2 laminates and one-third that of FR-




113

3 (Fig. 2.30). Many die designers lose sight of the fact that the force required to withdraw piercing punches is of the same magnitude as that required to push the punches through the material. For that reason, the question of how much stripper-spring pressure to design into a die is answered by most toolmakers: “as much as possible.” When space on the dies cannot accommodate enough mechanical springs to do the job, a hydraulic mechanism can be used. Springs should be so located that the part is stripped evenly. If the board is ejected from the die unevenly, cracks around holes are almost certain to occur. The bestquality holes are produced when the stripper compresses the board an instant before the perforators start to penetrate. If the stripper pressure can be made to approach the compressive strength of the material, less force will be required and the holes will be cleaner. If excessive breakage of small punches occurs, determine whether the punch breaks on the perforating stroke or on withdrawal. If the retainer lock is breaking, the cause is almost certain to be withdrawal strain. The remedy is to grind a small taper on the punch, no more than 11⁄2 in. and to a distance no greater than the thickness of the material being punched. If the grinding is kept within those limits, it will have no measurable effect on hole quality or size. The other two causes of punch breakage are poor alignment, which is easily detected by close examination of the tool, and poor design, which usually means that the punch is too small to do the job required. 2.6.1.2 Tolerance of punching holes. If precise hole size tolerance is required, the clearance between punch and die should be very close; the die hole should be only 0.002 to 0.004 in. larger than the punch for paper-based materials (Fig. 2.31 and Table 2.31). Glass-based laminates generally require about one-half that tolerance. Dies have, however, been constructed with as much as 0.010 all-around clearance between punch and die. They are for use where inspection standards permit rough-quality holes.

Proper sizing and locating of pierced holes for paper laminates.

Figure 2.30



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Figure 2.31 Proper tolerance of a punch and die.

A die with sloppy clearances is less expensive than one built for precision work, and wide clearance between punch and die causes correspondingly more breakage and less shear than a tight die will cause. The result is a hole with a slight funnel shape that makes insertion of components easier. Always pierce with the copper side up. Do not use piercing on designs with circuitry on both sides of the board, because lifting of pads would probably occur. 2.6.1.3 Hole location and size. Designs having holes whose distance from the edge of the board or from other holes approaches the thickness of the material are apt to be troublesome. Such designs should be avoided; but when distances between holes must be small, build the best die possible. Use tight clearance between punch and die and punch and stripper, and have the stripper apply plenty of pressure to the work before the punch starts to enter. If the distance between holes is too small, cracks between holes may result even with the best of tools. If cracks between holes prove troublesome, plan the process so that the piercing is done before any copper is etched away. The reinforcing effect of the copper foil will help eliminate cracks. Most glass-epoxy laminates may be pierced, but the finish on the inside of the holes is sometimes not suitable for through-hole plating. 2.6.1.4 Press size. The size of the press is determined by the amount of work the press must do on each stroke. The supplier of copper-clad TABLE 2.31

Tolerances for Punching or Blanking Paper-Based Laminates

Material thickness To and including 1 ⁄16 in. Over 1⁄16 in. to and including 3⁄32 in. Over 3⁄32 in. to and including 1⁄8 in.

Base material

Tolerance on hole size (in.)

Up to 2 in.

2–3 in.

3–4 in.

4–5 in.

Tolerances for blanked parts, overall dimension (in.)

Paper

0.0015

0.003

0.004

0.005

0.006

0.003

Paper

0.003

0.005

0.006

0.007

0.008

0.005

Paper

0.005

0.006

0.007

0.008

0.009

0.008

Tolerances (in.) on distance between holes and slots (90°F)




115

sheets can specify a value for the shear strength of the material being used. Typically, the value will be about 12,000 lb/in2 for paper-based laminate and 20,000 lb/in2 for glass-epoxy laminate. The total circumference of the parts being punched out multiplied by the thickness of the sheet gives the area being sheared by the die.

2.6.2 Blanking, shearing, and cutting of copper-clad laminates Blanking glass-based laminates. Odd shapes that cannot be feasibly produced by shearing or sawing are either blanked or routed. Glass blanking is always done at room temperature. Assuming a close fit between punch and die, the part will be about 0.001 in. larger than the die that produced it. The tools are always so constructed that a part is removed from the die as it is made. It cannot be pushed out by a following part, as is often true when the material has a paper base. If material thicker than 0.062 in. is blanked, the parts may have a rough edge. The life of a punch, pierce, or blank die should be evaluated with reference to the various copper-clad materials that may be used. One way to evaluate die wear caused by various materials is to weigh the perforators, or punches, very accurately, punch 5000 pieces, and then reweigh the punches. Approximately 5000 hits are necessary for evaluation, because the initial break-in period of the die will show a higher rate of wear. Also, of course, the quality of the holes at the beginning and end of each test must be evaluated. Greatly enlarged microphotos of the perforator can be used for visual evaluation of changes in the die.

2.6.2.1

2.6.2.2 Shearing. When copper-clad laminates are to be sheared, the shear should be set with only 0.001 to 0.002 in. clearance between the square-ground blades (Fig. 2.32). The thicker the material to be cut, the greater the rake or scissor angle between the top and bottom shear blade. The converse also is true: The thinner the material, the smaller the rake angle and the closer the blades. Hence, as in many metal shears, the rake angle and the blade gap are fixed; the cutoff piece can be twisted or curled. Paper-based material can also exhibit feathered cracks along the edge that are due to too wide a gap or too high a shear angle. This can be minimized by supporting both piece and cutoff piece during the shear operation and decreasing the rake angle. Epoxy-glass laminate, because of its flexural strength, does not usually crack, but the material can be deformed if the blade clearance is too great or the shear angle is too large. As in blanking, the quality of a part produced from paper-based laminates by shearing can be improved by warming the material before performing the operation.



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Figure 2.32

Typical adjustable shear blades for Cu-clad laminates.

2.6.2.3 Sawing glass-based laminates. When glass-based laminates are to be sawn, carbide-tooth circular saws can be used; but unless the volume of work is quite low, the added investment required for diamondsteel-bonded saws will be paid for in future savings. The manufacturer’s recommendation for saw speed should be followed; usually it will be for a speed in the neighborhood of 15,000 ft/min at the periphery of the saw blade. When economics dictate the use of carbide-tooth circular saws for cutting glass, use the instruction previously given for paper-based laminates (see Fig. 2.33 for tooth shape) and remember that each caution regarding runout, vibration, and alignment becomes more important when glass-reinforced laminates are sawn. 2.6.3 Routing

Modern circuit board fabricators rely principally on routing to perform profiling operations. The high cost and extended lead times for blanking dies, combined with the problem of design inflexibility of hard tooling, limit the punching operation generally to very high volumes or designs specific to die applications. Shearing or sawing are limited to

Figure 2.33 Typical saw tooth designs for paper and cloth laminates.




117

rectangular shapes and generally are not accurate enough for most board applications. In the modern circuit board fabrication industry, rapid response to customer lead times and economies of universal process application are well served by routing, especially multiple-spindle computer numerically controlled (CNC) routing. Routing consists of two similar, yet vastly different fabrication processes: CNC multiple-spindle routing and manual pin routing. The similarities consist of the use of highspeed spindles, utilizing carbide cutting tools, and generating high cutting rates. 2.6.3.1 Pin routing. Pin routing is a manual routing process utilizing a template machined of aluminum, FR-4 laminate, or a fiber-reinforced phenolic. The template is made to the finished board dimensions and has tooling pins installed to register to the board’s tooling holes. The package (which can have up to four pieces in a stack) is routed by tracking the template against a pilot pin protruding from the router table. The pin height is less than the template thickness. Usually, the machine pilot pin is the same diameter as the router bit and can be offset adjusted to give the operator flexibility in optimizing dimensions. Work should be fed against the rotation of the cutter to prevent the cutter from grabbing. Pin routing can be an economical process when a small generation of boards is profiled, or if the shapes required are relatively simple. For pin routing to be effective, generally a very skilled operator is required to fabricate the template and to route the boards. Outside machine shops can build aluminum route fixtures for each customer application; however, lead times and costs per order must be considered. Pin routing is usually used by small shops not able to invest in the CNC equipment and its associated support, or as a specialty process, offline from CNC routing. In the best pin routing operations, the volumes produced cannot be compared with multiple-spindle routing. 2.6.3.2 CNC operation. CNC router equipment has the ability to process high volumes of circuit boards very accurately and economically, yet it is coupled with features to enable quick program and setup. This coupling enables the same processing used for high volume to be utilized for prototypes and short-lead-time production. With circuit board data files so universally available, the part programming time has dropped to a few minutes, as opposed to the hours it once took, while setups remain at about 15 to 20 min, plus cutter labyrinth and first article routing. Router operation consists of multiple spindles (two to five) capable of operating at 6,000 to 36,000 rpm or more. The router path (x-y table



118

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movement and spindle plunge and retract) is determined by program. This permits any number of paths and any location. The preferred method of registration of the panel to the machine table is to use the full panel and the tooling holes previously drilled. Tooling holes internal to the part provide for the highest accuracy, although manufacturing panel tooling may be used if considered earlier in the process. 2.6.3.3 Tooling. To simplify tooling and expedite loading and unloading operations, effective hold-down and chop-removal systems should be provided as part of the machine design. Various methods may then be devised to mount the boards to the machine table while properly registering them to facilitate routing the outline. Some machine designs will have shuttle tables available so that loading and unloading may be accomplished while the machine is cutting. Others will utilize quick-change secondary tooling pallets or subplots that allow rapid exchange of bench-loaded pallets with only a few seconds between boards. Tooling plates. Tooling plates utilize bushings and a slot on the centerline of the active pattern under each spindle. They are doweled to the machine table (Fig. 2.34). The plates may be made by normal machine shop practice, or the router may be used to register and drill its own tooling plate. Mounting pins in the tooling plate should be light slip fit. Subplates. Subplates should be made of Benelax, linen phenolic, or other similar material. Subplates should have the pattern to be routed cut into their surfaces. The patterns act as vacuum paths and aid in chip removal. Part-holding pins should be an interface fit in subplates and snug to loose fit in the part, depending on cutting technique used (Fig. 2.35). It is recommended that the programmer generate the tool-

Figure 2.34

Typical tooling of numerically controlled routing.




119

Tooling schematics for numerically controlled routing.

Figure 2.35

ing and hold-down pinholes in addition to the routing program. That will provide absolute registration between the tooling holes and the routing program. 2.6.4 Scoring

Scoring is a circuit board fabrication method used to make long, straight cuts quickly, and therefore it is often used to create rectangular profile board shapes. More commonly, however, it is used in concert with CNC routing for complex shapes, enabling each tool to be used to its unique advantage. When used with routing, scoring has a much wider application and can provide simple breakaway for complex profiles (Fig. 2.36). 2.6.4.1

Operation. Two major types of panel scoring systems are

available:

Scoring process. (a) Typical scoring lines and routed corners. (b) Scoring lines and routed complex features.

Figure 2.36



120

Chapter Two

■

Dedicated CNC scoring machines utilizing high-speed carbide or diamond-embedded cutter blades, operating as a pair, one on each side of the board. This generates the V groove on each side simultaneously.

■

Drills or driller/routers equipped with scoring software and spadetype carbide bits, generating score lines on one side of the panel at a time (Fig. 2.37).

Dedicated scoring equipment. The dedicated CNC scoring machines are high-production, precision computer-driven machines. With an exception or two, they utilize blade-type cutting tools of all carbide or with carbide inserts, as well as diamond-embedded varieties, and are designed to self-center the panel. The panel feed rate is high due to the blade’s ability to operate at highsurface-feet cutting rates. Scoring both sides simultaneously with one pass contributes greatly to elevated production processing. This equipment utilizes pin or edge registration, with positioning of score lines and steps by programmed instructions. The vertical adjustment of the cutter blades permits variation in V groove depth, and on many models jump scoring is available. The ability to do jump scoring, or score/no-score segments along a simple line at desired points, is programmable. Multiple-role machines. Scoring with CNC drillers or driller/router machines equipped with scoring software produces score lines only on one side of the panel per machine cycle, although each spindle can be used. The panel and program data must be flipped to score the second side. The panel registration method is similar to that of routing, using existing tooling holes to pin the panel to the machined tooling plates. The tooling plates must be machined flat to assure uniformity of score depth. Brush-type spindle pressure foot inserts should be used to apply downward pressure during score line cutting. Spade-type carbide tools of various angles and configurations are used in the spindles. Typically, multiple passes (two or three) may be required to produce a clean, uniform score line.

2.6.4.2 Applications. Scoring is accomplished by machining a shallow, precise, V groove into the top and bottom surfaces of the laminate, gen-

Figure 2.37

Double-pin method.




121

erally with the use of CNC equipment. The two most significant elements of the score line are as follows: ■

The positional accuracy from the reference feature (usually the registration hole)

■

The depth of the score, which determines the web thickness

The final edges of a scored circuit board are yielded by breaking the panel, or border, at the score line (Fig. 2.38). The angle of the cutting tool is reflected in the V groove geometry, and limiting this angle to 30 to 90° will minimize score line intrusion into traces near the edges of the circuit board. The score line exposes the laminate glass fibers and resin. Measurements from these surfaces will vary greatly, even though the score line is precisely machined (Fig. 2.39). These irregular surfaces will be noticed as dimensional growth and should be considered in design or planning when designated as a scored edge. The dimensional accuracy of the final board is determined by the degree of precision with which the following are performed: ■

Misalignment within ⫾0.003 in. of the score line from the desired location

■

Web thickness within ⫾0.006 in. of the designated dimension

Typically, nominal web thickness is 0.020 in. for 0.060-in.-thick FR-4 boards and 0.014 in. for 0.030-in.-thick FR-4 laminate. For CEM-1 or CEM-3 materials, 0.040-in. and 0.024-in. nominal web thicknesses apply, respectively. These web thickness values enable sufficient module strength to avoid accidental or premature score separation, while providing simple breaking efforts without excessive edge roughness or growth.

Figure 2.38

Cross section of boards showing finished V grooves and break.



122

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Figure 2.39

Single-pin method.

2.7 References 1. Coombs, C. F. Jr., Printed Circuits Handbook, 4th ed., McGraw-Hill, New York, 1996. 2. Swiggett, Robert L., Introduction to Printed Circuits, John F. Rider Publisher, Inc., New York, 1956. 3. Senturia, S. D., N. F. Sheppard, H. L. Lee, and S. B. Marshall, “Cure Monitoring and Control with Combined Dielectric Temperature Probes,” Proc. SAMPE, 19(4):22–26, 1983. 4. Kranbuehl, D. E., S. E. Belos, and P. K. Jue, “Dynamic Dielectric Characterization of the Cure Process: LARC-160,” Proc. SAMPE, 19(4):18–21, 1984. 5. Stoll, R., “High Definition Imaging,” PC Fab, 17(6):31, June 1994. 6. Hecht, L., and M. Cibulsky, “Particle Collection Using a Cascade Impactor,” PC Fab, 34, May 1992. 7. Wisnosky, M., “Modeling of Defects in the Print and Etch Process of Printed Circuit Board Manufacturing,” Proc. IEEE Electronic Components & Technology Conference, p. 520, 1986. 8. Moreau, W., Semiconductor Lithography, Plenum Press, New York, pp. 267–281, 1989. 9. Crum, S., “Surface Preparation Process Improvements,” Electronic Packaging & Production, 24, July 1993. 10. Heden, D. J., “Improving Fine Line Resolution with High Intensity Exposure,” PC Fab, 48, December 1987. 11. Deckert, C. A., “Electroless Copper Plating,” ASM Handbook, vol. 5, pp. 311–322, 1994. 12. Murray, J., “Plating, Part 1: Electroless Copper,” Circuits Manufacturing, 25(2):116–124, February 1985. 13. Polakovic, F., “Contaminants and Their Effect on the Electroless Copper Process,” IPC Technical Review, 12–16, October 1984. 14. Blurton, K. F., “High Quality Copper Deposited from Electroless Copper Baths,” Plating and Surface Finishing, 73(1):52–55, 1986. 15. Lea, C., “The Importance of High Quality Electroless Copper Deposition in the Production of Plated-Through Hole PCBs,” Circuit World, 12(2):16–21, 1986. 16. Glasstone, S., Introduction to Electrochemistry, D. Van Nostrand, New York, 1942. 17. Potter, E. C., Electrochemistry, Cleaver-Hume Press, Ltd., London, 1961. 18. Raub, E., and K. Muller, Fundamentals of Metal Deposition, Elsevier, Amsterdam, 1967. 19. Lowenheim, F. A., Modern Electroplating, 3d ed., J. Wiley & Sons, New York, 1974. 20. Safranek, W. H., The Properties of Electrodeposited Metals and Alloys, 2d ed., American Electroplaters and Surface Finishers Society, Florida, 1986. 21. Bard, J., and L. R. Faulkner, Electrochemical Methods: Fundamentals and Applications, J. Wiley & Sons, New York, 1980. 22. Luke, D. A., “Electroplating Copper for Printed Circuit Manufacture,” Circuit World, 13(1):18–23, 1986. 23. Carano, M., “High Speed Copper Plating for Printed Wiring Boards,” Printed Circuit Fabrication, 6(7):1983.




123

24. Sullivan, B., “Electroplating Theory and the High Speed Copper Debate,” Printed Circuit Fabrication, 8(8):35–54, 1985. 25. Mattoon, T. R., P. McSwiggen, and S. A. George, “Printed Circuit Plating Bath Process Control,” Metal Finishing, 83: Parts I, II, and III, 1985. 26. Darikh, P. J., “Electro-deposited Copper for Hi-Rel PCs,” Electronic Packaging & Production, 17(3):61–65, 1977. 27. Jawitz, M. W., “Trouble Shooting Manual for Printed Circuit Production,” Insulation/Circuits, 22(4):5–36, 1976. 28. Strickland, G. R., “Pyrophosphate Copper Plating in Printed Circuit Manufacture,” Product Finishing, 4:20–24, 1972. 29. Rothschild, B. F., “The Effect of Ortho-phosphate in Copper Pyrophosphate Plating Solutions and Deposits,” Metal Finishing, 84(1):49–51, 1978. 30. Dini, J. W., H. R. Johnson, and J. R. Helms, “Effect of Some Variables on the Throwing Power and Efficiency of Copper Pyrophosphate Solutions,” Plating, 54(12):1337, 1967. 31. Rothschild, B. F., “Copper Electroplating Systems: An Evaluation,” Electronic Packaging & Production, 15(8):102–107, 1975. 32. Owen, C. J., H. Jackson, and E. R. York, “Copper Pyrophosphate Plating without Additives,” Plating, 54:821–825, 1967. 33. Hayes, L. E., “Organic Additives for Pyrophosphate Copper: Panacea or Poison?” Electronic Packaging & Production, 17:102–104, 1977. 34. Sherlin, D. E., and L. K. Bjelland, “Improve Electrodeposited Copper with Organic Additives and Baking,” Insulation/Circuits, 24(9):27–32, 1978. 35. Price, J. W., Tin and Tin Alloy Plating, Electrochemical Publications Ltd., AYR, Scotland, 1983. 36. Davis, P. E., and E. F. Duffek, “The Proper Use of Tin and Tin Alloys in Electronics,” Electronic Packaging & Production, 15(7), 1975. 37. Kilbury, R. G., “Producing Buried Via Multilayers: Two Approaches,” Circuits Manufacturing, 25(4):30–49, 1985. 38. Reid, Frank H., and William Goldie, Gold Plating Technology, Electrochemical Publications Ltd., AYR, Scotland, 1974. 39. Ali, H. O., and R. A. Christie, “A Review of Electroless Gold Deposition Processes,” Circuit World, 11(4):10–16, 1985. 40. Goldman, P., et al., “Enhanced SMT Solderability with No HASL: Proprietary Treatments for Copper Pads,” IPC Technical Review, December 1990. 41. Murski, K., and P. M. Wible, “Problem-Solving Processes for Resist Developing, Stripping, and Etching,” Insulation/Circuits, February 1981. 42. Deforest, S., Photoresist Materials and Processes, McGraw-Hill, New York, 1975. 43. Gorman, F., “Regenerative Cupric Chloride Copper Etchant,” Electronic Packaging & Production, 43–46, January 1974.




Source: Microvias

Chapter

3 Microvias by Mechanical Drilling

3.1 Introduction There is a strong global market trend toward handheld devices such as cellular phones and digital personal assistants. While the first challenge was miniaturization and weight reduction, the focus now is on additional features or customer value. Highly prized models combine more and more functions, increasing the complexity of the devices. Examples are integrated cell phones, Internet browsers, global positioning systems, and so forth. This trend coincides with ever shorter product lifetimes and decreasing prices. Hot products used this year will be either obsolete next year, or at best offered at much lower prices. Microvia technology can be successfully applied to achieve higher density and smaller feature sizes. Mechanical drilling covers a wide diameter range while pushing the limits toward smaller via sizes. Conventional mechanical drilling for non-microvias can drill all kinds of PCB materials, such as FR-4, Mitsubishi Gas and Chemical’s BT, General Electric’s GETEK, Hitachi Chemical’s MegTran (FR-4.5), and Matsushita’s MCL-679. There are many equipment vendors supplying various mechanical drilling systems, such as Advanced Controls, ATI, Ching Huei, Datron, Electro Scientific Industries, Inc., Excellon, Hitachi, OZO, Panasonic, Pluritec, Posalux, Sieb & Meyer, Technic, and Yaskawa.1 In general, mechanical drilling is not suitable for forming microvias. However, with innovative technologies of high-speed spindle and numerical control, it is still possible to make small holes at the scale of microvias by mechanical drilling. For instance, Excellon Automation has been developing an NC drilling machine that may form microvias down to 100 µm (4 mil).1 125


Microvias by Mechanical Drilling

126

Chapter Three

3.2 Mechanical Drilling for Via Formation Mechanical drilling is a proven technology, but still shows a high potential for innovation. High-speed spindles, for example, exceed 250,000 rpm, and high-velocity tables enable axis speeds in excess of 2,000 IPM. Parallel processing of up to eight panels or multiple spindles per panel greatly improves the throughput of the machines and makes the process more cost effective. Higher accuracy, on the other hand, is achieved by implementing “smart” sensor technology. For mechanical drilling of blind vias and microvias, there have been different approaches to control the drilling depth. In the past, accuracy of z-axis control on the order of ⫾50 µm (⫾2 mil) could be achieved, which is not sufficient to form microvias. A breakthrough in depth control technology brought forth a new concept—the electric field sensor (EFS). The EFS generates an electromagnetic field inside of the pressure foot. The drill bit is used as an antenna to sense this field and the output signal is monitored. The monitored signal dramatically changes when the drill bit touches a metal surface, such as the copper layer of the board. The drop of the antenna signal is used to “zero” the z-axis position and drill from this reference position precisely into the board material. This way, a depth accuracy of ⫾5 µm (0.2 mil) can be expected in a manufacturing environment. Additionally, EFS is extremely robust, since it involves neither optical parts that could be disturbed by debris nor mechanical parts that could wear out. The accuracy is not even affected by surface debris. Figure 3.1 shows microvias produced utilizing EFS technology.2 EFS produces nicely shaped vias with straight-angled walls down to 100 µm (4 mil), as detailed in the images in Fig. 3.1. EFS can be used on single-spindle and multiple-spindle machines and can even be retrofitted. Therefore, EFS offers an opportunity to start manufacturing microvias using (existing) mechanical drill equipment. The importance of being able to transit from traditional drilling to microvia formation on existing equipment must not be overlooked. This allows the PCB fabricator to fine-tune upstream and downstream processes (plating, inner-layer alignment, etc.) without having to consider new process variables from the hole formation process itself. If the upstream and downstream processes are understood, faster adoption of a laser via formation tool is possible. 3.3 Comparison Among Various Via Drilling Technologies Currently, NC drilling is the most common process for generating holes in PCB. However, NC drilling is technically limited to hole sizes of 200 µm and up (not really microvias). Although smaller holes may be pos-




127

Microvia formation with EFS depth control.

Figure 3.1

sible, these would come at the cost of significant productivity (minimal stack height). In addition, creation of blind vias is virtually impossible where typical dielectric thickness is 50 µm or less.3 In subsequent chapters, several other microvia forming technologies are introduced. Figure 3.2 shows the comparison of inner diameters for vias formed by various technologies.4 Further comparison is given in Table 3.1 as well. It is obvious that all other via-forming methods outperform conventional mechanical drilling. Figure 3.3 illustrates the via profiles with different forming processes.4 Although in general mechan-



128

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Figure 3.2 Comparison of via diameters formed by various technologies.

Figure 3.3

Typical via profiles with different forming processes.


25–50 µm

LPI/dry film

Phototool Developer

Average (3)

Yields/cleanliness Material development

25–50 µm

Material used

Consumables

Process control

Technical challenge

Resolution

Relative rating: 1 = lowest, 5 = highest

Productivity Process development

Medium-high (2)

Dielectric cost

Low-average (4)

Phototool Photoresist Gases

Liquid/film

Low-medium (4)

(2) Coater (liquid only) Laser system (∼$500,000)

(3) Coater (LPI only) Printer Developer

Initial investment

Low (1) 2–3

High (5) 60–120

Laser drill (cladded laminate)

Productivity (panels/h)

Photovia (bare resin)

Comparison of Various SBU Technologies

Items

TABLE 3.1

50–80 µm

Cost Productivity

Average-high (2)


Single-cladded laminates

Medium (3)

(3) Laser system (∼$500,000)

Low (1) 2–3

Laser drill (coated foil)

50–80 µm

Cost Productivity

Average-high (2)


Coated foil

High (1)

(3) Laser system (∼$500,000)

Low (1) 2–3

Laser drill (coated foil)

75–100 µm

Cost Productivity

Average-high (2)


Coated foil

High (1)

(3) Plasma unit ($300,000–400,000)

Low-medium (2) 12–18

Plasma etch (coated foil)



129


130

Chapter Three

ical drilling is not suitable for making microvias, compared to other processes this method has the merit of giving good via wall conditions (straight and smooth). Therefore, mechanical NC drilling is still a possible candidate for via formation in some special applications. 3.4 References 1. Lau, J. H., and C. Chang, “An Overview of Microvia Technology,” Circuit World, 26(2): 22–32, January 2000. 2. Kauf, M., L. Ekblad, and H. Martinez, “Mechanical and Laser Via Formation,” Board Authority, 2(2):61–65, July 2000. 3. Numakura, D. K., S. E. Dean, D. J. McKenney, and J. A. DiPalermo, “Micro Hole Generation Processes for HDI Flex Circuit,” Proc. HDI EXPO ’99, pp. 443–450, San Jose, CA, 1999. 4. Lau, J. H., Low Cost Flip Chip Technologies, p. 124, McGraw-Hill, New York, 2000.


Source: Microvias

Chapter

4 Microvias by Laser Drilling

4.1 Introduction Although lasers have been evaluated for use in the circuit board industry for many years, only since 1995 has laser drilling been used in mass production. As of early 1999, the total number of systems in use was estimated to be in excess of 400 units. The rate of installations is more than 50 percent greater than the previous 12-mo period, a clear indication of the rapid adoption of this technology in the organic substrate fabrication industry. This increase in the popularity of the laser as a via formation tool is due partly to the flexibility of the process and partly to the wide range of circuit board materials that are laser compatible. This provides fabricators with the lowest entry cost to high-density interconnect (HDI) available today. The rapid productivity advances provided by system manufacturers have ensured that laser technology is moving into high volume production, with more microvias formed today by laser than by any other method.1 While mechanical drilling is dominant for through-holes with large diameters, laser via formation is more favorable for blind vias and microvias. At the end of 1999, laser via formation was still limited to only a few products. Worldwide, there were 400 laser systems in production, with 300 of those systems installed in Japan. Between 2000 and 2002, this situation is expected to change dramatically. Estimates predict that 350 million phones will be needed for the cellular market in the course of these 3 years. Production of these 350 million cellular phones will require 2000 laser systems. This number does not even include the growing need for Internet communicators, personal computers, global positioning systems, and other devices.2 131


Microvias by Laser Drilling

132

Chapter Four

4.2 Mechanism of Laser Drilling There are two mechanisms by which the laser removes dielectric materials in the drilling process. These are photothermal ablation and photochemical ablation.1 4.2.1 Photothermal ablation

As is indicated by its name, photothermal ablation is a heating and vaporization process and is generally accomplished by using a laser that operates in the visible or infrared (IR) spectrum, between 500 and 10,600 nm. The absorbed laser energy heats the material, causing it to melt and vaporize. The area around the via is affected by the heat of the process, and the via sidewall is often carbonized, requiring cleaning with an aggressive desmear process before plating. 4.2.2 Photochemical ablation

This mechanism is seen only where photo energies exceed about 2 eV, with laser wavelengths in the ultraviolet (UV) spectrum below 400 nm. These high-energy photons can break bonds at the molecular level in long-chain organic materials.3 The resulting particles, occupying more volume than their original molecules, are forcibly ejected from the via and are usually left as a powder on the substrate surface or are removed by extraction mechanisms. This process is sometimes known as a “cold” process due to the general lack of thermal damage seen around the via. The cleaning process is used optionally, and tends to be less aggressive than that required in photothermal processes. Figure 4.1a shows a via formed with the photochemical process using a UV laser, which contrasts with Fig. 4.1b, a via in the same organic material formed with the photothermal process using an IR laser.

Vias formed with (a) UV laser energy, (b) IR laser energy. Figure 4.1

(a)

(b)




133

4.2.3 Combination processes

In practice, the nonhomogeneous nature of printed circuit boards consisting of both organic and inorganic materials often requires that the via formation process with UV lasers be a combination of both photothermal and photochemical processes. Results indicate that UV ablation of inorganic materials (copper and glass) is a thermal process. The shallow penetration depth, high energy absorption, and short pulse of the laser contribute to a fast cutting rate with minimum collateral thermal damage to surrounding materials. 4.2.4 Absorption curves

The key to efficient laser ablation is strong absorption in the target materials at the chosen laser wavelength. Figure 4.2 shows the absorption of some commonly used printed circuit board materials.4 The absorption of resins depends very much on the additives used in their fabrication. They all absorb strongly in the ultraviolet, but have variable characteristics through the visible and infrared, where they can absorb or transmit. Copper foil is a very strong reflector down to about 60 nm, at which point its absorption increases steadily into the ultraviolet. 4.3 Types of Laser Tools for Microvias

4.3.1 CO2 laser

Most of the older installed laser systems are equipped with CO2 lasers only, working in the far IR between 9,600 and 10,600 nm. These systems use the first-generation process invented in Japan, where a CO2 laser is used for drilling of the dielectric material. The CO2 laser beam can be simply focused onto the surface of the substrate via a mask with a projection lens. A variant of the first-generation process is the CO2 ablation of unclad rigid or RigiFlex material that lends itself well to reel-to-reel applica-

Strong absorption in all materials

UV

VISIBLE

IR

Resins vary in th based on additives be almost transpa

Total Absorption

1 0.9 0.8 0.7 0.6 0.5

FR4 Matte Cu

0.4 0.3 0.2 0.1 0

Glass

Copper is refl

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1 1.1 1.2

Energy absorption curves for FR-4 resin, E-Glass, and matte Cu.

Figure 4.2

Glass is transpa

Wavelength (microns)



134

Chapter Four

tions. A mask is imaged with a projection lens onto the surface of the material. The via diameter is then defined by the image size of the mask. Due to the long wavelength of the CO2 laser, the minimum size of the vias is also limited to approximately 100 µm (4 mil). The resulting accuracy is limited due to the tendency of unclad materials to stretch/shrink more during the lamination process than do clad materials. In addition, parallel surfaces have to be created to control impedance, and direct dielectric ablation is limited to processing only one single layer.2 To overcome some of the limitations, oxidized copper-clad material can be used to enable the absorption of the CO2 laser. The top copper layer has to be etched down to approximately 5 µm, and a black oxide layer is applied onto the surface. After the via formation process with the CO2 laser, the oxide is removed and the vias are plated. This process involves additional steps for etching, oxidizing, and later removing the oxide. Still, the attainable via diameter is limited by the long wavelength of the CO2 laser to approximately 100 µm (4 mil).2 In RF-excited CO2 laser, the gas plasma is excited by a radio frequency electrical pulse. These lasers are typically sealed units that require no external gas supplies. The rise time of the unmodified laser pulse is around 50,000 to 100,000 ns. To achieve the shorter pulses required to minimize thermal damage, some external modulation of the beam is often required. This limits maximum pulse rates to around 3000 to 4000 pulses per second.1 The transverse excited atmospheric (TEA) CO2 laser uses a highvoltage (12-kV) DC pulse to excite a gas plasma that generates a single large laser pulse. These lasers have been used in the marking industry for many years. The systems require external gas supplies, and fastflow versions of this laser can operate at between 300 and 600 pulses per second. Pulse duration varies between 100 and 1000 ns, depending on the gas mixture. Routine maintenance of these lasers involves replacing electrodes and optical components, making them more expensive to operate than the sealed CO2 units.1 The CO2 lasers have significantly higher productivity for holes larger than 70 µm in diameter. They can ablate more than 15,000 (100-µm diameter) holes through 50-µm-thick dielectric in 1 min. In general, the CO2 laser is used to drill in the dielectric layer and not to drill holes in copper, because the visible wavelength of CO2 is too large to give enough energy to penetrate the copper at high speed. Therefore, additional processing is required prior to drilling. For instance, windows must be selectively pre-etched through the copper foil at positions where holes in the dielectric are to be formed. (This is called the conformal mask method, and it presents the problem of higher costs and limitation of resolution in both vias and circuits.) Recently, Hitachi has




135

shown that with its CO2 laser drilling machine, it can drill through copper foil ( σ3 > σ2 > σ1) is shown in Fig. 9.3. These curves, which relate the stresses and creep strains at selected values of time for a constant temperature, are called isochronous stress-strain curves and can be used as the constitutive relations for creep strain analysis of structures.


Solders for Next-Generation High-Density Interconnects

296

Chapter Nine

Figure 9.2

Stress-strain rate curves.

9.2.4 Common empirical constitutive equations

Some of the commonest empirical uniaxial constitutive equations for describing the second (primary) and third (secondary) stages of creep (Figs. 9.1 though 9.3) are presented. In the broadest sense, the creep strain εc is a function of applied load or stress σ, time t, and temperature T, that is,

Figure 9.3

Isochronous stress-strain curves.




εc = p(σ, t, T)

297

(9.1)

which is usually assumed to be separable into εc = f (σ)g(t)h(T)

(9.2)

In Eq. (9.2), the stress dependence term has been proposed by Norton, Prandtl, Dorn, and Garofalo as

f (σ) =

冦

Aσn B(σ − F)n C sinh (ασ) D exp(βσ) E[sinh (γσ)]n

Norton Friction stress Prandtl Dorn Garofalo

(9.3) (9.4) (9.5) (9.6) (9.7)

The time dependence term has been proposed by Bailey, Andrade, Graham, and Walles as

g(t) =

冦

t ηtm (1 + ηt1/3)ekt Σ ηitmi

Secondary creep Bailey Andrade Graham and Walles

(9.8) (9.9) (9.10) (9.11)

The temperature dependence term in Eq. (9.2) is usually associated with the Arrhenius law and has the form: h(T) = G exp(−∆H/RT)

(9.12)

In Eq. (9.3) through (9.12), ∆H is the activation energy, R is Boltzmann’s constant, T is the absolute temperature, t is time, and all the remaining symbols other than σ are material constants that can be determined by fitting the creep curves from experiment. It can be seen from Eq. (9.2) to (9.12) that there are many ways to write the creep equation. 9.2.5 Creep constitutive equations of solders under twisting and axial force

For Pb97.5-Sn-2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders, it has been shown by Darveaus and Banerji23 that the Garofalo-Arrhenius creep equation fits very well with the test data (Figs. 9.4, 9.5, and 9.6, respectively). These curves can be used as the constitutive relations for creep analysis of solder interconnects at high temperatures. In this section, the load deformation behavior of twisting T of a thin-



298

Chapter Nine

Figure 9.4

Constitutive equation of Pb97.5-Sn2.5 solder.

walled circular solder interconnect in the presence of an axial force N as shown in Fig. 9.7 is studied. This kind of specimen (Figs. 9.8 and 9.9) is used for the creep test of solder materials under combined load.24,25 The material is assumed to be incompressible and to follow GarofaloArrhenius creep equation (Sec. 9.2.4). Hencky’s total strain theory is

Figure 9.5

Constitutive equation of Sn62-Pb36-Ag2 solder.




Figure 9.6

299

Constitutive equation of Sn96.5-Ag3.5 solder.

assumed to be valid. Due to the geometry of the structure and the loading conditions, σr = σθ = τrz = τrθ = d(γrθ)/dt = d(γrz)/dt = 0. It is also assumed that the thickness of the structure is so thin, compared with the inner radius, that all the nonzero stresses are uniformly distributed across the wall thickness.

Figure 9.7 Torsion (T) of thin-walled circular solder cylinder in the presence of axial force (N).



300

Chapter Nine

Figure 9.8

Thin-walled circular solder cylinder for creep testing.

The Garofalo-Arrhenius creep equation (see Sec. 9.2.4) is generally expressed as dγ G τ ᎏ = C ᎏ sinh ω ᎏ dt ⌰ G

冢冣冤

冢

冣冥

n

−Q exp ᎏ k⌰

冢冣

(9.13)

where γ is the shear creep strain dγ/dt is the shear creep strain rate t is the time C is a material constant G is the temperature-dependent shear modulus Θ is the absolute temperature (K) ω defines the stress level at which the power law stress dependence breaks down τ is the shear stress n is the stress exponent Q is the activation energy for a specific diffusion mechanism k is Boltzmann’s constant (8.617 × 10−5 eV/K)

Figure 9.9

Thin-walled circular solder cylinder for creep

testing.




301

For Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solder alloys, the material constants of Eq. (9.13) have been experimentally determined by Darveaux and Banerji with a single hyperbolic sine function and are shown in Figs. 9.4, 9.5, and 9.6, respectively. By using test data from Ref. 23 on the Pb97.5-Sn2.5 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢冣冥

7

(9.14)

where 1.62 × 107(1140 − Θ) −12765 γo = ᎏᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.15)

and τo = 1710 − 1.5Θ

(9.16)

By using test data from Ref. 23 on the Sn62-Pb36-Ag2 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢冣冥

3.3

(9.17)

where 802(508 − Θ) −6360 γo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.18)

and τo = 3163 − 6.23Θ

(9.19)

Again, by using test data from Ref. 23 on the Sn96.5-Ag3.5 solder alloy, Eq. (9.13) can be written as τ . γ = γo sinh ᎏ τo

冤

冢冣冥

5.5

(9.20)

where −5802 31(553 − Θ) γo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.21)



302

Chapter Nine

and τo = 3687 − 6.67Θ

(9.22)

If the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solder alloys obey the von Mises criterion, then Eq. (9.14) through (9.16) can be written as (for the Pb97.5-Sn2.5 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢冣冥

7

(9.23)

where 1.4 × 107(1140 − Θ) −12765 εo = ᎏᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.24)

and σo = 2962 − 2.6Θ

(9.25)

Similarly, Eq. (9.17) through (9.19) can be written as (for the Sn62Pb36-Ag2 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢冣冥

3.3

(9.26)

where 463(508 − Θ) −6360 εo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.27)

and σo = 5478 − 10.79Θ

(9.28)

Also, Eq. (9.20) through (9.22) can be written as (for the Sn96.5Ag3.5 solder alloy) σ . ε = εo sinh ᎏ σo

冤

冢冣冥

5.5

(9.29)

where −5802 18(553 − Θ) εo = ᎏᎏ exp ᎏ Θ Θ

冢

冣

(9.30)




303

and σo = 6386 − 11.55Θ

(9.31)

. In Eq. (9.23), (9.26), and (9.29), σ is the uniaxial stress, and ε is the uniaxial creep strain rate. The unit for σ, τ, σo, and τo is lb/in2 (psi), the . . unit for γ and ε is 1/s, and the unit for temperature Θ is degrees Kelvin (K), which is obtained by adding 273.16 to the temperature in degrees Celsius (°C). Equations (9.14), (9.17), (9.20) and (9.23), (9.26), (9.29) can only be applied to, respectively, pure shear and uniaxial tension conditions. For the combined stresses state, it is necessary to define an effective creep . strain rate εe and an effective stress σe as follows . . . 2 εe = 兹苶 ⁄3 εij εij

(9.32)

⁄2 Sij Sij苶 σe = 兹3苶

(9.33)

Sij = σij − 1⁄3σββδij

(9.34)

where

. In Eq. (9.32), εij is the creep strain rate tensor. In Eq. (9.33) and (9.34), Sij is the deviatoric stress tensor, σij is the stress tensor, and δij is the Kronecker delta. Assuming that there exists a universal stressstrain rate curve and it coincides with the uniaxial curves, Eq. (9.23), (9.26), and (9.29), then we have σ . εe = εo sinh ᎏe σo

冤

冢冣冥

n

(9.35)

which is shown in Fig. 9.10.

Figure 9.10 Stress-strain rate relation for this study.



304

Chapter Nine

In view of Fig. 9.4 (Pb97.5-Sn2.5 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 7, suggests a dislocation pipe-assisted diffusion deformation mechanism. It occurs by dislocation glide (dislocations moving along slip planes and overcoming barriers by thermal activation) aided by vacancy diffusion. The glide step produces almost all the strain, but the climb step controls the velocity. Since dislocation climb requires diffusion of vacancies or interstitials, the rate-controlling step is atomic diffusion. The activation energy (Q = 1.1 eV) is very close to that of the lattice diffusion in lead (1.1 eV), however, which is somewhat inconsistent with n = 7 for pipe-assisted diffusion (Q = 0.66 eV). In view of Fig. 9.5 (Sn62-Pb36-Ag2 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 3.3, indicates a dislocation viscous glide deformation mechanism (which involves dislocations moving along slip planes and overcoming barriers by thermal activation). Due to its stress dependence, the activation energy (Q = 0.548 eV) is somewhat below the expected value of solute interdiffusion. In view of Fig. 9.6 (Sn96.5-Ag3.5 solder), it can be seen that the power law breaks down at approximately τ/G = 10−3. The stress exponent, n = 5.5, indicates a dislocation climb deformation mechanism. It occurs by dislocation glide (dislocations moving along slip planes and overcoming barriers by thermal activation) aided by vacancy diffusion. The glide step produces almost all the strain but the climb step controls the velocity. Since dislocation climb requires diffusion of vacancies or interstitials, the rate-controlling step is atomic diffusion. Due to its stress dependence, the activation energy (Q = 0.5 eV) is somewhat below the expected value of lattice or dislocation pipe diffusion (1.1 and 0.66 eV, respectively). Figure 9.7 shows the thin-walled circular solder cylinder subjected to an axial force N and a twisting moment T. Due to the geometry of the structure and the loading condition, the nonzero stress and strain rate components are σz (normal stress in the z-direction), τθz (shear stress in . the z-direction of the plane normal to the θ-axis), εr (creep normal . strain rate in the r-direction), εθ (creep normal strain rate in the θ. . direction), εz (creep normal strain rate in the z-direction), and γθz (creep shear strain rate in the z-direction of the plane normal to the θ-axis). Consequently, Eq. (9.32) and (9.33) become 兹2 . . 2 . . 2 . . 2 3 .2 苶 . εr − εθ苶 + (εθ苶+ − εz) 苶 (εz −苶 ⁄2 γ zθ εr) + 苶 εe = ᎏ 兹(苶) 3

(9.36)

and




2 2 σe = 兹σ 苶τ zθ z + 3苶

305

(9.37)

. . Since σr = σθ = 0, then εr = εθ; and since the solder material is assumed . . . to be incompressible, that is, εr + εθ + εz = 0, then we have . . . εr = εθ = −1⁄2 εz

(9.38)

.2 1 . 2 . 苶 εe = 兹ε苶 z + ⁄3γ zθ

(9.39)

Equation (9.36) becomes

Substituting Eq. (9.37) and (9.39) into Eq. (9.35) yields 2 2 .2 1 . 2 兹σ 苶τ zθ z + 3苶兹ε苶 zθ = εo sinh ᎏᎏ z + ⁄3 γ苶 σo

冤

冢

冣冥

n

(9.40)

For the problem under consideration, the Hencky theory26 simplifies to . . 3εz γzθ ᎏ = ᎏᎏ σz τzθ

(9.41)

By solving Eq. (9.40) and (9.41), we have the following stress distributions σz = βσo sinh−1 (K1/n)

(9.42)

兹1 苶 − β2 τzθ = ᎏ σo sinh−1 (K1/n) 兹3 苶

(9.43)

and

in which . ε K = ᎏe > 0 εo . εz β = ᎏ. ᎏ ≤ 1 εe

(9.44) (9.45)

have been substituted. Thus, the strain rate components can be written as . εz = βKεo

(9.46)

and



306

Chapter Nine

. 2 苶β −苶 ) γzθ = Kεo兹3(1

(9.47)

The equilibrium equations for N and T are defined by the relations (Fig. 9.7):

冕 Rhσ dθ

(9.48)

冕 R hτ dθ

(9.49)

N=

2π

z

0

and T=

2π

2

0

zθ

Substituting Eq. (9.42) and (9.43) into Eq. (9.48) and (9.49) yields, respectively N = 2πRhβσo sinh−1 (K1/n)

(9.50)

2 苶 − β2 sinh−1 (K1/n) T = ᎏ πR2hσo兹1 兹3 苶

(9.51)

and

Equations (9.50) and (9.51) are plotted in Fig. 9.11 (for the Pb97.5Sn2.5 solder, n = 7), Fig. 9.12 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.13 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a wide range of values of β and K that were introduced for the sake of convenience. Thus, for a given temperature Θ and a set of values of twisting moment T and axial force N, the values of β and K can be read from Fig. 9.11, 9.12, or 9.13 (depending on which solder material) and the stresses (σz, . . τzθ) and creep strain rate (εz, γzθ) can be obtained from Eq. (9.42), (9.43), (9.46), and (9.47). The values of εo and σo for the Pb97.5-Sn2.5, Sn62Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.24), (9.27), (9.30), and (9.25), (9.28), (9.31), respectively. It is noteworthy that curves of constant β are nearly radial lines so that, as long as the ratio of N and T remains constant, each volume element of the solder interconnect can be assumed with negligible error to be subjected to proportional loading (a sufficient condition for the total strain theory coincides with the incremental theory). Similar behavior has been observed by Smith and Sidebottom26 for the case of a solid circular cylinder subjected to tension and twisting moment. Smith and Sidebottom have also shown that the error in using the incompressible solution to predict the behavior of tension-torsion members made of compressible materials is very small. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.



307

Dimensionless torsion and axial force interaction curves (Pb97.5-Sn2.5).

Figure 9.11

Dimensionless torsion and axial force interaction curves (Sn62-Pb36-Ag2).

Figure 9.12



308

Chapter Nine

Dimensionless torsion and axial force interaction curves (Sn96.5-Ag3.5).

Figure 9.13

Considering the geometrically compatible deformation of the cylinder (Fig. 9.7), we have . . . dφ γ zθ = Rϕ = R ᎏ dz

(9.52)

. . in which ϕ is the twist rate per unit length and φ is the total angle of the twist rate. Equations (9.47), (9.51), and (9.52) lead to the twisting moment–twist rate per unit length relation . 2 1 Rϕ 苶 − β2 sinh−1 ᎏ2 ᎏ T = ᎏ πR2hσo兹1 兹3 苶兹1 苶 − β 兹3 苶εo

冤

冥

1/n

(9.53)

and is plotted in Fig. 9.14 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.15 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.16 (for the Sn96.5Ag3.5 solder, n = 5.5). Thus, for a given Θ, N, and T, we can read the value of β from Fig. 9.11, 9.12, or 9.13 (depending on which solder mate. rial is used) and then read the value of ϕ from Fig. 9.14, 9.15, or 9.16 with β and T known.




309

Twisting moment vs. twist rate per unit length (Pb97.5-Sn2.5).

Figure 9.14

Figure 9.15 Twisting moment vs. twist rate per unit length (Sn62-Pb36-Ag2).



310

Chapter Nine

Figure 9.16

Twisting moment vs. twist rate per unit length (Sn96.5-

Ag3.5).

9.2.6 Torsion of thick-walled circular solder interconnects

Figure 9.17 shows a thick-walled hollow circular cylinder made of Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders subjected to a twisting moment T. The inner and outer radii of the cylinder are labeled a and b, respectively. For a solid cylinder, a = 0. Due to the geometry of the cylinder and the loading condition, the only nonzero . stress is τzθ and the only nonzero strain rate is γzθ. In this case, Eq. (9.14), (9.17), or (9.20) can be used directly and written as . γ zθ τzθ = τo sinh−1 ᎏ γo

冢冣

1/n

(9.54)

As in the previous case, by considering the geometrically compatible deformation of the cylinder (Fig. 9.17), we have . . dφ . γ zθ = Rϕ = R ᎏ dz

(9.55)

. . in which ϕ is the twist rate per unit length and φ is the total angle of twist rate. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.



Figure 9.17

311

Torsion of a thick-walled circular solder column.

Substituting Eq. (9.55) into Eq. (9.54) yields the shear stress distribution through the wall thickness . r bϕ τzθ = τo sinh−1 ᎏ ᎏ b γo

冢

冣

1/n

(9.56)

The twisting moment T equilibrium equation is defined by (Fig. 9.17) T=

冕冕 τ r dθdr b 2π

a 0

zθ

2

(9.57)

Substituting Eq. (9.56) into Eq. (9.57) yields T = 2πτob3

.

bϕ 冕 sinh 冢ξ ᎏ γ 冣 1

−1

α

1/n

ξ2dξ

(9.58)

o

where a α=ᎏ b

(9.59)

r ξ=ᎏ b

(9.60)

and



312

Chapter Nine

Equation 9.58 is plotted in Fig. 9.18 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.19 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.20 (for the Sn96.5-Ag3.5 solder, n = 5.5) for the case of a solid solder column . (α = 0). Thus, for a given Θ and T, the twist rate per unit length ϕ can be obtained from Fig. 9.18, 9.19, or 9.20 (depending on the solder material) and the stress distribution through the wall thickness is given by Eq. (9.56). The values of γo and τo for the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.15), (9.18), (9.21), and (9.16), (9.19), (9.22), respectively. For design purposes, sometimes it is convenient to introduce to nondimensional “shear stress ratio” λ defined by τmax λ=ᎏ τo

(9.61)

in which . bϕ τmax = τo sinh−1 ᎏ γo

冢冣

1/n

(9.62)

Twisting moments vs. twist rate per unit length of a solder column (Pb97.5-Sn2.5).

Figure 9.18




313

Twisting moments vs. twist rate per unit length of a solder column (Sn62-Pb36-Ag2).

Figure 9.19

Figure 9.20 Twisting moments vs. twist rate per unit length of a solder column (Sn96.5-Ag3.5).



314

Chapter Nine

is the largest stress that occurs at the exterior surface of the solder cylinder. Substituting Eq. (9.61) and (9.62) into Eq. (9.56) yields the shear stress distribution in terms of λ τzθ = τo sinh−1

冤冢ᎏb 冣 r

1/n

冥

sinh λ

(9.63)

Substituting Eq. (9.63) into Eq. (9.57), we have T = 2πτob3

冕 sinh 1

α

−1

(ξ1/n sinh λ) ξ2dξ

(9.64)

which is plotted in Fig. 9.21 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.22 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.23 (for the Sn96.5-Ag3.5 solder, n = 5.5) for convenience’s sake (α = 0). Thus, for a given Θ and maximum allowable shear strength, and the radius of a solder column, the allowable applied twisting moment can be determined from Fig. 9.18, 9.19, or 9.20 (depending on which solder material is used).

Figure 9.21

Twisting moment vs. shear stress ratio (Pb97.5-

Sn2.5).




Figure 9.22

315

Twisting moment vs. shear stress ratio (Sn62-Pb36-

Ag2).

Figure 9.23

Twisting moment vs. shear stress ratio (Sn96.5-Ag3.5).



316

Chapter Nine

9.2.7 Bending of thick-walled circular solder interconnects

Figure 9.24 shows a thick-walled hollow circular cylinder made of Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders subjected to a bending moment M. The inner and outer radii of the cylinder are labeled a and b, respectively. Due to the geometry of the cylinder and the loading condition, the only nonzero stress is σz and the only . nonzero strain rate is εz. In this case, Eq. (9.23), (9.26), and (9.29) have to be used and can be written as .ε σz = σo sinh−1 ᎏz εo

冢冣

1/n

(9.65)

Considering the geometrically compatible deformation of the cylinder (Fig. 9.24), we have y . εz = ᎏ . ρ

(9.66)

. in which ρ is the bending curvature rate (Fig. 9.24). Substituting Eq. (9.66) into Eq. (9.65) yields the bending stress distribution through the wall thickness

冢冣

y σz = σo sinh−1 ᎏ . εoρ

Figure 9.24

1/n

(9.67)

Bending of a thick-walled circular solder column.




317

The bending moment M equilibrium equation is defined by (Fig. 9.24) M=4

冕 σ ydA + 4 冕 σ ydA a

0

b

z

(9.68)

z

a

Substituting Eq. (9.67) into Eq. (9.68) yields M = 4σob3

b − ζ sinh 冢ζ ᎏ . 冤冕 ζ 兹1苶 ε ρ冣 1

2

1/n

−1

0

dζ

o

−

b 冕 ζ 兹α苶 − ζ苶 sinh 冢ζ ᎏ . ε ρ冣 α

2

2

0

1/n

−1

o

冥

dζ

(9.69)

where y ζ=ᎏ b

(9.70)

a α=ᎏ b

(9.71)

2 2 苶 − y2 − 兹a 苶 − y2苶) dy. . . . .0 ≤ |y| ≤ a dA = (兹b

(9.72)

2 dA = 兹b 苶. − y2 . . . .a ≤ |y| ≤ b

(9.73)

and

have been substituted. Equation 9.69 is plotted in Fig. 9.25 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.26 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.27 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a solid solder column. Thus, for a given temperature Θ and a moment M the cur. vature rate (ρ) can be read from Fig. 9.25, 9.26, or 9.27 (depending on which solder material is used) and the stresses distribution can be obtained from Eq. (9.67). The values of εo and σo for the Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 solders can be obtained from Eq. (9.24), (9.27), (9.30), and (9.25), (9.28), (9.31), respectively. For design purposes, sometimes it is convenient to introduce to nondimensional “bending stress ratio” µ defined by σmax µ=ᎏ σo

(9.74)

in which



318

Chapter Nine

Figure 9.25

Bending moment vs. curvature creep rate (Pb97.5-

Sn2.5).

Figure 9.26

Bending moment vs. curvature creep rate (Sn62-

Pb36-Ag2). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.



Figure 9.27

319

Bending moment vs. curvature creep rate (Sn96.5-

Ag3.5).

冢冣

b σmax = σo sinh−1 ᎏ. εoρ

1/n

(9.75)

is the largest bending stress that occurs at the exterior surface of the solder cylinder. Substituting Eq. (9.74) and (9.75) into Eq. (9.67) yields the bending stress distribution in terms of µ σz = σo sinh−1

冤冢冣 r ᎏ b

1/n

sinh µ

冥

(9.76)

Substituting Eq. (9.76) into Eq. (9.69), we have M = 4σob3

− ζ sinh 冤冕 ζ 兹1苶 1

2

−1

0

−

(ζ1/n sinh µ) dζ

冕 ζ 兹α苶 − ζ苶 sinh α

0

2

2

−1

(ζ1/n sinh µ) dζ

冥

(9.77)

which is plotted in Fig. 9.28 (for the Pb97.5-Sn2.5 solder, n = 7), Fig. 9.29 (for the Sn62-Pb36-Ag2 solder, n = 3.3), and Fig. 9.30 (for the Sn96.5-Ag3.5 solder, n = 5.5) for a solid solder column. Thus, for a given Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.


320

Chapter Nine

Θ, M, and a maximum allowable tensile strength of the solder σmax, the radius of the solder column b can be designed by reading the value of M/2πσob3 from Fig. 9.28, 9.29, or 9.30. 9.2.8 Summary

An exact creep analysis has been presented for (1) the twisting of a thin-walled circular solder cylinder in the presence of axial force, (2) the torsion of a thick-walled circular solder interconnect, and (3) the bending of a thick-walled circular solder column. The solder alloys are Pb97.5-Sn2.5, Sn62-Pb36-Ag2, and Sn96.5-Ag3.5 and obey the Garofalo-Arrhenius constitutive equation. Results have been presented in the form of equations and dimensionless charts. The use of these equations and charts has been shown for determining the shear and normal stress and creep shear and normal strain rate distributions in the solder interconnects. Also, the resultant axial force, bending moment, twisting moment, twist rate, and curvature rate acting on the solder interconnects are presented. The results presented herein can be used to interpret the test data of solders and to verify the finite element procedures for creep analyses. Also, it should be useful for studying the solder joint creep behavior of the ceramic column grid array package.27

Figure 9.28

Bending moment vs. bending stress ratio (Pb97.5-Sn2.5).




Figure 9.29

321

Bending moment vs. bending stress ratio (Sn62-

Pb36-Ag2).

Figure 9.30

Bending moment vs. bending stress ratio (Sn96.5-

Ag3.5). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website.


322

Chapter Nine

9.3 Low-Alpha-Bearing Solders Since the effect of alpha particles was first recognized by Intel in 1978, it has become well known that alpha particles from thorium and uranium impurities in packaging raw materials such as lead-bearing solder alloys do not cause permanent damage to the chip but are sufficiently energetic to produce soft errors (data loss)—random, nonrecurring single-bit errors.28,29 Alpha particles produce soft errors by penetrating through the lead-bearing solder joint, under-bump metallurgy (UBM), Al pad, passivation, silicon, and pn junction and generating carriers as a result of giving up kinetic energy as they slow down. The carriers generated by alpha penetration through the junction distort the electric field and also generate charges. In this section, some basic physics of soft errors and alpha particle emissions are discussed. Also, the sources, prices, and current usage of low-alpha-bearing solders are presented. 9.3.1 Soft error

Soft errors induced by alpha particles can be a reliability concern for microelectronics, especially semiconductor memory devices. The soft errors are (1) reversible and not associated with any permanent damage to the device, and (2) completely removed on the next write cycle, with the affected bits being no more susceptible to failure than any other bit in the device. Alpha particle radiation is the most common cause of soft errors in memory devices. The primary source of alpha particles in semiconduc237 tor devices is the decay chains of uranium (238 92 U), thorium (90 Th), polo212 210 210 nium (84 Po), and lead isotopes (82 Pb and 82Pb), which are present in trace amounts in the electronic packaging materials. The trend toward increased chip density, lower power supply voltages, and smaller device dimensions further increases the susceptibility of many devices to soft errors. Also, soft errors can be caused by cosmic rays at sea level or higher. If the material is very hot (i.e., emits many alpha particles), soft errors will be very significant. 9.3.2 Alpha particle emissions

The alpha particles are doubly charged helium nuclei containing two protons and two electrons. They are released from high-atomic-number atoms during radioactive decay and then interact with other atoms due to their charge and high energy. The energy range of alpha particles emitted from all naturally occurring elements that undergo alpha decay ranges from 1 to 9 MeV.28–30 Alpha particles released from the decay of 238U and 232Th in packaging materials can penetrate into silicon devices.




323

U has a radioactivity of 6.85 × 10−7 C/g.31,32 The decay of 238U to stable Pb produces eight alpha particles with energies ranging from 4.15 to 7.69 MeV.33,34 Alpha particles having this energy can travel 10 to 25 µm in alumina substrates that have a density of 3.85 g/cm.35 These high-energy alpha particles can travel up to 50 µm in silicon substrates that have a density of 2.3 g/cm3. 232 Th has a radioactivity of 1.1 × 10−7 C/g.31,32 The decay of 232Th to sta206 ble Pb produces six alpha particles with energies ranging from 3.95 to 8.8 MeV.33,34 Alpha particles having this energy can travel 9 to 31 µm in alumina substrates and can travel up to 50 µm in silicon substrates. The soft errors caused by the emission of alpha particles from packaging materials are due to the generation of electron-hole pairs. Highenergy alpha particles passing through the silicon device can generate up to 2.5 × 106 electron-hole pairs in several picoseconds.28 The number of electron-hole pairs produced depends on the energy of the emitted alpha particles and the density of the material. The amount of energy required to produce an electron-hole pair in silicon is 3.6 eV.31 Figure 9.31 shows the effect of an alpha-particle-generated electron-hole pair on a silicon device.28 For example, in n-channel metal-oxide semiconductor (MOS) memory devices, the charge carriers are electronic and the capacitors are potential wells in p-type silicon. Alpha particles emitted from trace levels of uranium and thorium in the packaging materials can penetrate the surface of the semiconductor device. As the alpha particle passes through the semiconductor device, electrons are dislodged from the crystal lattice sites along the track of the alpha particle. If the total number of generated electrons collected by an empty storage well exceeds the number of electrons that differentiates between a 1 and a 0, the collected electron charge can flip a 1 to a 0, generating a soft error in the semiconductor device. Alpha particle levels are reported as alpha activity or as alpha flux. Alpha activity is defined as the alpha particle disintegration rate per unit weight of the material—usually reported in pC/g (picocuries per gram). Alpha flux is defined as the rate (per time unit and per area unit) of alpha emissions from the surface of a material—usually reported in particles per hour per cm2. Alpha flux is the more common method of reporting alpha particle content. As a rule of thumb, an alpha flux of 1 alpha/(h⋅cm2) corresponds to ∼1 ppm of 238U in the material.35 The relationship between the 238U concentration and the alpha flux in ceramic (or other packaging materials) is shown as follows, based on the assumptions that (1) all of the decay isotopes of 238U have the same radioactivity as the parent 238U; (2) 25 percent of the generated alpha particles escape from the ceramic; and (3) the alpha particles travel 14.3 µm: 238

206



324

Chapter Nine

(a) Figure 9.31

Effects of an alpha particle.

Alpha flux = 1 ppm 238U/(g of ceramic) × 3.85 (g of ceramic)/(cm3 of ceramic) × 10−6 (g of 238U)/(ppm 238U) × 6.85 × 10−7 C/(g of 238U) × 2.2 × 1012 disintegrations/(min-C) × 8 alpha particle/(238U disintegration) × 14.3 µm {average alpha particle travel} × 0.25 {escape factor} = 0.996 alpha particle/(h-cm2)




325

(b) Figure 9.31

(Continued)

In memory devices, data are stored as the presence or absence of charge carriers in storage wells. The amount of charge typically stored in a potential well ranges from 0.3 × 106 to 3 × 106 electrons.28 However, the susceptibility of a memory device to soft errors does not depend primarily on the total stored charge but on the critical charge (the number of electrons that differentiates a 1 and a 0). When the number of electrons generated by an alpha particle and collected by a storage well exceeds the critical charge, a soft error occurs. Critical charge is the most important gauge of alpha particle sensitivity and soft error rates (SER) in memory devices.28 If a device has the critical charge larger than 2.5 × 106 electrons, soft errors are not generated by alpha particle emissions because naturally occurring alpha particles do not have enough energy to generate enough electronhole pairs. For critical charges less than 0.05 × 106, practically all alpha particle emissions result in soft errors. In the region between these two extremes, other factors such as cell geometry, collection efficiency,



326

Chapter Nine

alpha particle flux, and critical charge determine the SER in memory devices. 9.3.3 Alpha particle sources from solders

Lead-bearing solders have been identified as the primary source of alpha particles, as demonstrated by a study done at the Microelectronics Center of North Carolina (MCNC) (see Table 9.1)36 where the alpha emission was monitored step by step along with the waferbumping process. The radioactivity of lead can be traced back to 238U. Starting from 238 U, it decays into 210Pb, which further decays into Bi in 22 years, then to Po, then to 206Pb in 138 days as shown in Fig. 9.32. Besides alpha emission, the decay process also involves beta particle (electron) emission. The beta particle has no impact on soft error. The content of uranium in natural sources of lead differs by as much as three orders of magnitude. During the smelting and chemical purification process, although other elements may be removed, the radioactive 210Pb gets concentrated together with nonradioactive 206Pb, due to the same chemical nature of both lead isotopes. Lead having alpha activity as high as 100 alpha/(cm2⋅h) for secular equilibrium can be reached within 8 to 9 mo after smelting and purification. The following decay chain illustrates the birth of an alpha particle −1 −1 4 Pb ⇒ 210 ⇒ 210 ⇒ 206 83Bi + β 84Po + β 82Pb + 2α

210 82

9.3.4 Protection against alpha particle emission

Most of the elements involved in major viable lead-free alternatives such as Sn, In, Ag, and Cu are all considered safe, and hence pose no concerns about alpha particle emission in the coming lead-free era. However, Bi may be an issue, primarily due to the existence of radioactive 214Bi, which will eventually convert into stable 206Pb by going through three beta decays and two alpha decays in about 24 years. The primary concern about alpha particle emission is still associated with lead. For most of the flip chip applications, the challenge of soft error persists due to the continuous dependence on lead-bearing solders, especially the Pb95-Sn5. Although gold-wire bonding is still widely used on chips including DRAM and SRAM, solder-bumped flip chip is gradually applied to DRAM and SRAM devices. At the same time, in some other devices, particularly logic (ASIC) and microprocessor chips, solder-bumped flip chips become an indispensable option. Thus, the trend toward higher I/Os and performance prompts the


α counts / time (α / h)

104 / 23.49 68 / 23.25 102 / 25.85 2718 / 44.88

Si Si + BCB Si + BCB + UBM Si + BCB + UBM + PbSn

Background rate (α / h) 4.03 ⫾ 0.41 4.03 ⫾ 0.41 4.07 ⫾ 0.42 4.07 ⫾ 0.42

Gross α / time (α / h) 4.43 ⫾ 0.43 2.92 ⫾ 0.35 3.95 ⫾ 0.39 60.56 ⫾ 1.16

Baseline Alpha Measurements for MCNC’s Standard Solder-Bumping Process

Material

TABLE 9.1

710 ⫾ 71 900 ⫾ 90 900 ⫾ 90 335 ⫾ 34

Sample area (cm2)

0.7 ⫾ 1.0 −1.5 ⫾ 0.7 −0.2 ⫾ 0.7 198.4 ⫾ 15.1

Corrected activity (0.001 α/cm2 h)



327


328

Chapter Nine

Natural decay chain from 238U to Equilibrium, Pure Technologies Literature.)

Figure 9.32

206

Pb. (Source: Peter Bokhan, Secular

urgency of solving alpha particle emission problems.37 The most pressing concern is alleviating soft errors in larger systems, such as servers, that run on multiple processors and use large banks of DRAMs. Solutions may include increasing the size of the nodes. Although this will raise the level of the charge needed to touch off a false switch, thus reducing the chance of soft error, power consumption will rise.38 The alpha particle produced by the decay of 210Po (which comes from 210 Pb by two beta decays) has an energy of 5.4 MeV. Since there is considerable variation in travel distance, the range of the alpha particle




329

TABLE 9.2

Estimated Ranges for Alpha Particles in Common Materials Material

Range (µm)

Si Pb Al Cu Polyimide Au Resist Air

23.6 11.5 19.5 7.9 28 6.6 24 47,000 (4.7 cm)

can be specified with high accuracy. Table 9.2 shows the calculated ranges for the alpha particles produced by 210Po going through common materials. Although an alpha particle cannot pass through a 25-µm bump of solder, it can penetrate 25 µm of an Si layer.37 In addition, it can also easily pass through thin-metal films and many tens of micrometers of organic materials.37 For flip chip applications, lead is close to IC, and it needs 25 to 50 µm of polyimide passivation. For flip chip bipolar devices, there is substantial alpha particle release from glass frit. To protect the IC, 50 to 75 µm of silicone gel is used by IBM to keep alpha particles from reaching ceramic sources. For those designs, the I/O count is low, and solder bumps can be put at the perimeter of the chip; therefore it is acceptable for memory chips. However, for logic devices (ASIC), there is a very high I/O count, and the solder bumps have to be placed virtually everywhere on the IC surface.39 In this case, a low-alpha-particle-emission solder will be required. For wafer-level packages, such as WLCSP, the concerns about alpha particle emission due to solder interconnects are quite similar to those for flip chip packages, due to the proximity of solder bumps to ICs. 9.3.5 Sources of low-alpha lead-bearing solders37

Low-alpha leads can be obtained from several sources, including: (1) “cold” lead ore; (2) the laser isotope separation process; and (3) antique lead. Lead is extracted from lead sulfide ore. Some ores are colder (less alpha particle emission) than others. Current mines in operation yield materials with surface activity rates between 0.05 and 70.0 count/ cm2⋅h. Typical lead alpha particle emission rates are about 10 to 100 count/cm2⋅h. Some suppliers, such as Johnson Matthey, have found sources of lead ore with low alpha particle emission. The radiations of those ores are rated as LC1 (low count class 1), with alpha particle emission rates of 0.2 to 0.5 count/cm2⋅h, and as LC2 (0.05 count/cm2⋅h).



330

Chapter Nine

Cosmic ray has an alpha particle emission rate of ∼0.005 count/cm2⋅h and is considered LC3. The second low-alpha lead source is laser isotope separation technology. This technology, developed in Russia, uses laser radiation to vaporize the lead. The foundation for laser purification (isotope separation), as noted by Pure Technologies, is the capability of laser radiation to select specific frequencies (energies) from substances with great accuracy. All basic substances are formed from atoms. Atoms carry their own specific frequencies (energies), which may be specifically “excited” by specially tuned laser radiation. Laser radiation targeted at a specific frequency causes electrons in this frequency to selectively ionize, or become charged. These selectively charged atom particles are then separable and removable. Undesirable particles may, therefore, be removed, thereby cleansing the basic substances. This technology reduces 210Pb concentration by 10 to 100 times by means of one stage of isotope separation, and is claimed to be able to get the alpha activity down to less than 0.001 count/cm2⋅h. If the consumption rate of lowalpha lead exceeds the natural regeneration rate of natural low-alpha lead, this separation technology may eventually be the long-term source of low-alpha lead. The third low-alpha lead source is through sea salvage companies, such as Aloveo and Sea Recovery Ltd. (SRL). In many sunken ships, lead is used to clad holes to avoid barnacle formation underwater. In this lead, after it has sat on the ocean for 500 years, most of the 210Pb has already turned into very cold 206Pb through natural decay. Thus, there is no alpha particle emission concern. A lot of lead materials in sunken ships have been located. The 206Pb left on the ships can be purified for reclassification processing. About 600 tons of lead have been identified or located. The price is not very expensive, and the rating is about LC3.37 The alpha particle emission rate is even as low as 0.0002 count/cm2⋅h, according to the SRL data.37 Another source for antique lead is through recovering the old lead used for water pipes in ancient Roman cities or the old lead used in some old buildings, such as lead on the roofs of old churches in the U.K. There is at least one company, AFAIR, that offers to reroof old churches free provided the company can keep the old lead it removes.37 The limited quantity of antique lead suggests that this source may only be temporary. 9.3.6 Price of low-alpha lead-bearing solders37

Low-alpha lead is considerably more expensive than regular lead, which is about $0.30/lb. At this stage, the price of low-alpha lead may




331

vary significantly from vendor to vendor. The price range for low-alpha lead is detailed in Table 9.3, based on the listed prices of several vendors. Unless otherwise specified, the price in Table 9.3 refers to that of lead itself. For the LC3 class, antique lead seems to be cheaper than lead produced by laser isotope separation. 9.3.7 Current usage of low-alpha lead-bearing solders

Many companies, such as Intel, IBM, Delco, and Solectron, use lowalpha lead-bearing solders for advanced microprocessors and ASICs. Compaq also uses low-alpha lead-bearing solder for the Alpha chips. Commodity products do not need low-alpha lead-bearing solders at this stage. However, deep submicron (0.25 or 0.18 µm) applications will definitely have more need for low-alpha lead-bearing solders. The semiconductor industry is currently using solders with alpha particle emission levels ranging between 0.05 and 0.01 count/cm2⋅h (LC2 level). With increasing I/O density, decreasing power supply voltage, and further miniaturization of the IC devices, the requirement for alpha particle emission level may soon move to the LC3 level.37 Flip chip volume worldwide is expected to be 2514 million units by 2002, with a calculated annual growth rate of 34.62 percent.39 Assuming the average I/O of flip chip is 100, with each solder bump being 10 mil in diameter, and assuming the use of solder alloy Sn63-Pb37, the quantity of lead needed will be 6.2 metric tons. Obviously this is very likely the high end of low-alpha lead consumption needed for waferlevel interconnects, and appears to be well within the reach of the lowalpha lead supply.37

TABLE 9.3

Prices of Low-Alpha Lead-Bearing Solders

Alpha emission rate (count/cm2⋅h)

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