Conference Proceedings of the Society for Experimental Mechanics Series
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Tom Proulx Editor
MEMS and Nanotechnology, Volume 4 Proceedings of the 2011 Annual Conference on Experimental and Applied Mechanics
Editor Tom Proulx Society for Experimental Mechanics, Inc. 7 School Street Bethel, CT 06801-1405 USA
[email protected] ISSN 2191-5644 e-ISSN 2191-5652 ISBN 978-1-4614-0209-1 e-ISBN 978-1-4614-0210-7 DOI 10.1007/978-1-4614-0210-7 Springer New York Dordrecht Heidelberg London
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Library of Congress Control Number: 2011923429 The Society for Experimental Mechanics, Inc. 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
MEMS and Nanotechnology—The 12th International Symposium on MEMS and Nanotechnology (ISMAN)—represents one of eight volumes of technical papers presented at the Society for Experimental Mechanics Annual Conference & Exposition on Experimental and Applied Mechanics, held at Uncasville, Connecticut, June 13-16, 2011. The full set of proceedings also includes volumes on Dynamic Behavior of Materials, Mechanics of Biological Systems and Materials, Mechanics of Time-Dependent Materials and Processes in Conventional and Multifunctional Materials; Optical Measurements, Modeling and, Metrology; Experimental and Applied Mechanics, Thermomechanics and Infra-Red Imaging, and Engineering Applications of Residual Stress. Each collection presents early findings from experimental and computational investigations on an important area within Experimental Mechanics. The 12th International Symposium on MEMS and Nanotechnology (ISMAN) was organized by: Cosme Furlong, Worcester Polytechnic Institute; Gordon A. Shaw, National Institute of Standards and Technology; Barton Prorok, Auburn University; Ryszard J. Pryputniewicz, Worcester Polytechnic Institute. Microelectromechanical systems (MEMS) and nanotechnology are revolutionary enabling technologies (ET). These technologies merge the functions of sensing, actuation, and controls with computation and communication to affect the way people and machines interact with the physical world. This is done by integrating advances in various multidisciplinary fields to produce very small devices that use very low power and operate in many different environments. Today, developments in MEMS and nanotechnology are being made at an unprecedented rate, driven by both technology and user requirements. These developments depend on micromechanical and nanomechanical analyses, and characterization of structures comprising nanophase materials.
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To provide a forum for an up-to-date account of the advances in the field of MEMS and nanotechnology and to promote an alliance of governmental, industrial, and academic practitioners of ET, SEM initiated a Symposium Series on MEMS and Nanotechnology. The 2011 Symposium is the twelfth in the series and addresses pertinent issues relating to design, analysis, fabrication, testing, optimization, and applications of MEMS and nanotechnology, especially as these issues relate to experimental mechanics of microscale and nanoscale structures. The symposium organizers thank the authors, presenters, organizers and session chairs for their participation and contribution to this track. We are grateful to the SEM TD chairs who cosponsored and organized sessions in this track. The opinions expressed herein are those of the individual authors and not necessarily those of the Society for Experimental Mechanics, Inc. Bethel, Connecticut
Dr. Thomas Proulx Society for Experimental Mechanics, Inc
Contents
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Integrated Process Feasibility of Hard-mask for Tight Pitch Interconnects Fabrication C.-J. Weng, National University of Tainan/University of Kang Ning
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Thermoelectric Effects in Current Induced Crystallization of Silicon Microstructures G. Bakan, N. Khan, H. Silva, A. Gokirmak, University of Connecticut
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Evaluation of Resistance Measurement Techniques in Carbon Black and Carbon Nano-tubes Reinforced Epoxy V.K. Vadlamani, V.B. Chalivendra, University of Massachusetts Dartmouth; A. Shukla, S. Yang, University of Rhode Island
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4
A Nano-tensile Tester for Creep Studies L.I.J.C. Bergers, Eindhoven University of Technology/ Foundation for Fundamental Research on Matter/Materials Innovation Institute; J.P.M. Hoefnagels, E.C.A. Dekkers, M.G.D. Geers, Eindhoven University of Technology
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The Measurement of Cyclic Creep Behavior in Copper Thin Film Using Microtensile Testing K.-S. Hsu, M.-T. Lin, C.-J. Tong, National Chung Hsing University
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New Insight Into Pile-Up in Thin Film Indentation B.C. Prorok, B. Frye, B. Zhou, K. Schwieker, Auburn University
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Measuring Substrate-independent Young’s Modulus of Thin Films J. Hay, Agilent Technologies, Inc.
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Analysis of Spherical Indentation of an Elastic Bilayer Using a Modified Perturbation Approach J.H. Kim, Stony Brook University; A. Gouldstone, Northeastern University; C.S. Korach, Stony Brook University
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Nano-indentation Studies of Polyglactin 910 Monofilament Sutures L. Sun, V.B. Chalivendra, P. Calvert, University of Massachusetts Dartmouth
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10 Analytical Approach for the Determination of Nanomechanical Properties for Metals K.K. Jha, N. Suksawang, A. Agarwal, Florida International University
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11 Advances in Thin Film Indentation B. Zhou, K. Schwieker, B. Frye, B.C. Prorok, Auburn University
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12 Cyclic Nanoindentation Shakedown of Muscovite and its Elastic Modulus Measurement H. Yin, G. Zhang, Louisiana State University
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viii 13 Assessment of Digital Holography for 3D-shape Measurement of Micro Deep Drawing Parts in Comparison to Confocal Microscopy N. Wang, C. Falldorf, C. von Kopylow, R.B. Bergmann, BIAS GmbH 14 Full-field Bulge Testing Using Global Digital Image Correlation J. Neggers, J. Hoefnagels, Eindhoven University of Technology; F. Hild, S. Roux, LMT Cachan; M. Geers, Eindhoven University of Technology
93 99
15 Experimental Investigation of Deformation Mechanisms Present in Ultrafine-grained Metals A. Kammers, S. Daly, The University of Michigan
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16 Characterization of a Variation on AFIT's Tunable MEMS Cantilever Array Metamaterial M.E. Jussaume, P.J. Collins, R.A. Coutu, Jr., Air Force Institute of Technology
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17 MEMS for Real-time Infrared Imaging I. Dobrev, M. Balboa, R. Fossett, C. Furlong, E.J. Harrington, Worcester Polytechnic Institute
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18 New Insights Into Enhancing Microcantilever MEMS Sensors S. Morshed, B.C. Prorok, Auburn University
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19 A Miniature MRI-compatible Fiber-optic Force Sensor Utilizing Fabry-Perot Interferometer H. Su, M. Zervas, C. Furlong, G.S. Fischer, Worcester Polytechnic Institute
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20 Micromechanical Structure With Stable Linear Positive and Negative Stiffness J.P. Baugher, Wright State University; R.A. Coutu, Jr., Air Force Institute of Technology
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21 Terahertz Metamaterial Structures Fabricated by PolyMUMPs E.A. Moore, D. Langley, R.A. Coutu, Jr., Air Force Institute of Technology
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22 Investigations Into 1D and 2D Metamaterials at Infrared Wavelengths J.P. Lombardi, III, R.A. Coutu, Jr., Air Force Institute of Technology
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23 MEMS Integrated Metamaterials With Variable Resonance Operating at RF Frequencies D. Langley, E.A. Moore, R.A. Coutu, Jr., P.J. Collins, Air Force Institute of Technology
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24 Creep Measurements in Free-standing Thin Metal Film Micro-cantilever Bending L.I.J.C. Bergers, Eindhoven University of Technology/Foundation for Fundamental Research on Matter/Materials Innovation Institute; J.P.M. Hoefnagels, M.G.D. Geers, Eindhoven University of Technology
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25 MEMS Reliability for Space Applications by Elimination of Potential Failure Modes Through Analysis R. Soni, Nagesh Karajagi Orchid College of Engineering and Technology, Solapur 26 Analysis and Evaluation Methods Associated With the Application of Compliant Thermal Interface Materials in Multi-chip Electronic Board Assemblies J. Torok, S. Canfield, D. Edwards, D. Olson, IBM Corporation; M. Gaynes, T. Chainer, IBM T.J. Watson Research Center
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27 Hierarchical Reliability Model for Life Prediction of Actively Cooled LED-based Luminaire B.-M. Song, B. Han, A. Bar-Cohen, University of Maryland; R. Sharma, M. Arik, GE Global Research Center
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28 Direct Determination of Interfacial Traction-separation Relations in Chip-package Systems S. Gowrishankar, H. Mei, K.M. Liechti, R. Huang, The University of Texas at Austin
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Integrated process feasibility of hard-mask for tight pitch interconnects fabrication
Chun-Jen Weng
[email protected] Center for General Education, National University of Tainan Department of Logistic and Technology Management, University of Kang Ning, Tainan, Taiwan, R.O.C.
ABSTRACT As scaling continues beyond nano-technology, integrated circuit reliability is gaining increasing concerns in IC (Integrated Circuit) fabrication technology with decreasing transistor gate size, and the impact of trace interconnect failure mechanisms on device performance and reliability will demand much more from integration schemes, interconnect materials, and processes. An optimal low-k dielectric material and their related deposition, pattern lithography, etching and cleaning are required to form dual-damascene interconnect patterns fabrication processes. As technology nodes advance to nanotechnology, metal hard-mask such as TiN is used to gain better etching selectivity and profile controlling to the low-k materials during the pattern etching process. A hard-mask scheme approach of interconnects patterning of wafer fabrication is the ability to transfer patterns into under layers with tightest optimal dimension control. Employing a hard-mask scheme in the fabrication process, successfully achieved lithography patterning, dry etch selectivity in high aspect ratio interconnects comparison with a non hard-mask process were discussed. An optimal planarization treatment of photo-resist, good etch selectivity, a feasible manufacturing integrated process of hard mask dual damascene scheme, optimal profile controlling the critical interconnects and good electrical device performances were studied for tight pitch damascene interconnect architecture. KEYWORDS: Hard-mask, Wafer Fabrication, Interconnects processes integration.
1. INTRODUCTION The increase in integration on an IC leads to a high-density BEOL multi-level interconnection structure which communicates the transistors to the package. The back-end-of line (BEOL) RC delay has gradually become a critical limiting factor in semiconductor circuit performance as a result of the rapid shrinking of critical dimensions of trace width of the semiconductor electronics. Nanotechnology semiconductor wafer manufacturing process defects can often impact product yields, depending on the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. The fabrication process defects occurring in a semiconductor device, which involves forming layer patterns on a semiconductor wafer by film patterns formation based on the result of manufacturing processes, thereby reducing the difference in critical dimension of patterns in the patterning process effect, the topology of the wafer, and the difference processing parameter and material. For the implementation of copper and low-k materials into a small pitch damascene interconnect architecture, it is important to understand use of etching and lithography technology to improve the wafer fabrication process technologies. As design rules continue to shrink, the demand increases for effective inspection tools to detect defects that affect device yields. During BEOL schematic formation, via hole etching, and trench etching are the dominant etching steps to form Cu interconnect layers; these steps are widely applied to manufacture the 90 nm node and beyond. Fabrication defects are one of the principle causes for yield reduction of wafers for IC manufacturers. Defects specification has been a highly problematic aspect of the wafer fabrication industry. The critical applications of anisotropic etching, plasma ashing and cleaning to form precisely controlled profiles of high-aspect-ratio form precise via holes and trenches used in advanced Cu/low-k interconnects in the back end of line (BEOL) are described in detail [1]. Moreover, the investigation of resist pattern collapse with top rounding resist profile was shown in [2]. They found that the pattern size is reduced as the device is more integrated. The resist deformation phenomenon has been a serious problem under 100 nm line width patterns. Because 65nm BEOL trenches etch is apt to suffer the marginal photo-resist issue, it is a T. Proulx (ed.), MEMS and Nanotechnology, Volume 4, Conference Proceedings of the Society for Experimental Mechanics Series 999999, DOI 10.1007/978-1-4614-0210-7_1, © The Society for Experimental Mechanics, Inc. 2011
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big challenge for trench etches process to simultaneously satisfy the requirements for both metal sheet resistance (Rs) and connecting resistance (Rc). The advanced process control based on lithographic defect inspection and reduction was proposed [3]. They proposed a methodology based on post lithographic defect inspection, and defective die count analysis was used, which provided effective process monitoring and yield maintenance. The reliability challenges for copper interconnects were discussed [4]. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Effects of width scaling and layout variation on dual damascene copper interconnect electromigration were also demonstrated in [5-6]. By study and optimization of hard mask stacks and etching fabrication; [7] developed dry etch processes for the fabrication of EUV hard mask used for etching in CMOS technology. The controlling surface reactions during etching of SiOCH and organic material model were proposed [8]. With the wide application of low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification in most important reliability issues during Cu/low-k technology development [9,10]. A method of forming optimal dual damascene process for the BEOL process was proposed [11,12]. To overcome these challenges, accurate and repeatable depth assessment of damascene structures requires the ability to resolve high-aspect-ratio structures in both a high density and isolated structures in the manufacturing process by improving yield. 2. EXPERIMENTS As technology nodes advance to nanotechnology and beyond, IC companies are investigating the use of a metal hard mask in order to gain better etching selectivity to the low-k materials during the dry etching process. A hard mask mechanism approach of fabrication for the modification interconnects fabrication processes of low-k and copper interconnects is used for dual damascene process for critical dimension control to obtain tight profile. When scaling the critical dimensions into nanotechnology, the impact of layout and line edge becomes important. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process requires a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. The nanotechnology copper dual damascene architecture was fabricated according to the scheme shown in Fig. 1. Dual-damascene technology in the fabrication of advanced interconnects presents itself as an integration and reliability challenge. B ondi ng pad
(BEOL)
Metal interconnects
M6 Via 5 M5 Via 4
D ielec tr ic film s ta ck
Tr en ch
Trench
W id e D im ension
V ia
M4 V ia 3 M3 Via 2 M2
B EOL C riti cal Di mens ion
V ia 1 M1
(FEO L)
NMOS
P MOS
Si
Fig. 1. Semiconductor multilayer interconnects physical structure. As design rules continue to shrink, the demand increases for effective inspection tools to detect defects that affect device yields. Defect inspection metrology is an integral part of the yield ramp and process monitoring phases of semiconductor manufacturing. Systematic yield losses are process-related problems that can affect all die chips on a wafer. It is important to produce better die chip per wafer by minimizing the cycle time to detect and fix yield problems associated with the advanced process module technology. High aspect ratio structures have been identified as critical structures where there are no known manufacture solutions for defect detection. A serious problem in wafer fabrication is the defects issue during the pattern development process, because it decreases the yield of wafer production. Abnormal patterning phenomena lead to yield loss after the electrical device test and productivity yield losses. Pattern profiles strongly depend on many manufacturing module processes, and can be suppressed by optimization of lithography, cleaning and etch processes. The defects inspection
3
map can be revealed the abnormal pattern profiles, which results in yield loss and abnormal electrical device. In Fig. 2, the defects inspection of the fabrication processes was investigated. Fabrication defects are one of the principle causes for yield reduction of wafers for IC manufacturers. Defects specification has been a highly problematic aspect of the wafer fabrication industry. Interconnect line shorts defects have a high potential of becoming fabrication yield killers for semiconductor manufacturing. It is important for in-line inspections for detecting, classifying and correcting yield limiting defects on all critical manufacturing processes steps.
(b) SEM images of wafer center (Normal)
(a) Defects inspection
(c) SEM images of wafer edge (Pattern collapse)
Fig. 2. Inspection images of comparisons of structure after trench pattern etching. 3. RESULTS AND DISCUSSION Wafer manufacturing variations can be classified as process systematic and random variations. Process systematic variations are predictable in nature and depending on deterministic factors such as layout structure and surrounding topological environment. A comprehensive evaluation and investigation of the physically relevant causes to develop feasible integrated processes are important for critical dimension interconnect trace. As Fig.3 demonstrated, the hard mask patterning scheme preserves minimizing damage caused by the plasma and strip processes, and reducing the thickness requirement for the underlying barrier film, and enables superior CD and profile control. The comparison of feasible hard mask lithography planarization scheme for dense pattern was also shown in Fig.4. As technology nodes advance to nanotechnology and beyond, IC companies are investigating the use of a metal hard mask such as TiN in order to gain better etching selectivity to the film materials during the dry etching process. Hard mask etching processes have been developed which allowed us to obtain tight profile and CD control. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the dry etching process in order to achieve a vertical profile and to protect the low-k materials under the etching mask. As hard mask approach adopted for better CD controlling in manufacturing process, the deposition film stack thickness is also increased. Three steps photo-resist gap fill approach and etching back planarization techniques are the process of increasing the flatness or planarity of the surface of a semiconductor wafer. This treatment method for etching which can increase the metal-to-photo-resist etching selectivity of a metal layer aimed to be etched with respect to photo-resist layers overlaying the metal hard mask layer. Moreover, etching of hard mask presents a challenge, as etching process should find a balance between contradicting requirements of providing sufficient selectivity to photo-resist and avoiding formation of excessive sidewall polymer resulting in CD gain. Photoresist 3
Photoresist 1 Hard mask TiN/SiN
( a) Film stack
(b) Photoresist fill ing
Photoresist 2
(b) Photor esist filling (c) E tching back (Flatting)
(c) Patterning
Etching back
Fig. 3. Feasible hard mask planarization integrated processes approach of high aspect ration trench patterning.
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Photoresist 3
Hard mask Photoresist 2
Photoresist 1
Fig. 4. Comparison of feasible hard mask lithography planarization scheme for dense pattern. In the comparisons of top SEM view images and cross-section view of dense via chain pattern of Fig.5 illustrates the different critical via chain structure and critical pattern of the improvement for different locations of wafer. Because the extra added hard mask films, consequently the depth of the via is also increased in manufacturing patterning process. The impact of via etching performance of different via chain structure was investigated. Comparing the results from dense and isolation critical via chain schemes shows that this present optimal via profiles. After via etching process, the hard mask remain of dense pattern is enough for the buffer of follow-up processes as: trench etching and chemical mechanical polish. An improved resist etch-back technique using three resist layers also has been developed which offers enhanced planarity over the dielectric film layers process. A photo-resist gap-fill material is used to ensure that the lithography process produces the best profiles and enables critical dimension control. The impact of trench etching on the electrical and reliability performance of different via chain structure was investigated. Fig. 6 illustrates top view SEM image and cross-section of the critical dense via chain developed photo-resist structure. Comparing results of trench developed photo-resist profile, the optimal photo-resist can strongly effect on trench patterning. It was identified that the profile of photo-resist top was severely damaged due to via gap filling attack of the lithography process. To compare lithography photo-resist profile structure for different trench pattern density, the TEM cross section images of trench etching photo-resist profile are illustrated in Fig.7. In order to check the causes of this patterns collapse phenomenon, the profile of photo-resist profile of trench etching is important in process development. For the via-first dual damascene process, a good controlling of photo-resist and via gap filler photo-resist typically used to ensure a lithography process produces the best profiles and critical dimension control and integrates structures having small feature sizes. The via gap filler material treatment may include etching the dielectric layer and the gap-filling material layer to planarize the via gap filler material layer. Therefore, a planarizing bottom photo-resist film and via gap filler material are used to ensure a trench lithography process produces the best profiles and critical dimension control in follow-up etching process. Isolation via
Dense vias
Dense vias
Hard mask remain
300 nm
300 nm
100 nm
(a) Top view (b) Cross-section Fig. 5. Inspections of hard mask remain on different pattern density after via etching. Cross-section
Top view
Normal
100 nm
0.5 μm
100 nm
0.5 μm
Pattern Collapse
(a) After lithography
(b) After Etching
Fig. 6. Inspections of lithography photoresist profile effects on trench patterning.
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Developed trench Photoresist
(a) Wide trench
(b) Isolation via/dense trench
(c) Dense/dense trench
Fig. 7. Comparison of lithography photo-resist profile structure for different trench pattern density.
Edge
Center
Dry etching processes are commonly used to fabricate vertical sidewall trenches and vias for interconnect dual damascene fabrication processes. The important factor that causes the pattern profile in a dual damascene architecture is the locations and the design pattern density. In comparison the SEM pictures of Fig. 8 show trench etch results by optimal treatment planarization photo-resist gap filling for different dense pattern design. The optimal pattern profile controlling which makes no abnormal pattern even via chain, narrow and wide interconnect trace line for overall wafer. Different lines and via holes with feature sizes down to 100 nm have been realized by in-line process inspection and electrical device verification. The developed etch processes have been successfully applied for high aspect ratio hard mask fabrication. The impact of trench etching on the electrical and reliability performance of different via chain structure was investigated. Fig. 9 illustrates the cross-section of the critical dense via chain structure obtained that was after the trench etching. Comparing results from different critical dense via chain schemes shows that this present optimal integrated processes can also get effective pattern as demonstrated in post trench etch clean of via fist post trench dual damascene process.
Fig. 8. Feasible process inspections on different critical patterns after trench etching.
(a)
(b)
Fig. 9. Cross-section verification of different via chain pattern after trench etching. Fig. 10 shows the TEM micrographs of the cross-sectional profiles of Cu dual damascene structure along the silicon substrate / gate transistor / critical interconnects / wide metal interconnects, respectively. The damascene structure of the interconnect chain with the layers identified after copper processes. Consequently, the wafer fabrication integrated process provided the best electrical performance at both dense via chain and isolated via test structures by the present study. As demonstrated in Fig.11 (a) and (b), the electrical device test pattern is always used to check the semiconductor process in-line electrical device verification; The drain voltage (VD=1V), for source voltage (VS) and substrate voltage (VSUB); VS=VSUB=0V, and electrical current (Id). The electrical resistance is Rc= VD / Id. The distribution of electrical
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resistance is tight for optimal integrated process and there are no open electrical test data for optimal integration process. Figs. 11 (b) shows the representative cumulative resistance distribution of the dense via chains associated with the optimal treatment etch processes. The via contact resistance spread of dense via chains were also compared among the different wafer processes.
Fig. 10. TEM inspection of multilayer interconnect scheme. Rc (ohm/ Via) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
Electrical test cross-section
200 nm
wafer Resistance distribution
Fig. 11. Contact resistance of electrical device test of optimal integration process. Fig. 12 shows the distributions of sheet resistance measurements of the different interconnect trace width respectively. No significant deterioration of sheet resistance of good trench profiles after the etch process is shown in Fig. 12(b) for comparison. The resistance spread of dense trace lines were also compared among the different pattern width. It is obvious that the wafer fabrication process resulted in the tightest control of resistance spread even 70 nm width. Fig. 13 shows the cumulative distributions of leakage current measurements of the metal bridging-continuity. The line-to-line leakage current of both metal bridging-continuity structures were well controlled. No significant deterioration of line-to-line leakage current is demonstrated. The median leakage current of the trace / space combinations is located below 1.0E-9 A. That means the wafer process provided a better control of the pattern isolation even for 90 nm /90 nm (trace width/ space). Moreover, the integrated wafer fabrication processes resulted in tight distribution of leakage current compared different pattern designs. That means the integrated wafer processes provided a better control of the resistance spread and pattern isolated. R s (ohm/ sq) 0.250 0 .25 0 0.225 0 .22 5 0.200 0 .20 0 0.175 0 .17 5 RS (ohm/sq)
0.150 0 .15 0 0.125 0 .12 5 0.100 0 .10 0 W =0 .100
90
W =0.0 90
85
W =0. 080
80
W=0 .075
75
W = 0. 070
70
Interco nnect widt h (n m)
Fig. 12. Interconnect sheet resistance of different width by optimal integration processes.
7 B r id g e C u rr e n t ( A ) 1 .0E-0 5
1 .0E-0 7
1 .0E-0 9
1 .0E-1 1
1 .0E-1 3 9 0 /9 0
9 0 /1 0 0
9 0 /1 1 0
90 /12 0
9 0 / /1 3 0
T ra c e w id t h / s p a c e ( n m )
Fig. 13. Space effects of Interconnect bridge current of optimal integration processes. 4. CONCLUSIONS Hard mask etching processes have been developed which allowed us to obtain tight profile and CD control. The impact and improvement of high aspect ratio nanotechnology hard mask dual damascene by integrated manufacturing processes were studied. The effects of integrated fabrication processes on lithography, etching in dual damascene copper interconnects manufacturing processes have been investigated. With the understanding of the complexities involved in copper interconnects and the associated integration processes, a robust reliability is achievable for the new enhancement copper technology. ACKNOWLEDGMENT The author gratefully acknowledges the support and assistance of NSC 98-2221-E-426-002. REFERENCES [1]
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[10] Aelst JV, Struyf H., Boullart W, Vanhaelemeersch S. High aspect ratio via etch development for Cu nails in 3-D-stacked ICs, Thin Solid Films. Thin Solid Films 2008;516:3502–06. [11] Weng CJ, Lin YS, Chen CY. Method of forming Damascene Structure, US Patent 2007: US 7,189,640 B2 [12] Weng CJ. Nanotechnology copper interconnect processes integrations for high aspect ratio without middle etching stop layer. Materials Science in Semicon. Proces. 2010; 13(1):56–63.
Thermoelectric Effects in Current Induced Crystallization of Silicon Microstructures
Gokhan Bakan, Niaz Khan, Helena Silva, Ali Gokirmak Department of Electrical and Computer Engineering, University of Connecticut 371 Fairfield Way, U-2157, Storrs, CT 06269 USA
Abstract We have observed melting of nanocrystalline silicon microwires self-heated through single high-amplitude microsecond voltage pulses which leads to growth from melt upon resolidification. The resolidified regions form two single-crystal domains for wires with sub-micrometer widths. The current densities (J) involved in this process are ~ 1-10 MA/cm2 for suspended wires, and ~ 10-100 MA/cm2 for wires on oxide. These extremely high current densities and the resulting high temperatures (~ 1700 K) and temperature gradients (~ 1 K/nm) along the microwires give rise to strong thermoelectric effects. The thermoelectric effects are characterized through capture and analysis of light emission from the self-heated wires biased with lower magnitude AC voltages (J < 5 MA/cm2). The hottest spot on the wires consistently appears closer to the lower potential end for n-type, and the higher potential end for p-type microwires. Experimental light emission profiles are used to verify the linear thermoelectric models and material parameters used for simulations. Good agreement between these experimental and simulated profiles indicates that the linear models can be used to predict the thermal profiles for current induced crystallization of microstructures. However, the linear models are expected to be insufficient to fully explain the thermoelectric processes for higher current densities and stronger thermal gradients that are generated by high-amplitude short duration pulses.
Introduction Polycrystalline (poly-Si), amorphous (a-Si) and nanocrystalline silicon (nc-Si) are commonly used for large area electronics such as flat panel displays [1], x-ray imaging arrays [2] and solar cells. Currently a-Si is used for silicon thin film transistors (TFTs) for large area electronics [1] due to its uniformity and low-temperature processing, despite its relatively low electrical carrier mobility [3]. There is a growing demand for displays and sensors on larger areas, using flexible and shatter-proof substrates like plastics, that can operate at higher speeds and sensitivities. Large areas require uniformity, flexible substrates require low temperature processing, and higher speed and sensitivity require use of crystalline material instead of amorphous. Cost effective techniques to achieve single-crystal Si on arbitrary substrates will also enable significant technological advancements, such as integration of high performance circuitry with displays or sensor arrays as complete systems. The interest in achieving high speed circuitry for large area electronics has motivated studies on crystal growth on glass and plastics [4], transfer of crystalline structures onto glass and plastic substrates, and crystallization of low temperature deposited silicon [1, 2, 5]. Crystallization of low temperature deposited a-Si films is a promising approach that has been studied in the past decades. This requires thermal processing of a-Si. High temperature annealing of a-Si films typically results in polycrystalline films. However, it has been reported that patterning the films to form microstructures with widths smaller than 250 nm can result in growth of single crystals along the length with preferred crystal orientation. Metal induced crystallization [6, 7] reduces the required temperature significantly, making it more compatible with low-temperature substrates but there are some concerns regarding the metal contamination in the crystallized films [8]. Local heating techniques, where the energy required for heating is directly delivered to the film or the patterned structures, allow the substrate to remain at room temperature. These techniques include sequential lateral solidification using an excimer laser [9, 10], rapid melting and growth from melt using self-heating [11] or microfabricated heaters atop the structures [12]. Some of the laser annealing techniques, such as sequential lateral crystallization, are currently in industrial use.
T. Proulx (ed.), MEMS and Nanotechnology, Volume 4, Conference Proceedings of the Society for Experimental Mechanics Series 999999, DOI 10.1007/978-1-4614-0210-7_2, © The Society for Experimental Mechanics, Inc. 2011
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10 The approach described in this paper is crystallization of nc-Si microwires through single microsecond voltage pulses (J < 10 MA/cm2) leading to self-heating, melting and growth from melt in a very short time (~ 1 μs). Larger current densities (J~20 MA/cm2) are required for further reduction in voltage pulse duration (d ~ 20 ns). The short duration local heating of the structures to be crystallized makes this approach compatible with low-temperature substrates. Real-time current-voltage measurements can be made on these structures during the crystallization process which can help understanding the mechanisms involved. The extreme thermal gradients (~1 K/nm) and the short time scales involved in these experiments are similar to those in pulse laser annealing. The main differences in this case are due to formation of molten filaments in the current path and thermoelectric effects which appear to be very strong under the extremely high electric current densities during the voltage pulse. Here, we give an overview of our experimental observations on melting, growth from melt and thermoelectric effects, and computational studies on heating and cooling of the wires including the role of thermoelectric effects.
Fabrication The microwires are patterned on n- and p-type nc-Si films deposited on oxidized single crystal Si wafers (~500 nm SiO2) in a low pressure chemical vapor deposition (LPCVD) system at 580 C or 600 C with phosphorous doping or at 560 C with boron doping ([P], [B] > 1020 cm-3). The room temperature resistivities of the n-type films deposited at 580 and 600 C are 30.4 ± 5.6 and 23.0 ± 0.3 PȍFPUHVSHFWLYHO\DQGUHVLVWLYLW\RIS-W\SHILOPLVPȍFP Some of the microwires are suspended by etching the underlying oxide using buffered oxide etch. The ZLUHV¶ dimensions range from 0.5 to 5.5 ȝPin length and 100 nm to 1 ȝm in width. Metal extensions (Ti/Al stack) are deposited to form ohmic contacts to the Si pads.
Microsecond voltage pulse crystallization The experiments are conducted using a semiconductor probe station, a parameter analyzer, a pulse generator unit (PGU), and an oscilloscope. I-V characteristics of the microwires are measured before and after the voltage pulses using the parameter analyzer. The applied voltage and current through the microwire are measured by the oscilloscope during the pulse. Tungsten needles are used to probe the metal contacts or the silicon contact regions of microwires without metal extensions [13]. The melting of the wires is verified by extracting the wire resistivity during the pulse. This is achieved by calculating the resistance of a number of structures with different widths and lengths, yielding to resistivity of 73.3 ȝȍFP [13, 14]. This value is in good agreement with previous reports on liquid Si resistivity of ȝȍFPE\*OD]RYHWDO[15], 75.2±0.6 ȝȍFPE\6FKQ\GHUVHWDO[16] DQGȝȍFPE\6DVDNLHWDO[17]. Liquid silicon at melting temperature is reported to be ~10% denser than silicon at solid phase at room temperature [15], which scales down the extracted liquid silicon resistivity value to 66.0 ± ȝȍFP. Melting of the wires requires less current and the mechanical stress induced by the substrate is eliminated if the wires are suspended by removing some of the underlying oxide. The heat loss from the suspended wires is predominantly to the contact regions at the two ends. The as-fabricated suspended microwires, wide and thin with uniform nanocrystalline texture, as seen in scanning electron microscope (SEM) images taken after the pulse (Fig. 1a), acquire a cylindrical shape with smooth surfaces (due to surface tension) and a lump in the middle (Fig. 1b) upon melting and resolidification. The as-fabricated structures have compressive stress, seen as sagging of the structures after the release (Fig. 1a). The recrystallized wires are stretched between the contact pads indicating a tensile stress. The resolidification process starts from the silicon pads and move towards the middle of the microwire. Some of the liquid silicon cannot fit in the middle as the two solid-liquid fronts meet, since silicon expands as it solidifies. Excess silicon is ejected and forms a lump after resolidification (Fig. 1b). The microwires which experience longer duration pulses show tapering and breaking (Fig. 1c) through silicon migration towards the silicon pads. Strong thermal gradient along the suspended microwires, due to low heat loss to the substrate, is expected to suppress nucleation along the wire and consequently limits the number of grains to two, one starting from each end. The conductance of the microwires is enhanced after the voltage pulse. Fig. 1EVKRZVDȝPORQJPLFURZLUHZLWKSUH-pulse WRWDOUHVLVWDQFHRINȍ7KHWRWDOUHVLVWDQFH5 Si FRQVLVWVRIWKHPLFURZLUHaNȍ DQG6LSDGUHVLVWDQFHVaNȍ After the voltage pulse, the total resistance of the microwire in Fig. 1EZDVPHDVXUHGDVNȍZKLFKLVVPDOOHUWKDQWKH pre-pulse Si pad resistance. Low post-pulse resistance is attributed to conductance enhancement in both the microwires and the contact regions, even though the changes in the contact regions are not observable under SEM in this case. Resistivity of the pulsed, unbroken microwires is reduced by a factor of up to10x [18] indicating crystal growth rather than solidification in amorphous form.
11
(b)
nc-Si
(a)
(c)
lump SiO2
disconnected
Si accumulation L: 3.5 μm
1 μm
L: 2.5 μm
RInitial: 56.7 kȍ RFinal: 22.2 kȍ L: 3.5 μm
Fig. 1 (a) An as-fabricated, n-type, suspended microwire, and two microZLUHVDIWHUE 9ȝVDQGF 9ȝV pulse. Resistance of the wire in b) decreased significantly after the pulse [19]
Capture and analysis of light emission from the microwires under long duration biases The microsecond pulsing of the microwires results in very high current densities (1-100 MA/cm2). The peak temperature on the wire reaches the melting temperature of Si (1690 K) while the contact pads remain at room temperature, leading to thermal gradients on the order of ~1 K/nm. Thermoelectric effects are expected to be very significant at such current densities and thermal gradients [20, 21]. The transient effects in the short time scales involved in melting and crystallization in these experiments are difficult to probe. However, it is possible to gain some information about the steady-state temperature profile and the thermoelectric effects from the light emission from the wire as it is heated up to ~1000 K and beyond. This allows for verification of the high temperature materials parameters and models used for the computational studies. The first optical observation of thermoelectric effects in a single material system (Thomson effect) was reported by Mastrangelo et al. [22]. The authors observed that the peak light intensity (hottest spot) on p-type poly-Si micro-lamps was shifted from the center toward the higher potential end (V+). Englander et al. [23] observed a similar asymmetric light emission profile shifted towards the lower potential terminal in n-type poly-Si micro-heaters. Jungen et al. [24] also reported a shift towards the lower potential end for self-heated, n-type poly-Si, micro-bridges. Thermoelectric effects (thermoelectricity) is due to the coupling of electronic and heat transport through heat transfer by charge carriers. Direct electrical-thermal energy conversion for power generation, solid-state cooling [20, 21] and characterization of semiconductor materials [25] are the most common applications of thermoelectricity. Thermoelectricity can be observed as an open-circuit voltage across a temperature difference in a circuit of two different materials (Seebeck effect), heating or cooling at a current-passing junction between two different materials (Peltier effect) and heating or cooling along a current carrying homogeneous material under a temperature gradient (Thomson effect). The Seebeck voltage polarity and heating versus cooling for Peltier and Thomson effects depend on temperature-dependent thermoelectric properties of the material and directions of temperature gradient and electric current. The three thermoelectric effects are characterized by the Seebeck (S), Peltier (3 DQG7KRPVRQȕ FRHIILFLHQWVZKLFKDUHLQWHUUHODWHGE\WKHIXQGDPHQWDO.HOYLQUelationships [21]: 3
ST
E
T
, dS dT
(1) (2)
Thomson effect results in skewing of temperature profiles and is typically very small in macroscopic structures; however, it is significant in self-heated small-scale structures such as micro-lamps [22] and micro-heaters [23, 24] as mentioned above, as well as phase-change memory (PCM) elements [26], due to large current densities and temperature gradients. In all of these cases of self-heating at high temperatures, the hottest spot along the structures appears closer to the lower potential end (V-) for n-type structures and closer to the higher potential end (V+) for p-type structures, in agreement with expected hightemperature positive Thomson coefficient for n-type ȕ! and negative Thomson coefficient for p-type ȕ materials. DiCastro et al. [26] have calculated a Thomson coefficient of -1ȝ9.for SbTe above room temperature using an analytical solution for the hottest spot location and indicated that a 5% reduction in RESET current was obtained in
12 asymmetric PCM structures due to Thomson effect. However, changes in the material during the heating process can contribute to the asymmetry in the temperature profile and hence the observed asymmetries may be larger than what is due to the pure contribution of thermoelectric effects. In our experiments, we have recorded videos of light emission from self-heated nc-Si microwires using a high magnification optical setup and a commercial high-definition (full HD) camcorder at 30 frames per second. The wires self-heated to sufficiently high temperatures (T > 800 C [23]) emit light in the visible range. The speed of the measurement is limited by the sensitivity and the frame rate of the camera. Hence, the light emission from the wires was observed for low frequency AC signals at ~ 1 Hz. The light intensity profiles along the microwires and shift in the brightest (hottest) spot are extracted from the videos using MATLAB. Fig. 2a-b show glowing of a 2.5 ȝm long, suspended, n-type microwire during positive and negative cycles of an AC signal generated by the parameter analyzer. The hottest spot on the microwire alternates position as the current direction changes, confirming that the shift of the hottest spot is not caused by any asymmetric geometrical or thermal boundaries, but is due to thermoelectric effects. Fig. 2c shows current through the microwire and the shift in the hottest spot location as a function of time. The shift in the hottest spot for either cycle of the AC signal is approximately 250 nm (10% of the length).The shift in the hottest spot for the negative cycle gradually increases over time, showing a memory effect. Similar behavior is observed on other wires when they are biased with opposite polarity of the previous bias.
I (mA), 'x (Pm)
(a)
1.0
IWire : 0.95 mA
IWire : 0.93 mA
(b)
,
0.5
'x
0.0 -0.5
x
-1.0
(c)
20
21
22 time (s)
23
24
Fig. 2 A 2.5 ȝP long, suspended, n-type microwire during the (a) positive and (b) negative cycle of an applied square wave with ~ 0.95 mA (~3 MA/cm2) amplitude. Current levels and directions are as indicated. Wire center is located at x= 0. (c) Current (I) through the microwire and shift (ǻx) in the hottest spot location as a function of time [19]
Numerical modeling The experimental results are complemented by finite element analysis of a 2.5 ȝP long, suspended, n-type microwire using COMSOL Multiphysics software [27] including the thermoelectric effects, using the parameters available in the literature. The thermoelectric effects are included in both current continuity and heat transfer equations [28]: .J
d Si C P
.(
dT dt
V ST
U
.( k T )
)
0
,
U J . J TJ . S ,
(3) (4)
where dSi is the density, CP is the specific heat, k is the thermal conductivity, ȡ is the electrical resistivity and S is the Seebeck coefficient. The thermoelectric term (-TJ S) in Eq. 4 reduces to the Thomson heat for homogeneous structures (-dS/dTJ T). The resistivity of the microwire is modeled as an exponentially decaying function from its room temperature value of 23 PȍFPWRWKHPHOWLQJWHPSHUDWXUHYDOXHRIPȍFP [17], following the trend of the measured resistivity in the 300 - 650 K range (ȡ +195.5e-T/142 PȍFP). Temperature dependent thermal conductivity and Seebeck coefficient are not yet characterized for the heavily doped nc-Si used for the fabrication of the wires, nor are there any thermal conductivity or Seebeck coefficient data available in the literature on nc-Si, to the best of our knowledge. Hence, an inverse polynomial extrapolation function given in Ref. [29], fitting the experimental thermal conductivity of heavily-doped poly-Si in the 300 K to 800 K range, is used. Similarly, Seebeck coefficient of heavily doped poly-Si ([P] ~ 1020 cm-3) is used at low temperature
13 range (150 K ± 450 K) [30] and Seebeck coefficient of poly-Si with [P] = 6x 1017 cm-3 is used at high temperature range (700 K ± 1350 K) for modeling [31]. The Seebeck coefficient in the 450 K ± 700 K range is extrapolated linearly from these two poly-Si data sets which intersect at ~ 800 K, and it is also linearly extrapolated in the range between 1350 K ± 1690 K using the high temperature data. Density and specific heat of c-Si are close to those of poly-Si and a-Si [32] and change only slightly with temperature, therefore constant (room temperature) c-Si values [27] are used. The room temperature values of the modeling parameters of nc-Si, SiO2 and c-Si layers are shown in Table 1. Fig. 3a shows the 3D structure used for the modeling of the microwire and the electrical and thermal boundaries. A 5.8 V, 1 ȝs voltage pulse or square wave (AC) with increasing amplitude is applied across the wire. The current continuity and heat transfer equations including thermoelectric effects are solved self-consistently (Eq. 3 and 4). The modeling of pulsed wires is also performed without thermoelectric effects for comparison. Table 1 Room temperature values of the physical parameters used for the modeling
nc-Si SiO2 Si
ȡȍFP 23x10-3 d 1016 d 10-1
k (W/m.K) c 54 d 1.38 d 163
a,b
a
d (kg/m3) d 2330 d 2203 d 2330
CP (J/kg.K) d 703 d 703 d 703
S ȝ9/K) e,f -105 -
This work, bRef.[17], c Ref.[29], d Ref. [27],e Ref. [30], f Ref. [31]
Simulation results for the pulsed wire are seen in Fig. 3. The peak temperature on the wire reaches melting temperature of VLOLFRQ. LQȝVIRU91 ȝVYROWDJHSXOVHFig. 3b). The voltage pulse amplitude is chosen to keep the peak temperature on the wire below the melting temperature, since the phase change is not included in the modeling. The time to reach the melting temperature scales down as the voltage pulse amplitude is increased (Fig. 3c). The simulations suggest that the peak temperature on the wire can reach the melting temperature in less than 10 ns for voltage pulse amplitudes larger than 30 V. The cooling time of the wire is less than 250 ns for the given geometry. The simulated temperature profile along the wire just before melting is significantly skewed compared to the profile simulated without thermoelectric effects (Fig. 3d). The peak temperature is closer to lower potential end of the wire, which is in agreement with previous reports and our optical observations. Fig. 3d suggests that the melting of the wire starts on one end and continues until the whole wire melts. 1800
SiO2 (500 nm)
c-Si (5 ȝm)
(a)
0V 300 K
6 TMelt
1500
5 4
1200
3
900
2
600
1
300 (b) 0.0
0
1000
1800
0.5 1.0 1.5 Time (Ps)
VPulse (V)
Peak Temperature (K)
nc-Si (80 nm)
2.0
I 1200
T (K)
tmelt (ns)
1500
100
10
900 600
1
(c)
0
10
20 30 VP amplitude (V)
40
300
with TE effects
(d) -1.0
w/o TE effects -0.5
0.0 0.5 x (Pm)
1.0
Fig. 3 (a) 3D structure used for numerical modeling. A voltage pulse or a AC signal with increasing amplitude is applied to the square section of the left pad, while the square section on the right pad and the bottom surface of the substrate are set to 0 V. The temperature at these electrical boundaries is kept at 300 K. (b) Simulated peak temperature on the wire during the voltage pulse. (c) Simulated time required to reach the melting temperature of silicon (1690 K) on the wire as a function of voltage pulse amplitude. (d) Simulated temperature along the wire just before reaching melting temperature with and without thermoelectric effects. The arrow indicates the current direction (I: 0.74 mA) [19]
14 The light emission from the self-heated microwires is expected to be due to black-body radiation [22]. The light emission intensity profiles corresponding to the simulated temperature profiles are calculated using Eq. 5 [22] in the visible range to compare the simulated and experimental light intensity results. E (T )
³ H ( O , T ) E ( O , T )d O
,
(5)
O
where İȜ7 LVWKHHPLVVLYLW\ of the microwires which is assumed to be constant since it changes only very slightly throughout the visible range for silicon [33]. (Ȝ7 is the black-body radiation from the microwire as a function of radiation wavelength and temperature. The calculated light emission is convoluted using a point source approach to emulate the diffraction limited experimental light intensity profiles [34]. Each 1 nm segment of the microwire is assumed to be a point light source with a Gaussian intensity profile as given in Eq 6. I Gaussian ( x )
I ( x center ) 2 SV
2
( x x center )
e
2V
2
2
,
(6)
where xcenter is the point where the Gaussian profile is evaluated, I(xcenter) is the black-body radiation from WKDWSRLQWDQGıLV the width for the profile. 7KHRSWLFDOUHVROXWLRQRIRXUV\VWHPFDOFXODWHGDVȜ ZKHUHȜLVthe wavelength of the emitted light [34]ZDVXVHGIRUı7KHintensity profiles from each point source are added together and scaled to have the same peak intensity as the experimental profile. Fig. 4c shows the experimental (I = 0.95 mA, J~3 MA/cm2) and simulated light intensity profiles (I = 0.96 mA) showing 250 nm and 154 nm of shift in the hottest spot (Fig. 4a-b), respectively. The simulated light intensity profiles are in good agreement with the experiments, showing the correct direction of the asymmetry and a comparable magnitude for the shift of the hottest spot location. The difference is expected to be due to a mismatch between the actual physical nc-Si parameters (electrical and thermal conductivities and Seebeck coefficient) and those used for the simulation from the literature for similar materials.
1200
(a)
100
IWire: 0.96 mA
1000
I
x (b)
600
Light Intensity (a.u.)
50
800
400 K
(c)
Experiment
0 100
Modeling
(d) I
50
IWire: 0.96 mA 0
-1.0
-0.5
0.0
0.5
1.0
x (Pm)
Fig. 4 (a, b) Simulated temperature profiles of the suspended, n-type microwire for indicated current level and direction. Experimental and simulated light intensity for (c) positive and (d) negative voltage cycles. Current direction for each cycle is as indicated. The simulated light intensity profiles are calculated as black-body radiation from the microwires in the visible range, at a current level (0.96 mA) that matches the experimental value [19]
Summary Nanocrystalline silicon microwires are self-heated, melted and crystallized by microsecond voltage pulses. The crystallized microwires are under tensile stress and typically acquire a cylindrical shape with smooth surfaces. Significant reduction in resistivity of pulsed, suspended microwires indicates crystallization of the microwires upon resolidification, with growth of large single crystal domains.
15 The extremely high current densities (1-100 MA/cm2) and temperature gradients (~ 1 K/nm) reached along the microwires result in strong thermoelectric effects as observed through asymmetric heating of the microwires. These thermoelectric effects are analyzed through capture of asymmetric light emission from both n- and p-type microwires during low-frequency AC signals. The hottest spot is always closer to the lower potential end for n-type microwires and closer to the higher potential end for p-type microwires. AC voltage applied to the microwires results in alternating location of the hottest spot, confirming the thermoelectric nature of the observed asymmetric self-heating, rather than being due to any asymmetric geometrical or thermal boundary condition. Numerical modeling of the thermoelectric transport in an n-type microwire during an AC signal, including temperature dependent physical parameters shows good agreement with the experiments. Simulation results for a microsecond voltage pulsed microwire show significantly skewed temperature profiles for temperatures close to melting temperature of Si, suggesting this model can be used to predict the heating and cooling of microwires during the rapid self-heating and crystallization process. The findings of this work are relevant for studies on crystallization techniques and thermoelectric effects under high current densities and thermal gradients. Higher performance may be achieved for small-scale electronic devices, such as phasechange memories, by accounting for thermoelectric effects in device design.
Acknowledgements The devices were fabricated at the Cornell NanoScale Science & Technology Facility. SEM imaging was partially performed at the Harvard Center for NanoScale Systems. We thank Nathan Henry, Mustafa Akbulut and Cicek Boztug for their help with design and fabrication of the microwires. We also thank the CNF staff for their support for the fabrication of the structures. This work was supported by the National Science Foundation (ECCS 0702307, 0824171 and 0925973), the Department of Energy (DE-SC0005038) and the University of Connecticut Research Foundation.
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16 [14] G. Bakan, K. Cil, A. Cywar, H. Silva and A. Gokirmak, "Measurements of liquid silicon resistivity on silicon microwires," in Mater. Res. Soc. Symp. Proc. Spring 2009, 2009, pp. AA06-06. [15] V. M. Glazov, S. N. Chizhevskaya and N. N. Glagoleva, Liquid Semiconductors. N.Y.: Plenum Press, 1969, pp. 362. [16] H. S. Schnyders and J. B. Van Zytveld, "Electrical resistivity and thermopower of liquid Ge and Si," Journal of Physics: Condensed Matter, vol. 8, pp. 10875-10883, 1996. [17] H. Sasaki, A. Ikari, K. Terashima and S. Kimura, "Temperature Dependence of the Electrical Resistivity of Molten Silicon," Jpn.J.Appl.Phys, vol. 34, pp. 3426±3431, 1995. [18] N. E. Williams, E. Carpena, K. Cil, H. Silva and A. Gokirmak, "Temperature Dependent Electrical Characterization and Crystallization of Nanocrystalline Silicon," Mat. Res. Soc. Spring Meeting, vol. A17.9, 2010. [19] G. Bakan, N. Khan, A. Cywar, K. Cil, M. Akbulut, A. Gokirmak and H. Silva, "Self-heating of silicon microwires: crystallization and thermoelectric effects," Journal of Material Research (In press), 2010. [20] D. M. Rowe, Thermoelectrics Handbook:Macro to Nano. DRC, 2006, [21] D. K. C. MacDonald, Thermoelectricity: An Introduction to the Principles. Mineola, N.Y.: Dover Publications, Inc., 2006, pp. 133. [22] C. H. Mastrangelo, J. H. J. Yeh and R. S. Muller, "Electrical and optical characteristics of vacuum-sealed polysiliconmicrolamps," IEEE Trans. Electron Devices, vol. 39, pp. 1363-1375, 1992. [23] O. Englander, D. Christensen and L. Lin, "Local synthesis of silicon nanowires and carbon nanotubes on microbridges," Appl. Phys. Lett., vol. 82, pp. 4797, 2003. [24] A. Jungen, C. Stampfer and C. Hierold, "Thermography on a suspended microbridge using confocal Raman scattering," Appl. Phys. Lett., vol. 88, pp. 191901, 05/08. 2006. [25] D. K. Schroder, Semiconductor Material and Device Characterization. Wiley-interscience, 2006, [26] D. T. Castro, L. Goux, G. A. M. Hurkx, K. Attenborough, R. Delhougne, J. Lisoni, F. J. Jedema, M. A. A. i. '. Zandt, R. A. M. Wolters, D. J. Gravesteijn, M. A. Verheijen, M. Kaise, R. G. R. Weemaes and D. J. Wouters, "Evidence of the thermoelectric thomson effect and influence on the program conditions and cell optimization in phase-change memory cells," in IEEE International Electron Devices Meeting, 2007. IEDM 2007, 2007, pp. 315-318. [27] COMSOL-Multiphysics Modeling [28] E. M. Lifshitz, L. D. Landau and L. P. Pitaevskii, Electrodynamics of Continuous Media. ,2nd ed.MA: Pergamon Press, 1984, pp. 455. [29] A. A. Geisberger, N. Sarkar, M. Ellis and G. D. Skidmore, "Electrothermal properties and modeling of polysilicon microthermal actuators," J of Microelectromechanical Systems, vol. 12, pp. 513-523, 2003. [30] M. Von Arx, O. Paul and H. Baltes, "Test structures to measure the Seebeck coefficient of CMOS ICpolysilicon," IEEE Trans. Semicond. Manuf., vol. 10, pp. 201-208, 1997. [31] W. Fulkerson, J. P. Moore, R. K. Williams, R. S. Graves and D. L. McElroy, "Thermal Conductivity, Electrical Resistivity, and Seebeck Coefficient of Silicon from 100 to 1300° K," Physical Review, vol. 167, pp. 765-782, 1968. [32] C. Ong, E. Sin and H. Tan, "Heat-flow calculation of pulsed excimer ultraviolet laser's melting of amorphous and crystalline silicon surfaces," Journal of the Optical Society of America B, vol. 3, pp. 812-814, 1986. [33] T. Sato, "Spectral emissivity of silicon," Japanese Journal Op Applied Physics Vol, vol. 6, 1967. [34] D. G. Brandon and W. D. Kaplan, Microstructural Characterization of Materials. ,2nd ed.WILEY, 1999, pp. 536.
Evaluation of Resistance Measurement Techniques in Carbon Black and Carbon Nano-tubes Reinforced Epoxy Venkat K. Vadlamani1, Vijaya B. Chalivendra1*, Arun Shukla2, Sze Yang2 1 University of Massachusetts, North Dartmouth, MA 02747, USA 2 University of Rhode Island, Kingston, RI, 02881, USA * Corresponding author,
[email protected], 508-910-6572
ABSTRACT Two different resistance measurement techniques are used in an epoxy material reinforced separately with carbon black (CB) micro-particles and carbon nano-tubes (CNTs) to evaluate the effectiveness of both the techniques and type of reinforcement on damage detection under uni-axial tensile loading. Two techniques, namely traditional four-point probe (FPP) and fourcircumferential ring probe (FCRP) are employed and a constant current is applied through outer probes. The resulting voltage drop between inner probes is measured using a commercial high resolution electrometer based system. Since current density distribution in both techniques is different, the measured change in resistance (both qualitatively and quantitatively) is also different. In addition to change in current density due to different techniques, the size of conductive reinforcement also has significant impact on both current distribution and further change in resistance. CB reinforced epoxy showed very high percentage change in resistance against CNTs reinforced epoxy for both techniques. It was identified that CNTs reinforced epoxy showed no significant difference for both FPP and FCRP methods. However, for CB reinforced epoxy, significant difference in percentage change in resistance was observed for both resistance measurement methods.
1.
Introduction
Due to their high electrical conductivity, carbon black and carbon nanotubes were used as a sensory network in detecting damage initiation and growth in concrete [1-3] and in polymer composites [4-6] when they were subjected to mechanical loads. The damage initiation and growth was detected by measuring the change in resistivity of the above materials using traditional four point probe (FPP) measurement methodology [1-5]. In this methodology either constant current or voltage is supplied between two outer probes and respective change in voltage or current was measured through inner probes to record the change in material resistivity associated with the damage. To discuss few studies in this paper, Thostenson and Chou [4] recorded maximum percentage change in resistance of 300% due to damage at a peak load in glass fiber–epoxy composites. Nofar et al., [5] indentified a maximum percentage resistance change of about 40% due to damage in CNT reinforced laminated Bidirectional woven glass fibers epoxy composites during tensile and fatigue loading. However, traditional FPP methodology allows the current to flow though small depth below the surface and the damage detection zone is limited. However, to detect significantly large amount of damage inside the materials due to mechanical loads, we expected that a four circumferential ring probe (FCRP) methodology is a better choice. Although there are no many studies reported using FCRP approach, Park et al., [7] employed FCRP approach in determining change in resistivity due to damage during carbon fiber pull-out test of carbon nanotube reinforced epoxy composites. In this study, we conducted a comprehensive experimental investigation of both FPP and FCRP techniques in an epoxy material reinforced separately with carbon black (CB) micro-particles and carbon nano-tubes (CNTs) under uni-axial tensile loading. A constant current is applied through outer probes of above techniques and the resulting voltage drop between inner probes is measured using a commercial high resolution electrometer based system. Due to change in current density of above two techniques and also due to the size of conductive reinforcement, we expected to see significant change in resistance measurements (both qualitatively and quantitatively).
2. Experimental Procedures 2.1 Material Fabrication Given the simplicity of casting and low curing temperature, the matrix used in this study is an epoxy polymer based on bisphenol-A resin (Buehler Epothin (20-8140-128)) and an epoxy hardener (Buehler Epothin 20-8142-064). The mixing T. Proulx (ed.), MEMS and Nanotechnology, Volume 4, Conference Proceedings of the Society for Experimental Mechanics Series 999999, DOI 10.1007/978-1-4614-0210-7_3, © The Society for Experimental Mechanics, Inc. 2011
17
18 ratio of Part-A to Part-B was 50g to 18 g. The multi-wall carbon nanotubes (purity > 95%) used were supplied by NanoLab. The nanotubes had outside diameters of 30 ± 15 nm, lengths of 5 to 20 microns and a specific surface area of 200-400 m2/g. Two different weight fractions of CNTs 0.3 and 0.5% wt were tested to understand percolation threshold. Carbon black (CB) has irregular particle shape and has average size of 1-5µm and they have mass density of 1.8-2.0 gm/cm3. In this study a weight fraction of 10% was used in making composites. Due to high surface energy, carbon nanotubes tend to agglomerate into bunches. These agglomerations can act as defects rather than enhancements which directly affects the transport properties of the material [8]. To effectively disperse CNTs and enhance electrical response of the material under study, the present work implemented high-intensity ultrasonication and high-speed shear mixing.
Fig. 1. Schematic of nanocomposite fabrication procedure A schematic of the general procedure for material preparation is shown in Fig 1. Pre-measured amounts of Epothin Part-A Resin and carbon nanotubes were combined in a copper beaker. The mixture was mechanically stirred for 5 minutes. The mixture was then placed into a shear mixer (Ika Werke RW 16 Basic) outfitted with a 3-blade propeller stirrer (R1381 Propeller stirrer) operating at a speed of 450 RPM for 30 minutes. Following shear mixing, the mixture was then immediately irradiated. The ultrasonication process was applied for one hour on pulse mode, 4.5 sec on 9 sec off (Sonics & Materials Inc. VCX750). During the sonication process, the copper beaker containing the mixture was submerged into a cooling bath in order to maintain a mixture temperature of 18°C - 30°C. It is essential to control the temperature of the mixture during the entire process in order to prevent any avoidable damage that would occur to the nanotubes during the sonication process [9]. Any damage of the nanotubes would diminish the electrical properties of the final composite. Cooling bath was designed to control the temperature of the mixture by adjusting the flow rate of liquid nitrogen through a series of copper coils submerged in an anti-freeze solution. The weight fraction of CNTs in the solution may determine a required cooling rate for the temperature control. After the sonication process, the mixture was moved into a vacuum chamber to remove trapped air bubbles generated during the mechanical mixing process [10]. Once all air was removed from the mixture, it was combined with and mechanically stirred for 2 minutes. The mixture was once again placed back into the vacuum chamber for 5 minutes. Finally, the CNT-epoxy solution was slowly poured into pre-manufactured molds. The samples were allowed to cure for 24 hrs. In the case of carbon black, Epothin Part-A (Resin) and carbon black were combined in a copper beaker. The mixture was mechanically stirred for 5 minutes. The mixture was then placed into a shear mixer (operating at a speed of 450 RPM for 45 minutes). Then the mixture was placed in vacuum chamber until complete degassing was performed. Later the mixture was mixed with Part-B and shear mixed for 2 minutes. The final mixture was again placed in vacuum chamber for 5 min and after that the solution is poured in molds.
2.2 Electrical Characterization In the present study, dog bone specimen configuration was used for uni-axial testing. Two novel approaches four-point probe method and four-circumferential ring method were implemented to capture the electrical resistance change during mechanical loading. As seen in fig (4a), silver epoxy (MG Chemicals 8331-14G) was used for point method and as shown in fig (4b) silver paint (SPI-Paint 05001-AB) was used for circumferential ring method. A constant current was passed through the outer probes; voltage drop across two inner probes was measured to determine the electrical resistance of the middle section. Since
19 the current flow, i, was constant and the voltage change, V, between the two inner probes was measured, the instantaneous resistance between the two inner probes, R′, was calculated. Percent change in resistance was taken as,
R '− R 0 × 100 R0
(1)
where R0 is the initial resistance between the two inner probes. Due to the complexity and variability of the networks present within each specimen, the initial R value was served as a baseline resistance for each experiment. Suitable current must be chosen for the experiment. Various amount of current ranging from 100µA – 2nA passed and initial resistance is calculated for all currents. Within a range of currents the initial resistance will kept constant as seen in Table 1. A current should be selected from that range for experiment to avoid fluctuations in resistance measurements while applying mechanical loads. The experimental setup used in quasi-static tests is shown in Fig 2. A constant current source (Keithley Instruments Model 6220) was used to generate a constant current flow through outer probes. Two electrometers (Keithley Instruments Model 6514) measured the voltage reading at each of the two individual inner probe rings. The difference between the two voltage readings, which corresponds to the voltage drop across the two inner probes, measured by the electrometers would then be shown on a digital multimeter (Keithley Instruments Model 2000 DMM) and recorded using a LabView system.
Table 1. Selection of suitable current Current(amps)
Resistance(Ω)
100e-6
3.64e+5
75e-6
3.84e+5
50e-6
4.16e+5
25e-6
4.82e+5
200e-9
1.21e+6
175e-9
1.21e+6
150e-9
1.21e+6
125e-9
1.18e+6
100e-9
1.22e+6
75e-9
1.19e+6
50e-9
1.32e+6
25e-9
1.13e+6
2e-9
1.9e+6
Constant Current Source
Multimeter
Electrometer
Electrometer
Constant Current Source
(a)
Multimeter
Electrometer
Electrometer
(b)
Fig. 2. Experimental set-ups for measuring resistance change under quasi-static conditions (a) Four-Point, (b) Four circumferential ring
20
2.3 Quasi-Static Loading The quasi-static loading was implemented by a servo-hydraulic system (Instron 5582), as shown in fig (5). Specimens were loaded at a constant rate of 1 mm/min. The displacement of the loading head corrected by the machine compliance was utilized to calculate the strain of the specimen under quasi-static loading.
3. Results and Discussion 3.1 Percolation Behavior Study
Resistance(KΩ)
Prior to experimentally studying the electrical 3000 response of CNT- epoxy nanocomposites under loading, a detailed investigation was conducted to 2500 determine the percolation threshold of the fabricated composites under no loading conditions. This study 2000 was essential in order to determine the optimum duration of sonication as well as the concentration of 1500 CNTs for the manufacturing of the test specimens to ensure a proper network being formed within the 1000 material. Although the results are discussed here in this paper, we identified that 0.5% weight fraction 500 generates optimum percolation threshold. Previous 0 studies have shown similar electrical percolation 0 1 2 3 4 5 6 behavior in nanotube-epoxy composites [11]. Hours of sonication Beyond 0.5 wt% the percolation threshold, there is no further significant improvement in electrical Fig. 3. Experimental results of static resistance conductivity. Therefore, the concentration of CNTs measurements as a function of sonication duration was set to 0.5 wt. % in the present study. Using this 0.5% weight fraction, the effect of the duration of the sonication process on the base resistance of the material was determined. The resulting change in resistance with sonication time is shown in shown in Fig 3. 60 50
Stress (MPa)
While the base resistance show apprarent change immediately after one hour of sonication, it begins to drastically increase as sonication duration is further extended. This may be attributed to the nanotubes being damaged due to an excessive sonication. The high local temperatures and pressures during the sonication process may have damaged and weakened the nanotubes, thus creating a less efficient percolation network. From this observation, sonication was set to 1 hour during the specimen fabrication process in present study.
40 30 20
Epoxy Epoxy with CNT Epoxy with Carbon Black
10
3.2
Electro-mechanical response: 0
For statistical significance and consistency of the experimental data, minimum six experiments were conducted for specific case of material & technique. Having high confidence on our experimental data, we only present in this section, a representative data for each situation.
0
2
4
6 Strain (%)
8
10
Fig. 4. Engineering stress vs strain diagrams of pure epoxy, epoxy reinforced with CNT and carbon black
12
Before the electromechanical response of both CNT and carbon black reinforced epoxy is discussed in this section, typical engineering stress vs. strain diagrams of pure epoxy, epoxy reinforced with CNTs and carbon black is shown in Fig. 4. With the reinforcement of CNTs, the composite’s percentage elongation at break decreases to around 7.75% and the same for carbon black reinforced epoxy is at around 4.5%. There is no considerable change in tensile strength of all three materials. These stressstrain diagrams would be useful in explaining the nature of percentage changes in resistance of CNT & carbon black reinforced epoxy composites later in this section.
60
Stress (MPa)
4
200 30 150 20
100
10
50
0 1
2
3
4
5
6
8
Strain (%)
0 0
4
6
Strain (%)
Fig. 7. Typical stress-strain and electrical repsonse of CB reinforced epoxy using FPP methodology
Fig. 5. Typical stress-strain and electrical repsonse of CNT reinforced epoxy using FPP methodology
4.5 4
Stress (MPa)
50
3.5
40
3 2.5
30
2
20
1.5 1
10
0.5
0
0 0
2
4
6
8
Strain (%) Fig. 6. Typical stress-strain and electrical repsonse of CNT reinforced epoxy using FCRP methodology
50
200
40
160
30
120
20
80
10
40
0
0 0
1
2
3
4
5
Strain (%)
Fig. 8. Typical stress-strain and electrical repsonse of CB reinforced epoxy using FCRP methodology
Change in Resistance (%)
60
Change in resistance (%)
250
40
0 2
Stress (MPa)
300
2 20
0
Change in Resistance (%)
Stress (MPa)
50
3
0
Fig. 6 provides the variation of both applied stress and percentage change of electrical resistance against axial strain of CNT reinforced epoxy using FCRP methodology. A similar trend to that of FPP technique shown in Fig. 5 can be seen for FCRP case. All three stages as discussed for Fig. 5 can be noticed in Fig. 6 too. 350
40
1
Fig. 5 provides the variation of both applied stress and percentage change of electrical resistance against axial strain of CNT reinforced epoxy using FPP methodology. In the first stage (until 3% strain), as the applied strain increases, the resistance increases monotonically at rapid rate. In the second stage (beyond 3% strain until it reaches maximum stress value), the resistance of the specimen increases at a decreasing rate compared to stage-1. As soon as the maximum stress is reached, the resistance decreases (instead of further increase) due to relaxation of the material between maximum stress and breaking stress. As soon as the specimen breaks, the specimen realizes high resistance. The maximum percentage change in resistance recorded for CNT reinforced epoxy with FPP technique was about 4%.
60
5
Change in resistance (%)
21
22 The maximum percentage recorded for this technique is as well about 4%. Hence we conclude from Fig. 5 and 6 that both FPP and FCRP techniques resulted same stages and maximum value of change in resistance for CNT reinforced epoxy composites. Figs. 7 and 8 provide the variation of both applied stress and percentage change of electrical resistance against axial strain of CB reinforced epoxy using FPP and FCRP methodologies respectively. The first major difference between CB reinforcement against CNT reinforcement is that the maximum change in resistance in former case is 40 to 80 times higher than that of later case. The major reason for such a big change is severe voids formation that occurs around the CB particles and the resulting growth of damage. As it can be see from Fig. 4 that percentage elongation at break of CB reinforced epoxy is almost half that of pure epoxy and which is due to severe void formation around the CB particles. This phenomenon is significant in CNT reinforced epoxy. In can be noticed for both techniques for CB reinforcement, there exists again three stages of change of electrical resistance. Unlike in Figs. 5 and 6, in these both cases, the rate of change of resistance are less in the beginning until about 1% strain. In the second stage, after about 1%, the there is significant increase in the rate of change of resistance in both methods as shown in Figs.7 and 8. In the third stage, the maximum value of change in resistance happens before the mechanical axial load reaches maximum value. This is not the case for CNT reinforced epoxy as shown in Figs. 5 and 6. After reaching maximum value, the resistance varies about the maximum and tries to stay there again decrease that is seen in Figs. 7 and 8. The major significant difference that can be noticed in Figs 7 and 8, the FPP method notices higher change of resistance (about 315%) against maximum value (about 170%) in FCRP method for carbon black reinforced epoxy material under uni-axial tensile loading. We are not quite sure about the reasons for this difference and we would be able to explore them and present them in the conference.
4. Conclusions A comprehensive experimental study has been conducted to fabricate CNT and CB reinforced epoxy to verify the effectiveness of either four point probe or four circumferential probe measurement systems to capture electrical response during uni-axial tensile loading. Even though CB reinforcement generated very high percentage change in electrical resistance, CB reinforcement is recommended because the damage the reinforcement induces will corrupt the detection of actual damage of caused by the epoxy. Although CNT reinforcement induced reduction of percentage elongation to break by 30%, the resistance change can be directly attributed to damage of the epoxy matrix and may not be primarily due to CNT reinforcement itself. Moreover, both FPP and FCRP methods yielded similar qualitative and quantitative resistance changes, hence we recommend to use four-point probe methodology using CNT reinforcement as sensory network for detecting damage in polymer systems in future studies.
Acknowledgements This work was supported by the National Science Foundation (NSF) under grant number CMMI-0856463
References [1] H. Li, H-Q. Xiao, J-P. Qu, “Effect of compressive strain on electrical-resistivity of carbon black-filled cement based composites,” Cement and Concrete Composites, vol 28, pp. 824-828, 2006. [2] H. Li, J. Qu, “Smart concrete, sensors and self-sensing concrete structures,” Key Engineering Materials, vol 400-402, pp. 69-80, 2009. [3] L. Rejon, A. Rosas-Zavala, J. Porcoyo-Calderon, V.M. Castano, “Percolation phenomena in carbon black-filled polymeric concrete,” Polymer Engineering and Science, vol 40(9), pp. 2101-2104, 2000. [4] E.T. Thostenson, T-W. Chou, “Carbon Nanotube Networks: Sensing of Distributed Strain and Damage for Life Prediction and Self Healing,” Advanced Materials, vol 18, pp. 2837-2841, 2006. [5] M. Nofar, S.V. Hoa, M.D. Pugh, “Failure detection and monitoring in polymer matrix composites subjected to static and dynamic loads using carbon nanotube networks,” Composites Science and Technology, vol 69, pp.1599-1606, 2009. [6] M.A. Bily, Y.W. Kwon, R.D. Pollak, “Study of composite interface fracture and crack growth monitoring using carbon nanotubes,”Applied Composite Materials, vol 17(4), pp. 347-362, 2010. [7] J-M. Park, D-S. Kim, S-J. Kim, P-G. Kim, D-J. Yoon, K.L. DeVries, “Inherent sensing and interfacial evaluation of carbon nanofiber and nanotube/epoxy composites using electrical resistance measurement and micromechanical technique,” Composites: Part-B, vol 38, pp. 847–861, 2007.
23 [8] M.E. Kabir, M.C. Saha, S. Jeelani, “Effect of ultrasound sonication in carbon nanofibers/polyurethane foam composite,” Materials Science and Engineering A, vol. 459, iss. 1-2, pp. 111-116, 2007. [9] P. Ma, N.A. Siddiqui, G. Marom, J. Kim, “Dispersion and functionalization of carbon nanotubes for polymer-based nanocomposites: A review,” Composites Part A: Applied Science and Manufacturing, vol 41, iss. 10, pp. 1345-1367, 2010. [10] V.M.F. Evora VMF, A. Shukla, “Fabrication, characterization, and dynamic behavior of Polyester/TiO2 nanocomposites,” Materials Science and Engineering A, vol. 361, iss. 1-2, pp. 358-366, 2003. [11] W. Bauhofer, J.Z. Kovacs, “A review and analysis of electrical percolation in carbon nanotube polymer composites,” Composites Science and Technology, vol. 69, iss. 10, pp. 1486-1498, 2009.
A nano-tensile tester for creep studies
L.I.J.C.Bergers1,3,4 J.P.M. Hoefnagels1, E.C.A.Dekkers2, M.G.D. Geers1 1
Eindhoven Univ. of Technology, Dept. of Mech. Eng., P.O.Box 513, 5600 MB, Eindhoven, NL, 2 Eindhoven Univ. of Technology, GTD., P.O.Box 513, 5600 MB, Eindhoven, NL, 3 Foundation for Fundamental Research on Matter, P.O.Box 3021, 3502 GA Utrecht, NL, 4 Materials innovation institute, P.O.Box 5008, 2600 GA Delft, NL. E-mail:
[email protected] Abstract Free-standing metallic thin films are increasingly used as structural components in MEMS. In commercial devices, long-term reliability is essential, which requires determining time-dependent mechanical properties of these films. The uniaxial tensile test is a preferred method due to uncomplicated determination of the stress and strain state. However, at the MEMS-scale this method is not straightforward: specimen handling and loading, force and deformation measurement need careful consideration. Here we discuss the challenges of the application and measurement of nano-Newton forces, nanometer deformations and micro-radians rotation alignment ensuring negligible bending in on-chip tensile test structures during long periods. We then present a novel tensile-testing instrument with in-situ capabilities in SEM and Optical Profilometry. The design solutions to measure these small forces and deformations whilst ensuring a uniaxial stress state will be presented. Introduction Mechanical testing for material behavior characterization has brought much understanding into the mechanics of materials at the macro scale. Nowadays, however, miniature devices with dimensions at the sub-micrometer scale, such as MEMS, are processed routinely, which has revealed unexpectedly new mechanical micro-mechanisms. This has spurred research into new mechanical characterization techniques to understand the physical fundamentals at the (sub)-micron scale, e.g. nanoindentation [1], FIB-enabled in-situ micro-tensile testing [2], fully integrated and dedicated tensile test MEMS [3]. One important outcome of this research is that testing at the nano-scale is far from trivial [4;5]! To address this issue, a novel nano-tensile methodology is presented here for which all fundamental aspect of tensile testing have been reconsidered in its design. A suitable testing methodology faces a number of challenges. First of all, such a methodology needs to be sensitive enough to measure the nano-Newton forces and nanometer deformations involved at this scale. Well-defined loading conditions are preferred to facilitate interpretation of the deformation state, thus favoring the uniaxial tensile test. Boundary conditions should also be carefully controlled to minimize undesired influences, such as surface roughness or friction effects, while challenges of specimen handling, loading and alignment need to be addressed as well. Furthermore, easy specimen variation is required to enable systematic studies of the influences of, e.g., mechanical size-effects. Finally, in-situ SEM testing capability is necessary to unravel the physical origin underlying (the often complex) microscopic deformation mechanics [6]. Design of methodology The design of the methodology has the uniaxial tensile specimen at its heart. The specimen fabrication and variation determine the requirements for the loading method, force and deformation measurement. After establishing these requirements, suitable solutions to obtain them are discussed followed by their respective implementations in the design of the uniaxial tensile tester.
T. Proulx (ed.), MEMS and Nanotechnology, Volume 4, Conference Proceedings of the Society for Experimental Mechanics Series 999999, DOI 10.1007/978-1-4614-0210-7_4, © The Society for Experimental Mechanics, Inc. 2011
25
26 Specimen fabrication A common method [7-9] to create tensile specimens is the micro-fabrication of dog bone shaped specimens on a substrate, with one end and the gauge section free-standing e.g., by under etching. Considering specimen handling and fabrication, it is highly preferred to test on-chip structures instead of separate μm-sized structures. Moreover, applying the same microfabrication procedure as done for the actual device guarantees the relevance of obtained results. Therefore, dog bone shaped tensile specimens are designed and fabricated on silicon chips, see Figure 1. The cross section dimensions of the gauge section are varied to probe size-effects from sub-micron into the micro range, because MEMS devices are designed this range. The specimen length is made as long as possible to facilitate the elongation measurement. Based on these dimensions and the desire to perform creep measurements at tensile stresses of 1-100 MPa, the force range is determined. Finally, a chip of 10x10 mm2 is filled with ~60 specimens. In short, this approach takes advantage of the precision and ease of reproduction of microfabrication, and the ease of geometrical variation within a chip design.
Figure 1 Chip layout and tensile specimen design Load application The loading of the specimens has to deal with applying desired forces to the specimen and ensuring a homogeneous uniaxial tensile stress is attained. The application of the forces is simplified to mounting a chip and gripping the free end of the tensile specimen. Several approaches to gripping have been reported: electro-static clamping, application of adhesives and mechanically locking. These methods have their pros and cons, but a choice is only possible after considering the effect of incorrect gripping, because this can lead to misalignment resulting in undesired bending stresses in the specimen. Some forms of misalignment can occur (see Figure 2): i) force and specimen's longitudinal axis are parallel, but not co-linear, ii) force and longitudinal axis are at an angle. Based on a straight forward analysis of statics and elastic beam theory, the initial ratio of maximum bending stress to desired tensile stress can be estimated. The bending stress from non-co-linearity can be assumed negligible, if the point of force application is in-line with the specimen's longitudinal axis. Furthermore, actuation of translations should be feasible at this scale with 5-10 nm precision, which is less than 1% of the specimen width and thickness. The bending stresses resulting from rotational misalignment can be minimized by reducing the ration l/t or by minimizing the misalignment angles. As it is desirable to increase l (for the elongation measurement), the angles need to be minimized. Allowing for σbend/σtensile < 5%, then already θ 40,000 Poise), wettability at interfaces was poor, adding approximately 300C-mm2/W to unit thermal resistance. For a nominal bond-line of 1.5 mm, this represented an approximate 5 percent increase in the interface’s resistance. Besides acceptable thermal performance, this material also required an inherently low compression mating force as well as administered low tensile separation strength. These were key requirements to protect the functional integrity of the VTMs during heat spreader mating and during rework (i.e., when it is necessary to remove the common heat spreader). TIM characterization was completed in two phases. The first phase focused on acquisition of time zero material properties and processing, while the second phase assessed the long term stability of the material after exposure to a variety environmental stress conditions.
Bond Line, [um] Figure 3. TIM Thermal Conductivity vs. Applied Bond-line Thickness Parallel plate rheometry was used to measure the storage modulus versus temperature. (Figure 4). The room temperature modulus of 70-80 Pa was used in finite element modeling to estimate stresses at critical locations. The storage modulus was also measured during a temperature ramp of 30C/min up to 1500C and it was
determined that there was no significant decrease in flow to warrant using heat during the attachment of the heat spreader.
Figure 4. TIM Storage Modulus vs. Temperature The mating force applied to the heat spreader was limited to 250 kg; determined by assuming a uniform loading of all 37 modules to 90% of the compressive limit. Figure 5 is a plot of the TIM bond line vs. time and mechanical loading. As shown, the ultimate bond lines were not achieved with 250 kg mating force and time alone, but only after engaging the screws and securing to the standoffs were stable bond lines achieved (i.e., 1.2 to 1.7 mm). Given the typical strain rate dependency of the TIM with respect to stiffness during compression, instantaneous loads can be very high when the screws were engaged. Therefore, in order to ensure that the individual compressive loads on individual VTMs remained within the force limits, in situ force measurements were made. This work defined the required screw fastening sequence and rate to keep the instantaneous loading on any single VTM within the safe region.
Figure 5. Bond Line Measurement During Assembly vs. Time
181 Next, tensile adhesion testing was conducted on bonded samples of single components and aluminum plates. The tensile stress to separate the aluminum plate was consistently less than 0.04 MPa, which is below the upper limit rating of 0.05 MPa for the component. In addition, two cells of adhesion samples were exposed to 1000 hours of 1250C and 675 hours of 500C/80% RH, respectively. Again, tensile stress to separate remained stable at less than 0.04 MPa, thus assuring that the heat spreader could be removed without damage to components even after long periods of time under operational conditions. Given the above TIM stiffness properties, a piece-wise, multi-linear material model was used to approximate the modulus of the TIM. Force versus deflection data, for a variety of strain rates, was obtained from INSTRON® material tests on a sample that was of similar dimension to the actual application. A different material model was used as input to the FEM for each actuation strain rate case. To model the TIM’s force decay rate, seen in the INSTRON® tests, a pseudo-thermal contraction was enforced. This was accomplished by creating an artificial coefficient-of-thermal expansion for the TIM, which when combined with a small decrease in temperature, enforced only on the TIM, matched the Force vs. Time INSTRON® data (Figure 6). Force (lb) 24
T636 Peak 23.3 lbs
22 20 18 16
T636 Peak 13.0 lbs
14
ptl08 094653-1hold 1 ptl08 094653-2 hold 1 ptl08 094653-1hold 2
12 10 8 6 4
8030 Peak 2.1 lbs
2 0 0.0
-2
0.2
0.4
0.6
0.8
1.0
Time (min)
Figure 6. Force Decay Rate of TIM vs. Time at Different Applied Rates of Strain
Finite Element Analysis Results: The finite element model was subjected to a three separate total assembly times: 5 sec., 30 sec. and 120 seconds. The VTM loads at each site were recorded at T0 and at 120 minutes after assembly, to examine the initial and residual compressive loads on the VTM’s. Figure 7 shows the VTM site numbering scheme. Figure 8 and Figure 9 show a comparison of the VTM loads per site for the T0 and 120 minute assembly times, respectively. The results in Figure 8 show that slower actuation time reduces peak compression loading. The final actuation time was selected to provide the necessary VTM mechanical loading safety margin, while optimizing manufacturing throughput. In addition, examining the residual VTM loads showed that none of the sites resulted in a tensile force on the TIM material (a key indicator for interface reliability).
Figure 7. VTM Site Numbering
Figure 8. Initial VTM Compressive Loads
Figure 9. Residual VTM Compressive Loads Empirical evaluation techniques: Experiments were performed on prototype hardware to characterize detailed part dimensions, assembly tolerances and assembly forces. With regards to part characterization, investigations included non-contact laser scanning measurements of part details and assemblies, part flatness measurements during
183 subassembly construction, TIM gap measurements, PCB board strain measured through assembly operations, each completed during global heat spreader attachment. In addition, during this assembly assessment the applied forces on VTMs were measured. The heat spreader characterization was completed using a laser based scanning system. Analysis software was used to compare laser scanning data to the 3D model. Figure 10 shows a sample measurement on an initial prototype heat spreader demonstrating about 1.9 mm flatness variance across the entire surface. In practice, this part will bend during assembly to conform to the PCB assembly (i.e., stiffener to board, with mounted VTM components).
Figure 10. Heat Spreader Flatness (sample) Implemented as a design feature, the heat spreader incorporated fixed stand-offs (i.e., limited travel screw attach points) to establish the required TIM gaps. The stand-off dimensional height tolerance to individual pockets where TIM is applied is closely held during final machining of the heat spreader. These stand-offs make contact to the PCB surface when assembled. The PCB is also attached to a larger stiffener. Flatness data and VTM component height date were collected on six PCB subassemblies with the VTM component height being demonstrated to be within established tolerance limits. Following the aforementioned characterization, an effort was completed to understand the gap variation, a parameter critical for control of heat transfer (thermal resistance), forces exerted on VTMs through TIM
184 during assembly and volume of TIM to dispense during manufacturing. Several methods were employed and compared to characterize the gap. One method used putty assembled into the gap which was subsequently measured upon disassembly by laser scanning. The method, shown in Figure 11, is a side view of planes formed by the component and putty surface. As shown in Figure 12, the data gathered for various VTM sites indicate gaps for this set of initial parts that were on the low end of designed tolerance allowance and therefore provided an ideal worst case test vehicle for measurement of forces during assembly. Note, a capacitive bond line testing technique was also employed to quantify these gaps thereby correlating the putty gap measurements [2].
Figure 11. Putty Gap Laser Scan (sample)
Heat Spreader to VTM gap Metron measurements using putty in gap 2.2
Gap (mm)
2
Gap Nominal Upper Tol Lower Tol Min Max
1.8 1.6 1.4 1.2 1
ge Av er a
VT M
0 VT 1 M 0 VT 3 M 0 VT 4 M 0 VT 5 M 0 VT 6 M 1 VT 3 M 2 VT 7 M 3 VT 4 M 3 VT 5 M 3 VT 6 M 37
0.8
VTM location
Figure 12. VTM TIM Gap Measurement vs. Design Specification With the gap understood, two techniques were used to quantify the mechanical loads imparted to the VTMs. The first technique employed a pressure sensitive film [3]. Given the range of expected loads, this work was completed using the Extreme Low film (7.2-28 psi usage range). As required, two sheets were cut to size and deployed at each VTM site and stand-off locations. The two-sheet type of pressure sensitive film is composed of two polyester bases, one being coated with a layer of micro-encapsulated color forming material and the other containing a layer of the color-developing material. Figure 13 shows sample results of the PSF study. The deeper coloration represents areas of higher pressure (therefore force) and the color variation from VTM site to VTM site represents the load variation across the assembly. These results were compared to a known load vs. coloration calibration study and yielded reasonable correlation to the predicted loads indicated in Figure 8.
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Figure 13. Pressure Sensitive Film Study (sample) In order to fully understand both the dynamic load magnitude and load distribution during assembly, a force sensor employing pressure sensitive ink was used [4]. The sensor in this case is created on two films with pressure sensitive ink artwork forming a matrix of sensor elements. Each element is sampled and recorded. Note, pressure sensitive ink sensors need to be carefully calibrated for use with selected substrates (i.e., using a material’s test load frame and small capacity load cell). Specific to this application, the sensors were calibrated using a discrete VTM and dispensed TIM under various compression rates (i.e., TIM strain rates). Once calibrated, theses sensors were mounted in-situ to monitor forces during heat spreader assembly. Note, care was taken to ensure sensors did not block free flow of TIM paste as this would result in high hydrostatic pressures where the paste is dammed. During loading, the sensor element sums the data acquired for a given area of interest and plotted in time (Figure 14). As shown, a peak force of about six (6) pounds was observed on the VTM, with this force quickly decaying to two (2) pounds in approximately two (2) minutes. Correspondingly, a colorized pressure contour map of individual sensor elements shows areas of higher pressure on the VTM at the time of peak loading. As shown in Figure 15, a band of highest pressure (14 psi) is represented by the deep orange color, a band of green represents a pressure of 7 psi while the average load is shown in the upper right corner (i.e., six lb).
Figure 14. Individual VTM Site; Applied Force vs. Time
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Figure 15. I-Scan® Colorized Pressure Map Expanding beyond the single site noted above, Figure 16 depicts an example of four individual VTM sites being simultaneously mapped. In each case, peak and residual loads are recorded. These, again, correlated well with the predicted results noted in Figure 8.
Figure 16. Multi-VTM Site; Applied Force vs. Time
187 Summary and Conclusions: A new cooling solution for a new high-end, energy-efficient server has been developed and verified. In early conceptual phases of the design, detailed material characterization of candidate TIMs was performed and response models developed. The material characteristics were a critical input to FEM analysis to verify the design point and to start to develop manufacturing tooling and assembly processes. Later in the development process, prototype hardware was used with PSF and pressure sensitive ink sensors to verify the design, the material response and the assembly process on form factor hardware. The combination of these early analysis techniques was the development of an aggressive cooling solution without delaying the product introduction. Acknowledgements: The authors would like to thank Edward Yarmchuk retired member of the IBM Research team for his support with the development and execution of the CBLT test methodology and Robert Walsh and Ronald Spolverino of the IBM System and Technology Group for their assistance in data acquisition and analysis of the TIM gap and VTM loading measurements. References: [1] ANSYS v12.1, ANSYS, Inc., Canonsburg, Pa [2] Using In Situ Capacitive Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies, M. Gaynes et al, IMAPS Conference 2010, 43rd International Symposium on Microelectronics, pg 450-57. [3] Fujifilm Pressure Sensitive Film, Prescale Features; http://www.fujifilm.com/products/prescale/prescalefilm/features/ [4]Tekscan, Inc., I-Scan System®, http://www.tekscan.com/pressure-distribution-measurement-system
Hierarchical Reliability Model for Life Prediction of Actively Cooled LED-Based Luminaire Bong-Min Song†, Bongtae Han and Avram Bar-Cohen Mechanical Engineering Department, University of Maryland College Park, MD 20742 Rajdeep Sharma1 and Mehmet Arik2 1 Lifing Technologies Laboratory 2 Thermal Systems Laboratory GE Global Research Center Niskayuna, NY 12309 The interest in light-emitting diodes (LEDs) for illumination applications has been increasing continuously over the last decade due to two key attributes of long lifetime and low energy consumption compared to the conventional incandescent light and compact fluorescent light. Although LEDs are attractive for lighting applications due to the aforementioned advantages, unique technical challenges, such as the extreme sensitivity of luminous output and useful lifetime to LED junction temperature, need to be overcome for their large-scale commercialization. Among various types of lamps recess downlights are the most common luminaire type in new residential construction. Several LED-based luminaires incorporating more than a single LED chip have been developed to provide the required luminous flux of recess downlight while offering the advantage of higher luminaire efficacy (i.e., higher light output using the same power or lower power consumption for the same light output) over conventional luminaires [1]. Although increasing the number of LEDs in recess downlight results in higher luminous flux (higher total lumens), the overall cost of the final luminaire also increases because of the high cost of LEDs. More importantly the luminaire efficacy remains the same for the same level of drive current. In practice it will be most likely reduced due to the possibly higher junction temperature. There are two approaches for achieving higher luminous efficacy. An ideal and long-term solution is improvement of the internal and external quantum efficiency of LED chips. An alternative approach relies on lowering the LED junction temperature by utilizing advanced cooling techniques. Indeed, the latter approach has resulted in the development of several cooling solutions for LEDs to enhance the luminaire efficacy of LED-based recess downlights. Passive cooling solutions have been implemented for several LED-based recess downlights. Due to the limited cooling capacity offered by passive cooling, the maximum total lumen is limited to approximately 600 lumens with the highest luminaire efficacy of about 54 lm/W. In order to be accepted more widely for general illumination, the LED-based luminaires should reach face lumens of 1200-1500 lm with luminaire efficacy higher than 60 lm/W at acceptable cost while maintaining reliability [2]. These requirements necessitate development of active cooling solutions. The basic requirements of active cooling solutions for the recess downlight are cost and reliability. The cooling solutions have to be innovative to satisfy the specific requirements, including (1) low power consumption (the power
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Participant in the University of Maryland/Pusan National University Joint Doctoral Program
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consumed by cooling solutions reduces the luminaire efficacy); (2) low cost (LED chips are expensive and any substantial extra cost is not desired), (3) compact size (the recess downlight has a limited enclosure) and (4) excellent reliability (reliability of the cooling solution should be at least as good as that of LEDs). After selecting a suitable active cooling solution, the optimum design of LED-based recess downlights with either passive or active cooling is the use of minimum number of LED chips with an appropriate level of forward current, which meets the requirements of light output, cost and the lifetime (typically time for 70% lumen maintenance). Unlike luminaires with a passive cooling solution, however, the reliability of the luminaire with an active cooling device is dependent not only on the junction temperature but also on the reliability of the cooling method. This study suggest a novel, hierarchical physics-of-failure (PoF) based reliability model that can be used to assess the reliability of an actively cooled luminaire. The salient considerations for the design of the active cooling solution are offered first, followed by the discussion of the proposed reliability model. The model is implemented to predict the lifetime of a LED-based recess downlight with synthetic jet cooling. The effects of the time-dependent performance degradation mechanisms of the active cooling device on the lifetime of the luminaire are also discussed. ACKNOWLEDGEMENTS Authors would like to acknowledge General Electric for providing partial support for this research. This work was partially supported by the U.S. Department of Energy through contract# DEFC26-08NT01579. This work was also partially supported by the University of Maryland/Pusan National University Joint Doctoral Program funded in part by the BK21 Program in Korea.
RRFERENCES [1] [2]
Residential Recessed Downlights, in Energy Efficiency and Renewable Energy, LED Application Series, U.S. Department of Energy, 2008. M. Arik and S. Weaver, "Effect of chip and bonding defects on the junction temperatures of highbrightness light-emitting diodes," Optical Engineering 44(11), 111305-8 (2005).
Direct Determination of Interfacial Traction-Separation Relations in Chip-Package Systems Shravan Gowrishankar, Haixia Mei, Kenneth M. Liechti and Rui Huang Center for Mechanics of Solids, Structures, and Materials Aerospace Engineering and Engineering Mechanics The University of Texas at Austin 210 East 24th Street 1 University Station Austin, TX 78712-0235
[email protected] ABSTRACT Microelectronic devices are multilayered structures with many different interfaces. Their mechanical reliability is of utmost importance when considering the implementation of new materials. The cohesive interface modeling approach has the capability of modeling crack nucleation and growth, provided interfacial parameters such as strength and toughness of the system are available. These parameters are obtained through the extraction of traction-separation relations, through indirect either hybrid numerical/experimental methods or direct experimental methods. The direct method promises to determine the parameters in an unambiguous manner. All methods of extracting traction-separation relations require some local feature of the crack-tip region to be measured. The focus in this work is on the use of the crack opening displacements measured using infrared crack opening interferometry (IR-COI), which are analyzed and incorporated into the cohesive interface modeling approach. A series of mode-I experiments that were performed on laminated silicon/epoxy/silicon interface specimens are described where crack growth and normal crack opening displacements (NCOD) were measured. Global measurements of load/displacement provide the J-integral as a function of the NCOD at the end of the cohesive zone. The path independence of the J-integral then allows the cohesive traction-separation relation for the interface to be extracted by differentiation. Results are compared with analytical and numerical models.
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