Logic-timing Simulation And the Degradation Delay Model

Logic-timing Simulation and the Degradation Delay Model This page intentionally left blank LogIc-timing Simulation ...

Author: Manuel J. Bellido | Jorge Juan | Manuel Valencia

56 downloads 483 Views 9MB Size Report

This content was uploaded by our users and we assume good faith they have the permission to share this book. If you own the copyright to this book and it is wrongfully on our website, we offer a simple DMCA procedure to remove your content from our site. Start by pressing the button below!
Report copyright / DMCA form

DOWNLOAD PDF

Logic-timing Simulation and the Degradation Delay Model

This page intentionally left blank

LogIc-timing Simulation and the Degradation Delay Model

Manuel J. Bellido Jorge Juan Manuel Valencia

University of Seville, Spain & Institute for Microelectronics of Seville, Spain

Imperial College Press

Published by

Imperial College Press 57 Shelton Street Covent Garden London WC2H 9HE Distributed by

World Scientific Publishing Co. Re. Ltd.

5 Toh Tuck Link, Singapore 596224 USA ofice: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601

UK ofice: 57 Shelton Street, Covent Garden, London WC2H 9HE

British Library Cataloguing-in-PublicationData A catalogue record for this book is available from the British Library.

LOGIC-TIMING SIMULATION AND THE DEGRADATION DELAY MODEL Copyright 0 2006 by Imperial College Press All rights reserved. This book, or parts thereoJ may not be reproduced in any form or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permissionfrom the Publisher.

For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher.

ISBN 1-86094-589-9

Printed in Singapore by World Scientific Printers (S) Pte Ltd

To our families


Prologue

“And God made the two great lights; the greater light to rule the day, and the lesser light to rule the night: he made the stars also. And God set them in the firmament of heaven to give light upon the earth, and to rule over the day and over the night, and to divide the light from the darkness: and God saw that it was good” (Genesis 16-1 8). This is history’s first synchronous system run by a non-overlapping twophase clock (the greater light to rule the day, and the lesser light to rule the night). In this system we are confronted for the first time with the problem of clock skew since the phases may overlap although the system has been built as immune to such clock skew. This example should serve to illustrate how aspects of timing are cmcia1 in nature and inherent to the very fact of existence. For this reason the analysis and study of these aspects is of decisive importance for understanding system behaviour. From the point of view of the design of electronic systems we should keep in mind that the functioning of a system is no more than a succession of events in the signals that run through the paths connecting the devices. Establishing an adequate succession of events, with respect to signal sequencing and the generation of adequate levels of voltage and current will determine the correct or incorrect functioning of the system. According to Moore’s Law, the number of transistors per square millimetre on an integrated circuit is doubled every two years. This means that as the scale of integration grows, so does the functionality and complexity of electronic systems. On the other hand, performance requirements are increasingly restrictive in terms of operating speed and power

vii

viii

Prologue

consumption. In submicron technologies delays in the lines of interconnections become comparable to those of logic gates. Problems of clock skew, jittering and synchronization create serious restrictions in system design. All these aspects make the design process increasingly need the support of tools which facilitate the tasks of analysis, simulation and synthesis. Such tools should incorporate realistic behavioural models of the devices. The work presented here encompasses the main aspects related to the logic timing simulation of circuits and digital systems. This work arises as the product of the experience of the authors and their deep knowledge on the subject. In almost twenty years of research this team has produced new models of system behaviour making it possible to increase the precision of logic timing simulation without significantly having to increase costs in computing time or resources. This book presents a review of logic timing simulators, focusing on the modelling of the behaviour of the logic devices. The authors guide us through a review of the different logic gate delay models showing us the restrictions and positive qualities of each model. This is a natural way of presenting the new contributions that the authors themselves have made through the incorporation of new effects into the model. The influence of these new delay models may be seen in the realization of more precise logic simulators and applications for the analysis of power consumption in digital circuits. This book constitutes a basic work of reference for any professional digital designer. It is also a reference manual for researchers developing new analysis and simulation tools for digital systems. I believe that with this work it will be easier to understand how designers see timing effects and how this vision makes it possible to construct adequate models to study the timing behaviour of systems.

Angel Barriga Microelectronics Institute of Seville

Preface

From the beginning of its development until the present day, microelectronic technology has made continuous and unstoppable advances in the miniaturization of the basic components of integrated circuits. This miniaturization has had two fundamental consequences. First of all, the capacity to implement extremely complex systems within a single chip. Secondly, an increasingly higher operation speed in the circuits, more and more comparable to the propagation speed of the electrical signals passing through the conductors of the chip. In order to achieve such highly complex system designs, the designer needs to use CAD tools for synthesis as well as for verification. The latter are meant to check that each design description meets the behavioural specifications. An aspect which is often overlooked is that the tools or, rather, the precision of the results obtained with those tools, is very sensitive to technological variations. In particular, verification tools lose precision because the behavioural models of the devices they implement lose validity with technological evolution. In order to avoid this loss of precision in the results it is necessary to carry out a constant update of the tools by analysing and improving behavioural models. The timing behaviour of digital circuits is undoubtedly one of those with the greatest sensitivity to technological variations. This, along with the fact that the aim is to achieve a maximum circuit operation speed, implies a constant scientific need for analysis and improvement of the timing behavioural models which allow the tools to obtain results which are sufficiently reliable for the designer.

ix

X

Preface

This book focuses on this line of work. More specifically, it deals with the modelling of the timing behaviour of logic devices (especially of logic gates) and the simulation tools at the logic level which allow for the timing analysis of large digital circuits. Precision in the timing analysis at gate level is of the utmost importance for several reasons. On the one hand, it is important from the point of view of the designer, who normally follows a Top-Down methodology, because it is at the gate level where timing behaviour is first encountered physically since at a previous level only clock cycles are modelled. In addition, it is important because the gate level is the last one common to practically all forms of implementation: Full-custom, Standard Cell Semi-Custom, and even FPGAs. On the other hand, from the point of view of timing simulation applications, there are several reasons: 1) it is essential not only for verifying the correctness of the design at the timing level but also for characterizing the performances, an aspect which may in turn be applied to the redesign of those parts of the circuit which do not offer the desired performance; 2) analysis and treatment of collisions and glitches, with applications in the study of asynchronous interactions or desynchronized signals and in the prevention of undesired behaviour such as metastability; 3) measuring switching activity, with direct application to the analysis of consumption and noise generation in mixed analog-digital circuits. We have structured the book into eight chapters. The first two chapters are general while subsequent ones deal with the specific results of our research team in this line of work, both in delay modelling as well as in the implementation of simulation tools and their application to the verification of the designs. The first chapter is devoted to the fundamental aspects of timing simulation. Specifically, various techniques are analysed which were developed so that a designer may carry out the timing simulation of a design. Thus, simulation is analysed at the electrical level, undoubtedly the one with the most precise results, which, in addition, serves as a reference for measuring the quality of the other types of timing simulation. However, the excessive use of computer resources (CPU time, memory, etc.) makes it completely nonviable, especially when aiming to simulate the behaviour of systems of considerable complexity. In this chapter other alternatives for the timing simulation are also analysed, such as simulation at the

Preface

xi

transistor level or at the logic gate level. Advantages and disadvantages are described along with a brief description of the event-driven simulation technique employed in these kinds of timing simulations. In Chapter 2 we focus on the logic timing simulation at the gate level and, more specifically, on the delay models which are implemented in the simulators. A review of the delay models is carried out, starting with the zero delay model, that is, without considering any specific timing behavioural effect, followed by a presentation of successive models of increasingly higher complexity. Thus, models are presented which include static effects as well as dynamic effects which affect the propagation delay. The so-called inertial and degradation effects are introduced in Chapter 3. The behaviour of the gates with respect to these effects is studied and the so-called Degradation Delay Model (DDM) is presented. By applying the DDM, a study is carried out on the importance of the degradation effect, concluding that specially in very high speed designs, it is fundamental to take it into account in order to achieve a correct verification of the designs. On the other hand, a detailed analysis is given of the inertial effect and the so-called inertial delay, a model widely used to include this effect within the logic simulation. In this chapter it is shown how the Inertial Delay can produce significant errors in the simulation results and an alternative algorithm is proposed to include said effect within the logic simulation, resolving the problem. Chapters 4 and 5 are devoted fully to developing the DDM. Specifically, Chapter 4 presents a very exhaustive characterization of the typical DDM parameters with respect to the technological parameters of a CMOS inverter. The step from modelling a gate with a single entry such as the inverter to modelling gates with several entries is not a trivial one. Indeed, the model may be realized by obtaining an equivalent inverter, but also by applying the same DDM concept to the different gate entries. In Chapter 5 an extension of the model to the complex CMOS gates is made. The next two chapters are devoted to presenting the characteristics of a simulation tool called HALOTIS (High Accuracy Logic TIming Simulator), which implements the DDM model along with the results obtained. Chapter 6 is devoted to presenting the general structure of the tool along

xii

Preface

with the basic characteristics of the simulation engine and the delay model interface. Chapter 7 is in turn devoted to presenting the results of HALOTIS simulation using two different behavioural models, the DDM and the CDM (Conventional Delay Model, which differs from the DDM in that it does not include the degradation effect). These results are moreover compared with those obtained by means of electrical simulation. Three types of results are presented which we consider significant: simulation of pulse propagatiodpulse trains through a chain of gates; calculation of the operating frequency of a three-inverter ring oscillator; and the simulation of the metastable behaviour in several latches designed at the logic gate level. The results clearly show that there is quite a significant increase in the precision of the results when the degradation effect is included in the logic simulation. Lastly, in Chapter 8 of this book a detailed analysis of the switching activity within the digital circuits is carried out with different types of timing simulators. The switching activity is a direct measurement of the average number of changes in the nodes of a circuit. It is a fundamental parameter for measuring the consumption and the switching noise in digital circuits. Actually, most tools for estimating the consumption of energy in digital circuits employ switching activity as a fundamental parameter. In this chapter, on the one hand, a detailed quantitative study on the ISCAS85 benchmark circuits is carried out, demonstrating that the activity due to glitches can become as significant as the functional activity inherent to the circuit (the one due to the operation of the circuit). The numerical values here presented show the great importance of treating glitches when measuring switching activity. On the other hand, the measurements of this parameter obtained with logic simulators are presented, showing that commercial simulators can make serious errors, whereas HALOTIS (using DDM) increases precision significantly.

Contents

Prologue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

1

2

Fundamentals of Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

...........................................

1

......................................

5

1.1

Introduction

1.2

Circuit Simulation

1.3

Transistor-Level Simulation ............................. 10 1.3.1 Switch-level simulation ........................... 10 1.3.2 Advanced transistor-level simulators . . . . . . . . . . . . . . . . 12 .

1.4

Timing Gate Level Simulation ........................... 13 1.4.1 Delay models at gate level ......................... 16 1.4.1.1 Zero and unit delay models . . . . . . . . . . . . . . . . . . .16 1.4.1.2 Static delay models ......................... 16 1.4.1.3 Dynamics effects ........................... 17 1.4.2 The event-driven simulation technique . . . . . . . . . . . . . . . .17

1.5

Summary and Tendencies

...............................

19

Delay Models: Evolution and Trends..............................

23

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Deterministic delay models ........................ 2.1.2 Non-deterministic delay models .....................

23 23 25

2.2

Deterministic Delay Model Types ........................ 2.2.1 Zero and unitary delay models ...................... 2.2.2 Assignable delay models .......................... 2.2.2.1 Static delay models .........................

26 26 27 27

...

XI11

xiv

Contents

2.2.2.2 Example of static delay model parameter characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2.3 Dynamic delay models . . . . . . . . . . . . . . . . . . . . . . 2.3

3

4

30 33

State of the Art in Delay Models .......................... 35 2.3.1 Classification of the proposed delay models . . . . . . . . . . .35 2.3.2 Delay model performance ......................... 40 2.3.3 Evolution and trends in delay models . . . . . . . . . . . . . . . . .42

Degradation and Inertial Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Degradation and inertial effects .....................

47 47

3.2

Degradation Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 51 3.2.1 Behaviour regions . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.2 Degradation modelling . . . . . . . . . . . . . . . . . . . 3.2.3 Physical interpretation of the degradation parameters . . . .56 3.2.4 Limits between behaviour regions . . . . . . . . . . . . . . . . . . .59 3.2.4.1 Limit between the normal propagation region and the degradation region . . . . . . . . . . . . . . . . . . 59 . 3.2.4.2 Limit between the filtering region and the 59 degradation region . . . . . . . . . . . . .

3.3

62 The Importance of the Degradation Effect . . . . . 3.3.1 Maximum device operation frequency . . . . . . . . . . . . . . . .64 3.3.2 Comparison with classical calculations and results . . . . . .66

3.4

Inertial Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.1 Inertial delay model failure . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.2 Inertial effect algorithm . . . . . . . . . . . . . . . . . . . . . . . 71 . . . . . . .72 3.4.3 Results . . . . . . . . . . . . . . . . . . . . . . ....

CMOS Inverter Degradation Delay Model ....... ..................

75

..........................................

75

4.1

Introduction

4.2

Technological Parameters

4.3

Normal Propagation Delay .............................. 81 4.3.1 CMOS inverter transient response: regions of operation . .82 4.3.1.1 Region I: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.1.2 Region 11: short-circuit ...................... 86 4.3.1.3 Region 111: discharge . . . . . . . . . . . . . . . . . . . . . . . . 87 . 4.3.2 Actual response of the CMOS inverter . . . . . . . . . . . . . . . 87

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Contents

xv

4.3.2.1 Step input response of the CMOS inverter . . . . . . .88 4.3.2.2 Limits between slow and fast input transitions . . . .90 4.3.2.3 Critical transition time calculation . . . . . . . . . . . . .91 4.3.2.4 Delay calculation for fast input transitions . . . . . . .93 4.3.2.5 Delay calculation for slow input transitions . . . . . .95 4.3.3 Output transition time calculation . . . . . . . . . . . . . . . . . . 96 .

5

4.4

Input-to-Output Coupling Capacitance Modelling . . . . . . . . . . . .98 4.4.1 IOCC calculation for micron MOSFET’s . . . . . . . . . . . . . .99 4.4.2 IOCC calculation for submicron MOSFET’s . . . . . . . . . .102 4.4.2.1 Reduced IOCC estimation from SPICE model card .................................... 105 4.4.3 Comparison of IOCC models ...................... 105 4.4.4 IOCC modelling impact in the Inverter’s timing 108 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5

Modelling the Degradation Parameters .. . . . . . . . . . . . . . . . . . . 109 4.5.1 Modelling the first degradation parameter . . . . . . . . . . . .111 4.5.2 Modelling the second degradation parameter . . . . . . . . . .113 4.5.3 Ranges of interest for the external and internal parameters of the CMOS inverter . . . . . . . . . . . . . . . . . . .116

4.6

Obtaining the Value of Technological Parameters . . . . . . . . . . .118 4.6.1 Verification of the model for the first degradation parameter ..................................... 118 4.6.2 Verification of the model for the second degradation parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.7

Discussion

..........................................

125

Gate-Level DDM

......................................

127

.........................................

127

5.1

Introduction

5.2

DDM for Multi-Input Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.2.1 Gate-level delay equations ........................ 131 5.2.1.1 Normal propagation delay . . . . . . . . . . . . . . . . . . . 131 5.2.1.2 Degradation parameters .................... 132 5.2.2 Gate-level degradation parameter multiplicity in multi-input gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.2.3 Exhaustive gate-level degradation model . . . . . . . . . . . . . 136

5.3

Degradation Parameter Characterization Process . . . . . . . . . . . . 138 5.3.1 General degradation model validation . . . . . . . . . . . . . . .138 5.3.2 Gate-level degradation parameters extraction . . . . . . . . . 140

xvi

Contents

141 5.3.2.1 Variation with the output load . . . . . . . . . . 5.3.2.2 Variation with the input transition time . . . . . . . . 142 5.3.3 Characterization process complexity . . . . . . . . . . . . . . . 142 . 5.4

Analysis of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Characterization results . . . . . . . . . . . . . . . . . . 5.4.2 Simplified model ................

148 149 150

5.5

Simplified Model Equations

............................

153

5.6

Simplified Model Characterization Process . . . . . . . . . . . . . . . .155 5.6.1 Basic model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.6.1.1 Basic model equations . . . . . . . . . . . . . . . . . . . . . 163 5.6.1.2 Basic model characterization process . . . . . . . . . .163 5.6.2 Error estimation for the propagation delay . . . . . . . . . . . .165 5.6.2.1 Expressions for error propagation . . . . . . . . . . . . .166 5.6.2.2 Example of error propagation towards the propagation delay . . . . . . . 169

5.7

Discussion of Results

5.8

6

....

...............

174

Appendix: Calculation of Error Sensitivity in the Propagation Delay With Respect to the Degradation Parameter Error . . . . . .176 5.8.1 Sensitivity of the pro pro agation delay with respect to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 parameter 5.8.2 Sensitivity of the propagation delay with respect to To . . 178 5.8.3 Sensitivity of parameter z with respect to A . . 178 5.8.4 Sensitivity of parameter z with respect to B . . . . . . . . . . .178 5.8.5 Sensitivity of To with respect to C . . . . . . . . . . . . . . . . . .178

Logic Level Simulator Design and Implementation . . . . . . . . . . . . . . . . .181 6.1

Introduction

.........................................

181

6.2

Object Oriented Methodologies: UML . . . . . . . . . . . . . . . . . . . . 6.2.1 UML introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 UML representation .............................

183

...........................

186

183 184

6.3

Global Analysis of HALOTIS

6.4

Analysis of Requirements

..............................

190

6.5

HALOTIS Design and Modelling ........................ 6.5.1 HALOTIS use case diagrams ...................... 6.5.2 Object models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

192 192 194

xvii

Contents

6.6

7

8

HALOTIS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.6.1 Implementation language and platform . . . . . . . . . . . . . .199 6.6.2 Intermediate formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.6.3 Simulation core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.6.4 HALOTIS tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

DDM Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

203

.........................................

203

7.1

Introduction

7.2

Pulse Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Isolated pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Train of equidistant pulses ........................

205 206 208

7.3

Ring Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Simple oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Oscillator with out-buffer . . . . . . . . . . . . . . . . . . . . . . . . .

214 215 217

7.4

Metastable Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

219 222

Accurate Measurement of the Switching Activity . . . . . . . . . . . . . . . . . . 227 .

.........................................

227

.....................

229

8.1

Introduction

8.2

Selection of the Testing Environment

8.3

Measurement of the Switching Activity Based on DFWII

. . . . .234

8.4

Measurement of the Switching Activity Based on HSPICE

. . . .237

8.5

Comparison between DFWII versus HSPICE Measurements

8.6

Accurate Measurement of the Switching Activity: A HALOTIS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

244

.........................................

249

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

251

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

265

8.7

Conclusions

. .239


Chapter 1

Fundamentals of Timing Simulation Carlos J e s h Jiminez Fernandez Manuel ValenciaBarrero

1.1 Introduction The design process of VLSI integrated circuits has different options and many stages. In general, there are great differences between the design process of analog and digital integrated circuits. Figure 1.1 outlines these design processes. In every design process, the tasks to test the correctness of the design are as important as the design itself. The sooner failures are detected, the sooner failures are corrected, and the sooner and less expensive it will be to make those possible corrections. In general, the starting point for an analog design is a circuit at the transistor level. Although in some cases it is useful to start off with functional descriptions composed of blocks of higher level (mainly amplifiers of different types), it is always necessary to extract the characteristics of these blocks and their design with transistors. Once the description of the circuit has been obtained at the transistor level, it is necessary to verify it. The layout design is usually manual, following a methodology called full-custom. The verification of the correctness of a layout is divided into three main areas. First of all, the verification of construction rules for layout imposed by the foundry, DRC (Design Rule Check). Secondly, it must be verified that the devices implemented by the layout exist within the netlist of transistors, LVS (Layout versus Schematic). And thirdly, it must be verified that the functional behaviour continues within the margins anticipated by the designer. For this last verification, a netlist with the par-

1

2

Logic-TimingSimulation and the Degradation Delay Model

Architectural level

HDL description

verification

I 1

I

Gate netlist

andtiming . verification

I I

I verification

Layout

I

Layout

Transistor netlist

I

Geometrical verification LVS verification

verification

Fig. 1.1 a) Analog design flow b) Digital design flow.

and timing verification

Chapter 1. Fundamentals of Timing Simulation

3

asitic capacitances is extracted from the layout for its simulation with a circuit simulator. The process of digital VLSI design is, in general, quite different from the analog design process. Although the same analog full-custom methodology can also be followed in the design process of digital circuits, the development of CAD tools allows the design process to be automated and therefore to follow a semi-custom methodology. The starting point of this methodology consists of raising an architecture (architectural level) from which an HDL description is usually obtained at the register transfer level. In these levels of design, the verifications are directed, mainly, at verifying the correct functional behaviour of the design, schemes of timing, etc. In these phases of the design, the descriptions are technologyindependent, so other types of verifications which need technological data cannot be made. Automatic synthesis tools transform the HDL description into a netlist at the logic gate level. In some cases, the description at the transistor level of the logic gates is available, so it is possible to generate a netlist of transistors from the netlist of logic gates. In these levels of design and the successive levels underneath, the descriptions contain technology information. Thus, in addition to the functional verification, a timing verification can be made. An analysis of the design taking into consideration the dynamic behaviour of the different components which constitute the circuit also has to be carried out. This analysis is of use to evaluate the final performance of the chip, as maximum operation frequency and outputs delay times. But in addition errors in the behaviour of the circuit caused by the propagation delays can be detected. The layout is generated from the logic gate netlist by the use of automatic tools. The verifications focus on geometrical aspects, checking the violation of the layout rules. Our interest is centred on the analysis of the problem of timing verification. This task is acquiring more and more importance due to two factors. On the one hand, the development of deep sub-micron technologies is producing a reduction in the delays of logic gates, so that the interconnecting delays have an increasing importance. On the other hand, circuits with a higher operating frequency and with faster interfaces with other components are needed. Thus, timing verifications with more precision and over bigger circuits are needed.

4

Logic- Eming Simulation and the Degradation Delay Model

In timing verification tools, timing behaviour is obtained by the use of delay models of the components of the circuit. Among these tools for the analysis of timing behaviour, the main one is the simulator. The simulator is a computer program whose inputs are the netlist of a circuit and a set of stimuli data introduced in the circuit inputs. The simulator imitates the behaviour of the circuit and obtains the value of internal signals and outputs related to the input stimulus. At gate and transistor levels, the use of timing simulators means that the simulation is always a timing simulation (as well as a functional simulation). With these simulators it is possible to analyse different aspects of a system: The sensitivity of the system to variations in component delays. If the design is free of critical races, oscillations, forbidden input conditions or clockout states. The comparison of different designs. The possibility of starting the simulation at any initial state. The analysis of the behaviour of synchronous circuits with asynchronous inputs. Another group of temporal verification tools are the temporal analysis tools. The main objective of these tools is to establish the critical paths of a circuit (mainly combinational). The critical paths are the paths which connect the inputs with the outputs of a circuit with a maximum or a minimum value in the propagation delay [Mizco (1986)l. Sometimes the critical paths obtained by these tools are never activated [McGeer and Brayton (1 99 l)]. It is important to eliminate these paths to carry out the timing analysis, mainly when a high frequency system is under design. This problem is usually called the false critical path problem. The objective of temporal analysis is to guarantee that the propagation delays of a circuit are not going to affect the correct behaviour of the circuit, as well as to estimate the maximum operating frequency of synchronous sequential circuits and to calculate the delay time of the outputs. Of both types of tools, the timing simulation is much more general, so from now, the focus will be on it. Taking into account the level at which they operate, the simulators can be divided into three main groups: the circuit simulators, the switch level simulators and the gate level simulators. The simulators that are fitted in each one of these types have common characteristics which will be described in the next sections.

Chapter I . Fundamentals of liming Simulation

5

In order to analyse how ideal each of the simulators is, some characteristics are defined which allow to be classified according to this quality. These characteristics are: The maximum circuit size which can be simulated with the existing computer resources The time needed to obtain the results (efficiency) The accuracy of the results (reliability) A simulator of maximum quality is one which can simulate very large circuits, in just a short time and with very accurate results. As will be seen subsequently, while a simulator is more near to some of these characteristics more moves away of the other. For that reason, it is very important in the whole simulation process that the customer knows the limitations of each type of simulator and may then choose the best simulator which fits the needs of the circuit under design.

1.2 Circuit Simulation Circuit simulation treats circuits as dynamic systems whose variables (voltages and currents) are continuous signals. The reference simulator is SPICE, a freeware simulator developed at the University of Berkeley [Newton et al. (1993)], but there are also commercial versions of SPICE (for example, HSPICE [Hspice (1999)], PSPICE [PSPICE] and others). These commercial SPICE simulators are distributed independently but also included in design environments. In general, circuit simulators are programs for simulating circuits which may contain resistors, capacitors, inductors, independent voltage and current sources, some types of dependent sources, lossless and lossy transmission lines and the four most common semiconductor devices: diodes, BJTs, MESFETs and MOSFETs. Circuit simulators have built-in models for the semiconductor devices, and the user needs to specify only the pertinent model parameter values. In the special case of the SPICE simulator, the model for the BJT is based on the integral-charge model of Gummel and Poon. However, if the Gummel-Poon parameters are not specified, the model is reduced to the simpler Ebers-Moll model. In either case, charge-storage effects,

6

Logic-Timing Simulation and the Degradation Delay Model

ohmic resistances, and a current-dependent output conductance may be included. The diode model can be used for junction diodes or for Schottky barrier diodes. The JFET model is based on the FET model of Shichman and Hodges. Six MOSFET models are implemented: MOS 1 is characterized by square-law I-V characteristics, MOS2 is an analytical model, while MOS3 is a semi-empirical model [Vladimirescu and Liu (1 98O)J; MOS6 [Sakurai and Newton (1990)l is a simple analytic model, accurate in the short-channel region, MOS4 [Sheu et al. (1985); Pierret (1984)l and MOS5 are BSIM (Berkeley Short-channel IGFET Model) and BSIM2 [Min-Chen (1990)]. SPICE can carry out different types of analysis, among which the following should be pointed out: DC Analysis The DC analysis portion of SPICE determines the DC operating point with inductors shortened and capacitors opened. A DC analysis is automatically performed prior to a transient analysis to determine the transient initial conditions, and prior to an AC small-signal analysis to determine the linearized, small-signal models for nonlinear devices. The DC analysis can also be used to generate DC transfer curves: a specified independent voltage or current source is stepped over a userspecified range and the DC output variables are stored for each sequential source value. AC Small-Signal Analysis The AC small-signal portion of SPICE computes the AC output variables as a function of frequency. The program first commutes the DC operating point or the circuit and determines a linearized, small-signal model for all the nonlinear devices in the circuit. The resultant linear circuit is then analysed over a user-specified range of frequencies. Transient Analysis The transient analysis portion of SPICE computes the transient output variables as a function of time over a user-specified time interval. The initial conditions are automatically determined by a DC analysis. All sources which are not time dependent (for example, power supplies) are set to their DC value. Pole-Zero Analysis The pole-zero analysis portion of SPICE computes the poles and/or

Chapter I . Fundamentals of llming Simulation

7

zeros in the small signal AC transfer function. The program first computes the DC operating point and then determines the linearized, small-signal models for all the nonlinear devices in the circuit. This circuit is then used to find the poles and zeros of the transfer function. The method used in the analysis is a sub-optimal numerical search. For large circuits it may take a considerable time or fail to find all poles and zeros. Small-Signal Distortion Analysis The distortion analysis portion of SPICE computes steady-state harmonic and intermodulation products for small input signal magnitudes. If signals of a single frequency are specified as the input to the circuit, the complex values of the second and third harmonics are determined at every point in the circuit. If there are signals of two frequencies input to the circuit, the analysis determines the complex values of the circuit variables at the sum and difference of the input frequencies, and at the difference of the smaller frequency from the second harmonic of the larger frequency. Sensitivity Analysis SPICE will calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an output variable with respect to all circuit variables, including model parameters. Spice calculates the difference in an output variable (either a node voltage or a branch current) by perturbing each parameter of each device independently. Since the method is a numerical approximation, the results may demonstrate second order effects in highly sensitive parameters, or they may fail to show very low but non-zero sensitivity. Furthermore, since each variable is perturbed by a small fraction of its value, zero-valued parameters are not analysed (this has the benefit of reducing what is usually a very large amount of data). Noise Analysis The noise analysis portion of SPICE does an analysis of device-generated noise in the given circuit. When provided with an input source and an output port, the analysis calculates the noise contributions of each device (and each noise generator within the device) to the output port voltage. It also calculates the contribution of input noise to the circuit, equivalent to the output noise coming from a specified input

8

Logic-Eming Simulation and the Degradation Delay Model

source. This is done for every frequency point in a specified range. The calculated value of the noise corresponds to the spectral density of the circuit variable viewed as a stationary Gaussian stochastic process. After calculating the spectral densities, noise analysis integrates these values over the specified frequency range to arrive at the total noise voltage/current (over this frequency range). This calculated value corresponds to the variance of the circuit variable viewed as a stationary Gaussian process. All input data is assumed to have been measured at a nominal temperature (typically 27°C). This value can be overridden for any device which models temperature effects by specifying a parameter on the model itself. The first step underlying simulation is, the formulation of a coupled set of nonlinear first-order, differential algebraic equations representing the behaviour of the interconnected set of devices comprising the circuit. The second step is the replacement of the time derivatives on the differential equations by means of finite difference approximations (known as integration formulas) which discretise time, in general, in a non-uniform way. This step transforms the nonlinear differential equations, at each discretized time point, into a time independent set of nonlinear equations. The third step is to solve the nonlinear equations, at each discretized time, by means of the Newton-Raphson technique which approximates them with a linear set of equations based on an initial estimate of the solution. A repeated solution of the linear set, with relinearization of the equation set after each iteration, is used to refine the estimated solution until it is deemed that adequate precision has been achieved pichols (1994)l. The converged solution of the Newton-Raphson process is then tested as an adequate solution of the differential equation set for this time point. The mechanisms used for the calculation of an output variable imply the resolution of differentials equations. Action is necessary when the Newton-Raphson iterations fail to converge to a solution, or convergence is attained but the circuit solution is too imprecise or is numerically unstable. The action taken normally involves cutting the time increment and repeating the solution process at the same time point. Having arrived at a satisfactory solution at the time point, a trial time increment to advance to a new point is selected, and a prediction of the

Chapter 1.Fundamentals of Eming Simulation

9

solution at the new point is made. This prediction is used as the initial estimate of the solution for the Newton-Raphson process at the new time point. Thus simulation proceeds as a march-in-time through a sequence of discretized time points selected to achieve both convergence of the Newton-Raphson process and adequate precision of simulation. A key factor in this kind of simulator is that there is not delay model by itself. The functional model includes the delay model, too. So the computation of the output variables cannot be divided, as described later for other kinds of simulators, into the computation of the functional behaviour and the computation of the delays. This type of simulation is characterized by its high precision. However, it requires a long time and a great amount of computation resources to generate results. Computation time grows quickly with the size of the circuits. For this reason, this type of simulation is generally used to verify circuits of a small size or independent modules which belong to larger, high precision circuits. These simulators are also used to compare the results produced by simulators which are more efficient in computation times, but less precise. Other tools use SPICE as a reference simulator in order to produce designs optimized for some parameters while maintaining some other performances. Sometimes the smallest area of the transistors is the desired target. The purpose of circuit simulators is the electrical characterization of circuits. Although they can carry out transient analysis, it is not their main function, so they are not optimized for that task. For this reason, although they achieve the maximum precision among all kinds of simulators and their outputs are used as a reference for other simulators, the performance of speed and the maximum size of circuits which can be simulated with this kind of simulator is not good enough for simulating complex deep sub-micron circuits. But there is another important reason which does not allow the use of this kind of simulator in the design of digital circuits. These simulators need a netlist description of the circuit at the device level (transistors, capacitors and inductors). In the design of digital circuits, based on a semi-custom design flow, the design is based on standard cells and macro cells, but it is not usual to have the device level description of the stand-

10

Logic-lhing Simulation and the Degradation Delay Model

ardmacro cells of the foundry libraries. In these cases the use of this type of simulator is impossible.

1.3 Transistor-Level Simulation

1.3.1 Switch-level simulation

In contrast with circuit simulation, in switch level simulation the signal values are discrete and the transistors are modelled as bidirectional resistive switches. In this type of simulation, the tension values in the nodes are discrete, mainly 0, 1 and X (undefined value). Besides, sometimes the value of high impedance is included (represented by the letter Z). The switch-level simulation technique operates directly on the structure of the circuit designed with transistors and, for that reason, it makes it possible to consider many properties of the circuit which are difficult, if not impossible, to consider at gate level. For example, the bidirectional effect of a signal, the effect of load distribution or the control of the geometric parameters of transistors. The basic way for modelling the transistor is to replace it by a switch controlled by the voltage in the gate. If this switch models an N-MOS transistor, it is closed when there is a voltage equivalent to a logic “1” in the gate and it is open when the voltage is equivalent to a logic “0” (a PMOS transistor is controlled by complementary values). A discrete value of strength can be introduced in the transistor model which is used to characterize the conductance. With this parameter it is possible to analyse circuits with several transistors, and with different geometries and sources connected to the same node. Thus, a subcircuit compound with transistors connected in series has an equivalent strength to the weakest transistor of the chain, but the strength of a subcircuit with transistor in parallel is the strongest transistor. The input nodes, such as power, clocks, input data, have the highest strength, so they can always influence the state of the remaining nodes of the circuit but not inversely. On the other hand, the internal nodes of the circuit are considered storage nodes with the capacity to accumulate load. These nodes have dis-

Chapter 1. Fundamentals of Eming Simulation

11

Crete sizes assigned to them which depend on the relative value of their equivalent capacities. This size is used when the internal nodes are disconnected from the input nodes. In this situation an effect called distribution of load occurs, so that the nodes of greater size dominate the load of the nodes of minor size connected to them. The simulation of the whole circuit uses an event-driven scheme. This technique is the one which provides the high speed of generation of results and makes it possible to analyse very complex circuits. The main difference is that now there are no blocks with predefined functionality, but blocks composed by serial-connected transistors. This simulator structure allows for the simulation of digital circuits with structures without logic gates, as well as circuits constructed with dynamic or differential logic. Concerning temporal aspects, there are two basic ways for the calculus. The first one makes use of a circuit simulator to estimate the delay and the waveform of the signals. A partition of the circuit is made, establishing which nodes change their value. With this information, those subcircuits whose output nodes had changed their value are selected. The circuit simulator is applied to these subcircuits so that the analog simulation can be carried out now. The CPU time and the memory required are reduced considerably because the simulation is not performed over the whole circuit but over the subcircuit with a node which has changed. With this technique the propagation delays of signals are obtained with very good precision. Nevertheless, although a great reduction of CPU time and other computer resources are obtained with respect to circuit simulation, when the circuit under simulation is large, the CPU time needed is too high. This type of simulator is not useful for circuits with more than 10.000 components. The second way to make the simulation consists of using the eventdriven simulation technique in a way similar to that used in the logic timing simulation at gate level. This way a higher simulation speed is reached than with the previous alternative. On the other hand, the precision of the results depends on the delay model used. In order to apply the eventdriven simulation technique it is necessary to have models of the dynamic behaviour or a generic network of transistors. This kind of simulation, with the increase of speed of operation at the cost of precision, has numer-

12


ous disadvantages. In the first place, there is still a great complexity in the design and it is not possible to simulate circuits of great size. On the other hand, the entry point is a netlist with descriptions at the device level (mainly transistors), which prevents its use if there are no suitable models. This type of simulation, halfway between circuit simulation and gate level simulation is falling into disuse, and is being replaced by other transistor-level simulators.

1.3.2 Advanced transistor-level simulators

The need to verify deep sub-micron circuits of very great size has led to the appearance of a new type of simulator, which perform a timing verification at transistor level with a precision similar to that obtained with electrical simulators but with much greater speeds. These commercial simulators (such as Synopsys’s NanoSim or Mentor Graphics’ Mach TA) combine the following characteristics: They use an intelligent partition making it possible, with the synchronization of the design, to carry out parallel operations. They combine the “time-based” and “event-driven’’ simulation techniques, without losing precision in the results. They use SPICE, Verilog and other input netlists. They manage devices such as BJT, JFET, MOSFET, etc. But the core of this type of simulators are not the models they use, but how they use them. Due to the commercial secrets which prevail over these simulators, there is little information available, we know the way of operation consists of tabulating the behaviour of the devices so that the execution of the program is much faster and more efficient. Although these simulators increase the benefits of the circuit simulator with a small degradation in the behaviour, nevertheless they have two strong drawbacks: They still have restrictions on the size of the circuit being simulated. They need netlists based on transistors. The last restriction can be crucial in semi-custom designs based on library cells without a transistor level description. In such a case the only simulation that prevails is the timing-logic simulation.

13

Chapter 1. Fundamentals of7iming Simulation

OUT

IN+ vin

- GND

Static Behaviour Dynamic Behaviour

(4

Static Behaviour Dynamic Behaviour

(b)

Fig. 1.2 a) CMOS inverter, b) Logic model of a CMOS inverter.

1.4 Timing Gate Level Simulation The gate level timing simulators make an abstraction of the waveform of the signals, which in fact are continuous signals (Fig. 1.2 (a)) but are transformed into waveform with discrete values (0, 1, X, Z, ...) (Fig. 1.2 (b)). At the functional level, such abstraction makes it possible to use Boole’s Algebra for the mathematical processing of the circuits, which makes it possible to specify formally and, consequently, to design the digital systems. In addition, this abstraction establishes a temporal relation between the inputs and the outputs of a gate, represented by the intuitive notion of propagation delay. For example, the output of the inverter of Fig. 1.2 (b) changes at moment tl + $, as a reply to the input change which occurred in tl. That is why it may be said that the inverter has a propagation delay of value $,. These two levels obtained from the functional temporal abstraction are separated to make a different treatment for each one. A given instance of a real gate may be split in two types of blocks, a first type that consid-

14


Real

Log1c Gate

X,

4

x3

-

D namic hock

D namic

1 ~

6lock

(4

Fig. 1.3 Partition of a real logic block into two blocks: functional and dynamic. a) real logic gate, b) delay model before the gate, c) delay model after the gate.

ers the functional behaviour of the gate and a second one that considers the dynamic effects, that is to say, the propagation delay. The second type of blocks are named the delay elements. As may be observed in Fig. 1.3, there are two possible configurations for these blocks which in principle are non-excluding. In the configuration for Fig. 1.3 (b), the dynamic blocks or delay elements are placed between the input signal and the functional block. Thus, there are as many blocks as inputs. However, in the configuration of Fig. 1.3 (c) only one dynamic block is placed between the functional block and the output signal. On account of the use of many more elements, the first model gives much greater flexibility than the second one. Nevertheless, most timing simulators and timing analysers use the second option because it requires much less data storage. The delay element is fully characterized when it has a delay model associated with it. A model of this nature is characterized by a set of rules and parameters which are used to determine the value of the propagation delay for an input transition. In order to establish a delay model, the following aspects must be considered because they are going to characterize the model:

Chapter I . Fundamentals of liming Simulation

15

On the one hand, the effects considered in the model. Basically these effects can be grouped into two types: static and dynamic. The static ones are those invariant in time, whereas the dynamic ones are changing in time. The more typical static effects considered are: the pure delay, the dependency with the output load and the dependency on the geometry of the transistors. The dynamic effects of greater importance are the dependency on the slope of input transitions and the dependency on the closeness between transitions, that is to say, effects such as collisions and glitches. The method of obtaining the relations which describe the timing behaviour. There are two ways to obtain these relations, an analytical method and a heuristic method. In the analytical method, the initial point is the simplified model of the transistors, from which the behaviour of the output is deduced as a function of the parameters of the simplified models (geometry, loads, etc.) and the input waveform. The heuristic method is based on the extraction of an important amount of information from the electrical simulation to look for the expressions and/or methods which best describe these data. There are some adjustment methods and among them the Piece-Wise Linear (PWL) method is very common. This way, a digital circuit in the logical-timing level is made up of blocks which make logic functions along with blocks which incorporate the dynamic behaviour by means of the evaluation of the propagation delay. The behaviour of the circuit is determined by the transitions or events in the signals (i.e. the logical changes from 0 to 1 or from 1 to 0) and the propagation of these events through the blocks which compose the circuit. In order to analyse the behaviour of this type of system, the eventdriven simulation technique is used. The delay model and the eventdriven technique are the two basic characteristics of the simulator tools at the logical level. The model determines the precision of the results and the event-driven technique is the one which provides the greatest efficiency in the generation of results. We are going to present briefly some of the simplest static delay models and the event-driven simulation technique.

16


1.4.1 Delay models at gate level

The simulators, at gate level, can include different types of delay models, with a different level of complexity. The simplest ones will be useful, mainly, for the functional verification, and the most complex ones will also be useful for timing verification.

1.4.1.1 Zero and unit delay models

The zero and unitary delay are the models of lesser complexity. They are useful mainly for the functional verification, since they do not contain a minimum degree of precision in the simulation to be able to consider timing aspects. The model consists of only one parameter of one unit. With this model, all the gates which compose a circuit design have the same timing behaviour. Although the results provided by the use of this model are not precise and it is not possible to consider that a timing verification has been made, it is possible to detect some timing phenomena such as, for example, the hazard.

1.4.1.2 Static delay models

The first model which begins to contribute a sufficient degree of precision in the results in the logical timing simulation is the denominated model of assignable delay. It is characterized by having each logical gate its own delay element associated to it, that is to say, the values of the parameters of the model are different for each gate. The simplest version consists of a single parameter, D,called pure delay, for each delay element. The difference between this version and the Unitary Delay Model is that the value of D can change from one gate to another. The second version considers two different values for the pure delay of an element, one for the transition from 0 to 1 (Dlh) and the other for the transition from 1 to 0 (Dhl).Another version arises when the delay value is a function of the load at the output of the gate.

Chapter I . FundamentaIs of Eming Simulation

17

1.4.1.3 Dynamics eflects

The wide use of static models has made it possible to observe some of the inaccuracies obtained in the timing logic simulation. The main reason for this resides in the fact that the propagation delay of a gate changes according to the waveform of the input signal. This has led to the development of new delay models in which these effects are considered. These delay models are called generically Dynamic Delay Models. At the moment, the existing dynamic models consider mainly two effects of the waveform: the slope of the input signal and the closeness between consecutive changes. This last effect is called the effect of collisions [Melcher et al. (1 992)].

1.4.2 The event-driven simulation technique Figure 1.4 shows the different elements necessary to carry out a simulation process. The simulation program arranges, on the one hand, the netlist of the circuit and the stimuli and control parameters provided by the user. On the other hand, it has to count on the behaviour models of the components used in the circuit, often obtained from a precharacterized library. After developing the simulation process, a set of results is generated. The verification of a design consists in verifying that the results obtained when simulating that design match the desired behaviour of the circuit. The event-driven technique consists in evaluating exclusively the time in which events take place and how they propagate through the different components of the circuit. In most cases, an event is associated to the change in the value of the signal, so that an event in the input of a gate may, when coming out, cause a new event in the output of this gate. This implies a fundamental difference with respect to circuit simulation, in which an analysis of the value of the signals is made in continuous time, that is to say, the signals are analysed at every necessary instant in order to be able to represent the signal by a continuous curve. For this reason

18


Simulation

program

Results

netlist)

Behavioural

models Fig. 1.4 Elements in a digital simulation process.

logical simulation is several orders of magnitude faster than circuit simulation, needing, in addition, much fewer resources of memory and CPU time. In the following, event-driven simulation will be analysed. In this type of simulation it is said that an element is active when an event occurs in some of its input signals. Whenever an active element exists in a given moment, the simulator should carry out the evaluation of this element. This evaluation consists of determining if the output of the active element is going to change in value and, if so, with what propagation delay. This is why it is necessary to use a delay model of the element. The simulation process begins by analysing the events which occur in the input signals of the circuit, which have been defined previously by the designer in the input stimuli file. As these events are evaluated, they generate new events in the remaining wires of the circuit and, thus, they activate new elements which are not connected directly to the input signals. Thus, a double propagation of events takes place: in time and in the elements which compose the circuit. The temporary flow mechanism of the simulation handles the events so that they are evaluated following an increasing timing order. In order to do so, the events are stored in what is called a queue of events, according to the moment in which they occur. This queue of events is being modified continuously, eliminating those

Chapter I . Fundamentals of Kming Simulation

19

events which have been evaluated and incorporating the new events which have been generated and have become active elements. Figure 1.5 shows the main flow of this type of simulation. Once a period of time is evaluated the simulator advances to the following time in which pending events exist, which becomes the present time of simulation. Later, the simulator obtains from the queue of events those events which occur in that moment and updates the value of the active signals. The active elements are determined from the list of active signals. Later, the active elements are evaluated and new events can arise. These events are introduced in the queue following the order in which occur. The process is repeated for each event at the present moment. The simulation continues as long as there is activity in the circuit.

1.5 Summary and Tendencies Table 1.1 summarizes the characteristics of the different types of timing simulation, based on the maximum size of the circuit, the speed of obtaining results and precision. A basic conclusion may be observed: the faster the simulation, the less precise are the results, and inversely. Table 1.1 Characteristics of different types of simulation.

Simulation type

Maximum circuit size

Speed

Circuit 10-1000gates very low simulation

Precision

Notes

very high

Only for small circuits

Switch-level simulation

lo5 gates

medium

medium

Only in circuits with transistor-leveldescription

Gate level

> lo6 gates

high

low

The only one used in semi-

simulation

custom designs

In all that has been presented so far, there are clear tendencies. The need for high precision timing simulations which are able to support very great circuits does not allow for the use of electrical simulators due to two factors. In the first place, the complexity of the calculations makes this

20


I

Init

the next simulation time ~

Next event in actual time

i

Actualization of active

signals

1

Computation of new events

1

YES

Fig. 1.5 Flow diagram in an event driven simulation algorithm.

type of simulations slow and applicable only to small circuits. Secondly, it is necessary to have device-level descriptions of the circuits. Although switch level simulations simplify calculations and thus yield greater speeds making it possible to simulate greater circuits, use device level netlists it is a drawback. Gate level simulators are better to fulfil the present and future necessities of design verification. Nevertheless the low precision of their results can be a great problem, mainly in the current deep sub-micron technologies.

Chapter 1. Fundamentals of liming Simulation

21

This makes it necessary to increase the timing precision of these simulators and to include models with more precision. Although the complexity of calculations will increase, the models used in circuit simulators will always be much simpler because they are referenced to the logical level and not to the electrical level.


Chapter 2

Delay Models: Evolution and Trends Manuel J e s h BelIido Diaz David Guerrero Martos

2.1 Introduction In logic timing simulation, a delay model is used to predict the dynamic behaviour of every element of the circuit (transistor net in transistor level simulation, logic gates in gate level simulation). The simulation precision depends on the precision of the delay model used. Delay models can be classified into two categories: deterministic and nondeterministic. These categories have several subtypes (Table 2.1) which will be presented in this chapter.

2.1.1 Deterministic delay models In this model, every circuit component has a single delay value which may depend on several factors. There are two types of delay models: Unitary delay models: In these models every circuit component has the same delay. Assignable delay models: In these models the delay of each component may differ. Assignable models can consider different effects to calculate the delay of each element. For example, when considering the output capaci-

23

24

Logic- Timing Simulation and the Degradation Delay Model

Table 2.1 Classification and characteristics of delay model types.

Zero delay Outputs change instantaneously when inputs change. Only functional simulation is carried out. Unitary delay The delay value is the same and fixed for every circuit component. The timing information obtained is qualitative.

Deterministic Calculate a specific value for the propagation delay.

Non-deterministic They find bounds for the delay. They enable simulation of random phenoma but the results obtained are often pessimistic.

Assignable delay Delay has a separate value 'or each circuit component.

Static The delay depends on the circuit nd parameters that do not change with time. The results are quite iccurate under bounded operating conditions. Dynamic The delay depends on the waveform as well as on static parameters. Different delay values are possible for separate simulation instants. Results can be very accurate in a wide range of operating conditions.

Minimum-maximum Assign the same probability to every delay value within a range. Statistical The probability of a delay value is ruled by a probability function, usually Gaussian.

tame of a gate, C,, the delay value is determined by the following expression [Abramovici et al. (1990)l: t, =

tpcfo

+ %CL

3

(2.1)

Chapter 2. Delay Models: Evolution and Trends

25

where tpc,,, is the intrinsic delay of the gate (the delay when C, = 0), and m,, models the influence of the output capacitance of the gate. We can consider two types of assignable deterministic delay models: static and dynamic [McGeer and Brayton (1991)l. In a static model, the delay of a gate depends only on the circuit and on gate characteristics which do not change in simulation time. In a dynamic model, the delay also depends on the input waveform of the element and may vary in simulation time. Static models are less precise than dynamic models since they do not take into account the history of the input waveform, but they can be quite accurate if the operation conditions are well-defined and the elements have been properly characterized. There are several factors in the input signals which can change the propagation delay, for example, the input slope or the temporal proximity of transitions in a gate input (input collisions). Modelling this effect would make it possible to deal in logic simulation with effects such as glitch propagation in circuits as well as to detect and to control oscillatory states [Abramovici et al. (1990)l.

2.1.2 Non-deterministic delay models Non-deterministic delay models do not specify a single delay propagation value for each element of the circuit. Instead they calculate lower and upper bounds for the real delay value. There are two types: Minimum-maximum delay (min-max), which consider that the probability of the delay of a gate is uniformly distributed in an interval. Thus, during the simulation the minimum and maximum possible delay values are calculated, since they are the most significant cases. Statistical delay [Vasuneda (1993)], which assigns a non-uniform probability to the values of the delay within a range bounded by a maximun and a minimun value. Usually, a Gaussian distribution is used. The distribution is centred in a value called typical delay, so that the probability decreases from the typical delay to the maximum or minimum.

26


The main advantage of non-deterministic delay models is that they can deal with model random issues such as variations of the propagation delay of each element in the production process and the environmental conditions, but they have several disadvantages. On the one hand, they lead to results which are too pessimistic about the circuit behaviour and, on the other hand, they require much more computation time during simulation. Moreover, they do not allow for the simulation of several issues such as propagation of short pulses in a circuit or oscillation state detection. Finally, this type of model can lead to simulation results which are not possible in several circuits [Mizco (1986)], so it is necessary to pay special attention to detecting this type of wrong results. With deterministic delay models it is always possible to make two estimations of the circuit operation using first maximum delay values and then minimum delay values, which make it possible to allowing problems due to extreme delay values. Because of this, we will focus exclusively on deterministic delay models. In the next section, a more detailed analysis of this type of model will be presented.

2.2 Deterministic Delay Model Types

In this section we will see different delay models following in rising order of complexity and accuracy. We will first look at those helpful in functional verification and we will follow with those which allow timing verification.

2.2.1 Zero and unitary delay models

The simplest models are the zero delay model and the unitary delay model, which are employed in the functional verification of the circuit without taking into account timing issues. The zero delay model does not take into account the propagation delay. Only the functional behaviour of the gate is considered. (Fig. 2.1) The unitary delay model uses a single delay element in the gate modelling. As may be seen in Fig. 2.2, the model has a single parameter that is

27


Fig. 2.1 Zero delay model.

I IN-

N

2

I

OUT OUT

3

Iu

Fig. 2.2 Unitary delay model.

the propagation delay from an input gate to the output. It must be emphasized that in this model all the gates of a circuit have the same timing behaviour. Although the results obtained with this model are not yet accurate enough for temporal verification, they allow for detection of some timing phenomena such as glitches (Fig. 2.3).

2.2.2 Assignable delay models The models that allow for sufficient precision in logic simulation are the assignable delay models. In these models each logic gate has its own delay element, that is, each gate has its own delay parameters. Assignable models can be static, if they do not take into account the input waveform, or dynamic.

2.2.2.1 Static delay models

Here four static assignable delay models will be presented in rising order of complexity as an example.

28

Logic-Ening Simulation and the Degradation Delay Model

\Hazard Fig. 2.3 Logic timing simulation with unitary delay model.

The simplest one has only parameter, t, , called pure delay, for each delay element. In this model any change at the input of a delay element will change the output with a delay equal to t,, as may be seem in Fig. 2.4 (a). Unlike the unitary model, in this model each gate can have a different t , value. A second version of the model allows for two separate values for the pure delay of the same element: one for transitions from 0 to 1 (t,,) and the other one for transitions from 0 to 1 (tPf). Fig. 2.4 (b) shows this model working. For any gate, t,, y t,, are usually different. In the third version of the model, the propagation delay depends on the output capacitance. There is a lineal dependence between them which follows this expression: t , = t,, + mcCL

(2.2) where CL is the output capacitance t,,and m, are gate parameters. If necessary, it is possible to use separate values of t,, and m, for falling and rising transitions. Fig. 2.4 (c) shows a delay element working with this delay model. This model takes into account issues related to the placement of the gate within the circuit (such as fanout). 3


IN

tP

29

OUT

IN

OUT

I

OUT

Fig. 2.4 Static assignable delay models: a) Pure delay. b) Pure delay with separate rising and falling values. c ) Pure delay taking into account the output capacitance. d) Inertial pure delay with t p i = t , .

A fourth version of assignable model can introduce the so-called inertial effect [Unger (1969)l. This is an effect observed in real gates which prevents short pulses from propagating through the gates. In this version each delay element has two parameters: t , or the pure component and tPi or the inertial component. The model works this way (Fig. 2.4 (d)): a pulse of width T , at the input of a delay element appears at the output with a total delay t, if T , > tPi ,but it is eliminated (that is,

30

Logic- 7iming Simulation and the Degradation Delay Model

the input does not change) if T , I t p i .Pure delay, t, is modelled as in Version 3. In summary, we have presented four versions of a static assignable delay model which take into account the following issues about the real behaviour of the gates: Version 1: pure delay propagation effect: t , parameter. Version 2: separate propagation delay for falling and rising transitions: t,, and tPf parameters. Version 3 : influence of the output capacitance over the propagation delay: tpOr,t P o f ,mcr and mcf parameters for the gate and C , parameter for the circuit. Version 4: Version 3 including the inertial effect: additional parameters: tpir and t P i f . In order to use these models it is necessary to get their parameter values ( t p O r ,t p o f etc.) , for each gate. This task is called parameter characterization. Usually, these models have a characterization process of its values which is relatively straightforward and fast without having to develop analytical models to obtain them.

2.2.2.2 Example of static delay model parameter characterization

As an example we will consider a gate, in this case an inverter (Fig. 2.5), in order to characterize it for the versions of the static assignable delay models which we have seen. For this characterization, analog simulation will be employed, namely with the HSPICE [Hspice (1999)l simulator. First of all, we must set the measurement criterion for the timing parameters. Generally, this criterion must be specified by the model itself. We will use the usual measurement criterion, that is, the pass through 50% of the polarization range (Fig. 2.6). The characterization of the simplest versions of assignable delay models (Versions 1 and 2) is carried out with a single simulation, whose result is shown in Fig. 2.7 (a). As may be seen, parameters t,, and tPf of


31

P wdP1 =8/0.8 Fig. 2.5 CharacterizedCMOS inverter. 0.7pm CMOS technology.

v~~ v~~ 2

O(GND)

I

--

1

0 Fig. 2.6 Criterion to approximate a real signal to a pure digital signal.

Version 2 are obtained directly from simulation, while t, parameter of Version 1 is obtained as a mean of both values: t , = ( t P r+ t,)/2. The third version, which includes load dependency, requires several simulations with different load values at the inverter output. Table 2.2 shows these results. There is a lineal relation between delay and load and the values of the parameters obtained are m, = 0.524ps/fF and t,, = 6 0 . 5 ~ sThese . values are approximately the same for both types of transitions, so it is not necessary to make a distinction between them, For the fourth version of the assignable model we must set the inertial delay value. Taking into account the measurement criterion, this value is obtained from the transitory simulation of an input pulse which produces

32

Logic-TfmingSimulation and the Degradation Delay Model

. .:

~

; . . ... . . . . . . . .

;

INYERSOR.EF!

.-

Fig. 2.7 Transitory analysis of a CMOS inverter. a) Measure of t p r , tPf y t p . b) Measure of the inertial delay.

an output pulse reaching 50% of the polarization but does not go beyond it (Fig, 2.7 (b)). The value of the inertial delay is practically equal to the propagation delay for all the load conditions, so it will be assumed that tP I'X = tp x ' To sum up, the inverter parameter values for each model version may be seen in Table 2.3.


33

Table 2.2 Propagation delay value of an inverter for several output capacitances.

95.06

66.24

130.1

132.5

164.6

198.7

199.2

.

265.0

Table 2.3 Delay parameter values for assignable delay models in a CMOS inverter.

Version 1

Version 2

Version 3

Version 4

t , = 1 6 5 ~t,,~ = 1 6 4 ~ ~t,, = 6 0 . 5 ~ ~ t,, = 6 0 . 5 ~ ~ m, = 0.524psIfF tPf = 166ps m, = 0.524ps/fF tPi = t ,

2.2.2.3 Dynamic delay models

The widespread use of static delay models makes it obvious that the logic simulation results obtained with these models are not accurate enough. The main reason is the strong dependence of the gate propagation delay on the input signal waveform. Because of that, new assignable delay models, generally called dynamic delay models, have been developed to take into account these effects. The existing dynamic models take into account two issues of the input waveform: the input slope and the proximity between consecutive changes. The last one is called the collision eflect [Melcher et al. (1992)l. Fig. 2.8 shows examples of both. The input slope is relevant because real signals are continuous and do not change instantaneously between logic levels. To model the wave form each transition is commonly approximated by a straight line. This linealization can be carried out following different criteria, for example, the

34


IN' >OUT IN2

OUT

IN

IN2 O U T T \ \

Ak-~

I-'

?-,

OUT

tp*tpnomal

P (a>

(b)

(c)

Fig. 2.8 Dynamic effects: a) input slope, b) input collisions which produce opposite changes at the output, c) input collisions which produce the same effect at the output.

passing through 10% and the 90% of the polarization range, or taking the straight tangent to the real curve when it passes through 50% of the polarization range. Both methods lead to satisfactory results. Each transition is thus characterized by its slope or by the time employed to commute between polarization rails, which is called transition time. As shown in Fig. 2.8 (a), if the transition time changes, the propagation delay changes significantly. There are two types of collisions. The first one (Fig. 2.8 (b)) occurs when input changes that are near in time produce output changes in opposite directions. This type of input change generates small pulses or glitches at the gate output which can propagate through the circuit (glitch collisions). In the second type input changes that are near in time produce changes in the gate output in the same direction (Fig. 2.8 (c)). This can accelerate the output transition in same cases or delay it in others [Melcher et al. (1992)l. Nowadays it is necessary to include dynamic effects to provide enough accuracy. The dependency of the delay on these effects is related to the production technology of I.C., so it is necessary to develop different models for each technology. Moreover, technological breakthroughs


35

make it mandatory to verify model accuracy continuously. This is why there are many works published in this field. We will now make a systematic review of a series of articles introducing innovations on delay models which we consider representative enough.

2.3 State of the Art in Delay Models

The research community has made, and is currently making, remarkable efforts to develop delay models and timing simulation techniques to achieve a better characterization and analysis of integrated digital circuits. These efforts have produced a huge number of articles published on this issue, especially in the last two decades. The delay model field is a hot issue since technological breakthroughs and increasing circuit perfomance oblige a continuous verification and improvement of the existing models. Here we present a wide variety of works published within the last few years in the delay model field. We will focus on those dealing with deterministic delay models for CMOS technologies. The works presented are not an exhaustive but a representative showing of the evolution of this field of research. First of all the main criteria to classify delay models which we will use with the selected works will be introduced. Then the performance reached by several implementations of delay models will be analysed, considering accuracy and simulation time. Finally, the evolution in the delay model field and possible future trends will be discussed.

2.3.1 Classification of the proposed delay models

It is not easy to obtain suitable criteria to classify the delay models developed, since there are multiple viewpoints that have led to their development. We propose a classification based on four criteria which are summarized in Table 2.4: technology, abstraction level, effects taken into account and the method of analysis. Each one is described below.

36

Logic- liming Simulation and the Degradation Delay Model

Table 2.4 Delay models classification criterion. Technology:

Abstraction level:

NMOS CMOS BiCMOS etc.

Transistor level Gate level

Effects taken into account: Static effects only Static and dynamic effects

Analisys method: Analytic method Heuristic method

Technology: This refers to the integrated circuit design technology the model was developed for. It may be NMOS, CMOS, BiCMOS or others. Many models focus on a specific technology, usually CMOS because it is currently the most widespread technology for I.C. production. Abstraction level: The viewpoint in the development of a delay model depends on whether it is applied in discrete circuits at the logic gate level or at the transistor level. For example, when it is applied at the transistor level, it is necessary to obtain the explicit dependence with the geometric parameters in the delay equations, while models for logic simulation at gate level can be described at a higher description level, considering each component as a black box whose input-output behaviour has been modelled. Effects considered: As seen in Sec. 2.2, deterministic delay models can be static or dynamic, depending on the effects they consider. Analysis method: The goal of the modelling process is to obtain an expression to describe the dynamic behaviour of the circuit components. There are two main non-exclusive methods to obtain this: a m lytic and heuristic. Analytic models use simplified transistor models and solve the differential equations which describe the behaviour of a circuit component for a given load and stimuli. Heuristic models, on the other hand, have a previous phase of data collection about the behaviour of the component, obtained from a prototype or by precise


37

Table 2.5 Summary of characteristics for several delay models.

ABSTRAC. DYNAMIC METHOD REMARKS LEVEL EFFECTS

REF.

TECH’

Ousterhout (1985)

MOS

transistor

Lai et al. (1987)

MOS

transistor

Deschant et al. (1988)

CMOS

transistor

Deng (1988)

CMOS

transistor

Deng and Shiau (1990)

CMOS

transistor

Wu and Shiau (1990)

CMOS

gates

Yang and Hoburn (1990), Vemuro and CMOS Smith (199 1)

slope

slope

0.f. (lineal 2

intervals)

Analytic

General

Analytic

General

Analytic

General

Heuristic

General lineal fit by interval

Anal/Heur Uses generic RC theory Analytic

transistor

slope

AnaVHeur

Jeppson (1994)

CMOS

gate (inverter)

slope

Analytic

Embabi and Damodaran ( 1994)

CMOS, BiCMOS

gate (inverter)

slope

Analytic

Capacitance coupling

electric simulation. In a second phase they are analysed to obtain expressions able to describe the dynamic behaviour of the component using few parameters. In fact, pure analytic or heuristic models are not used. The equations to be solved in an analytic approach are usually too complex so it is necessary to make simplifications by introducing fit parameters. On the other hand, the search for modelling expressions in heuristic models is much more efficient if there is a previous analysis. Tables 2.5, 2.6 and 2.7 show selected works and their characteristics concerning the former criteria.


38

Table 2.6 Summary of characteristics for several delay models (continuation). REF.

TECH- ABSTRAC. DYNAMIC METHOD REMARKS NOLOGY LEVEL EFFECTS

Zukowski and Chen (1988)

MOS

Jun et al. (1 989)

MOS

operation frequency gates

0.f., colli-

sions

Heuristic

Tabular Methods

Heuristic

Polynomial fit

slope, 0.f., exponential

Eisele et al. (1990)

slope

Switch

Heuristic

Polynomial optimization models

Analytic

Models for BRASIL simulator

Hoppe et al. (1 990)

CMOS

gates

Warmers et al. (1990)

MOS

transistor

Navavi-Lishi and Rumin ( 1994)

CMOS

gate (inverter)

Uebel and Bampi (1994)

CMOS

gates

Hallam et al, (1995)

CMOS

gates

Daga et al. (1996b)

CMOS

inverter

slope

Analytic

Submicron Technology

Liu and Chang (I 998)

CMOS

transistor

slope

Analytic

Gate resistance

Hirata et al. (1998)

CMOS

transistor

slope

Analytic

Bisdounis et al. (1998a) Bisdounis et al. (1 998b)

CMOS

inverter

'lope

Analytic


Daga and Auvergne (1999)

CMOS

gates

'lope

Analytic


Chatzigeorgiou et al. (1999a)

CMOS

gates

'lope

Analy/Heur

Collision reduction

0.f., expo-

nential

colli-

0.I.

sions

slope

Current and Analitic delay calculus

Anal/Heur

REFFModelling

Heuristic

39


Table 2.7 Summary of characteristics for several delay models (continuation).

REF.

ABSTRAC. DYNAMIC

TECHNOLOGY HH LEVEL

Casu et al.

EFFECTS

METHOD

REMARKS

CMOS

transistor

slope

Analytic

Hamoui and Rumin (2000)

CMOS

inverter

slope

Analytic

delay, current and power

Sakurai and Newton (1991)

MOS

gates

slope

Analytic

Short channel effect

Kayssi et al. (1992)

CMOS

inverter

slope

Analytic

DCFLISDCFL

gates

slope

Analytic

CMOS

gates

Bafleur et al. (1992)

CMOS

transistor and gates

Chow and Feng ( 1992)

CMOS

gate (inverter)

Shousna and Aboulwafa (1 993)

CMOS

gate (inverter)

CMOS, DCFL

Shih et al. ( 1993)

(2000)

Hernandez et Hernandez et al. (1993) Melcher et al. (1992)

0.f.,

collisions

Polinomic fit Jun et al. (1989)

Collision Heuristic classification Analytic

Can be used in mixed simulation

Analytic

Channel modulation

slopa

Analytic

Application of 1-V model

gates

slope

Heuristic

Input slope influence

MOS

transistor

0.f.

Analytic

Reduction to generic primitive

Bellido (1994)

CMOS

gates

glitch-like co11ision s

Lai and Cheng (1994)

BiCMOS

Kayssi et al. (1993)

gates

0.

f.

Heuristic Pulse degradation

Analytic

Basic cell

40


2.3.2 Delay model performance

The quality of a delay model within its range of application is determined by the performance reached by the simulation tool implementing that model. Performance depends on two main issues: accuracy and simulation speed. These are usually opposite criteria, since a more accurate model will probably be more complex and, consequently, slower and vice versa. As mentioned, electric simulation is used to evaluate and to compare delay model implementations, since it reaches accuracy levels above logic simulation. The electric simulator most used for this task is SPICE mewton et al. (1993)l or any of its commercial versions [Hspice (1999)l. Thus, the accuracy of a model implemented in a logic simulator is usually expressed as an error percentage with respect to the electric simulation results running over the same system. The same applies to simulation speed. Table 2.8 shows the data obtained by different authors. The estimation accuracy is approximately 10% with respect to electric simulation, which can be considered an acceptable margin for the results obtained by logic simulation. On the other hand, as already mentioned in this chapter, the speed-up in simulation velocity with respect to electric simulators is about 2 or 3 orders of magnitude, depending on the size of the circuit being simulated Figure 2.9 shows a summary averaging the results in Table 2.8 and distinguishes four different types of models by abstraction level and method of analysis. Gate level delay models are usually faster and, among them, heuristical models are the fastest. This result is foreseeable if we consider that gate level simulators lack the partitioning phase of the transistor level simulation and use equations obtained by heuristical methods that are simpler. Gate level delay models are also slightly more accurate, maybe because the dynamic partitioning used in the transistor level logic simulation is a source of error which does not appear in gatelevel logic simulation. Therefore both can reach similar accuracy despite the fact that the first one uses a more detailed simulation level. However, we must keep in mind that transistor level simulation may be applied to circuits which cannot be simulated at gate level.

41


Table 2.8 Performance comparison for several proposed model. speedup compared with compared SPICE in magniwith SPICE tud order deviation

REF.

IMPLEMENTED IN:

Ousterhout (1985)

CRYSTAL: timing analyser

Lai et al. (1 987)

JADE: timing simulator, transistor level

Deschant et al. (1990) PATH-RUNNER timing simulator, transistor level Deschant et al. (1993)

- 10% -10%
ntran(exh) ncoAexh) n(n + 11 n + 1 In Table 5.21 we show the value of this relationship for gates of up to five inputs. Apart from the important reduction in the characterization time, the most important conclusion is that in the simplified model the complexity of the characterization process presents a linear dependency on the number of inputs of the gate, and not the quadratic dependency of the exhaustive model. Table 5.21 Relationship between the characterization times of the simplified model and the exhaustive one.

1

2

2

100

2

6

4

0.67

3

12

6

0.50

4

20

8

0.40

5

30

10

0.33

5.6.1 Basic model

Due to the results observed in Figs. 5.5 to 5.8 it is possible to think about other simplification methods in order to reduce the number of parameters necessary to characterize a gate and, at the same time, to simplify the characterization process and to reduce even more the time required. Taking as example the curves corresponding to the NAND-4 gate of previous sections (this example follows the general characteristics observed in all the analysed gates) we present several ideas to obtain simpler models. In all the cases we refer to the variation of the parameters with the index i : Type 1 collisions, parameter A : this case shows'a not very lineal variation with the value of i f For this reason, linear adjustment would not

162

Logic-liming Simulation and the Degradation Delay Model

express in an appropriate way the dependence that is observed. More complex curves would be necessary. Type 1 collisions, parameter B : this parameter is approximately constant or suffers small and approximately linear variations. Type 1 collisions, parameter C: this parameter presents small and approximately linear variations. Type 2 collisions, parameter A : this parameter presents small but not linear variations. Type 2 collisions, parameter B : this parameter presents approximately linear small variations. Type 2 collisions, parameter C : this parameter presents accused variations and not too linear. In general, modelling these variations is not feasible in those cases in which two or three fitting parameters are needed along with a similar number of points to fit, which occurs in the case of gates with only a few inputs, since the number of points in each case is similar to the number of inputs of the gate. Also, these fitting processes are an additional source of error when calculating the delay. Thus, the method we propose is to continue using the simplified model explained in the previous section, without looking for new dependencies which will only simplify the model at a high cost in accuracy, Nevertheless, and especially due to the small variations with i that some parameters present (parameter B ,parameter A in type 2 collisions, and parameter C in type 1 collisions), we consider it interesting to explore a model simplified to the maximum allowing us to obtain an upper bound of the error which can be found using other less drastic simplified approaches. We will refer to this model as the basic degradation model at gate-level, and it consists of reducing each of the gate-level degradation parameters to only one value, without distinguishing among different inputs, but only among types of transitions (type 1 or type 2) corresponding to raising or falling outputs, depending on the case. The parameter characterization process of this model will also be simplified to the maximum. Obviously, we must expect important accuracy losses when using this model. The precision of the model will be evaluated in the subsequent sections.

Chapter 5. Gate-Level DDM

163

In the next section, we will formalize the equations which make up this model and its characterization process.

5.6.1.1 Basic model equations

According to the above-stated idea the matrices of degradation parameters at gate-level are reduced to a single value. If A is any of the parameters, these matrices can be expressed as: As = As

-

As = As.

(5.27)

Thus, the complete set of degradation parameters for a gate is reduced to six values, regardless of the number of gate inputs. These values are: (5.28) A s , B s , Cs, A s , B s , Cs.

5.6.1.2 Basic model characterization process For the characterization process, the simplest procedure consists of assigning the value obtained from the characterization of a certain collision to each parameter of Eq. (5.28), chosen according to this formula: ‘ S

=

A-S = A-Skl .

(5.29)

Keeping in mind the monotonous variation of the parameters within the index of the input, it is convenient to take intermediate values for k and I , for example: k = int(:]

+1

-i-).

I = int( n + l

(5.30)

Thus, k and 1 are also not coincident whenever the number of inputs of the gate allows for it. As an example, in Table 5.22, the vectors of the parameters are shown for the basic model corresponding to the gates of Tables 5.9 to 5.14.

164


Table 5.22 Parameters for the basic model of the degradation effect at gate level.

NAND-2

Value

Error

Value

Error

A,

252.685 f

45.54388 A ,

126.194 f

38.53486

Bf Cf

20.2306 f

.1183983 B ,

11.4375

f

1.668743

1.13477 f

.2464625 C, 2.54086 f

,749332

NOR-2

Value

Error

Value

Error

A/

272.206 f

29.35611 A,. 142.057 k

78.39844

By Cf

5.26297

f 2.37859 f

.645704

B, 2.43184 f

.42695815

.710381

C, 1.45051 f

.1261873

Error

Value

Error

NAND-3 Value

Af

312.815 f

Bf C,

15.6922 f 1.2401

f

85.21219 A ,

200.834 f

47.51632

B,

11.2297 f

1.064762

.2732269 C,

2.49735 k

.8168868

.60212

NOR-3

Value

A, B,

Cf

Error

Value

f 54.6685 A,. 144.228 k 5.48288 f .3960767 B, 2.79995 f 2.37431 k .680135 C, 1.46403 f 484.18

Error 188.2899 .3121505 .2101839

NAND-4

Value

Error

Value

Error

Bf

k 109.6104 A , 391.429 f 62.76919 15.3365 f .730258 B, 15.7685 f 1.4759276

C,

1.27071 k

A,

432.19

.3061028 C, 2.90767 f

1.275152

For the model characterization, the process is simplified drastically, since the number of collisions (nco,)is now only two, regardless of the


165

Table 5.23 Relationship between the characterization times of the simplified model and the exhaustive one (n,,,(bas) = 2 ).

n

nc,,(exh) nc,,(simP) n ( n + 1) 2n

tchar(bas) tchar(bas) tch ar(exh) t c , a Asimp)

1

2

2

1.00

1.oo

2

6

4

0.33

0.50

3

12

6

0.17

0.33

4

20

8

0.10

0.25

5

30

10

0.07

0.20

amount of gate inputs. Thus, performing an analysis similar to the one shown in Eq. (5.26), we can see how the basic model characterization time is related to those times for simplified and exhaustive models:

(5.31) The value of these relationships for gates of up to five inputs is shown in Table 5.23. For example, the characterization time for four input gates decreases in an order of magnitude with respect to the exhaustive characterization and to a quarter with respect to the time needed to characterize the simplified model.

5.6.2 Error estimationfor the propagation delay

The values of the parameters obtained for all the models are subject to errors which have their origin, in the first place, in the fitting process employed on the electric simulation data. In the case of the simplified and basic models, we also find the error generated by approximating the set of values corresponding to various inputs by only one value. In fact, in these models, the error due to the adjustment of each particular value becomes negligible compared to the error introduced by the simplification. Ultimately, our interest resides in being able to evaluate what impact these

166

Logic-&zingSimulation and the Degradation Delay Model

errors have in the final value of the calculated delay, especially the errors introduced in the simplified and basic models. In this section we will present the expressions which allow us to propagate the error of the degradation parameters to the propagation delay. For the sake of clarity, the details in the obtention of these expressions are shown at the end of the chapter in an appendix. Several general characteristics of the error propagation process are deduced from the expressions obtained. Later, as an example, we will apply the expressions obtained to the evaluation of the influence which the simplifications performed in previous sections produce in the error of a NAND-4 gate delay.

5.6.2.1 Expressionsfor error propagation In the first place we will define some concepts: We define the relative error of a magnitude x as: (5.32) where x is the value of the magnitude and Ax is the uncertainty or absolute error of this value. The relative error is always a positive quantity. We define the relative error of a magnitude x with respect to another magnitude y as: (5.33) We call sensitivity of magnitude x with respect to the magnitude y :

pj,

(5.34)

= Sj:&(y).

(5.35)

sj: = so Ey(X)

We can prove easily that

s: = sp;.

(5.36)


167

This way, 5': represents how the relative error propagates from a magnitude x to another magnitude y which depends on the first one. Likewise, Eq. (5.36) allows us to obtain the sensitivity of a magnitude with respect to another by means of successive intermediate steps. The problem we want to solve is how to obtain of the sensitivity of the propagation delay ( t , ) with respect to the degradation parameters at gate-level (A, B, and C). In the first place, by applying Eq. (5.1) and the previous definitions, we can obtain the sensibilities of the delay with respect to parameters z and T o: (5.37) (5.38)

In the same way, by applying Eq. (5.11) and Eq. (5.12) we can obtain the sensitivities of z and T o with respect to A , B, and C s:' = 1BCL ' (5.39) 1+A (5.40)

1 s$, = -

(5.41) 1-- V D D 2c The obtention of these expressions is detailed in the appendix of this chapter. Finally, by applying Eq. (5.36) and the previous equations it is possible to obtain expressions of the sensitivity of t , with respect to A , B, and C. For the case of S," we have also used Eq. (5.11) and Eq. (5.12) to obtain a result as a function of A , B and C: (5.42)

168


s,B

Si A '

=

(5.43)

1+-

BCL

s,c

C = s2-VDD

'in

-

'-

S2A

cBCL'in

+

'

(5.44)

In these expressions, we have introduced two coefficients (sI and s2 ) which facilitate the interpretation of the result. These coefficients depend exclusively on the degradation factor d = t,/t,,, in the following way: (5.45) These coefficients act by modulating the sensitivity of the delay depending on the quantity of the degradation effect which takes place. In Table 5.24 we show the values of s and s2 corresponding to several values of d.

,

Table 5.24 Values of s1 and s2 depending on the degradation factor.

d

Degradation %

0.90

10

0.256 0.111

0.80

20

0.402 0.250

0.70

30

0.516 0.429

0.60

40

0.611 0.667

0.50

50

0.693

s1

s2

1

Observing the previous expressions we can deduce several aspects about the sensitivity of the propagation delay with respect to degradation parameters at gate-level. We will enumerate some of them: Sensitivity with respect to any of the parameters increases with the percentage of degradation, due to the evolution of coefficients s, and s2 (Table 5.24). Sensitivity of t, with respect to A and B is always smaller than one unit and it varies in one way or another depending on the relative


169

importance of the terms A and BCL . This means that the relative error of the delay due to A and B is always smaller than the relative error of parameters A and B. Parameter A expresses the remainder value of z when C L = 0 and its origin is in the capacity that the gate itself contributes to its output. This way, for BCL D A , the intrinsic output capacity of the gate, represented by A , is negligible compared to the output load capacity and this results in: Sf + 0 . Otherwise, for BC, G A , the output load capacity is negligible compared to the intrinsic output capacity of the gate, which yields:

s;B+o. t, becomes more sensitive to the variations of C for slow inputs with respect to the value of z , which, on the other hand, is usually of the same order of magnitude as the value of the propagation delay of the gate. The sensitivity of the delay with respect to C is modulated by factor C / V D , which represents, in relative terms, the voltage threshold of the input of a gate with respect to the supply voltage. The delay in inputs with lower thresholds (as those closer to the supply rail in a transistor chain) will present smaller sensitivity to variations of parameter C.

5.6.2.2 Example of error propagation towards the propagation delay

In this section we present an example which will allow us to evaluate the precision of the degradation model at gate level, represented by Eq. (5.1), Eq. (5.1 1) and Eq. (5.12), and the precision of the different proposed models: exhaustive, simplified and basic. The example consists in the analysis of the propagation delay error produced by a collision with degradation in a NAND gate. Three cases are considered: Case 1: The exhaustive model is used. We thus have to consider the values obtained for the degradation parameters obtained for each input collision in an independent way. In this case, the error of param-

170

Logic-7iming Simulation and the Degradation Delay Model

eters A , B, and C is produced only by an error of the fitting process for these parameters to the expressions in Eq. (5.11) and Eq. (5.12). Case 2: We use the parameters of the simplified model for the gate. In this case, the error we must propagate is due to the fitting process as well as to the simplification that this model supposes. Case 3: The parameters of the basic model are used. Again, the error is due partially to the fitting process, but mainly to the strong simplification process that this model supposes. Other details of the characterized example are: We analyse collision-32 of the NAND-4 gate in this section, i.e. a rising transition at input 2 followed by a falling transition at input 3. This gate has been chosen from those analysed in Figs. 5.5 to 5.8 because it presents the clearest variations of the parameters with the input index. Thus, we avoid having to study an excessively favourable case whose results would not be representative. We have chosen the collision-32 because it is an intermediate case and it also corresponds to the typical case we have employed to obtain the value of the parameters in the simplified and basic models. This way the comparison between the different proposed models is facilitated. We have chosen an output load corresponding to double the input capacity of the gate. Again, this case is not the most favourable for the sensitivity of the propagated error, which gives more generality to the example. We have used an input transition with a duration of T,, = 2 t,, ,where t,, is the delay for a step input. This case corresponds to a typical transition of moderate speed. The error of the three models will be evaluated for two different values of the degradation factor: moderate degradation ( d = 0.80) and strong degradation ( d = 0.50 ). As already mentioned, the error of the degradation parameters for the case of the exhaustive model is directly the fitting error, just as we can observe in Table 5.13. For the case of the simplified model, the fitting error and the approximation error have been added. It has been considered


171

as approximation error the largest difference between each parameter and the group of values it represents: (5.46) approximation error = max { Asii - Asd, 'dj ] .

1

In a similar way, the approximation error for the basic model is: (5.47) approximation error = max{ IAzij - A31, 'di,j } .

In Table 5.25 the values of the degradation parameters are shown for the three mentioned models corresponding to collision-32 of the example, together with their corresponding errors. The value of the parameters has been extracted from the full set of values for this gate, presented in Table 5.13. The value of the parameters is the same for all the models (exhaustive, simplified and basic) because we have chosen collision-32 as an example, although the error which affects each parameter is different for each model depending on the approaches that each one of them implies. Table 5.25 Degradation parameters values and errors for the example collision.

Parameter Value Error exh. model Error simp. model Error basic model A

391.4

2.4

8.8

63

B

15.77

0.050

0.17

1.48

C

2.91

0.15

0.24

1.28

Other necessary data for the calculation of the propagation of the error are the specific values of the output load and the transition time which we calculated from the input capacity and t p s , according to the approaches previously presented: C, = 8fF C, = 2C, = 17fF, (5.48) t,, = 218ps z i , = 2t,, = 436ps. (5.49) On the other hand, the sensitivity of the delay with respect to the degradation parameters at gate level is obtained by applying Eq. (5.42), Eq. (5.43), Eq. (5.44), and the data of Table 5.24 and Table 5.25. Again the calculation is simplified because, for collision-32, the sensitivities are

172

Logic-RimingSimulation and the Degradation Delay Model

the same for the three models. In Table 5.26 the results are shown for the two mentioned cases of degradation ( d = 0.80 and d = 0.50 ). Table 5.26 Sensitivity of delay with respect to the different degradation parameters at gate level for two cases: moderate degradation (d = 0.80) and strong degradation (d = 0.50).

Factor

Moderate degradation (d = 0.80)

Strong degradation (d = 0.50)

sr,

0.233

0.406

s; s:

0.169

0.294

0.47

1.88

Finally, with the errors of Table 5.25 and the sensitivities estimated in Table 5.26 we can calculate the relative errors propagated to the delay by applying Eq. (5.35) for each pattern and for the two degradation cases. The results are shown in Table 5.27, Table 5.28, and Table 5.29. Table 5.27 Results of the propagation of the error from the degradation parameters at gate level to the propagation delay: relative errors of the degradation parameters. ~

~~~~

X

exh.

simp.

basic

A

0.61

2.2

16

B

0.32

1.07

9.4

C

5.1

8.08

44

In the light of these results, we can make the following observations: The relative error of the different parameters of the exhaustive model (Table 5.27) is very small for parameters A and B, and sensibly larger, but acceptable, for parameter C. In this model, the error is produced only by the fitting process, so it demonstrates the ability of the basic expressions of the model, Eq. (5.6) and Eq. (5.7), to adjust to the results of the electric simulation.


173

Table 5.28 Results of the propagation of the error from the degradation parameters at gate level to the propagation delay: delay relative error for moderate degradation.

&,(t,) (%) (d = 0.80) X

exh.

simp.

basic

A

0.14

0.5 1

3.7

B

0.054

0.18

1.6

C

2.4

3.8

21

Table 5.29 Results of the propagation of the error from the degradation parameters at gate level to the propagation delay: delay relative error for strong degradation.

Ex(tp) (%) (d = 0.50) X

exh.

simp.

basic

A

0.25

0.89

6.5

B

0.094

0.31

2.8

c

9.6

15

83

For the simplified model, the error introduced by its parameters in the delay is of the same order, although always a bit larger that the one of the exhaustive model. This result justifies its use instead of the exhaustive model due to the important improvements it implies in the simplification of the model and in the improvement of characterization times. The error propagated by the parameters of the basic model is larger than the one of the exhaustive model in more than one order of magnitude in most of the cases. However, the final error it produces can be acceptable in some cases, as we will see later on. Parameters A and B show the best behaviour in the relative error of degradation parameters themselves as well as the smallest sensitivity in the delay error to them. The error propagated for these parameters is even located below 1% for the case of strong degradation in the exhaustive and simplified models, and close to 5% for the basic model.

174


Parameter C propagates the largest error. This is due mainly to three reasons: a larger fitting error than the one already present in the exhaustive model, an appreciable variation with the input index which affects mainly the basic model error, and a larger sensitivity to the delay to variations of C, mainly when the degradation effect is stronger (Table 5.26). Even this way, for the case of moderate degradation, the error propagated towards the delay is acceptable for the exhaustive (2%) and simplified (4%) models, and it is not excessive in the case of the basic model (2 1%). For the case of strong degradation, the error introduced by the basic model is excessive (83%) and important in the exhaustive (9.6%) and simplified (15%) models. This fact is due to the behaviour which the sensitivity of the delay presents regarding parameter C which increases quickly in the cases of strong degradation and amplifies the error propagated from parameter C to the delay (Table 5.26). To conclude, we can note that the sensitivity of the propagation delay to the variations of the parameters A , B, and C are generally smaller than one unit. This makes the errors in these parameters, those produced by the fitting process as well as those produced by the simplification of the model, affect the propagation delay in an attenuated way. This behaviour of the sensitivity only changes in cases of strong degradation (close to %YO),where the sensitivity with respect to parameter C can be larger than one unit. This fact, together with the stronger incidence of the fitting error on parameter C, makes this parameter the most important source of error and determines the limits in which each version of the model can be applied, maintaining a certain degree of precision.

5.7 Discussion of Results

In this Chapter we have presented the extension to the gates of the degradation delay model for the CMOS inverter analysed in Chapters 3 and 4. This extension has been made in order to apply the model to the logic timing simulation at the gate-level, using standard library cells.


175

In the first place, a model has been formulated which contemplates the exhaustive characterization of the set of degradation parameters (A, B, and C) for each possible input collision able to produce degradation. The model thus obtained describes in a complete and precise way the degradation effect in a gate. It is necessary to highlight that the model is not only presented, but also a detailed description of the necessary characterization process to obtain the values of the parameters is given, which is essential for making any feasible and reproducible model. Likewise, the complexity of this characterization process has been analysed. We have shown the necessity to automate the process to be able to obtain a usehl amount of data to drive the characterization process. In this sense a tool for automatic characterization has been developed which generates the complete set of degradation parameters from the description of a logic gate. This tool makes it feasible to characterize whole libraries of gates. Starting from the analysis of the characterization results for a representative group of gates, we have proposed a simplified model which reduces in a substantial way the number of parameters necessary to describe a gate with respect to the exhaustive model (almost 1/3 for four input gates) while conserving a precision similar to the one of the exhaustive model. The characterization time is reduced by the same factor. We have also presented a model of extreme simplicity named basic model which reduces to only six the number of parameters necessary to characterize the degradation in any gate, although it reduces the precision of the results. Finally, the propagation of the error from the degradation parameters to the propagation delay has been studied. This allows us to evaluate the precision of the fitting expressions on which the models are based, as well as the simplifications we have carried out. We have demonstrated that the error in parameters A and B is always attenuated when it propagates towards the delay. This means that a certain relative error in these parameters produces a smaller relative error in the delay. This attenuation grows as a smaller degradation takes place. However, parameter C appears as the main source of error in the models, especially in cases of strong degradation, in which the relative error in this parameter can be propagated to the propagation delay in an ampliJied way,

176


We have carried out a detailed analysis of the error propagation in a representative example that reveals how the exhaustive model describes with great precision the degradation effect, which validates the basic expressions of the model. The simplified model is also valid and it has a precision similar to that of the exhaustive model, making it the preferred model for production. The basic model is even applicable in cases of moderate degradation (20%) in those cases in which a high precision is not needed. The results obtained in this Chapter indicate different continuation tasks concerning the study of the degradation effect modelling at gate level. Some of these tasks are: To explore more deeply the modelling of parameters T o and C, which are the main sources of error. To look for equivalencies in the value of the degradation parameters among different gates, as a way to additional simplifications of the model. To explore the dependence of parameters A , B, and C on the technological variables, as a way to extend the model to levels lower than that of the logic gate. To generalize the study of collisions to complex logical gates, extending the application of the model to macrocells.

5.8 Appendix: Calculation of Error Sensitivity in the Propagation Delay With Respect to the Degradation Parameter Error

In this appendix, we explain in detail the process of obtaining Eqs. (5.37) to (5.41). For more information you can consult the corresponding section. In the first place, we reproduce here the equations necessary for the explanation. The expression sensitivity of the magnitude x with respect to magnitude y refers to: (5.50)


177

The basic equation of the DDM is: t, = t p o ( l - e

--T - T T

1.

(5.51)

Parameters z and To are expressed as a function of the degradation parameters at gate level as: A + BCL z = (5.52) VDD

’

(5.53)

5.8.1 Sensitivity of the propagation delay with respect to parameter z

First we calculate the partial derivative of t, with respect to z :

(5.54) From Eq. (5.51) we have: --T - T o

(-t,o)e

-

t,- t p o .

(5.55)

Therefore:

(5.56) We calculate the sensitivity: (5.57)

From Eq. (5.51) we have: (5.58)

Therefore:

(5.59)

178

Logic- Enzing Simulation and the Degradation Delay Model

5.8.2 Sensitivity of thepropagation delay with respect to To First we calculate the partial derivative and simplify by applying Eq. (5.55): (5.60) Now we calculate the sensitivity: (5.61)

5.8.3 Sensitivity ofparameter T with respect to A (5.62) We apply Eq. (5.52) to write the result as a function of A and B: A 1 = IA+BCj BCL * 1+A

':'

5.8.4 Sensitivity ofparameter

'I:

(5.63)

with respect to B

In a similar way: (5.64)

5.8.5 Sensitivity of To with respect to C (5.65)


179

We apply Eq. (5.53) to write the result as a function of C:

(5.66)


Chapter 6

Logic Level Simulator Design and Implementation Jorge Juan Chic0 Paulino Ruiz de Clavijo Vkzquez

6.1 Introduction In previous chapters we have developed what we believe is a highly accurate delay model: the degradation delay model (DDM). We have also presented a new algorithm to handle the inertial effect in Sec. 3.4.2. To be able to exploit the model’s benefits we need to include it in a logic-level simulation tool. Conventional logic-level simulators like the VHDL or Verilog standard simulators, are not suited to implement the DDM nor the new inertial effect handling algorithm. Regarding the DDM, extra information not present in conventional event-driven simulators is necessary to take account of the degradation effect. On the other hand, the new inertial effect algorithm is threshold-based instead of delay-based, as implemented in conventional approaches. For these reasons, we have developed a new logic-level simulation tool which is able to implement the special characteristics of the DDM and the new inertial effect algorithm, besides the traditional techniques. This simulator is named HALOTIS, which stands for High Accuracy Logic TZming Simulator. Among the main features of HALOTIS are its modularity and object-oriented design. These make it possible to implement a variety of delay models apart from the DDM, which is useful for making comparisons between them. Furthermore, it can be easily extended with new delay models. HALOTIS reads Verilog format for

181

182


compatibility with existing commercial tools, but the parser side is also modular and can be extended to support other formats. Although HALOTIS is still in active development, it is already a flexible and extensible logic-timing simulation tool. In the development of a complex software tool, it is necessary to use some development methodology. At the present time every methodology includes a group of basic tasks: analysis, design and implementation, traditionally called the software life-cycle. There are numerous methodologies of software development that cover the wide life-cycle. Besides these three basic tasks, the methodologies include other tasks or subdivide some tasks being able to process the different aspects of the software conceptually, mainly in the design stage. This subdivision of the basic tasks in the life-cycle originates different methodologies, some aimed to solve specific types of problems, and more general ones able to include several cases. The modelling concept is common to every methodology. A model is no more than a representation in some medium of the subset of the reality to be dealt with, that is to say, it can be considered as an abstraction of a certain reality. The model will allow us to capture and enumerate the requirements and the knowledge domain thoroughly, so that all the agents implied in the project can understand them and may agree with them. Lastly, it is necessary that all models incorporate a certain system of notation, which should be common to all the persons involved in the project. This notation gave way to a certain methodology. During the development of HALOTIS we have gone through the different stages of the life-cycle: problem analysis, design and implementation. The different tasks of the life-cycle can be simplified if the design is based on some software object-oriented methodology. Nowadays it is admitted that if the design of complex software is developed with an object-oriented methodology we can obtain a result which is, on one hand, easy to implement in a programming language, and on the other hand is easy to maintain, to debug and to expand. The objective of this chapter is to summarize some details about its design and implementation of the HALOTIS simulator. In the following sections we will present a brief introduction to the object-oriented methodology, a general description and requirements of HALOTIS, finishing off with some details about its implementation.

Chapter 6. Logic Level Simulator Design and Implementation

183

6.2 Object Oriented Methodologies: UML

6.2.1 UML introduction

Nowadays object-oriented design methodologies are widely accepted in software engineering. These methodologies first appeared around the middle of the 70’s and the early 80’s. During the period 1989-1994, the number of modelling languages increased considerably from less than ten to more than fifty, but many users were not satisfied with these techniques. This started the so-called war of methods, among which are Booch’93, OMT and Fusion. UML (Unified Modelling Language) [Rumbaugh et al. (1999)l appeared as the evolution of this collection of methodologies and has been standardized and accepted worldwide. First of all, UML is an object-oriented methodology. With the object concept we intend to group together in an abstract entity certain aspects of the domain of the problem which share some attributes, as occurs in our daily reality. In an object-oriented methodology, the designer should think about how to group the attributes of what he/she wants to model, thus defining different objects, so that the sum of all of the objects represents the whole domain of the problem. UML is also a language used to specify, build, visualize and document software systems. With UML we have a visual language for modelling software, but not a visual programming language, that is to say, from it we cannot derive the code automatically into some programming language. The excellent aspect of this methodology is that the architecture and structure of the system can be expressed and understood perfectly by different people of different knowledge areas. Also, with this methodology, we cover all the stages of software development: analysis, design, programming and testing. The history of UML started in October 1994 when Grady Booch and Jim Rumbaugh from Rational Software started to work on the unification of the modelling languages Booch and OMT. It is then that they started to be recognized worldwide as leaders in the development of object-oriented methodologies. They concluded their unification effort by writing a draft of version 0.8 of the so-called U n g e d Method in October 1995. Afterwards, and also in 1995, Ivar Jacobson, father of the OOSE methodology,

184


joined Rational Software to create UML 0.9 and 0.91 in June and October 1996, respectively. After that, several companies’ joined Rational Software to produce UML 1.O and UML 1.1, which have evolved into UML 1.4 and 2.0 at present. UML has then been adopted by several organizations and companies as a standard methodology in the development of processes and products, with the advantage that, as an open standard, it is available to the scientific community.

6.2.2 UML representation Throughout this chapter we will use a set of graphic elements that are part of the UML methodology. These graphic elements form a standard and easy-to-use description language. This is one of the main objectives of the use of UML: to share a certain system of notation and to be able to exchange information without having to devote a great deal of effort to these tasks. UML has different visual constructions to represent the system, these are called views. Each of these views tries to represent different features of the software. During the various stages of the life-cycle we will use the UML views that we consider necessary according to the type of software we want to model. More precisely, we will use the following views:

Use Case Diagrams: It is desirable to do high-level system descriptions from a functional point of view. These diagrams describe the system’s functionality following a descending methodology, so that we start at a high-level vision of the system and we continue decomposing the system into more concrete parts. The objective of use case diagrams is to define a part of the system’s behaviour without showing the internal structure of the system. The notation consists of cir-

Among these companies are Microsoft, Hewlett-Packard, Oracle, Sterling Software MCI Systemhouse, Unisys, ICON Computing, IntelliCorp, i-Logix, IBM, ObjectTime, Platinum Technology, Ptech, Taskon, Reich Technologies and Softeam.


185

cles representing tasks that can be achieved, which are connected through lines with two qualification types: Uses: These represent an inclusive relationship, so that a task is formed internally by other tasks. Extends: These represent an extension relationship. We can understand them as different forms of realization of a task or a specialization of this task. Object Diagrams: These diagrams represent static aspects of the system being developed. These static features model the internal structure of the source code such as the internal representation of data stored in the system. This is the core of all software developments so it is very important to achieve a good modelling since we will thus obtain high quality software. Therefore, we should spend great effort on this task. These diagrams are formed by objects, represented by squared boxes, linked together through relationships which connect the objects. The set of objects and relationships is an abstraction of the reality that we want to represent. It should include all the elements and features of the system that we want to build. Activity Diagrams: With these diagrams we model the dynamic behaviour of the software. In UML notation, an activity diagram consists of a box divided into a series of columns where each column represents an objectlclass, so that when the object does some activity, the description of the activity that takes place is included and displayed in a box. The result of an activity is a set of data represented within a new box which is located on the boundary between two columns. With this representation we indicate that the resulting data flows between the classes associated to the columns. Finally the whole diagram is bound by arrows that show the order in which the system runs the different activities. Once the basic components of the UML methodology have been introduced, they will be used to describe the stages involved in the life cycle of software development. The following points enumerate these stages and the UML elements that are typically associated with them:

186


(1) Global analysis or conceptualization:The main objective of this stage is to set up the overall picture of the problem to be solved. Sets of requirements, tasks and results are typically specified at this stage. (2) Analysis of requirements: In this stage, the sets of requirements of the first stage are better organized and further specified in order to detect possible inconsistencies, lack of features, redundancies, etc. (3) System design: With this stage we will obtain a global vision of the system from a high-level point of view. Use case diagrams are used during this stage. (4) Object design: Now the objective is to build an object model that will be implemented in the next stage. This model should represent precisely the reality of the system. Objects, classes, states and activity diagrams are the UML components to be used in this stage. (5) Implementation: The above mentioned components need now to be coded in a given programming language. The pros and cons of different languages should be taken into account in order to select the best option for our system.

The rest of this chapter is devoted to describing these stages in detail during the development of HALOTIS.

6.3 Global Analysis of HALOTIS We will start the global analysis by specifying the general requirements from the user’s point of view. We will also give a general description of the tool’s functionality, including aspects like the user interface, different hardware description languages that the tool must interpret, the output data.format, etc. The general objective is to build an event-driven simulation tool that can simulate digital circuits. The tool should be able to use different behavioural models, different circuit technologies and different sirnulation algorithms. The user should be able to specify behavioural models and simulation parameters by creating, editing or deleting these behavioural models or the parameters of the digital electronic components. A first type of user interaction is adding or modifying the application’s


187

HALOTIS

Netlist

Simulation

Cell Library

/ Prcgramrner

Behavioural models

Fig. 6.1 General high level system view.

source code, normally by adding or editing the code of a module corresponding to a given behavioural model or algorithm. The system should be modular enough to facilitate these tasks. This way of interaction, however, will be most commonly useful for future extensions of the tool capabilities by experienced users. A much more common task will be the modification of cell libraries which hold specific simulation data of the circuit’s building blocks. This data is typically obtained by a characterizing procedure. The user should be able to append, delete or modify cell libraries and the model parameters easily. After this first analysis, it is possible to obtain a general idea of the HALOTIS operation depicted in Fig. 6.1, following the UML notation by using a use case diagram. This diagram represents the complete system and establishes the border between the external elements through the rectangular box. Also, inside the rectangular box, three fundamental blocks or tasks are included, using ellipses for their representation. These tasks are strongly related to the main operations of the tools, which are:

188


Simulation of VLSI digital integrated circuits. Manipulation of cell libraries. Manipulation of behavioural models and algorithms, since a new behavioural model may imply a new simulation algorithm. The simulation of digital circuits in a circuit development environment consists, fundamentally, in the ability of the designer to obtain results that are similar to the real behaviour of the circuit once fabricated. In this case, these results are a timing evolution of a set of signals when different stimuli are applied. The description of the circuit design, called netlist, is typically done in a standard hardware description language (HDL) while the stimuli or patterns used for the simulation can be described in the same or in another, dedicated, description language. Both descriptions are stored in plain text computer files which have been directly edited by the designer or automatically generated by a design environment. Therefore, the first problem that the tool faces is that it must be able to understand (parse) these design languages. Currently, one of the weak points of the tools that work with HDL is the lack of error handling and recovery mechanisms. To facilitate the work of the designers it is necessary to make a greater effort in the development of parsers and lexers that interpret the HDL language. We should integrate a good mechanism of error recovery so that the tool provides the designer with exact and useful information about syntax errors. Figure 6.2 shows the component diagram of the tool. We propose a system division in three independent executable modules: an HDL parser, a cell library manager and a simulation engine. These three modules can be directly and independently executed in the command line. Input files are specified through command-line parameters, besides additional parameters that indicate different simulation options such as the model to use, the library to use, simulation time-out, output file name, statistical calculation, output format, etc. Having the HDL parser in an independent module makes it easy to create future extensions to support additional input languages. Focusing on the cell libraries, digital designs are commonly built with standard components (library cells) which are part of a library provided by a given


189

Fig. 6.2 HALOTIS component diagram.

manufacturer or foundry. To simulate a design, we need some information about these components, such as: The logic function at each output node of the cell. This data is called the logic block. A set of characteristicparameters which models the cell behaviour for a given behavioural model. These parameters will be used by the sim-

190


ulation engine to calculate the response of the cell when stimuli is applied. This data is called the dynamic block. Cell library data is strongly related to the behavioural model used in the simulator, since each cell will have a collection of parameters for each behavioural model included in the simulator. Cell library makers typically include data for basic behavioural models such as rise and fall times and delays and fan-out delay factors. However, the use of different behavioural models is a fundamental point during research, where many such models need to be tested and compared in order to discover better solutions. Having said that, another important objective in the design of HALOTIS i,s to create a tool with a high flexibility that can be easily adapted to include new behavioural models, library data and simulation algorithms. It is obvious that when we append new algorithms, it is necessary to write them in some programming language together with the tool source code. In order not to alter the design and structure of the tool we will include source code stubs to which new modules or algorithm routines can be linked.

6.4 Analysis of Requirements In this section we will describe the requirements that led to the current version of HALOTIS. Among these requirements we find the hardware description language that it interprets (netlist format), the output data format, and current criteria to specify cells libraries and how to include new simulation algorithms. Regarding the netlist, HALOTIS currently understands a subset of Verilog and VHDL formats, as depicted in Fig. 6.2. The stand alone HDL parser executable would read a Verilog or VHDL netlist and generated an error-free pre-compiled netlist in binary format. The starting point to the development of the HDL parser is the Verilog language specification, which is easier to analyse from a computer program’s point of view than a VHDL description. For the description of stimuli patterns, different formats are available. A very simple and convenient format is the one used by MATCHTA tool


191

[Mach (2000)l. This format consists of a small header including some general data about the simulation process such as time units, transition fall and rise time and input grouping; followed by lines, each corresponding to a test vector that contains a time instant when it is applied, the binary values of the circuit’s input signals and the expected binary values of the circuit’s outputs. As mentioned before, the simulator will also need the following information to carry out a logic-timing simulation of the circuit:

a cell library, a simulation time-out instant to force the simulation to stop, which is necessary in some circuits that contain feedback loops or that operate autonomously. Every computer system should include some utilities to ease the user’s work. In our simulator we propose including the following facilities through command-line options: Netlist verification to detect different types of errors such as lexicons, syntactic and semantic errors. These checks will detect netlist incoherency such as non-wired input or output signals, non-wired cell ports, unused modules, etc. Statistical calculations and presentation. Options for different output formats that are compatible with different graphic viewers and plotting tools. With respect to the cell libraries, we establish a mechanism based on templates in order to be able to define any library specification with a free number of parameters and their values. A library may include several cells and set of parameters for each behavioural model implemented in the simulator. We have initially created two libraries. The first one consists of a group of basic cells called HALOTIS-CELLS, and is used mainly for testing purposes during the simulator’s development; and another library corresponding to a real of 0.35pm technology from the Austria Mikro Systeme foundry (AMS) called AMS-035.

192


In a similar way, we also define a template system for simulation algorithms that greatly facilitates the inclusion of new behavioural models. There are currently two behavioural models implemented in the simulator: the traditional Inertial Model and Inertial and Degradation Delay Model (IDDM) proposed in this book. By including both models we will be able to explore the IDDM benefits by comparing to conventional models, which is the objective of the next two chapters of this book. Besides the above mentioned particular requirements, we are also aware of general requirements that any large software system should fulfil. These are:

A structured and flexible design of the code so that it can be easily extended and maintained. This is especially important in an experimental tool that will develop as new research provides better models and algorithms. A fast operation is essential in a simulation tool. This will affect the programming language selection, since it should support optimization and provide an efficient compiled code. It is also desirable that the system run in a variety of hardware/software platforms in order to be able to scale from personal computers to powerful workstations.

6.5 HALOTIS Design and Modelling In this section we will present an architectural and modular view of HALOTIS using the UML methodology. We will first introduce a modular view using use case diagrams and then we will go into the structure of individual modules using object models.

6.5.1 HALOTIS use case diagrams

Figure 6.1 should be considered the top-level use case diagram of HALOTIS in which main tasks are depicted: netlist creation, library creation, simulation and models and the handling of algorithms. Netlist creation


193

Fig. 6.3 Simulation use case diagram.

and edition is done using a conventional plain text editor, so no further description of this task is needed. Model and algorithm creation is a matter of implementing new software modules and is based on the object models explained in the next subsection. Since it is a special task done by developers we will not include use case diagrams for it here. The diagram in Fig. 6.1 may be expanded in the two use case diagrams shown in Fig. 6.3 and Fig. 6.4. The first one shows the use case diagram corresponding to simulation and related tasks while the second one corresponds to the tasks associated with cell library creation and maintenance. The simulation task is the main objective of the system and we can see that it generates the most complex diagram. This task is actually divided into four steps which are executed in a sequential order:

194


Fig. 6.4 Cell libraries use case diagram.

netlist reading, pattern reading, simulation of a given algorithm and the display of the results. The cell library creation module consists of a compiler that processes the necessary library data and generates a binary file containing information for each cell that will be used by the simulation core at run-time. The content of this binary file will be discussed in the following section.

6.5.2 Object models

This section presents the internal structure of the different modules in HALOTIS by using object models following the UML notation. These object models consist of a set of classes that will be mapped to a source code during the implementation phase. Through the proposed object models, we should obtain an architecture that is able to adapt to several simulation algorithms, therefore, we will try to generalize as much as possible the degree of functionality of each class we define. For this reason, we may define some objects or data elements that are not used by current algorithms but are available for future developments. A good starting point to describe the object model is the set of classes related to cell library operations, since these classes will be used by most of the application’s modules. Figure 6.5 shows this set of classes and their


195

+Write()

1 -Name

out -Name

.

1

1 -Expression

Assignable Model -Delay

DegradationModel -Degradationparameters

ConventlonalModel -InertialParameters

Fig. 6.5 Object model related to cell library operation.

relationships, including their main attributes (prefixed by “-”) and procedures (prefixed by “+”). Class names designate the elements that we want to represent. One of the most interesting points in this diagram is the way it includes the parameters of the behavioural model: it consists of a ternary relationship that takes place between one output node, one input node and a given behavioural model. This way, each cell output has a set of behavioural model parameters for each possible input of the cell. Another class that requires special attention is TreeNode, which holds the logical expression to calculate the value of the cell output. Logical expressions are stored in a tree form. From an abstract syntax describing the logical expression, a set of classes is generated representing any logical expression in tree form making its calculation fast and easy. Figure 6.6 shows object model for logical expressions and its abstract syntax. The other important set of classes is related to the simulation process. These can be clearly divided into static elements that persist unmodified during the simulation process, and dynamic elements that are constantly created and destroyed as simulation runs. Static elements are represented by classes associated to the circuit’s netlist. These classes are shown in Fig. 6.7, which should be extended with other classes in Fig. 6.5 through

196


#Ri(ht

1

TreeUnaryOp

TreeExp

#Index : int

TreeLteral

TreeOperatorNot

(a) ~-

Equation:: s : out i e : exp out:: index : integer exp:: lit : literal

I e:

in

I left : exp ; op : opb ; right : exp I op : op-u i e : exp I e : exp literal :: value : boo1 in :: index : integer op-u :: not op-b :: and I or I nand I nor I xor 1 xnor 1

Fig. 6.6 Logical expressions: a) object model, b) abstract syntax.

the class Cell, shown in a grey background. With this structure, the netlist is described by two groups: one of logical cells and another one of wires. Both groups link together to form the circuit, that is to say, the wires are associated with the input and output nodes of the gates, making the circuit. Each gate is actually a cell of the library that will use the corresponding logical and dynamic behavioural model during simulation.


197

Fig. 6.7 Object diagram showing the static elements of the simulation.

z

I

Takeplace

*

1

1

Fig. 6.8 Object diagram showing the dynamic elements of the simulation.

On the other hand, the so-called dynamic elements are depicted in Fig. 6.8. During simulation, HALOTIS distinguishes between what we call events and transitions to model the circuit’s dynamic behaviour. This

198


V

vddh

-

I I

I I

. . I I

1 1

@ Rise transition @ Fall transition @ Incomplete transitions

vddl

f=x

t=x+TI t=y t=y+T2

z

Fig. 6.9 Transitions examples.

is done in order to be able to implement the new inertial effect handling method presented in Sec. 3.4.2. The simulation process generates events from transitions dynamically and destroys them when they have been processed and new transitions have been generated. The transition is a simple model for logic value switching in the wires of the circuit. Transition from 0 to 1 and from 1 to 0 are characterized through the rise and fall times respectively. Also, this approach allows us to work with incomplete transitions as may be seen in Fig. 6.9. Events, on the other hand, are the elements that guide the simulation process. Events take place at the inputs of gates when a transition reaches the logic threshold of the input, hence a single transition in a wire can generate several events in different gate inputs. When a simulation algorithm is included in HALOTIS, this algorithm will calculate a new transition for each processed event. The new transition will generate new events that will be calculated using information from the transition which generated the original event and the gate’s parameters corresponding to the behavioural model in use. Finally a class called stuts which is linked to the simulation class serves to collect and display results and statistical information about the simulation process.


199

6.6 HALOTIS Implementation Although a detailed description of the implementation of HALOTIS is beyond the scope of this book, in this section we will summarize the main aspects that drive the implementation process.

6.6.1 Implementation language and plaatform The whole system has been implemented using mainly the C++ programming language [Stroustrup (2000)l. For the implementation of common data structures (lists, array, etc.) present in the set of classes described in previous sections, the Standard Template Library (STL) [Schildt (1999)l has been used. The STL is freely available to any C++ development environment and is recognized as a mature, well documented and efficient set of functions. The lexical analysers and grammar parsers used for the netlist and test pattern input are also implemented using the standard and widely available toolsflex and bison from the GNU project2. These tools generate both C and C++ code. GNULinux has been used as the development platform for the project and it should compile and run without modifications on any UNIX-like operating system. Although it has not been tested, it may also compile and run on MS-Windows operating systems provided that GNU tools are available, except for the graphical output. The system is fully implemented using free software libraries and tools so future maintenance and availability is assured. The project itself will be released as free software once it is sufficiently stable and mature.

6.6.2 Intermediate formats A number of binary intermediate data formats are used throughout the operation of the system. These intermediate formats correspond to: http://www.gnu.org

200


Netlist: once a netlist is parsed and errors have been checked, a binary data file containing a direct representation of the memory data structure is saved. Test patterns: in a similar way, input test patterns are checked and compiled in a binary data file. Library cells: behavioural models of the library cells are mapped onto an internal tree structure as described in the previous section. This is also saved as a data file for later use. The purpose of using these binary formats is to improve simulation performance. Parsing, error checking and compiling are costly tasks. These intermediate formats allow us to run these tasks only once. For example, once a netlist and library are compiled and binary formats saved, the designer may run several simulations without having to recompile the netlist or library models, so that if only the set of test patterns is changed, previously compiled netlist and library information will be used and simulation setup time will be greatly improved.

6.6.3 Simulation core

As may be expected, the simulation core is the most important and complex part of a logic-timing simulator. While a simulation process is running, two main tasks are executed in each simulation cycle: calculation of the behavioural model equations and event handling. It is thus critical to optimize these tasks in order to achieve a good performance. The time spent in the calculation of the behavioural model equations will depend mainly on the complexity of these equations. In order to improve the calculation time, model equations are compiled only once into the tree structure described in Sec. 6.5.2. These compiled expressions are part of the optimized library cell’s intermediate format mentioned in the previous section. As mentioned before, HALOTIS is an event-driven simulator. The event and the transitions-handlingmechanism is common to every behavioural model. Simulation is driven by the events present in the event queue, which are ordered in an ascending time fashion. New events are


20 1

inserted and old ones removed constantly in the event queue. In order to optimize these operations, the event queue is implemented using a binary tree. These data structures have the important property of a low and predictable insertion and removal time. This time is in the order of logyz, where n is the number of elements in the tree.

6.6.4 HALOTIS tools

The HALOTIS system is actually a set of software tools that can be run separately, allowing individual tasks to be run and tested independently. In the following we include a list of these tools along with a short description:

hparser reads a netlist in a hardware description language (currently, Verilog) and generates an intermediate compiled format that will be used by the simulation core. Syntax errors and inconsistencies are reported. hcells generates a compiled version of a library of cells, including cell parameters and behavioural models. hmatchta pre-processes input patterns in Matchta format and generates the corresponding intermediate binary format. halotis runs the simulation core. Netlist, cell library and input patterns need to be previously compiled using the above mentioned tools. hnetlistdump extracts an already compiled netlist to a higher level format. This is used mainly for error checking and debugging. hcelldump extracts a library file previously compiled using hcells. The output is the same one used by hcells, so it may be compiled again. It is also useful for error checking and debugging. hwaves is a graphical tool for plotting the simulation results generated by halotis.


Chapter 7

DDM Simulation Results Manuel Jesus Bellido Diaz Paulino Ruiz de Clavijo Ezquez

7.1 Introduction The previous chapter was devoted to presenting the implementation of the HALOTIS logic timing simulator, whose main characteristic is that it implements the DDM model and the new inertial effect algorithm which were presented before. In that chapter we focused on presenting the technical characteristics of HALOTIS, its general structure, the simulation motor, and analysed its performance from the point of view of software application (speed in the generation of results, consumption of computer resources, etc.). In this chapter, though, we are interested in analysing the performance of HALOTIS from the point of view of the quality or reliability of the results it provides. Although these results depend to a certain extent on the technical characteristics of the tool, they basically reflect the precision of the delay model used in the simulation. That is, in this chapter we shall analyse the precision of the DDM model together with the inertial effect algorithm. In order to carry out this analysis we shall develop a series of simulations using both the DDM model as well as the CDM model (see the previous chapter), and we shall compare these results with those obtained from the HSPICE electrical level simulator. The comparison with HSPICE will allow us to quantify the precision of the DDM model (the results from HALOTIS-DDM). The comparison with HALOTIS-CDM

203

204


will in turn allow us to determine to what extent precision increases when degradation is included in the logic timing simulation. To realize this task we have selected two different data banks. The first one consists of a set of circuits of low complexity, while the second one is made up of the circuits that are part of the benchmark ISCAS85 [Bryan and Fujiwara (1985)l. These circuits are generally of a greater complexity than the ones belonging to the first bank, that is, they have a greater number of digital components and a greater number of inputs and outputs. With the first bank of circuits we intend to analyse the precision of the DDM comparing the waveforms of the signals generated by the different types of simulation. However, in the case of the ISCAS85 circuits, due to their greater complexity, we will not analyse the signal waveforms but will rather concentrate on studying in depth the treatment that the different types of simulation give to the generation, propagation and elimination of glitches, with the switching activity as the parameter used to indicate this behaviour. This study is of great importance because the switching activity of a circuit is a parameter used in various phases within the optimization process of a digital circuit. Specifically, in the estimation of power consumption and even in the estimation of switching noise, so that a precise measurement of switching activity would contribute to a design process with greater chances of success. Since each analysis of the behaviour of the DDM model on each circuit test bench is sufficiently extensive, we shall divide the results into two chapters. This first one will be devoted to the results of the first test bench and the next one will analyse the switching activity in the circuits of the second test bench. In this chapter, the circuits to be analysed are selected so as to describe clearly the capacities and possibilities of the DDM with respect to the waveform of the signals. They can be classified into three groups, each of which will have its own section within this chapter: Pulse propagation through multiple gate levels, the simplest case of DDM application, which also illustrates the basic capabilities of the model. (see also Fig. 3.16).

205

Chapter 7. DDM Simulation Results

out1 in

out2

v-

out3

v"

Out4

v-

out5

v-

out6

v-

out7

v-

Fig. 7.1 Inverter chain for the modelling of an active route in a multilevel combinational circuit.

Simulation of ring oscillators, showing how this type of oscillator is affected by the degradation effect since they operate at high frequencies, and also to what extent the DDM makes it possible to improve the estimations of oscillation frequency. Application to the characterization of oscillatory metastability, showing the capacity of the model to handle situations and phenomena beyond the reach of conventional logic models.

7.2 Pulse Propagation

The most direct application of DDM is the study of the propagation of relatively narrow pulses through the different levels of a combinational circuit. In this section a chain of inverters is used (Fig. 7.1) to represent a possible active route in a multi-level combinational circuit, and a study is made of the propagation of three different excitations: 9

9

An isolated positive pulse A train made up of four equidistant pulses A train of four pulses with a small timing separation between the first and the last pairs of pulses.

Each simulation will be carried out in three different ways: using the DDM, using the delay model without degradation (CDM), and using the HSPICE electrical simulator.

206

Logic-TimingSimulation and the Degradation Delay Model

in out1

out2 out3 out4

out5 out6

out7 0

500

1000

t (PS)

Fig. 7.2 Simulation of an isolated pulse. Results from HSPICE.

7.2.1 Isolatedpulse

Figure 7.2 shows the results of an HSPICE-simulation of the propagation of a narrow pulse passing through the different gate levels of the circuit from Fig. 7.1. The first thing to remark is the qualitative aspect: the pulse is degraded each time it passes through a gate level, and is finally eliminated at a certain point of the chain. This same result is obtained in the simulation with DDM (Fig. 7.3), yielding, as with HSPICE, a propagation of the input pulse up to the fourth level, from which point it is filtered. The result of the model without degradation (Fig. 7.4) is, however, completely different since it propagates the pulse in an unchanged way throughout the entire chain 1. At the quantitative level, we have compared the pulse widths at each level, as obtained from the three types of simulation. The widths are

207


in our1

out2 out3 our4

outs out6 out7

Fig. 7.3 Simulation of an isolated pulse. Results from the DDM.

in

out1 out2 out3 out4 out5

our6 out7 0

500 (PSI

Fig. 7.4 Simulation of an isolated pulse. Results from the CDM.

1000

208

Logic-finzing Simulation and the Degradation Delay Model

Table 7.1 Simulation of a pulse. Comparison of the width pulse.

Node

HSPICE

DDM

CDM

in

151.5

151.5

151.5

out1

137.4

144.07 (4.9%)

148.2 (7.9%)

out2

116.1

126.5 (8.6%)

149.3 (28%)

out3

82.78

108.8 (32%)

148.2 (79%)

62.89

149.3

out4 out5

148.2

out6

149.3

out7

148.2

measured according to a voltage threshold V D D / 2 and the results are shown in Table 7.1. The widths obtained with DDM show a marked reduction in each stage, maintaining a good degree of precision with respect to HSPICE except for the last stage, in which the pulse is strongly degraded and the model begins to lose precision. Nevertheless, both HSPICE and the DDM eliminate the pulse from that moment on, so that the precision of the result is completely recovered. As for the CDM, it loses precision rapidly with each level since, as has been mentioned, it does not modify the width of the pulse and provides a result completely different from the real one.

7.2.2 Train of equidistant pulses Here a simulation is made of the propagation of a train consisting of four uniformly spaced pulses through the same circuit seen before. Figure 7.5 shows the results obtained with HSPICE. We can observe that the train is smoothed when it crosses the different gate levels, propagating clearly until the second level and showing a strong degradation in levels three and


209

in outl out2 out3 out4

out5 out6 out7

0

500

1000

1500

2000

(PS)

Fig. 7.5 Simulation of a train of equidistant pulses. HSPICE results.

in outl out2 out3 out4 out5

out6 out7

t (PS)

Fig. 7.6 Simulation of a train of equidistant pulses. DDM results.

210


in out1

our2

out3 out4 out5

out6 out7

Fig. 7.7 Simulation of a train of equidistant pulses. CDM results.

four. From the fifth level on the train degenerates to a single pulse of a width practically identical to that of the full initial train. The results obtained with the DDM (Fig. 7.6) are practically identical, and they even reproduce quite exactly the three small glitches which appear in line out4 as a result of the strong degradation which has taken place in the train up until that moment. As occurs with HSPICE, the train of pulses degenerates into one single pulse of a width comparable to that of the initial train, from the fifth level on. In Table 7.2 some data measured from the curves in Figs. 7.5 and 7.6, are compared, showing the level of agreement between both the degree of precision reached by the DDM. This example and the one presented in the next subsection, are clear examples of how the DDM can handle the evolution of high frequency waveforms properly. By way of comparison, Fig. 7.7 shows the results obtained without considering the degradation effect. Since all the pulses of the train have a sufficiently large enough width to surpass the threshold imposed by the inertial effect, the complete chain propagates without alterations through-

21 1


Table 7.2 Simulation of a train of equidistant pulses. Comparison of train widths and pulses at the different gate levels in the different types of simulation. The error refers to a percentage of deviation with respect to HSPICE.

HSPICE

DDM (error%)

Train width in in

1255

1255 (0%)

Train width in outl

1256

1254 (0.2%)

Train width in out7

1256

1252 (0.3%)

Single pulse at level

5

5

in

outl out2 Out3

out4 out5

out6 Out?’

t (PSI

Fig. 7.8 Simulation of a pulse train with a timing separation. Results from HSPICE.

out all the levels, yielding, once more, a result completely different from reality. Here, too, a simulation is made of a train of four pulses, but a small timing separation is introduced between the first and second pair of pulses. The results from HSPICE are shown in Fig. 7.8. One can see how the smaller pulses in the chain have become significantly attenuated already at the first gate level and, barely appreciable at the second level,

212


in out1

out2 out3 Out4

Out5

out6

out7

t (PS)

Fig. 7.9 Simulation of a pulse train with a timing separation. Results from the DDM.

may practically be considered to be eliminated from the logic point of view. Thus, the original pulse train appears at the exit as a pair of relatively wide pulses separated by a small intermediate pulse. Again, the results obtained with the DDM, shown in Fig. 7.9, are practically identical to the results from HSPICE in all the nodes of the circuit, with a significant initial degradation in the first level and the emergence of the resulting pair of pulses from that moment on. In Table 7.3 a comparison is made of the data on the pulse train width measured on the curves in Figs. 7.8 and 7.9, showing a good level of agreement between HSPICE and the DDM. The results obtained without applying the degradation effect, shown in Fig. 7.10 present a behaviour similar to that of the previous examples: the propagation of the pulse train occurs without alterations, producing a behaviour qualitatively different from the real one.


213

Table 7.3 Simulation of a pulse train with a timing separation. Comparison of train widths and pulses in different circuit nodes for the various types of simulation. The error refers to a percentage of deviation with respect to HSPICE.

Data

HSPICE

DDM (error%)

Train width in in

1200

1200

Train width in outl

1200

1197 (0.25%)

Train width in out7

1202

1197 (0.42%)

Pulse width 1 in out7

497.9

518.3 (4.1%)

Pulse width 2 in out7

584.7

497.2 (15%)

in outl out2 Out3

Out4 out5 out6 out7

Fig. 7.10 Simulation of a pulse train with a timing separation. Results from CDM.

214


Fig. 7.1 1 Sample ring oscillators. a) Simple oscillator, b) Oscillator with an out-buffer.

7.3 Ring Oscillator Frequency Another example which shows the benefits of taking into account the degradation effect is the simulation of ring oscillators and the determination of their oscillation frequency, especially when these oscillators are made up of short chains and present a high oscillation frequency. In this section we shall analyse the two oscillators which appear in Fig. 7.1 1. The first one is a simple oscillator made up of three inverters and the second one is practically the same circuit except that it has been given an out-buffer so as to reinforce the signal. Figure 7.12 shows the waveforms obtained with HSPICE in each node of the oscillator of Fig. 7.1 1, and how the signals in the different nodes have an amplitude below the polarization voltage V,, . This fact makes it reasonable to expect that each transition in the oscillator will be propagated with a certain factor of degradation and, consequently, with delays slightly shorter than the normal propagation delay (without degradation). This phenomenon will affect the oscillation time, calculated as: n

(7.1) i= 1

making it shorter with respect to the one expected when the degradation effect is not considered. In this section we shall simulate and obtain the oscillation times (and the frequency) of the two oscillators of Fig. 7.1 1, comparing the results of

215


5

in1

0

5

out1

0

5

out2

0 0

1000

2000

3000

4000

t (PS)

Fig. 7.12 Simple ring oscillator simulation. Results from HSPICE.

the DDM with those from HSPICE and with those of the model without degradation.

7.3.1 Simple oscillator Figure 7.13 shows signal in1 obtained from the simulation with the DDM and with the CDM. At first glance it is difficult to notice any differences

216


in I

in1

I . . . . . . . . . , . . . . . . . . . I . . . . . . . .

0

1000

2000

3000

. 4000

t (PS)

Fig. 7.13 Waveform in node in1 of the simple ring oscillator. a) Results from the DDM, b) results from the CDM.

because here the degradation is weak and one has to resort to measurements such as oscillation time to appreciate the difference. Table 7.4 shows the times and frequencies measured in the three types of simulation, along with the error in the logic simulations with respect to HSPICE. As expected, the model without degradation slightly overestimates the value of the oscillation time. The difference is small, though, and is within the degree of precision expect of a logic simulator, which explains why the degradation effect has gone unnoticed, even when ring oscillators were used to validate conventional delay models. Still, we see how the


217

Table 7.4 Simple oscillator simulation results: Cycle time and frequency.

HSPICE

CDM

DDM

Cycle time(ps)

420.2

428.9

419.8

Frequency (GHz)

2.380

2.332

2.382

Error with respect to HSPICE

0

2.1

0.1

(%)

Table 7.5 Oscillator with out-buffer simulation results: Cycle time and frequency.

HSPICE

CDM

DDM

Cycle time(ps)

611.7

705.5

648.8

Frequency (GHz)

1.635

1.417

1.541

Error with respect to HSPICE

0

15.3

6.1

introduction of the degradation effect corrects this overestimation and improves noticeably the precision of the results. A more evident improvement can be seen in the next example.

7.3.2 Oscillator with out-buffer

In this case we shall simulate the oscillator in Fig. 7.1 1 (b), similar to the previous one, but will include an out-buffer. The buffer affects the oscillation frequency by introducing an additional capacitive charge into node inl, and it also influences the effect that the degradation effect has on the results. Figure 7.14 shows the curves obtained in node in1 for the three types of simulation. At first glance, one can see how the additional charge produces a greater degradation in the signal with respect to the previous example, so that a greater incidence of the degradation effect in the value of the oscillation time may be expected. In the Table 7.5 a comparison is made of the results obtained in terms of oscillation times and frequency.

218

Logic-Enzing Simulation and the Degradation Delay Model

in1

in1

(b)

. . . . . . . . . . . . . . .. .. I

I . . . " . ' . , . .

I

.

.

.

I

.

.

.

.

.

.

.

in 1

I .........I......... 0

1000

I

.........

2000

3000

.

.

.

.

..I 4000

(PS)

Fig. 7.14 Waveform in node in1 of the ring oscillator with an outbuffer. a) Results from HSPICE, b) results from the DDM, c) results from the CDM.

Here we can see how degradation affects the values obtained much more obviously than in the previous example. Now the overestimation of the model without degradation reaches 15%, an error which may not be disregarded. The DDM, however, corrects the result significantly, reducing it to 6%, bringing it within an acceptable margin for a logic simulation. In this specific application (estimation of oscillation times) conventional models provide results which are correct from the qualitative point


219

S

Fig. 7.15 a) RS-NOR latch. b) Time skew. c) Puke width.

of view, but we have shown that the incorporation of the degradation effect can significantly improve the precision of the results obtained.

7.4 Metastable Behaviour

The phenomenon of metastability in a flip-flop consists in its operation either around an unstable equilibrium point, or by switching (oscillating) between stable states for an indeterminate period of time, theoretically infinite, before reaching a definite logic state. In the working field of metastability, it is convenient to define first a set of terms: the marginal input conditions or critical triggering conditions of a flip-flop (or a circuit in general) are the input signals that cause the metastable operation of any of its signals. Taking an RS-NOR latch as an example (Fig. 7.15 (a)), two critical triggering conditions can be found [Kacprzap and Albicki (1987)l:

220


Simultaneous change of R and S signals. A narrow pulse (glitch) in any input. Such a pulse is not wide enough to change the stored state in the flip-flop immediately. The critical triggering conditions must be quantified by means of a convenient parameter. Thus, the time skew (g) is used for the simultaneous change of R and S, measuring the time elapsed between the falls of R and S. Normally, the initial time reference is taken at the change of R, so that g is positive when S changes after R, and negative in the opposite case (Fig. 7.15 (b)). In the case of a narrow pulse input, pulse width (T,) is used (Fig. 7.15 (c)). For each RS-latch there is a range of g values (T, values) which causes metastable operation. This region of critical triggering conditions is called the marginal window (also glitch window or aperture). As previously mentioned, there are two types of metastability [Reyneri et al. (1990)]: a) analogue metastability, when the output signals ( q and settle to an indefinite logic level, with a voltage value near the threshold of the gate as shown in Fig. 7.16 (a); and b) oscillatory metastability, when output signals, q and switch repeatedly between both logic levels as shown in Fig. 7.16 (b). The first type of metastability relates to the existence of an unstable equilibrium point in the V , - V q plane, where the system can remain stable for an indeterminate amount of time [Bellido (1994)l. The second type, oscillatory metastability, “occurs when the loop delay, TL (the sum of propagation delays of the gates and the delay stages) is higher than a critical value” [Reyneri et al. (1990)l. This type of metastability is typical in flip-flops with long delay stages in the feedback loops: long interconnection lines, PLA implementations of n-stable devices, gate coupling after a buffer (flip-flops built from spare gates), etc. Consider an RS latch with long propagation delays in the loop as shown in Fig. 7.17 (a); a narrow pulse whose width is less than the loop delay will propagate through the entire loop and reach the first gate to propagate once again. Thus, oscillation appears at the output as shown in Fig. 7.17 (b). This oscillation persists until the pulse is filtered by the gates in the loop. The pulses are eliminated by the degradation they suffer

4)

4,


22 1

V(R)and V(S)

0

5E-8

1E-7

t(s)lSE-7

(4 -. -...- -

..

Fig. 7.16 Metastable behaviour. a) Analogue type. b) Oscillatory type.

in each gate; consequently, a good analysis of oscillatory metastability would require models that account for the degradation effect. In every case of analogue and oscillatory metastability indecision arises at the output state that remains during a resolving time (t,), after which the flip-flop settles in a stable logic state. The resolving time depends on the characteristics of the flip-flop and the input timing. A measurement of the resolving time as a function of the input timing ( g or

222

Logic- Riming Simulation and the Degradation Delay Model

R

4

S

Fig. 7.17 RS-NORlatch exposed to oscillatory metastability.

TJ gives a quantitative view of how metastable operation affects the behaviour of the circuit. In the case of oscillatory metastability, the number of oscillations before reaching the final state can be used as an alternative to the resolving time.

7.4.1 Simulation results This section shows the capability of the DDM to simulate the oscillatory metastable operation. This is done by comparing the simulation results obtained from the logic simulation of the DDM with those obtained by using the circuit simulator HSPICE, for the set of flip-flops in Fig. 7.17. For the sake of completeness, we also show what is obtained from a delay model which does not take into account the degradation effect, only the inertial effect. This model will be referred to as a CDM. All flip-flops studied are RS-latches built out of NAND gates. Similar results are obtained using NOR gates, which are omitted due to lack of space. Additional inverters are used in the loop to operate as the delay

223


-

4

S

R

4

Fig. 7.18 Flip-flops under analysis. a) RS-latch with 2 inverters per branch. b) RS-latch with 4 inverters per branch. c) Asymmetric RSlatch.

stages needed for the flip-flop to show oscillatory metastability. We have chosen three different types of flip-flops. The first two are symmetric latches with 2 and 4 inverters per branch, respectively (Fig. 7.17 (a) and Fig. 7.17 (b)), The third is an asymmetric latch with 2 inverters in one branch and 4 in the other (Fig. 7.18 (c)). To carry out the different types of simulation, delay parameters for each gate have been characterized for both the DDM and the CDM, through delay measurements from HSPICE. Particular gate conditions (output load, input slope, etc.) are taken into account.

224

Logic- Rming Simulation and the Degradation Delay Model

Metastability is hlly characterized by plotting the resolving time (or number of oscillations) versus the time skew (g) in the case of simultaneous input change, or pulse width (Tw)in the case of narrow input pulse. In this section, the number of output oscillations (n) has been chosen. Figure 7.19 shows these curves as obtained with HSPICE, the DDM and the CDM. The first thing to notice in Fig. 7.19 is that the curves from HSPICE and the DDM are qualitatively (and also quantitatively) very similar, while CDM curves only reflect two kinds of behaviour: no oscillation or an infinite number of oscillations. This conduct is directly derived from the analysis of models that do not take into account the degradation effect, which only consider pulse filtering through an inertial effect or otherwise through normal, non-degraded, propagation. Thus, if a pulse is propagated through the entire loop the first time, it will propagate indefinitely. With respect to HSPICE and DDM curves, a range of infinite oscillations has not been obtained in any case. At most, a single extrapolated value for the input timing parameter which would correspond to an infinite number of oscillations could be extracted. This value separates two regions of different behaviour, corresponding to opposite logic states reached after the oscillatory phase. In both regions, the number of oscillations rises from the edges to the centre of the plot, as input timings become more and more critical. It is also interesting to notice that for the asymmetric latch and a simultaneous change critical timing (Fig. 7.19 (e) and Fig. 7.19 (0) the plot is not centred around the g=O point as in the symmetric latches. The same figures show that the DDM gives basically the same results as HSPTCE with a high degree of agreement. An especially interesting parameter is the marginal window width which defines the range of input timing in which one or more oscillations take place. Table 7.6 and Table 7.7 show the measurements of the marginal window widths for the three models and both cases are under analysis. Results using the DDM are very close to HSPICE measurements, within 10% in most cases. It is worth noticing that a CDM may be used with some degree of accuracy just to determine the marginal window width but, as stated above, it fails to account for more than one output oscillation.


8.0

n

6.0

1: 4.0

2.0

0.9 'X

Fig. 7.19 Number of oscillations vs. marginal triggering for various RS-NAND latches. a) Symmetrical short loop delay latch. b) Symmetrical long loop delay latch. c) Asymmetrical latch. All times are measured in ns.

225

226


Table 7.6 Location and width of marginal window. Simultaneouschange: g-marginal window edges and window width

CDM

DDM

HSPICE

Sym. short loop

(-0.04,0.04) 0.08 (-0.25,0.25) 0.50 (-0.25,0.25) 0.50

Sym. long loop

(-0.70,0.70) 1.40 (-0.81,O.Sl 1.62 (-0.75,0.75) 1.50

Asymetric

(-0.05,0.70)0.75 (-0.28,0.86) 1.14 (-0.25,0.85) 1.10

Table 7.7 Location and width of marginal window..Narrow pulse.:T,-marginal window edges and window width.

CDM

DDM

HSPICE

Sym. short loop

(0.30, 1.31) 1.01 (0.58, 1.45) 0.87

(0.65, 1.35) 0.70

Sym. long loop

(0.56,2.40) 1.84 (0.64,2.63) 1.99 (0.6-1.0, 2.5) 1.5-1.9

Asymetric

(0.56, 1.75) 1.19 (0.64, 1.98) 1.34

(0.6-1.0, 1.95) 0.95-1.35

Chapter 8

Accurate Measurement of the Switching Activity Carmen Baena Oliva Manuel ValenciaBarrero

8.1 Introduction In this book, up until now, several aspects about timing behaviour have been presented. This chapter is devoted to a specific application, the switching activity measurement in a digital circuit. Switching activity is not a timing measurement but it measures the number of transitions Lowto-High or High-to-Low that occur in the nodes of a circuit during its operation. Evaluating the switching activity in CMOS digital circuits is a key point to calculate their power consumption [Ghosh et al. (1992), Monteiro et al. (1994)l. Low power design is a very important topic in a significantly high percentage in the integrated systems which are implemented nowadays. One only needs to observe the very high number of portable systems existing today (PCs, mobile phones, digital photo and video cameras, etc.), as well as bioelectronic systems or space applications. All of them have the same main problem, power consumption, which must be reduced as much as possible. In the design process of these kinds of systems it is fundamental to use tools that estimate energy consumption and allow us to select the design with the lowest consumption. Most of the estimation tools of energy consumption in digital circuits use switching activity as the most fundamental parameter. The reason is that the two main sources of power consumption in CMOS VLSI circuits, the one due

221

228


to switching and the other due to the short-circuits, are generated when a signal changes from low to high or high to low. Also, in mixed-signal circuits, the switching activity of the digital part creates a switching noise which is transferred to the analogue part [Aragonks et al. (1999); Allstot et al. (1993); Tsividis (1995)]. The switching noise is the cause of failures in mixed-signal A/D circuits, so it is really necessary to be able to analyse carefully the effects of the switching activity in the digital parts. Furthermore, as digital circuits become faster and larger, the influence of glitches in the switching activity grows because there are more and more input collisions [Melcher et al. (1992); Metra et al. (1 995); Eisele and Berthold (1995); Bellido et al. (2000)l. Thus, evaluation of switching activity is today a major topic in the design process of both purely digital, and mixed-signal integrated circuits. Now, it is our goal to establish methods of measuring switching activity in an accurate, reliable and sure way and with reasonable computational costs. Measuring switching activity in a digital circuit concerns three important questions: the first one is how to determine the representative input stimuli which must be obtained in order to obtain an accurate estimation of the switching activity. The second one is concerned with the timing simulator. In the timing simulation of digital circuits, standard gate-level logic simulators (such as Verilog [Verilog (1999)l) are able to handle very large circuits and are commonly used by circuit designers. Otherwise, accurate evaluation of the switching activity is possible by using electrical simulators (such as HSPICE [Hspice (1999)]), but these simulators are limited to rather small circuits, they spend a great deal of computational resources, and are not used in a typical digital design flow. The third issue focuses on the origin of logic transitions in the nodes of the circuit. Input changes cause two types of logic transitions. First, proper operation generates functional transitions and second, the generation and propagation of spurious transitory signal pulses (glitches) causes non-functional transitions. The basic method to estimate power consumption at logic levels consists in obtaining a final value by summing up the power contribution of each node every time it makes a transition. It is thus necessary to calculate the total number of transitions in the circuit besides the use of a power model to estimate the consumption at each node. In this chapter, we dem-

Chapter 8. Accurate Measurement of the Switching Activity

229

onstrate that switching activity can be greatly overestimated when calculated with conventional logic simulators such as Verilog. This overestimation is mainly due to an inaccurate propagation and elimination of glitches, which happens regardless of the model used among those provided by the foundry, or of the inclusion of post-layout information. We will then introduce the application Halotis in order to reduce that overestimation. This Chapter is organized as follows: the first section, Section Eq. (8.2), deals with the method used for switching activity computation applied to ISCAS’85 benchmark circuits. In the following sections we present the measurements based on a standard logic simulator in Section Eq. (8.3), as well as those based on an electrical simulator in Section Eq. (8.4) and then we analyse and compare the results of both simulators in Section Eq. (8.5). The measurement of switching activity using Halotis is summarized in Section Eq. (8.6). Finally, in Section Eq. (8.7), we draw some conclusions on the evaluation of switching activity.

8.2 Selection of the Testing Environment We are interested in finding a procedure which lets us measure accurately the typical switching activity in a digital circuit. Basically, the procedure would consist in selecting the stimuli and the analysis tool to be used, and counting the transitions in order to obtain their typical value. Initially, we will use two kinds of simulators: logical and electrical. Our final goal will be to establish which one must be used. There are three main aspects which must be emphasized in order to achieve our objective: 1) Choosing an adequate set of circuits to try out the procedure, obtain data and draw some objective conclusions; 2) Establishing how to select the stimuli to be used in the simulations in order to achieve an adequate trade-off between an accurate result and the effort to obtain it (CPU time). We are not referring to the type of simulator to be used but only to the selection of the stimuli, because of the high input-pattern dependence on the switching activity inside a circuit [Najm (1994)l. Besides, generally, the number of input vectors to be used

230


cannot be complete so we will have to determine how to select the most adequate subset of input vectors. 3) The switching activity in a circuit depends on the circuit behaviour, the treatment of the collisions and the generation and propagation of glitches. The latter also depend on how they are modelled in the simulator and the circuit architecture. In relation to the first point, we decided to illustrate the method using the ISCAS’85 benchmark circuits [Bryan and Fujiwara (1985)l. The main reasons for that selection is that, on one hand, they are considered standard circuits, readily available. On the other hand, they are very different one from the other according to the function they implement. In addition, they offer great diversity in the number of inputs and outputs. They vary from very simple circuits with very few terminals to circuits with a very high number of terminals. And, finally, because the number of levels inside a circuit is another important characteristic that has a considerable effect on the transitions of the signals along the different levels in the circuit, in that set of circuits we have examples with varying degrees of depth. In the following Table 8.1, we specify the circuits which are considered as giving the details each one has such as number of inputs, outputs and number of gates. Once the selection of the test circuits has been considered, we go on to the second point, the selection of the stimuli used in simulations. Switching activity inside a circuit is highly input-pattern dependent [Burch et al. (1993)], thus, simulation results are directly related to the specific input patterns used. A direct approach consists in simulating the circuit using long-enough input vector sequences in order to obtain meaningful power estimations but these techniques cannot be used for large circuits. Other approaches simplify the problem by specifying the typical behaviour of the inputs circuit using probabilities [Cirit (1987), Najm (1991)l. These techniques are known to be slightly dependent but it is necessary to consider correlations among internal node values in order to get good accuracy obtaining the power estimation of the circuit. Then, a trade-off between accuracy and speed must be established. A third alternative approach can be considered and it will be the one selected in our study. This technique combines the accuracy of simulation-based approaches with the weak pattern dependence of the probabil-

Chapter 8. Accurate Measurement ofthe Switching Activity

23 1

Table 8.1 ISCAS85 benchmark circuits.

no. of inputs

no. of outputs

total gates

c432

36

7

160

c499

41

32

202

c880

60

26

383

c1355

41

32

546

c1908

33

25

880

c2670

233

140

1193

c3540

50

22

1669

c5315

178

123

2307

c6288

32

32

2416

c7552

207

108

35 12

istic approaches. It is considered a statistical method and consists of applying random input patterns to the circuit and calculating power estimation by using a simulator. The idea is based on a Monte-Carlo method [Burch et al. (1993)l. The simulation is continued until a value of the power is obtained with a desired accuracy having used a finite number of random input patterns. In our work, the two main objectives when selecting a set of input patterns are to generate an “average” switching activity and to use a number of patterns that is small enough to limit the costs of computational resources. The method described in the following paragraphs accomplishes both objectives and a scheme of it is represented in Fig. 8.1. First of all, we run several Verilog simulations using 1000 random input patterns and get the number of transitions in the whole circuit for each sequence. We could verify that for such a number of random patterns, similar global switching activity was obtained (within 2%) for any set of patterns, thus, the result is an average measure of the switching activity in the circuit. After that, for each previous simulation the number of transitions per input vector was calculated (SA-i). Then, the mean value of all measurements is taken as a standard value for the switching activity of the circuit (SA-1000).

232


several logic simulations with 1000 random patterns

I switching activity per stimuli, SA-i

SA-1000

Fig. 8.1 The procedure to obtain the average measure for the switching activity.

Secondly, we look for a sequence of input patterns short enough to be used even for large circuits and representative, in the sense that it makes it possible to obtain a good power estimation value. To do this we follow the process shown in Fig. 8.2. We simulate the circuit several times using only 50 random test vectors to look for a set of input patterns which generate a number of transitions per stimuli within the 3% of the mean value previously determined. Thus, these 50 random input patterns represent a generic input case and are not expressly selected for obtaining good results. This set of fifty vectors is then used to obtain the switching activity using logic and electrical simulators and, then, both results can be compared counting the exact number of transitions on all of the nodes in the circuit after having applied the exact set of stimuli. Besides, the reduced size of the set of input vectors lets us decrease significantly the computational time when running electrical simulations on medium-large sized circuits. At this point, we have the benchmark circuits and the stimuli to be used in the different simulations, so now we show what kind of tests are going to be held.


233

switching activity per stimuli, SA-50

Fig. 8.2 Procedure for obtaining a representative and adequate input sequence.

Specifically, we want three types of measurements of switching activity in a circuit, 1) hnctional 2) pre-layout and 3) post-layout. First we want to obtain the switching activity of the circuit due to the logic function itself, removing the contribution of the glitches. To do that, we run the simulations using a zero delay model for all the gates in the circuit. So in this case we obtain the switching activity in the circuit as the response to the input vector, avoiding the effect of the number of levels of gates inside a circuit. After that, to obtain the pre-layout value for the switching activity, the simulation is done using for each gate the delay model the simulator uses as default. In our case, the inertial delay model where each module has a delay with three different values named minimum, typical and maximum. We then have a value for the switching activity which is considered a normal operation of the circuit, i.e. taking into account the glitches that may appear after the application of the stimuli because there may be some very close transitions within the same input or the different branches and levels inside the circuit that can generate spurious pulses. And finally, the third measure, post-layout, will be the one obtained after considering the parasitic effects in the gates, the post-layout effects, which involve a change in the delay of the modules so that they may affect the final result.

234


In the next two sections we will show the procedure for obtaining all these measurements; in Sec. 8.3, the results obtained through the use of a logic simulator, as well as with an electric simulator in Sec. 8.4.

8.3 Measurement of the Switching Activity Based on DFWII

In this section, we compare different measurements of switching activity in a circuit using a logic simulator. Verilog [Verilog (1999)] is the simulator chosen because of its standardization. A scheme of the measuring procedure is presented in Fig. 8.3. We start with a description of the circuit, provided by the ISCAS85 benchmark document [Bryan and Fujiwara (1985)l. This description must be translated to another format suitable for the design environment, Design Framework11 (DFWII) in our case [DFWII (1999)l. To do this translation, a software parser has been written using the PEFU language [Wall et al. (1 996)]. The parser takes the original description of the circuit as supplied with the set of benchmarks, and produces the corresponding Verilog netlist. The parser also needs a simple mapping library which assigns the proper cell for the current technology to each logic operator. In our case, circuits are implemented in an AMS CMOS 0.35pm technology. Once the circuit description is loaded in DFWII, we start with the logic simulation using the timing information of each cell and the Verilog standard simulator. Verilog uses an ideal gate model (i.e.the delay is zero) or an inertial delay model, as mentioned before. We begin with the zero delay model for each gate in the circuit. The results of this simulation provide a measurement of the minimum switching activity required by the logic functionality of the circuit. No glitch effects may be included. We will note this result as Ntransz,,. Then, to obtain the pre-layout result, the three values for the delay, min, typ and m a , can be used. From the results of this simulation the global number of transitions (i.e. all of the nodes in the circuit, Ntrans) is computed. These will be named Ntrans,i,, Ntrunstyp and Ntransmax, respectively. In order to do this, we have developed a program, Log-


235

benchmark circuit

DFWII

P&R

V

A1

/*/-

A=O

Ntransz,,

Fig. 8.3 A scheme of the method for switching activity computation using a logic simulator.

Count, which scans the Verilog output and returns the number of logic transitions in each node, as well as the total number of transitions. Finally, we want to consider the effects of routing on each node in order to have a more realistic description of the circuit. To this end, we used the Silicon Ensemble tool and following an automatic process we get

236


the layout of the circuit. We thus obtain a new set of delay values for each node which includes the wire effects and new capacity values. After that, we run another logic simulation using this new information and, following the same procedure we used before for the logic simulation Fig. 8.3, we obtain the number of logic transitions in each node, as well as the total number of transitions, which is named NtranspOstla,,. The whole previous method will be applied to ten of eleven ISCAS85 benchmark circuits (circuit c17 was too simple to be considered in our study) in order to compare the switching activity obtained with logic simulation including pre- and post-layout against the intrinsic switching activity (zero delay). For each benchmark, the number of transitions for the simulation of 50 test vectors (using Verilog considering two delay models) is shown in Table 8.2. The NtransZerocolumn shows the results for the Zero delay columns show the model, and the Ntransmin,Ntransqp and Ntrans,, results for minimum, typical and maximum inertial delay model values for each gate. Table 8.2 Number of transitions using 50 input vectors.

Circuit

NtransZero Ntrunsfin Ntrans,,,

Ntrans,,, ax

c432

3637

4719

4735

4753

c499

4868

6423

6417

6421

c880

7707

11353

11337

11331

c1355

10420

16318

16190

15990

c1908

18465

32393

3241 1

32441

c2670

26279

45095

44979

45029

c3540

28799

6 1044

60920

60376

c5315

48899

100589

100295

100327

c6288

44378

421909

418815

416729

c7552

76315

174682

174292

174062

Finally, in order to be more realistic doing logic simulation, in the “post” column of Table 8.3 we show the number of transitions obtained

237


after considering the parasitic effects in each node using minimum, typical and maximum delay for the gate. Furthermore, in the “pre” column of Table 8.3, the results obtained before the layout are included again in order to compare them to the new ones. In the “%” column we show the percentage of { (per-post)/per} value. The analysis of results obtained in the two previous tables will be presented in Sec. 8.5. Table 8.3 Number of transitions pre/post-layout.

.-s

Ntransmi,

Y

2

Ntrans,,,

Ntrans,,,

‘ij

pre

post

%

pre

post

%

pre

post

%

c432

4719

4499

4.7

4735

4505

4.8

4753

4511

5.1

c499

6423

5937

7.6

6417

6260

2.4

6421

5977

6.9

c880

11353

11495

-1.2

11337

11493

-1.4

11331

11485

-1.3

15990

15297

4.3

16318

15447

5.3

16190

15383

5.0

~ 1 9 0 8 32393

32976

-1.8

32411

32880

-1.4

32441

32782

-1

~ 2 6 7 0 45095

50122

-11.1

44979

50106

-11.4

45029

50072

-11.2

~ 3 5 4 0 61044

61465

-0.7

60920

60979

-0.1

60376

61005

-1

~ 5 3 1 5 100589

108587

-7.9

100295

108441

-8.1

100327

108015

-7.7

c6288

421909

365702

13.3

418815

362870

13.3

416729

361019

13.4

c7552

174682

166908

4.4

174292

166806

4.3

174062

166709

4.2

c1355

8.4 Measurement of the Switching Activity Based on HSPICE

The other procedure considered for measuring switching activity is based on HSPICE simulation. This result is accurate and will be used as a reference in our next comparison. For this purpose, we need first of all to translate the same stimuli used before in the logic simulations into piece-wise-linear functions for each input in the circuit, to use them in the electric simulation. In this way, we avoid the possible changes in the results if we use another set of input vectors because of the high interdependence between the stimuli in a circuit and the transitions in its nodes. Manually translating the input vectors to PWL format is not feasible and this functionality cannot be found in

238


Description of the

I ooeration-to-cellI

A VERILOG netlist

DFWII HSPICE description

HSPICE

Fig. 8.4 A scheme of the method for switching activity computation using HSPICE.

the design environment. Hence, a general-purpose program that translates Verilog vectors to SPICE PWL format has been developed to generate the appropriate stimuli. On the other hand, we need an HSPICE netlist of the circuit, but this one is obtained from the verilog netlist in DFWII. These stimuli joined to the HSPICE netlist are all the necessary data for the HSPICE simulator. The scheme of the procedure followed is presented in Fig. 8.4. The files generated with these simulations become the input of a software program, Elec-Count. This program is dedicated to counting the

Chapter 8. Accurate Measurement of the Switching Activiy

239

number of times each node in the circuit crosses the Vdd2 voltage. The final result is the switching activity for the whole circuit and is noted as NtrunsHSpICE. The whole method will be applied again to all nine ISCAS85 benchmark circuits, in order to get the “accurate” value obtained with HSPICE. The result of the simulation, NtrunsHSpICE,is included in Table 8.4. Table 8.4 Number of transitions using 50 input vectors.

Circuit

NtransHSPICE

c432

4517

c499

6196

c880

11033

c1355

13960

c1908

25873

c2670

38655

c3540

52303

c5315

79803

c6288

194784

c7552

144535

8.5 Comparison between DFWII versus HSPICE Measurements

In this section, we want to emphasize some conclusions drawn from all the previous logic and electrical simulations. Beginning with the logic simulation, if we analyse Table 8.2 and compare minimum and maximum delays with the typical delays, we see that the number of transitions does not increase (nor does it decrease) uniformly while we look through the minimum, typical and maximum values in the delays (Table 8.2). In fact, in some cases, for example in circuit c880, the number of transitions using the minimum value for the delay is larger than the result obtained using a typical delay, and this one is larger than the maximum delay. However, in other cases, for example c432 or

240


c1908, the opposite occurs, and in other benchmarks the number of transitions for minimum and maximum values are larger than for the typical value delay, i.e. c499 or 15315. In relative numbers, in all of the cases, the differences in the total number of transitions comparing minimum with typical and maximum with typical is less than 1%. Therefore, to take into account the three different values for the delay has very little effect on the final result of the switching activity in a digital circuit. We also want to show how unreliable logic simulators are when considering the transitions in each node in the circuit. To do this, in Table 8.5 we represent the relative error between Ntrunstyp and NtrunsHSPICE Table 8.5 Relative errors in relation to NtransHSpICE.

Circuit

%errAl-HSp %erraro-Hsp

c432

4.8

19.5

c499

3.5

21.4

c880

2.7

30

c1355

16

25.3

c1908

25.2

28.6

c2670

16.3

32

c3540

16.5

45

c5315

25.7

38.7

c6288

115

77.2

c7552

20.6

47.2

(%errAl-Hsp)and the relative error between Ntranszero and NtrunsHSPICE (%errZe,,-Hsp). From these numbers some conclusions can be drawn in two ways. On the one hand, the relative error between Ntranstyp and N t r ~ shows n ~the inaccuracy ~ ~ ~ in ~the logic ~ ~simulation (Ntrunstyp)in comparison to the “reality” (Ntr~nsHSpIcE).From the results in Table 8.5, it can be seen in the %errAl-Hspcolumn that in each example, the relative


24 1

error between Ntranstypand NtransHSPICE varies between 3% for c880 and 115% for c6288, It is important to emphasize the result in the case of c6288 because of the huge error that can be produced by logic simulation. On the other hand, when we compare NtransZeroto NtransHSPICE, we observe that a high contribution to the switching activity is due to the glitches generated and propagated inside the circuit. In all cases, the contribution of the glitches is between 20% and 50%, except for the case of c6288 for which this contribution is even greater than 77%. This high result is due mainly to the size of this circuit and especially to the high number of levels (123, [Rabe et al. (1998)l) that the circuit has. In general, activity due to glitches has a remarkable contribution to the overall switching activity. Thus, we should emphasize the great importance of adequately handling glitch generation and propagation effects by timing simulators so that, in all of the examples there is at least one glitch for every five transitions and in the case of c6288 they reach 77% in the global activity. Another result we want to point out is the post-layout effect. In Table 8.3 we show the number of transitions obtained after considering the parasitic effects (capacity and wire effects included) in each node using minimum typical and maximum delay for the gate and we compare them to the results obtained previously before layout. For the three values of the delay we can say that the relative deviation between pre- and postlayout is not very significant, less than 10% except in the case of c2670 (11%) and in the case of c6288 (13%). As we said for Table 8.3, in some of the circuits the error is positive and in other examples it is negative. In addition, in Table 8.6 we present the relative error in the number of transitions after a logic simulation having used post-layout typical delays versus HSPICE simulation'. Generic conclusions drawn are similar when we compared the results with the pre-layout logic simulation (Table 8.5). The simpler circuits (c432, c499 and c880) have a relative error which is really close to the HSPICE value, but in others the difference can reach 86%, as in the case of c6288. It is important to notice that there are cases in which the post-layout results are worse than the pre-layout ones. Indeed, Unfortunately, for this technology, the necessary data to run post-layout electrical simulation was not available.

242

Logic-Ening Simulation and the Degradation Delay Model

although c6288 decreases its relative error from 115% (pre-layout) to 86% (post-layout), in the case of c2670 the change is from 16.3% (pre) to 29.6% (post) making the post-layout worse than the pre-layout result. After analysing the results presented in Table 8.2 and Table 8.3, we can conclude that, in general, the post-layout information does not improve the computation of the switching activity when using logic simulators because these deviations are much more insignificant than the ones obtained when we compare the logic results to the electric ones. Thus, post-layout values do not guarantee an accurate measurement of the switching activity. The overestimation measured by logic simulaTable 8.6 Relative errors, number of transitions post-layout vs HSPICE.

Circuit

c432

%err

postlay-Hsp -0.2

c499

1

c880

4.2

c1355

10.2

c1908

27.1

c2670

29.6

c3540

16.6

c5315

35.9

c6288

86.3

c7552

15.4

tors persists even when minimum and maximum values are used and postlayout effects are taken into account. The greatest variation between m i d max is 1% and between pre- and post-layout is 13%. Both deviations are much smaller than the average value of the overestimation comparing logic and electric results. Hence, logic simulators are neither precise nor reliable at measuring switching activity. This is due to the fact that they are not accurate at simulating glitch propagation.


243

The results obtained in the different tables make us conclude that Verilog simulation is not an appropriate way to measure switching activity in a circuit accurately. This is so for two main reasons, the first one being that the relative error can be very high in some cases: in the case of circuit c6288, the result is not valid at all; and the second one is the great variation in the percentage among the different examples which makes the results for the switching activity unreliable in comparison to HSPICE. Finally, in Table 8.7 we show the approximate amount of CPU time spent in each simulation. From these results we can point out the wellknown conclusion that electrical simulators are limited to rather small circuits because their cost is high in computational resources and CPU time. These kinds of electrical tools are restricted to critical parts of a digital circuit. Table 8.7 Simulation CPU time.

VERILOG simulation

CPU time (s)

CPU time (s) HSPICE simulation

c432

6.4

2714

c499

7.2

8087

c880

8.3

15240

c1355

8.3

2841 1

c 1908

9.9

83989

c2670

16.7

260106

c3540

14.8

722935

c5315

24.1

1518849

c6288

34.2

836644

c7552

31.3

4577727

From these results it can be concluded that the deviation in the power consumption estimation of a circuit obtained from logic simulators is derived from the overestimation in the switching activity. Thus, the way to improve this result with these kinds of tools is to achieve a more accurate switching activity estimation through the use of new delay models

244


with a better treatment of glitch generation and propagation [Juan et aZ. (2OOOb)l.

8.6 Accurate Measurement of the Switching Activity: A HALOTIS Application Finally, in this section we face a new measurement of the switching activity using HALOTIS, the new simulator presented in a previous chapter. Following the same procedure used with Verilog and HSPICE, we will take the same set of ISCAS85 benchmarks and the same set of stimuli in order to make the comparison of results afterwards. A scheme of this procedure is shown in Fig. 8.5. The first step consists of extracting the files of the standard cells in HSPICE format which will be used in the benchmarks. To do this we follow an automatic process with the DFWII tool. After that, from those files we obtain some parameters such as the geometry of the transistors and, using the AUTODDM and AUTOTPN tools and following an automatic process, we obtain all the parameters needed for the Inertial Degradation Delay Model (IDDM) which will be used by the Halotis simulator for each cell to represent the timing response of circuit. Then, with all the parameters obtained, a Halotis Cell Library Text File is created. This file also includes the capacities, geometry and the logic equation for each cell. After that, this file is compiled by the Hcell tool of the Halotis simulator and finally, a binary file is generated with all the information of the cells library. On the other hand, when we did the simulttions of the benchmarks using Verilog we already had the verilog description of each circuit. Now, taking that file as an input to the Halotis Verilog compiler, a tool called Hverilog, we obtain a second binary file. This tool checks the syntaxes of the Verilog file using the cell library to verify that each cell is defined in the library and also to check the connections between modules. Finally, the set of stimuli in Verilog format is easily converted to Machta format using DFWII. Then, with another tool of the Halotis simulator called Hmachta we obtain the third binary file with the Halotis patterns.


I I

I

245

I I I

I

I I I I I I I I I

I I I I

I I

Halotis cells Library

I

I I I

process

1

I I I I I

I I I

Verilog benchmark

Halotis cell compiler (Hcy)

I

Machta pattern file

Halotis cell library

I I

I I I I

I I I I

I I I I I I I

I I I

(Hmachta)

J. Halotis patterns

Halotis verilog compiler (Hverilog)

e l L4 Halotis C.U.T. binary file

I

HALOTIS

I

Simulation process

Fig. 8.5 A scheme of the method for switching activity computation using HALOTIS. (C.U.T.: circuit under test).

I I I I I I I I I I I I I I I I I

I

246


Once we have the three binary files with the all information needed, the cell library, the description of the circuit and the stimuli, we proceed to simulate using HALOTIS. The switching activity in the different simulations for each circuit is presented in Table 8.8 and Table 8.9. In the first table, the switching activity in absolute numbers is presented. In the first column we repeat the previous result using the HSPICE simulator (for easy comparison) and the second column shows the new values for the activity called NtrunsmLOTIS.In Table 8.9 we show several relative numbers. The first column repeats the ones we presented in Table 8.5 when we compared the results after having simulated with Verilog and HSPICE, and in the other column we present the comparison between HALOTIS and HSPICE. Table 8.8 Number of transitions using 50 input vectors with HALOTIS.

c432

45 17

4599

c499

6196

5336

c880

11033

11189

c1355

13960

13948

c 1908

25873

28123

c2670

38655

36774

c3540

52303

56880

c5315

79803

81852

c6288

194784

242014

c7552

144535

146251

Analysing the results and having drawn some conclusions it can be seen that the numbers obtained with HALOTIS are very close to the ones obtained with HSPICE. Indeed, we have achieved very good accuracy. In most cases, the result with Halotis is a bit larger than the one obtained with HSPICE. In three cases, c499, c1355 and c2670, the switching activity obtained with HALOTIS is smaller. The reason for this is that with the new delay model (IDDM) some glitches generated and propagated inside


247

Table 8.9 Relative errors in relation to N t r a n s ~ ~ p ~ c ~ .

c432

4.8

1.8

c499

3.5

-13.9

c880

2.7

1.4

c1355

16

-0.8

c 1908

25.2

8.7

c2670

16.3

-4.9

c3540

16.5

8.7

c5315

25.7

2.5

c6288

115

24.2

c7552

20.6

1.2

the circuit are filtered as occurs with the real circuit but sometimes glitches are filtered before they would be eliminated in the real case. On Table 8.9 the comments are similar to the previous case. We can even say that the conclusions are drawn easily when we analyse the relative numbers between HALOTIS and HSPICE. In nearly all of the cases the percentage is less than 10%. In fact, in two cases the result is 9% and for the rest of the examples the number is under 5%. The case of c6288 is different. The relative number is 24% but considering that when we simulated with Verilog the error was 115%, we have to emphasize the huge improvement obtained with this new result. In general, these results are much better than those obtained with the logic simulator, with some others advantages such as a CPU execution time similar to the logic simulation and a precision in the result similar to the electrical simulation. In Table 8.10 we present the CPU time simulation with HALOTIS. Afterwards we show the numbers of Table 8.7. As may be seen, the new results are comparable to the ones obtained with the logic simulator. Due to the complexity of Verilog, in this case the numbers are even larger than the ones obtained with Halotis. In any case, with the new simulator, the

248


CPU time measured is very far from the one consumed with the electrical simulation, which is the main obstacle in managing medium-large sized circuits. Table 8.10 Simulation CPU time.

CPU time (s) VERILOG

CPU time (s) HSPICE

CPU time (s) HALOTIS

simulation

simulation

simulation

c432

6.4

2714

0.05

c499

7.2

8087

0.08

c880

8.3

15240

0.12

c1355

8.3

28411

0.15

c 1908

9.9

83989

0.25

c2670

16.7

260106

0.36

c3540

14.8

722935

0.44

c53 15

24.1

1518849

0.78

c6288

34.2

836644

2.02

c7552

31.3

4577727

1.35

Considering all this data, the good effect of using Halotis can be justified in two ways. On the one hand, a new delay model for the cells is used in this simulator. A model which treats the generation and propagation of glitches inside a circuit in a much better way than with the model used by commercial logic simulators such as Verilog. We thus gain much better results. On the other hand, due to the type of simulator it is, it follows an event-driven process of simulation, the speed in obtaining the switching activity in a circuit is significantly increased, which is the greatest difficulty when using electrical simulators.


249

8.7 Conclusions

This chapter deals with switching activity estimation in digital CMOS circuits at gate level. The procedures to be used and some results of switching activity when they are measured using standard and HALOTIS simulators has been presented. We are interested in finding an accurate value of mean switching activity and quantifying functional and anomalous contributions. In order to be impartial, ISCAS85 benchmark circuits have been selected as circuits to be tested. Also, to specify test input patterns we have chosen a method that selects stimuli in order to generate an “average” switching activity and to use a number of patterns small enough to limit the cost of computational resources. Thus, the random medium length stimuli generated have been applied to the circuits being tested. As reference values, we have selected those obtained by the electrical simulator HSPICE (i.e. NtransSpICE).As a standard logic simulator we have used Verilog. With Verilog, the use of minimum, typical and maximum delay values have not produced an important effect on the switching activity measurement, which only varies around 1%. In the same way, there is a very little variation, around 5%, between pre- and post-layout simulations. These variations are little significant in comparison to the effect of glitches or the simulator’s own errors, as it may be seen afterwards. The glitch contribution to the global switching activity is given by the relative error %errzero-Hsp.Generally, activity due to glitches has a remarkable contribution (from 19% for c432 to 77% for c6288) to the overall switching activity. Thus, we should emphasize the great importance of adequately handling the glitch generation and propagation effects through timing simulators. When the results of standard logic simulation (Verilog) are compared to accurate data (HSPICE) (i.e. Ntrans vs. NtrunsHspIcE), it is observed that the overestimation of the Ntrans varies appreciably, i.e. from 3% for c880 to 115% for c6288. That overestimation persists even when minimum and maximum values are used and post-layout effects are taken into account. The greatest variation between midmax is 1% and between preand post-layout it is 13%. Both deviations are much smaller than the aver-

250


age value of the overestimation. Hence, logic simulators are neither precise nor reliable at measuring switching activity. This is due to the fact that they are not accurate at simulating glitch propagation. Indeed, HALOTIS switching activity measurements are very close to HSPICE accurate values, reducing the gap of the logic simulator Verilog by 4-to-1. This useful effect due to HALOTIS uses a good delay model (i.e. IDDM) for the cells. On the other hand, HALOTIS simulation CPU times are typical of event-driven logic level simulators. Thus, an objective and accurate estimation of switching activity in large digital circuits is suitably obtained by the methods established in this Chapter. It has immediate applications in the analysis of the energy consumption and switching noise determination. Also, as Halotis achieves the measurements with reasonable costs, it can be applied in many ways to the design of Low PowerLow Noise VLSI circuits.

References A Abramovici, M., Breuer, M. A. and Friedman, A. D., ‘Digital Systems Testing and Testable Design’, Computer Society Press, (1990). Allstot, D. J., Chee, S-H. and Shrivastawa, M., ‘Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs’, IEEE Transactions on Circuits and Systems I, Vol. 40, pp. 553563 (1993). Aragonb, X., Gonzalez, J. L. and Rubio, A., ‘Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs’, Kluwer Academic Publishers, (1999). Auvergne, D., Deschacht, D. and Robert, M., ‘Explicit formulation of delays in CMOS VLSI’, Electronics Letters, Vol. 23, No. 14, pp. 741-742 (1987). Auvergne, D., Azemard, N., Deschacht, D. and Robert, M., ‘Input Waveform Slope Effects in CMOS Delays’, IEEE Journal of SolidState Circuits, Vol. 25, No. 6, pp. 1588-1590 (1990).

B Bafleur, M., Buxo, J., Teixeira, J. P. and Teixeira I. C., ‘Physical Macromodelling of the Dynamic Behaviour of CMOS VLSI Circuits’, Elsevier Science Publishers Ltd. Microelectronics Journal, Vol. 23, pp. 599-623 (1992). Bellido, M. J., Juan-Chico, J., Acosta, A. J., Valencia, M. and Huertas, J. L., ‘Logical modeling of delay degradation effect in static CMOS gates’, IEE Proceedings-G Circuits, Devices and Systems, Vol. 147, NO.2, pp. 107-117 (2000).

25 1

252

Logic-lfming Simulation and the Degradation Delay Model

Bellido, M. J., ‘Biestables CMOS VLSI bajo entradas asincronas: Problemas y Aplicaciones’, Ph.D. Thesis, University of Seville, (1994). Bisdounis, L., Nikolaidis, S. and Koufopavlou, O., ‘Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices’, IEEE Journal of Solid-state Circuits, Vol. 33, NO.2, pp. 302-306 (1998). Bisdounis, L., Nikolaidis, S. and Koufopavlou, O., ‘Propagation delay and short-circuit power dissipation modeling of the CMOS inverter’, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 259-270 (1998). Bryan, D. and Fujiwara, H., ‘A neural netlist of 10 Combinational Benchmark Circuits and a target Translator in Fortran’, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 695-698 (1985). Burch, R., Najm, F. N., Yang P. and Trick, T. N., ‘A Monte Carlo Approach for Power Estimation’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 1, pp. 63-71 (1993). C

Casu, M. R., Masera, G., Piccinini, G., Ruo Roch, M., Zamboni M., ‘A high accuracy-low complexity model for CMOS delays’, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-455-458 (2000). Chatzigeorgiou, A. and Nikolaidis, S., ‘Collapsing the CMOS transistor chain to an effective single equivalent transistor’, IEE Proceedings-G Circuits, Devices and Systems, Vol. 145, No. 5, pp. 347353 (1998). Chatzigeorgiou, A., Nikolaidis, S. and Tsoukalas, I., ‘A modeling technique for CMOS Gates’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 18, No. 5, pp. 557-575 (1999). Chatzigeorgiou, A., Nikolaidis, S. and Tsoukalas, I., ‘Single transistor primitive for modeling CMOS gates’, Proceedings of IEEE Inter-

References

253

national Conference on Electronics, Circuits and Systems (ICECS), pp. 1553-56 (1 999). Chen, J. Y., ‘CMOS Devices and Technology for VLSI’, Englavood Clifs (New Jersey), (1990). Chow, H. C . and Feng, W. S., ‘An Analytical CMOS Inverter Delay Model Including Channel-Length Modulations’, IEEE Journal of Solid-state Circuits, Vo1.27, No.9, pp. 1303-1306 (1992). Cirit, M. A., ‘Estimating dynamic power consumption of CMOS circuits’, Proceedings of IEEE International Conference on ComputerAided Design (ICCAD), pp. 543-537 (1987).

D Daga, J. M., Turgis, S. and Auvergne, D., ‘Design Oriented Standard Cell Delay Modelling’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 265-274 (1996). Daga, J. M., Turgis, S., and Auvergne, D., ‘Analytical Timing Macromodeling for CMOS Submicronic Process’, Proceedings of XI Design Circuit Integrated and Systems Conference (DCIS), pp. 593-598 (1996). Daga, J. M. and Auvergne, D., ‘A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics’, IEEE Journal of Solid-state Circuits, Vol. 34, No. 1, pp. 42-55 (1999). Dartu, F. and Pileggi, L. T., ‘Modeling signal waveshapes for empirical CMOS gate delay models’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 57-66 (1996). Deng, A. C., ‘Piecewise-Linear Timing Modeling for Digital CMOS Circuits’, IEEE Transactions on Circuits and Systems, Vol. 35, No. 10, pp. 1330-1334 (1988). Deng, A. C. and Shiau, Y. C., ‘Generic Linear RC Delay Modeling for Digital CMOS Circuits’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 9, No. 4,pp. 367-376 (1990).

254


Deschacht, D., Robert, M. and Auvergne, D., ‘Explicit Formulation of Delays in CMOS Data Paths’, IEEE Journal of Solid-State Circuits, Vo1.23. No.5, pp. 1257-1264 (1988). Deschacht, D., Pinede, P., Robert, M. and Auvergne, D., ‘PATH RUNNER: An accurate and fast timing analyser’, Proceedings of IEEE Electronics Design Automation Conference (EDAC), pp. 529-533 (1990). Deschacht, D., Robert, M. and Auvergne, D., ‘Synchronous-Mode Evaluation of Delays in CMOS Structures’, IEEE Journal of SolidState Circuits, Vo1.26, No.5, pp. 789-795 (1991). Deschacht, D., Robert, M., Auvergne, D. and Azemard-Crestani, N., ‘Post-Layout Timing Simulation of CMOS Circuits’, IEEE Transactions on CAD ofrntegrated Circuits and Systems, Vol. 12, NO. 8, pp.1170-1177 (1993). ‘Design Framework 11. Version 4.4.3’, Cadence Design Systems, Inc., (1999).

E Eisele, V., Hoppe, B. and Kiehl, O., ‘Transmission Gate Delay Models for Circuit Optimization’, Proceedings of IEEE Electronics Design Automation Conference (EDAC), pp. 558-562 (1990). Eisele, M. and Berthold, J., ‘Dynamic Gate Delay Modelling for Accurate Estimation of Glitch Power at Logic Level’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 190-201 (1995). Elmore, W. C., ‘The Transient Response of Damped Linear Networks with Particular regard to Wide-Band Amplifiers’, Journal of Applied Physics, Vol. 19, No. 1, pp. 55-63 (1948). Embabi, S. H. K. and Damodaran, R., ‘Delay Models for CMOS, BiCMOS and BiNMOS Circuits and Their Applications for Timing Simulations’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 13, No. 9, pp.1132-1142 (1994).

References

255

F Favalli, M. and Metra, C., ‘The Effect of Glitches on CMOS Buffer Optimization’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 202-212 (1995).

G Ghosh, A., Devadas, S., Keutzer, K. and White, J., ‘Estimation of Average Switching Activity in Combinational and Sequential Circuits’, Proceedings of ACM IEEE 29th Design Automation Conference (DAC), pp. 253-259 (1992). H

Hallam, P., Mather, P. J. and Brouwer, M. ‘CMOS Process Independent Propagation Delay Macromodelling’, Electronics Letters, Vol. 3 1, NO. 9, pp. 702-703 (1 995). Hamoui, A. and Rumin, N. C., ‘An analytical current, delay, and power model for the submicron CMOS inverter’, Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1547-1551 (2000). Hernindez, A., Gbmez, L. and NGez, A., ‘Modelo analitico de la respuesta transitoria de puertas DCFL‘, Proceedings of VII Congreso de Diserlo de Circuitos Integrados, pp. 377-383 (1992). Hernandez, A., Gomez, L. and Nuiiez, A., ‘GASTIM: Un Analizador Temporal para Circuitos Digitales en GaAs’, Proceedings of VIII Congreso de DiseEo de Circuitos Integrados, pp. 53-58 (1993). Hirata, A., Onodera, H. and Tamaru, K., ‘Estimation of propagation delay considering short-circuit current for static CMOS gates’, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 45, No. 11, pp. 1194-98 (1998). Hoppe, B., Neuendorf, G., Schmitt-Landsiedel, D., ‘Optimization of High-speed CMOS Logic Circuits with Analytical Models for Signal Delay, Chip Area, and Dynamic Power Dissipation’, IEEE

256

Logic-7hing Simulation and the Degradation Delay Model

Transactions on CAD of Integrated Circuits and Systems, Vol. 9, NO. 3, pp. 236-247 (1990). ‘HSPICE User‘s Manual Release 96.1’, Meta-Software, Inc., (1996) J

Jeppson, K. O., ‘Modeling the Influence of the Transistor Gain Ratio and the Input-to-Output Coupling Capacitance on the CMOS Inverter Delay’, IEEE Journal of Solid-state Circuits, Vo1.29. No.6, pp. 646-654 (1994). Juan-Chico, J., Bellido, M. J., Acosta, A. J., Barriga, A. and Valencia, M., ‘Delay degradation effect in submicronic CMOS inverters’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 2 15-224 (1 997). Juan-Chico, J., Bellido, M. J, Acosta, A. J., Barriga, A. and Valencia, M., ‘Fully physical characterization of the delay degradation effect in submicronic CMOS inverters’, Proceedings ofXII Design Circuit Integrated and Systems Conference (DCIS), pp. 465-470 (1997). Juan-Chico, J., Bellido, M. J, Acosta, A. J., Barriga, A. and Valencia, M., ‘CMOS inverter input-to-output coupling capacitance modelling for timing analysis’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 73-82 (1 998). Juan-Chico, J., Bellido, M. J, Acosta, A. J., Barriga, A. and Valencia, M., ‘Accurate Input to Output Coupling Capacitance Modelling for Digital CMOS Inverters’, Proceedings of XII Design Circuit Integrated and Systems Conference (DCIS), pp. 368-373 (1998). Juan-Chico, J., Ruiz-de-Clavijo, P., Bellido, M. J., Acosta, A. J. and Valencia, M., ‘Degradation delay model extension to CMOS gates’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 149-158 (2000). Juan-Chico, J., Ruiz-de-Clavijo, P., Bellido, M. 3. , Acosta, A. J. and Valencia M., ‘Gate-level modeling of the delay degradation effect’, Proceedings of X I Design Circuit Integrated and Systems Conference (DCIS), pp. 537-542 (2000).

References

257

Juan-Chico, J., Bellido, M. J., Ruiz-de-Clavijo, P., Baena, C. and Valencia, M., ‘AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model’, Proceedings of International Conference on Electronic, Circuits and Systems, (ICECS), pp. 16311634 (2001). Jun, Y., Jun, K. and Park, S., ‘An Accurate and Efficient Delay Time Modeling for MOS Logic Circuits Using Polynomial Approximation’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 8, No. 9, pp. 1027-1032 (1989).

K Kacprzap, T., and Albicki, A., ‘Analysis of Metastable Operation in RS CMOS Flip-Flops’, IEEE Journal of Solid-state Circuits, SC-22 n. 1 (1987). Kayssi, A., Sakallah, K. A. and Burks, T. M., ‘Analytical transient response of CMOS inverters’, IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 39, No. 1, pp. 42-45 (1 992). Kayssi, A. I., Sakallah, K. A. and Mudge, T. N., ‘The Impact of Signal Transition Time on Path Delay Computation’, IEEE Transactions on Circuits and Systems-11: Analog and Digital Signal Processing, Vol. 40, No. 5, pp. 302-309 (1993). L

Lai, F., Rao, V. B. and Trick, T. N., ‘JADE: A Hierarchical Switch-Level Timing Simulator’, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 592-595 (1987). Lai, P. T. and Cheng, Y. C., ‘A Closed-Form Delay Expression for Digital BiCMOS Circuits with High-Injection Effects’. IEEE Journal of Solid-state Circuits, Vol. 29. No. 5, pp. 640-643 (1994). Liu, W. and Chang, M. C., ‘Transistor transient studies including transcapacitive current and distributive gate resistance for inverter circuits’, IEEE Transactions on Circuits and Systems-I: Funda-

258


mental Theory and Applications, Vol. 45, No. 4, pp. 416-422 (1998). M

‘Mach Ta User’s and Reference Manual, V3.0’, Mentor Graphics Corp., (2000). Maurine, P., Rezzoug, M. and Auvergne, D., ‘Output transition time modeling of CMOS structures’. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 5, pp. 363-366 (2001). Maurine, P., Rezzoug, M., Azemard, N. and Auvergne, D., ‘Transition time modeling in deep submicron CMOS’. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 21, Iss. 11, pp. 1352-1363 (2002). Min-Chie Jeng, ‘Design and Modeling of Deep Submicrometer MOSFETSs’, ERL Memo Nos. ERL M90/90, Electronics Research Laboratory, University of California at Berkeky, (1990). Mizco, A., ‘Digital logic testing and simulation’, Harper and Row (1986). McGeer, P. C. and Brayton, R. K., ‘Integrating functional and temporal domains in logic design’, Kluwer Academic Publishers, (1991). Melcher, E., Rothig, W. and Dana, M., ‘Multiple Input Transitions in CMOS Gates’, Microprocessing and Microprogramming, Vol. 35, pp. 683-690 (1992). Metra, C., Favalli, M. and Riccb, B., ‘Glitch Power Dissipation Model’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 175-189 (1995). Moll, F. and Rubio, A. ‘Spurious Signals in Digital CMOS VLSI Circuits: A Propagation Analysis’, IEEE Transactions on Circuits and Systems-11: Analog and Digital Signal Processing, Vol. 39, NO. 10, pp. 749-752 (1992). Monteiro, J., Devadas, S. and Lin, B., ‘A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits’, Pro-

References

259

ceedings of ACM IEEE 3Ist Design Automation Conference (DAC), pp. 12-17 (1994).

N Najm, F. N., ‘Transition density, a stochastic measure of activity in digital circuits’, Proceedings of ACM IEEE 28th Design Automation Conference (DAC), pp. 644-649 (1991). Najm, F. N., ‘A Survey of Power Estimation Techniques in VLSI Circuits’, IEEE Transactions on VLSI Systems, Vol. 2, num. 4, pp. 446-455 (1994). Nabavi-Lishi, A. and Rumin, N. C., ‘Inverter Models of CMOS Gates for Supply Current and Delay Evaluation’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 13, No. 10, pp. 1271-1279 (1994). Newton, A. R., Pederson, D. 0. and Sangiovanni-Vicentelli,A., ‘SPICE3 Version 3€3 User’s Manual’. Department of Electrical Engineering and Computer Sciences, University of California at Berkelq, (1993). Nichols, K. G., Kazmierski, T. J., Zwolinski, M. and Brown, A. D., ‘Overview of SPICE-like simulation algorithms’, IEE Proceedings-G Circuits, Devices and Systems, Vol. 141, No 4, pp. 242250 (1994). 0

Ousterhout, J. K., ‘Switch-Level Delay Models for Digital MOS VLSI’ Proceedings of ACM IEEE 21st Design Automation Conference, pp. 489-495 (1 984). Ousterhout, J. K., ‘A Switch-Level Timing Verifier for Digital MOS VLSI’. IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. CAD-4, No.3, pp. 336-349 (1995).

260


P Pierret, J. R., ‘A MOS Parameter Extraction Program for the BSIM Model’, ERL Memo Nos. ERL M84/99 and M84/100, Electronics Research Laboratory, University of California at Berkeley, (1984). ‘PSPICE Users Manual’ OrCAD, inc., (1998).

R Rabe, D., Fiuczynski, B., Kruse, L., Welslau, A. andNebel, W., ‘Comparison of Different Gate Level Glitch Models’, Proceedings of Power and Timing Modelling, Optimization and Simulation (PATMOS), pp. 167-176 (1996). Rabe, D., Jochens, G., Kruse, L. and Nebel, W., ‘Power-simulation of cell based ASICs: accuracy-and performance trade-offs’, Proceedings of Design, Automation and Test in Europe (DATE), pp. 356-361 (1998). Reyneri, L. M., del Corso, D. and Sacco, B., ‘Oscillatory Metastability in Homogeneous and Inhomogeneous Flip-flops’. IEEE Journal of Solid-state Circuits, Vol. 25. No. 1, pp. 254-264 (1990). Rubinstein, J., Penfield, P. and Horowitz, M. A., ‘Singnal Delay in RC Tree Networks’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. CAD-2, No. 3, pp. 202-21 1 (1983). Rumbaugh, V. J., Jacobson, I. and Booch, G., ‘The Unified Modeling Language. Reference Manual’, Addison Wesley, (1999).

S Sakurai, T. and Newton, A. R., ‘Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas’, IEEE Journal of Solid-state Circuits, Vol. 25, No. 4, pp. 584-594 (1990).

References

26 1

Sakurai, T. and Newton, A. R., ‘Delay Analysis of Series-Connected MOSFET Circuits’. IEEE Journal of Solid-state Circuits, Vol. 26, NO.2, pp. 122-131 (1991). Schildt, H., ‘STL Programming from the Ground Up’, McGraw-Hill, (1999). Sheu, B. J., Scharfetter, D. L. and KO, P. K., ‘SPICE2 Implementation of BSIM’, ERL Memo No. ERL M85/42, Electronics Research Laboratov, University of California at Berkeley, (1985). Shih, Y. H., Leblebici, Y. and Kang, S. M., ‘ILLIADS: A Fast Timing and Reliability Simulator for Digital MOS Circuits’, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 12, No. 9, pp.1387-1402 (1993). Shousha, A. H. M. and Aboulwafa, M., ‘A Generalized Tanh Law MOSFET Model and Its Applications to CMOS Inverters’, IEEE Journal of Solid-state Circuits, Vo1.28. No.2, pp. 176-179 (1993). Stroustrup, B., ‘The C++ Programming Language (Special 3rd Edition)’ Addison- Wesley Pub Corp., (2000). T

Tsividis, Y. P., ‘Operation and Modelling of the MOS Transistor’, McGraw-Hill, (1988). Tsividis, Y. P., ‘Mixed Analog-Digital VLSI Design and Technology’, McGraw-Hill, (1995).

U Uebel, L. F. and Bampi, S., ‘A timing model for VLSI CMOS circuits verification and optimization’, Proceeding of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 439-442 ( 1 994). Unger, S. H., ‘Asynchronous Sequential Switching Circuits’, WileyInterscience, (1969). Unger, S. H., ‘The essence of logic circuits’, Prentice-Hall International, Inc., ( 1 989).

262


V

Valencia, M., ‘Modelado discreto, descripcion logica y sirnulacion de fenbmenos metaestables en circuitos secuenciales’, Ph.D. Thesis, Departamento de Electrbnica y Electromagnetismo, University of Seville, (1 986). Vasuneda, N., ‘Timing issues in sequential circuits’, Ph.D. Thesis, Graduate Division of the University of California at Berkeley, (1993). Vemuro, S. R. and Smith, E. D., ‘Accurate delay estimation model for lumped CMOS logic gates’, ZEE Proceedings-G, Circuits, Devices and Systems, Vol. 138, No. 5 , pp. 627-628 (1991). ‘Verilog-XL Reference Manual’, Cadence Design Systems, Znc., (1999). Vladimirescu, A. and Liu, S., ‘The Simulation of MOS Integrated Circuits Using SPICE2’, ERL Memo No. ERL M80/7, Electronics Research Laboratory, University of California at Berkeley, (1980).

W Wall, L., Christiansen, T. and Schwartz, R. L., ‘Programming P E W , O’Reilly, (1996). Warmers, H., Sass, D. and Homeber, E. H., ‘Switch-Level Timing Models in the MOS Simulator BRASIL‘, Proceedings of ZEEE Electronics Design Automation Conference (EDAC), pp. 568-572 (1990). Wu, C. Y., Shiau, M. C., ‘Efficient Physical Timing Models for CMOS AND-OR-Inverter and OR-AND-Inverter Gates and Their Applications’, ZEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 9, No. 9, pp. 1002-1009 (1990).

Y Yang, H. G. and Hoburn, D. M., ‘Switch-level timing verification for CMOS circuits: a semianalytic approach’, ZEE Proceedings-G, Circuits, Devices and Systems, Vol. 137, No. 6, pp. 405-412 (1990).

References

263

Z Zukowski, C. and Chen D. P. ‘Variable Reduction in MOS Timing Models’, Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 124-128 (1988).


Index A abstract syntax 195 activity diagrams 185 AMS CMOS 0.35pm technology 234 analog metastability 220 analysis of requirements 186, 190 assignable delay models 23,27,30,33 autoddm 146

design for Low Power/Low Noise 250 Design Framework I1 (DFWII) 234 design process 1 deterministic delay models 25,26, 35 development environment 188 development methodology 182 discharge region 87 dynamic behaviour 197 dynamic delay models 17, 33,43 dynamic effects 34,43,45

B basic degradation model 161 binary tree 201 bison 199 Booch’93 183

E electric simulation 37,40,43, 68 electrical level simulator 40, 68,203, 228

C C++ programming languge 199 capacities values 236 carrier’s mobility 76 characterization 30,35,44, 138, 142, 149,155 circuit simulation 5 CMOS inverter 64 CMOS technologies 35 collisions 34,44, 134, 230 conceptualization 186 CPU time 243 critical paths 4 critical transition time 91

error estimation 165 error propagation 166, 169 error sensitivity 176 estimation of the switching activity 228 event queue 200 event-driven scheme 11,200 events 197 exhaustive model 136 extends 185

F fast input transitions 90 filtering region 59 flex 199 free software 199 functional 233 functional transitions 228 fusion method 183

D DDM (degradation delay model) 49,50, 54,67,75,203,204 degradation effect 47,214 degradation parameters 54, 56,76, 109, 140 degradation parameters matrices 136 degradation region 59 delay calculation 93, 95 delay element 14 delay models 23, 75

G gate-level 127 gate-level delay 131 gate-level logic simulators 228 gate-to-drain capacitance 99 glitch collisions 134

265

266

glitch window 220 glitches 25,27,34,45, 134,228 global analysis 186 GNU project 199 GNULinux 199 Grady Booch 183 H HALOTIS 181,186,199,203,229 HDL 188 HDLparser 188, 190 HSPICE 228 I IDDM 71,192 implementation 186 inertial degradation delay model (IDDM) 244 inertial delay model 233 inertial delay model failure 67 inertial effect 29,30,47, 50,52, 67 Inertial effect algorithm 71 input collisions 228 input stimuli 228 input transition time 142 input vectors 230 input-pattern dependence 229 input-to-output coupling capacitance 98 intermediate data formats 199 inverter 75 IOCC 98 ISCAS85 benchmark circuits 229 ISCAS85 204 isolated pulse 206 Ivar Jacobson 183

J Jim Rumbaugh 183

Index

maximum device operation frequency 64 metastability 219 metastable behavior 219,221 Meyer model 99 Miller capacitance 105 minimum-maximum delay 25 Monte-Carlo method 23 1 multi-input gates 130, 134

N netlist 191, 196, 200 non-deterministic delay models 25 non-functional transitions 228 normal propagation delay 5 1 , 81, 131, 214 normal propagation region 59 0 object design 186 object's diagrams 185 object-oriented 181 objetct-oriented methodologies 182, 183 OMT 183 OOSE 183 operator time 144 oscillatory metastability 220 output load 141 output transition time 96 overestimation 229 overshoot region 84 P parasitic effects 233 PERL language 234 piece-wise-linear functions 237 post-layout 233 power consumption 227 power model 228 pre-layout 233 propagation delay 13 pulse propagation 205 pure delay 30

L library cells 200 life-cycle 182 logic sensitizing value 133 logic timing simulation 23, 204 logic-level simulation 181

R

M marginal input conditions 219 marginal window 220 MATCHTA 190

random input patterns 23 1 ranges of interest 116 rational software 183 regions of operation 82 relative error 166

267

Index

resolving time 22 1 ring oscillator 214 rising step input delay 88 routing 235 S sensitivity 166 short-circuit current 86 short-circuit region 86 Silicon Ensemble tool 235 simplified degradation model 150, 153,

T technological parameters 76, 1 18 technology 34,36,44 temporal analysis tools 4 test patterns 200 timeskew 220 timing simulation 23, 35 timing simulator 228 timing verification tools 4 transient response 82 transitions 197,227

155

simulation 2 11 simulation of a pulse train 2 13 simulation results 203,222 simulation time 144 simulation tool 40 simulation with the DDM 2 15 slow input transitions 90 sources of consumption in CMOS VLSI circuits 227 SPICE 5 spurious pulses 233 Standard Template Library (STL) 199 static CMOS gates 127 static delay models 27 statistical delay 25 statistical method 23 1 step input response 88 switching activity 204,227 switching noise 228 system design 186

U

UML 183 unified method 183 unitary delay models 26 23 use case diagrams 184

V validation 138 Verilog 181, 190,228 Verilog netlist 234 VHDL 181,190 VLSIdesign 3 W waveform 204 weak pattern dependence 230 wire effects 236 Z

zero delay model 26,233

Logic-timing Simulation And the Degradation Delay Model

Logic-timing Simulation And the Degradation Delay Model

Model Reduction for Circuit Simulation

Polymer Degradation and Performance

Simulation: The Practice of Model Development and Use

Degradation 1

Degradation Rites

Ordinary and Delay Differential Equations

Degradation 2

Stabilization and Degradation of Polymers

The Delay of the Heart

Delay differential equations and applications

Model selection and model averaging

Model Selection and Model Averaging

Delay differential equations and applications

The Degradation of American History

Atmospheric Degradation and Corrosion Control

Advanced dynamic-system simulation: model-replication techniques and Monte Carlo simulation

Delay Differential Equations and Applications

Airline Operations and Delay Management

Advanced Dynamic-system Simulation: Model-replication Techniques and Monte Carlo Simulation

Extracellular Matrix Degradation

Applied delay differential equations

Delay in Transit

Extracellular Matrix Degradation

The Model

Delay in Transit

Applied delay differential equations

Time-Delay Systems

Microbial Degradation of Xenobiotics

The Model

Logic-timing Simulation And the Degradation Delay Model