Invention Of Integrated Circuits: Untold Important Facts (International Series on Advances in Solid State Electronics)

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INVENTION OF INTEGRATED CIRCUITS Untold Important Facts

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ASSET International Series on Advances in Solid State Electronics and Technology Founding Editor: Chih-Tang Sah

INVENTION OF INTEGRATED CIRCUITS Untold Important Facts

Arjun N Saxena Emeritus Professor & Patroon Rensselaer, USA

World Scientific NEW JERSEY

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Published by World Scientific Publishing Co. Pte. Ltd. 5 Toh Tuck Link, Singapore 596224 USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601 UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE

British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library.

International Series on Advances in Solid State Electronics and Technology INVENTION OF INTEGRATED CIRCUITS Untold Important Facts Copyright © 2009 by World Scientific Publishing Co. Pte. Ltd. All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the Publisher.

For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher.

ISBN-13 978-981-281-445-6 ISBN-10 981-281-445-0

Disclaimer: This book was prepared by the authors. Neither the Publisher nor its Series Editor thereof, nor any of their employees, assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information. The contents, views, and opinions of the authors expressed herein do not necessarily state or reflect those of the Publisher, its Series Editor, and their employees. Printed in Singapore by World Scientific Printers (S) Pte Ltd.

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Dedication This book is dedicated with love and regards to my parents, teachers, my wife (Veera Saxena) and our children and their families.

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Foreword A historically and technically accurate document about the invention of silicon integrated circuit has been the gasping hole in the literature on the history of semiconductor electronics. The fact that such an account has been lacking is not only because those participated starting some fifty years ago (1959-2008) are all still occupied, either professionally active, hence lack of time, or retired, hence also lack of time, but also that the details were hidden and tedious to collect and to discover. It is our pure luck and my ultimate delight that one of my colleagues and co-workers of that era, who had maintained contact with me all these fifty some years, just happened to be interested, if not pure hobby pastime, in the history, for years, the entire 50 years, a fact which I had not known even we have had so many technical and personal communications. In fact, Arjun Saxena has been diligently collecting evidences, through patent searches as well as continued personal contacts with those at the scene and contributed, half a century ago. So to our mutual delight when we discovered each other's hobby, we agreed that he should put his collections and analyses into a monograph, not only to share with all others but also to put the history right. It then became immediately obvious that this subject, on the history of the invention of the integrated circuits, fits perfectly the monograph series on the design of transistors and active and passive diode devices, which are the basic building blocks for the very silicon (and also other semiconductor) monolithic integrated circuits. This book is the first and only in the literature to give a technically authoritative and historically in-depth, correct account of the invention of the silicon integrated circuit, because the invention has been attributed to two inventors, each from a combating manufacturer in rivalry, eventually with compromised stipulations ruled by the judge in a settlement reached in court, compounded subsequently by popularity recognition of the U.S.Presidential National Technology Award in engineering and also the World's Nobel Prize in Applied Physics, all of which further confused the facts underlying the invention of the integrated circuits. It is hoped that this monograph puts an end to the stipulations and the reader-attracting tales about the IC invention history and its two rivalry and colorful personal-life inventors. The invention of IC is quantitative engineering technology, thus, amenable to precise solution rather than uncertain extrapolations by those without the hands-on information from personal involvement in the events of fifty years ago. This book presents the history as a detective story, by the person who was involved and was on the scene, and who has continually kept track. But at the end, also discovered discrepancies and ambiguities in the incomplete historical records, even appeared meddled intentionally, which have not been known for fifty years, and which would take further efforts using modern techniques from using the integrated circuits themselves to figure out, if at all possible, showing the superior of human intelligence in disguise, not surmountable by human-developed diagnostics techniques using the very integrated circuits themselves. But nevertheless, after reading this book, we will all have learned the documented historical truths rather than the grapevine propagated tales originated from those who had not even the vigorous semiconductor and transistor physics classroom background necessary to judge and delineate. Chih-Tang Sah (Tom Sah) Gainesville, Florida, USA September 11, and December 25,2008

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Preface The main reason I am writing this book is to get history right and set the records straight on the invention of the integrated circuits (ICs). Getting history right can be a monumental, daunting and an unrewarding task. This is especially true if the subject matter is of fundamental importance and wide popularity having direct impact on the bottom line of a huge market. The task is compounded further if its prevailing view has been misleading, and has lasted for a long time, e.g., for more than four decades in this case of the invention of ICs. Another dimension is added to its monumental aspect when world caliber and colorful personalities in highly respected institutions with impeccable records are involved in this whole saga of the mystery of the IC invention. Almost everybody in the microelectronics field involving physics, chemistry, engineering etc in the entire world appear to have accepted the erroneous information of the IC invention for more than four decades because they have done nothing so far to correct it. Nevertheless despite the daunting aspect of the task, I feel that it needs to be done because it is important to get history right. The previous accounts of the invention of ICs given by several science history writers have been erroneous. I shall give all the relevant and well documented facts to set the records straight, and get history right for the invention of ICs in this book. These facts can be verified by anybody, as it is the accepted hallmark procedure in good scientific research: any result claimed must be verifiable by independent workers. However, this book has not been written like an esoteric thesis. It reads like a mystery novel, but the intrigues and their solutions are given in an easy to read style based on well established facts. The readers will find it amazing that the real truth of the IC invention has been swept under the rug earlier by the powers to be in a manner unparalleled in the history of mankind. A capsule of the details given in various chapters is presented in this Preface. I hope that the brief discussion given below will make a compelling case for reading and enjoying this book, ix

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INVENTION OF INTEGRATED CIRCUITS: UNTOLD IMPORTANT FACTS by Arjun N. Saxena

and to learn about the facts of this historic invention which has changed mankind forever. For the sake of convenience of the readers, I shall repeat the discussions of some of the important facts and published documents in appropriate places to avoid going back and forth in this book. Since the misleading information on the invention of ICs has lasted in the literature for such a long time, it is particularly important to give credible documentation and discussions even repeatedly. This is meant to convince the readers and rectify the misinformation that has been prevailing all these 40+ years all over the world. Also those who may not be familiar with the various scientific abbreviations, acronyms and symbols, I shall repeat them a few times so that the readers will become conversant with their usage in this book. However, all the abbreviations, acronyms and symbols are also defined and listed in Appendix 6.

1. Getting History Right Why getting history right is important? Being cognizant of the yore so that the past mistakes shall not be repeated is a prudent wisdom to follow, as we forge ahead with innovations and improvements in the future. The expanded version of the adage “Those who do not learn from their elders’ wisdom and experiences, and their own past mistakes, are condemned to relive them”, has been proven repeatedly throughout the history of human endeavor including scientific research. The inspiration for the younger generation to innovate for the future is provided by the leaders of the past. If the past accomplishments are misrepresented by the spin meisters of the present, it negates this key process of progeny of innovation for the future. Those who stop innovating and stop keeping up with the critical inventions indispensable in our daily lives are left behind and destined to lose, collapse, and demise not unlike the Roman Empire. Therefore getting history right is of utmost importance and that is the purpose of this book.

2. Importance of the IC Invention Since the creation of human life and evolution of human intelligence, there has been no invention more important than the IC for the development and progress of mankind at least from the mid 20th century onwards.

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Earlier, the industrial revolution, the printing press, and the agricultural revolution also revolutionized the human life. However, even these earlier outstanding innovations have needed the enhancements enabled by the present ICs used in their control systems, without which their efficiencies and efficacies cannot be harnessed as well as it has been attained today. Almost no business can operate, and to make a bold but true statement, almost no human at least in the developed countries can carry on with their lives without an IC. Its use is indispensable worldwide in many applications (partial list given alphabetically): banking, biotechnology, communications, computers, education, entertainment, government, hospitals, internet, medicine,nanotechnology, research, travel, and in almost every commercial, defense and industrial businesses. All the electronic systems in these applications currently use Ultra Large Scale ICs (ULSICs) which are much more advanced and complex than the ICs invented originally. However, the stems of all ULSICs are rooted in the basic invention of the ICs 50 years ago. The ULSIC business has now grown to multi-hundred billion dollars annually, which is the heart and soul of the entire electronic systems market place of several trillion dollars per year. The growth of this ULSIC business and its impact on the society and newer businesses shall forever be increasing. Therefore it is important to know what were the basic inventions of the ICs, who invented them, when and how.

3. What is an IC? The details of “What is an IC?” have been given in Chapter 1 and in subsequent chapters in this book. Briefly, an IC is an electronic circuit consisting of various active (transistors) and passive (resistors and capacitors) devices integrated electrically by interconnecting them with single or multilevel metallizations delineated as thin, narrow, electrically conducting metal lines on a piece of single crystal silicon (Si). It is popularly referred to as the chip. The only kind of ICs sold from the very beginning have been the monolithic-ICs, commonly termed as just the ICs, made from Si. An exception to this statement are the microwave ICs which are hybrid consisting of Si monolithic-ICs and those fabricated from compound semiconductors. One of the technologies mandatory for the fabrication of Si monolithic-ICs is called the planar technology. The reason I am mentioning about it here in the Preface is that Jean Hoerni of Fairchild is given the sole credit for the invention of the planar technology. Even though this

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book is to correct the history of the invention of IC, it is also important to know the truth about “Who invented the planar technology?” since the ICs cannot be fabricated without it. The readers will be surprised to learn from the documented facts given in Chapter 6 that the invention of the planar technology was built upon the original work of several other people done earlier. Hoerni had combined all this information to reduce to practice the very first transistors fabricated with planar technology. Immediately after this accomplishment, Hoerni had filed and received his patents to claim the planar technology invention. The other earlier inventors and contributors of each of the basic building-blocks of the planar technology did not do anything about it and they were ignored. This is another mystery added to the saga of the invention of ICs which has been officially and popularly recognized as the invention only by Kilby and Noyce, which is the main focus of this book.

4. Sole Credit to Kilby and Noyce The sole credit for the invention of ICs has been given in the literature to late Jack Kilby and late Bob Noyce after their inventions were disclosed in their respective patent filings at the US Patent and Trademark Office (USPTO) about 50 years ago. Unfortunately this recognition accorded to Kilby and Noyce is only partially correct and justifiable. Most of the other authors on this subject have failed to appreciate the fallacy of this exclusive recognition. Indeed Kilby and Noyce did play key roles in the invention of ICs, but not quite the way they have been portrayed in the literature. For example, they have been credited in folkloric manner as if they had invented the IC all by themselves, thereby given an iconic stature by the hero worshippers. Moreover, some of the important facts have either been overlooked or not understood at all by the previous authors and those publicizing such folklore. These facts have been documented in this book. They tell an accurate but different story about the real contributions of Kilby and Noyce. The readers will find here in my book, that Kilby’s descriptions and documentations underlying the concepts of the ICs were incomplete. He had missed the key requirements which are: the devices must be connected also by monolithic interconnects adherent to the surface layers (not by gold wires bonded to the devices and flopping in the air above the chip

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which Kilby had used), and the planar (not mesa) technology must be used to fabricate and electrically isolate the devices in a piece of single crystal semiconductor such as Si. The IC concepts described by Kilby in his patents had a striking similarity to those published earlier by Dummer. Moreover, such similarity was also limited and confined only to the same incomplete and partial description of the IC concepts described independently by Dummer earlier. These points raise intriguing questions and speculations of possibly borrowing from the past and forgetting to acknowledge the previous contributor(s). Another way to express such actions is that as if surreptitious or deliberate plagiarism was done, although one cannot prove it. Similar practice appears to be popular among some of the authors on the history of ICs when they continue to condone the incorrect facts of such an important invention. Some aspects of these practices may be debatable; they can also be excused due to the vast literature and the limited human (rather than computer) search engines available in the earlier times. Kilby, however, did refer to Dummer’s concepts in his post-patent journal articles and in his Nobel speech much later (in 2000), but not in his patents filed 41 years earlier in 1959. This is called “acknowledgement after the fact”, or “post facto acknowledgement”, or “reconnaissance après coup”, or “nachtr¨ agliche Anerkennung”, or “scoperte a posteriori”, or “pahley churaya, baad mein shukriya”, or whatever in several other languages. In addition to the equivalence of the Kilby’s description of the IC concepts to that of Dummer earlier, essentially similar basic ideas were also described by Johnson of RCA and Stewart of Texas Instruments (TI), earlier than Kilby. Stewart had been working at TI for a few years before Kilby had joined TI in 1958. Kilby did not acknowledge either Johnson’s or Stewart’s concepts in his patents or papers. Of these two contributors, it is more surprising that Stewart was ignored because both he and Kilby had been working in the same company, viz., TI, at that time and Stewart’s patent was issued even exactly on the same date as Kilby’s IC patents.

5. Key Points to Get History Right The key points given briefly in the subsequent sections of this Preface are very important to get history right about the invention of ICs. They

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will become clearer after reading their details in the book. Some of them will startle and surprise many people, including the scholars. But my key objective is not to sensationalize such an important invention. I shall present the facts many of which have not been reported earlier in the literature correctly. These facts have been derived by me from Kilby’s and Noyce’s published documents such as their US patents and journal articles, and my communications with other authoritative sources such as the United States Patent and Trademark Office (USPTO), Nobel Committee members, and several other original contributors to the invention of ICs. Some of the facts are also based on my first hand knowledge of participating and contributing in the historic events from the inception of the invention by Bob Noyce to the subsequent advancement of the ICs when working in R & D at Fairchild directed by Gordon Moore, and elsewhere. The technical nature of the facts given below can be understood better by the scientists and engineers in the microelectronics field, than by the laypersons. Nevertheless even the laypersons can appreciate the significance of most of these facts after reading this book. All the readers will find that the saga of the invention of ICs is quite different from what has generally been described in the literature. It is amazing that the entire popular story of the invention of ICs has the makings of a mystery novel. But this book is based on facts, not on fiction; hopefully the readers will find it engrossing, educational and entertaining as well. In order to set the stage for this book, the key points of Kilby’s and Noyce’s inventions of the ICs are summarized at the outset. If some of them come to you (the reader, even the experienced ones in the IC profession) as a surprise, please do not get alarmed; be inquisitive with an open mind and learn from the facts given in this book.

6. Key Points of Jack S. Kilby’s Invention 6.1. Kilby did not invent the monolithic-ICs made from silicon (Si), the only kind sold from the very beginning in the microelectronics business in 1960 and onwards. (An exception to this statement is the microwave IC.) This fact was also confirmed by a Nobel Committee member in his recent written communications with me regarding Kilby’s invention and the Nobel Prize in Physics awarded to him in 2000. It will surprise particularly many

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of the diehards who are of the firm opinion that the Nobel Committee decisions to give the awards in Physics are always non-controversial. They assume that such decisions to select the Nobel Prize awardees must be based on precise incontrovertible principles of physics. 6.2. Kilby’s suggestion to fabricate multiple devices within a single piece of semiconductor was of course a key but only a small contribution. Similar suggestions had been made earlier than Kilby by other authors, e.g, Geoffrey Dummer in England, Harwick Johnson of RCA and Richard Stewart also of Texas Instruments (as Kilby was from TI too but joined TI later) right here in the USA. 6.3. Kilby’s original disclosure, issued patent(s), and reduction to practice did not specify nor use the planar technology to fabricate the devices which is mandatory for monolithic-ICs made with silicon (Si). For reduction to practice, Kilby had used mesa technology and germanium (Ge). 6.4. Kilby had used gold (Au) wires bonded to the devices made in germanium (Ge) pieces to interconnect them, flopping over the chip from one device to another to complete his IC. The monolithic interconnects to connect electrically the various devices on a chip, which should also be adherent to the insulator layers, were neither specified correctly nor used by Kilby. It was adjudged by the Board of Appeals of USPTO to be a key omission by Kilby. This fact alone, over and beyond a few other serious drawbacks in his patent(s), had cost Kilby the sole ownership of the IC invention. 6.5. Kilby’s specification for the electrical isolation of devices in a chip was mesa technology, which has never been used in Si monolithic-ICs. The monolithic p-n junction isolation process was invented by Kurt Lehovec of Sprague Electric Company earlier. Kilby lost the patent interference to Lehovec, as his claim to have anticipated Lehovec’s invention was rejected by the USPTO. 6.6. Kilby continued to regard the monolithic concept as controversial until as recently as in his 1998 IEEE Proceedings article discussing the invention of IC. There has been no controversy about the monolithic concept since the silicon (Si) monolithic-ICs were sold from the very

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beginning in 1960 and onwards. If anybody who should have been crystal clear about the monolithic concept, it should have been Kilby, because the company he had worked for, Texas Instruments (TI) was among the first to sell the silicon (Si) monolithic-ICs in the entire market at the time and soon after filing of the Kilby patents. 6.7. Kilby’s patent(s) were awarded a few years after Noyce was awarded his patent, even though Kilby had filed earlier than Noyce. The filing date of Kilby’s Original Application (OA) in 1959 appears never to have been resolved, as evidenced by the recent communications of USPTO with me in 2005 (46 years after the original filing). In addition, it appears that the laws of the US Patent code 35 USC 112 and associated protocols were possibly compromised in the procedures used by USPTO to issue the patents to Kilby, as documented by their filing dates, specifications and claims. 6.8. The quintessence of Nobel’s Will is that the Nobel Prizes shall be awarded to person(s) irrespective of nationality who, during the preceding year has (have) conferred the greatest benefit on mankind. For detailed discussions of the Nobel Prizes in Physics awarded throughout their entire history, and for the Nobel Prize given to Alferov, Kroemer and Kilby, see Appendix 7. See chapters 1 and 12 also for the technical issues related to the IC invention. Nobel Prize is not awarded in the field of Engineering. The Nobel Prize in physics 7 was awarded in 2000 jointly to Alferov, Kroemer and Kilby, and their names were listed in this order. Noyce had died in 1990; the Nobel Prizes are not awarded posthumously. Had Noyce not died, in my opinion he would have been definitely included in this award. Perhaps then the entire Nobel Prize award would have been worded and even awarded differently. The inventions of Kilby and Noyce did not involve any basic contributions to physics. However, the work of Alferov and Kroemer did involve basic contributions to physics. The Nobel Prize money was distributed as 1/4 each to Alferov and Kroemer, but 1/2 to Kilby. The citation of the Nobel Award to Kilby did not explain what was his part to invent what kind of IC? Kilby’s citation in the Prize was incomplete and inconsistent with his contribution to the purported invention of monolithic-ICs for which he was given the Nobel award. No explanation has been offered so far by the Nobel Committee

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for the vague and imprecise citation of such an important world renowned Prize. I had written communications in 2006 with two members of the Nobel Committee which was responsible for the Nobel award in Physics in 2000. To the best of my knowledge, I was the first to raise the issues of the incomplete characterization in the citation of the award to Kilby. They had invoked Nobel’s original Will, and declined to answer my questions. An aura of mystery was created in these communications because neither clarifications of Kilby’s invention nor any further recourse to get them were given. This mystery was heightened also by the refusal of Nobel Committee to explain why Kilby was given twice the amount of financial award than to each of the other two co-recipients whose fundamental contributions did involve physics? Such a monetary award was unlike the equal amounts given in the Nobel Prize in Physics awarded to Shockley, Bardeen and Brattain for their invention of the transistor earlier in 1956. Additional fact that remained unexplained was that neither the listing of Shockley, Bardeen and Brattain in 1956, nor that of Alferov, Kroemer and Kilby in 2000 had followed an alphabetical order. Most of the other 3-person recipients of the Nobel Prizes in Physics had been listed alphabetically throughout the history of the Nobel awards (see Appendix 7). The readers would come away with the impression that Shockley was the senior recipient because he was listed first, not in alphabetical order, in 1956. However, as mentioned above, from the monetary aspects of the Nobel award he was not the senior recipient because he had received equal amounts as given to Bardeen and Brattain. As discussed above, Kilby was listed as the last person in the Nobel award in 2000, not listed alphabetically. Most of the readers would know from the popular literature that Kilby’s award was for the invention of the IC. They might get the impression that Kilby being listed as the last person in the 3-person Nobel award may signify that the Nobel Committee regarded the invention of IC as less important than that the inventions in optoelectronics by Alferov and Kroemer. But the readers would not normally realize that from the monetary aspect of the award. Kilby was actually the senior most recipient because he got twice the amount of prize money than the other two recipients. These are the facts which can give confusing and misleading information to the readers about the Nobel award in 2000 and about the original intention of the Nobel

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Committee. These facts, however, do not clarify the actions of the Nobel Committee. (See Appendix 7 for details.) It is generally known that the highly revered private group of the Nobel Committee acts as a powerful closed institution which feels strongly that they do not owe any explanation to anyone regarding their choices and decisions. Without casting any aspersions on any party concerned, respectfully and punctiliously I only wish to state that the manner in which Kilby’s Nobel citation and award had been handled was quite inexplicable. My communications with the Nobel Committee and their refusal to shed light on both the citation of the award and the double amount of the financial award to Kilby, had created more intrigue to the mystery. Nevertheless one cannot obliterate the facts as published by the Nobel Committee itself and elsewhere in the literature. They are cast in concrete and therefore stated as such in this book. However I have done further research using the original Nobel website on the Nobel Awards in Physics throughout their entire history of existence. Based on my research, I can offer an explanation only for the sequence of listing of the names, and the unequal financial awards by the Nobel Committee to Alferov, Kroemer and Kilby. Such an explanation deduced by me from the facts of the Nobel Awards for the first time in the literature, has not been given by Nobel Committee or anyone else ever before. But I still cannot fathom the imprecise citation of the award and the choice of Kilby by the Nobel Committee, which remains a mystery. For details, see Appendix 7 and chapter 12. The above list may give an erroneous impression to a casual reader as if Kilby, USPTO and the Nobel Committee are being assailed. However an unbiased, knowledgeable and serious reader will find that such is not the case at all in this book. As I have stated in my paper(s) published recently, Kilby did make a key contribution to the invention of ICs, but it was only a small part of the complete invention needed. This will become even clearer after reading this book. Kilby was a great man who went on to make important contributions to other technologies thereafter, but not to the ICs after his part of the invention was allowed as patents by the USPTO. The procedures of USPTO itself used in the processing of Kilby’s applications and patents in the 1960s were circumspect if the laws of US Patent code 35 USC 112 and associated protocols are taken into account.

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The Nobel Committee consists of highly qualified people belonging to a highly respected institution with an impeccable record. But as one of my late very distinguished physicist professor, who had produced both PhDs and Nobel Laureates, had told me recently in a tongue-in-cheek manner, “You must not forget that they are also human beings who can be fallible sometimes!”

7. Key Points of Robert (Bob) N. Noyce’s Invention Most of the key points of Noyce’s invention of ICs given below are not as surprising as they have been given above for Kilby. Nevertheless some of the details of Noyce’s invention also have not been covered in the literature properly. Some of the key points of Noyce’s invention are summarized as follows. 7.1. There is no controversy about the filing and issuance of the key patent to Bob Noyce for his invention of the IC. Late Bob Noyce, or perhaps more appropriately his patent attorney, late John Ralls who was the chief architect to write his patent, says it all regarding the invention in the very first paragraph of his patent. He had specified all the key processes and materials required for fabricating the monolithic-ICs, in particular the planar technology with silicon (Si), and the monolithic interconnects of aluminum (Al) adherent to the oxide layers. He had described p-n junction isolation in his patent and it was used in the reduction to practice of his invention, but he did not claim it. I have discussed the latter point with Sah 69 and I have given the technical reasons in Chapter 6 for why Noyce may not have claimed the p-n junction isolation in his patent. Noyce’s patent describes essentially how the monolithic-ICs are still made with silicon, although most of the processes and materials used currently are much different and more advanced than those given originally. 7.2. Noyce was the top boss at Fairchild, which of course meant that everybody else including Moore, Hoerni, Last and the others were working for him. Noyce’s invention and its patent were based on the disclosure in his notebook which was not witnessed. Some of his co-workers had felt that he had usurped their contributions which had made the ICs a reality, and that Noyce had written in his notebook in a hurry to claim it all himself.

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7.3. Noyce had used Hoerni’s invention of the planar technology and Lehovec’s invention of the p-n junction isolation, but did not acknowledge them in his patent. The issue of the sole inventorship of the planar technology by Hoerni has been discussed briefly in section 3 above. To repeat, Hoerni had combined all the information from the work of the others elsewhere earlier than him and at Fairchild, several engineers and technicians other than Hoerni reduced his invention to practice, but Hoerni filed and received his patents to claim the planar technology invention. This is another mystery added to the saga of the invention of ICs by Kilby and Noyce which has also not been discussed before in the literature. However, its details are discussed in Chapter 6. 7.4 The reduction to practice of Noyce’s invention was accomplished by several others under his direction, in addition to his own contributions in the design and construction of the step-and-repeat camera. The sole credits for their respective inventions, coupled as the only two co-inventors of ICs, have been bestowed to Kilby and Noyce for all these years in the technical and popular literature. The above points regarding their invention clearly warrant clarifications of what actually their contributions were, and what did they actually invent? Much of the information perpetuated all this time for more than four decades, has been misleading and gives a distorted view of who did what? Additional incongruous events have accentuated the mystery which needs unfolding by incontrovertible documented and other facts from credible sources. 8. Other Contributors Efforts other than those of Kilby and Noyce to invent the ICs shall also be described briefly in this book. There were several other inventors and contributors who had given their concepts for the invention of ICs earlier than Kilby and Noyce. It is rather unfortunate that an accurate and a thorough account of their contributions along with Kilby’s and Noyce’s, has not been published previously by the other experts and scholars in the microelectronics industry, academia and patent law. I have published a few papers recently which give the issues and facts of the inventions of ICs by Kilby and Noyce. I could describe the roles and contributions of the others to the invention of ICs only briefly in them, because of the

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limitation in the length of my papers imposed by the publishers. However I shall describe them in more detail in this book. For example, Geoffrey Dummer in England, Harwick Johnson of RCA and Richard Stewart also of Texas Instruments (as Kilby was from there too but joined TI later) right here in the USA, had described the concept of fabricating multiple devices within a single piece of semiconductor earlier than Kilby. I shall provide appropriate documents of Dummer (published papers), Johnson (patent) and Stewart (patent) for this purpose. Even though I had published a paper in 1953 based on which I had also given the concepts for ICs independent of and earlier than Kilby and Noyce, I shall not discuss them in the main text of this book. I shall only refer to them in some relevant comparisons. However following Gordon Moore’s sage advice (see Section 11 below), I shall defer giving details of my concepts to Appendix 2 for the sake of completeness of the historical record. It provides the available documents and discusses briefly what actually my contributions were. Appendix 1 also gives a brief summary of my contributions and patents in various fields of physics and microelectronics from 1953 onwards. They will also serve as a background for where I am coming from in writing this book. I have discussed briefly in my earlier published papers why the previous writers of the history of invention of ICs may have had difficulty in giving a complete and accurate description. This is because the facts of the invention of ICs are intricately entwined technically, chronologically, and legally patent wise. To understand them, it is critical to know what are monolithic-ICs which are the only kind sold from the beginning in the IC industry, and how do hybrid-ICs differ from them. This apparently continued to be a bone of contention with Kilby even until later years in his life. The details of all the facts and their discussions are given in the various chapters of this book to unravel all the complexities. An exception to the Si monolithic-ICs which have also been sold in the recent years are the microwave ICs (e.g., in cellular phones and other products) which use both Si monolithic-ICs and ICs made from compound semiconductors packaged together by hybrid techniques. To re-emphasize, Kilby’s invention was not a Si monolithic-IC, the only kind sold from day one in the huge Si IC market. (Please note the exception

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to this in the previous paragraph regarding the microwave ICs.) Kilby’s invention was a hybrid-IC. He did give some of the concepts but only in a very limited manner which could be applicable for the monolithic-ICs. Noyce’s invention was complete but he had used others’ (Hoerni, Lehovec) inventions for fabricating the monolithic-ICs, and it was not reduced to practice by him; it was done by his co-workers. There were no irregularities in the processing of Noyce’s patents. But in Kilby’s case, there were some irregularities in the filing, processing and issuing of his patents by the USPTO. The Nobel Prize awarded to Kilby did not specify what was his part to invent what kind of IC? It is rather perplexing why all the documented facts have been overlooked so far for the past five decades by the various experts?

9. Lack of contributions of Kilby and the others to pursue monolithic-ICs Another important fact proven by the published records is that neither Dummer nor Stewart or Johnson had pursued the development of ICs further after disclosing their respective versions of the original concepts, even after Noyce’s patent disclosing the monolithic-ICs had become public knowledge. This is important, because “diligence” is one of the key factors to claim an invention. The other is “reduction to practice” which is also important but not considered mandatory. It is not required that the inventor must reduce to practice his or her original invention; it may be done by the others working with the inventor. Still another important fact is that after receiving his patents on ICs, Kilby continued to regard the monolithic concept as controversial and made little if any contributions to the monolithic-ICs. The Nobel Prize awarded to Kilby “for his part in the invention of the integrated circuit” in 2000 is rife with controversy regarding what was his part in inventing which kind of IC. To a casual reader but with the knowledge of prior Nobel Awards, the double financial awarded to Kilby than to his co-winners Allferov and Kroemer would come as a surprise. I have offered an explanation for this unequal award, even though the Nobel Committee refrained from doing so. Even more striking fact is that neither Lehovec nor Hoerni contributed to the advancement of monolithic-ICs after their respective pioneering inventions crucial for the invention of ICs were patented. To be specific, Lehovec left the Sprague Electric Company and

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became a professor at University of Southern California (USC). He obtained several patents and published several papers mostly in areas other than in advanced ICs. However, Lehovec did publish a few rejoinders to Kilby’s papers which had misinterpreted Lehovec’s claims in his patent. Lehovec essentially left the science and technology field and became a poet and a philosopher, and has published a few books on the collections of his poetry. Hoerni started a few semiconductor companies after leaving Fairchild, but they did not become major corporations such as Intel or AMD in Silicon Valley.

10. Historical Perspective and Accuracy Times and conditions change, therefore, an accurate account of the historical events in the invention of ICs necessitates that it must be given from the perspective of when they had taken place. The account should not be a descriptive hindsight or “Monday morning quarterbacking”. Of course some aspects of hindsight will benefit the narrative of the progression of events as they had occurred, but they must be documented with published records and inputs from the key participants during these events. This is not an easy task for a conventional science history writer who perhaps maybe qualified and a skillful writer, but did not live through the entire period to participate and experience first hand most if not all the events as they had occurred and evolved. This may be the reason why none of the history writers have succeeded so far to give a comprehensive account accurately. Even the fragmented accounts in bits and pieces published by several authors have not given the facts correctly about the invention of ICs. Wrong information is easy to contend with in proving their falsehoods, but misleading information is akin to half-truths and it is much more difficult to clarify and perhaps impossible to rectify its damage. Nevertheless the misleading information must be corrected and the truths must be uncovered for the sake of posterity. Our future generation must not be disillusioned about the events of the past. They must feel inspired to achieve their maximum potential and continue to make the future innovations for the benefit of mankind. The spin meisters may succeed in presenting what is white as black and vice versa temporarily, but the truth has a way to emerge eventually, especially in the technical and scientific fields. Thus, the

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very purpose of this book is to present the history from the positive point of view to document the truth of the invention of IC. For the sake of convenience of all the readers, especially the scholars, I shall give in this book some of the key original patents and papers which may not be easily accessible to some of you. I shall also analyze each claim of a few of these patents which, to the best of my knowledge, have not been published before. Nevertheless these analyses and interpretations of the claims are strictly mine, so I regret sincerely if some errors and omissions may have crept in unwittingly. Further, I shall not only give all the facts comprehensively in this book to prove unequivocally within their realm who invented what in ICs, but I shall also present a few questions at the end on the invention of ICs. Surprisingly they have remained as yet unanswered even after 48 years since Bob Noyce’s patent was issued in 1961, and the IC invention had become public knowledge. I hope that all the readers, experts and laymen alike will find the pedantic historical accounts given here to be educational and thought provoking as well. The latter is particularly interesting when one realizes that many a participant (technical contributors as well as nontechnical contributors), who have played key roles from the inception and during the progression up to the ULSICs, have remained silent rather than to publish and set the records straight earlier. The silence on the part of some may be understandable if they did not have first hand knowledge or if they were not involved directly in the various key events. I have given all the facts in this book based on the various documents I could obtain so far, which is more than ever done before in the literature. However, I will concede at the outset that some of these facts may still be incomplete. As an example, despite my best attempts to get the case history files of Kilby’s and Noyce’s patents from the US Patent and Trademark Office (USPTO), I have not yet been able to get them so far. (See Chapter 15 on Conclusion.) As it is well known, the business volume of ULSICs currently is in the range of multi-hundred billion dollars feeding into the systems market of several trillion dollars per year. Several of these participants have also parlayed and amassed huge fortunes, which is almost unparalleled in the

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entire business history of the world. It is natural for the entire society to expect them to publish and document the facts that they were privy to during these exciting years. Or they should at least speak up and correct the wrong information which had been given about the key inventions for more than four decades. But why haven’t they done so? This fact adds to the unanswered questions which are discussed in this book.

11. My Experience The readers may be curious about who am I and what are my qualifications to interpret and correct the history of one of the most important invention which has changed mankind forever? I shall describe them below briefly, and I have summarized my experience in Appendix 1. In the main text of this book, I have attempted to give all the relevant documents available for the invention of ICs by Kilby, Noyce and several others in this book, and analyze them thoroughly. For the sake of completeness of the historical record, I have also included the concepts of ICs given earlier by me. However, instead of giving them in the main text of the book, I have given the available documents in Appendix 2 at the end of this book. They have been written following the sage advice given to me by Gordon Moore, “On the part relating to your early insight you should do whatever you think is appropriate. . . . I think that your job is to distinguish your insight from what others saw as the potential.” My objective is to do just that when I give my concepts of ICs in Appendix 2. I think that it is appropriate to at least document them and give the relevant comparative information to distinguish my insight from the others, not coming as a hindsight but as it occurred originally in time and as it progressed. (See the original documents and papers in Appendix 2.) I shall quote another statement by Gordon Moore from his paper, “I had the good fortune to be part of this important chapter in semiconductor history and would like to take this opportunity to record some of my recollections.” Dittoing this statement, but more humbly, I wish to state that I was also among the lucky ones who had joined during the early years of Fairchild Semiconductor co-founded by (listed alphabetically) Julius Blank, Vic Grinich, Jean Hoerni, Gene Kleiner, Jay Last, Gordon Moore, Bob Noyce, and Sheldon Roberts. I had the distinct privilege of

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knowing them all personally. At Stanford, I had received the single crystals of Si from Texas Instruments in 1956-57 before Jack Kilby had joined it in 1958. Let me give a brief historical account of the start of Shockley Semiconductor Laboratory of the Beckman Instrument Corporation in Mt. View, CA, which is relevant to when did Bob Noyce, Gordon Moore et al start to work with Si in this laboratory. Arnold Beckman and Bill Shockley held a news conference on February 14, 1956, to announce their plans to start the lab 71 . At the suggestion of John Linvill, a professor at Stanford University, Shockley rented a dilapidated building at 391 South San Antonio Road, Mt. View. It needed a lot of work to make it suitable for the work he and his colleagues wanted to do in his laboratory. He announced at the March meeting of the American Physical Society in Pasadena that he was hiring. Shockley hired Bob Noyce, Gordon Moore, and the others rapidly. The work was started around April, 1956. Shockley Semiconductor Laboratory of the Beckman Instrument Corporation later became the Shockley Transistor Corporation. Shockley, Noyce, Moore, et al had started to use Si a few months earlier than I did. They had used it for making devices, but I had used the single crystals of Si for my PhD research in 1957 at Stanford (see Appendix 1). For whatever it is worth, I have also published in the topmost journals such as the Physical Review, Physical Review Letters, and Proc. Phys. Soc. (London), and others. I had not only participated in the exciting events originally in the Silicon Valley and later too, but I was not confined to it. I have also worked in the East Coast of US, and in Europe, and interacted with several key personnel in other countries including Japan, Taiwan and Korea. Further, I have worked in both the corporate and academic sectors of the business, and also interacted with the government sector. Therefore, I have a global perspective on the invention of ICs and their future developments.

12. Useful Product Another key observation I have is that unless an invention can be converted into a useful product, which can be commercialized successfully,

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it may be the most wonderful discovery, but at best it will be destined to remain in research journals and text books only. The inventors of the transistor won the Nobel Prize, but they were not successful to reap the harvest of their invention. However, Bob Noyce put two and two together with the invention of the planar transistor, co-invented the monolithicIC, led a highly motivated team including Gordon Moore and several others, and commercialized it. It grew and advanced rapidly into the hugely profitable business of ULSICs consisting of many successful corporations in the world. I was very fortunate indeed to have been associated with Bob Noyce, Gordon Moore and the others in the early years.

13. Funding for putting all the facts of the invention of ICs on historical record Unlike several of the other authors who have written about the Invention of ICs, I would like to state up front that I have neither solicited nor received any financial support from various sources to write this book. All of the facts presented by me about the invention of ICs in this book are well documented and available in the public domain. I have, however, also used the inputs on the invention of ICs from a few key individuals which have not been published before. In this regard, I have used my judgment and professional discretion not to disclose some of their names. However in most such cases, I have the inputs shared with me in writing, e. g., via letters and e-mails. My aim is to put all these facts of the invention of ICs on historical record, and interpret them objectively and accurately to bring out the truth as an insider to this whole saga of their birth and progression to the ULSICs. The fervent desire to get history right for the benefit of everyone: all professionals, laymen and laywomen, especially the younger generation, has helped me in overcoming many an impediment, disparaging moments, even portentous reactions and diatribe.

14. Acknowledgements I am deeply indebted to a large number of scientists and engineers, with whom I have discussed many aspects of physics, transistors, ICs, ULSICs and beyond during the past half a century from the early years to the present. They have provided me with very helpful insight, advice

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and comments. It is almost impossible to list them all. A few key ones to whom I am grateful are as follows (listed alphabetically): Julius Blank; Federico Faggin; (late) S. N. Ghoshal; Jay Last; Kurt Lehovec; Toshiaki Masuhara; Dan Maydan; Gordon Moore; Bob Norman; (late) Bob Noyce; (late) W. K. H. Panofsky; Sheldon Roberts; Chih-Tang (Tom) Sah; Simon Sze; Rob Walker. I wish to single out Tom Sah particularly to acknowledge with thanks his invitation to write this book for his ASSET series of books, and critical reading of the manuscript to affirm the accuracy of all the facts documented by me. I appreciate helpful comments on the patent and legal issues from Roger Borovoy and Gideon Gimlan. I am also grateful to my daughter-in-law, Mrs. Karen Saxena, for her help with the computer, and to my wife, Mrs. Veera Saxena, for her forbearance and support. Arjun N. Saxena Palo Alto, CA 94306 September 13, 2005

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Contents

Foreword

vii

Preface 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

ix Getting History Right Importance of the IC Invention What is an IC? Sole Credit to Kilby and Noyce Key Points to Get History Right Key Points of Jack S. Kilby’s Invention Key Points of Robert (Bob) N. Noyce’s Invention Other Contributors Lack of contributions of Kilby and the others to pursue monolithic-ICs Historical Perspective and Accuracy My Experience Useful Product Funding for putting all the facts of the invention of ICs on historical record Acknowledgments

Chapter 1:

x x xi xii xiii xiv xix xx xxii xxiii xxv xxvi xxvii xxvii

Introduction

1

1. What is an IC? 2. Key Requirements for making the IC and did Kilby and Noyce meet them? xxix

3 4

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3. Sole credit to Kilby and Noyce 4. A few facts in the mystery of the invention of ICs 5. My qualifications 6. Getting history right 7. The case of Einstein 8. Why getting history right is important? 9. Documented facts 10. What are documented facts? 11. All ICs sold from day one have been Si monolithic ICs 12. Three questions need to be answered up front 13. Victory/success and defeat/failure 14. Disclosure of the basic concept for ICs by others earlier than Kilby 15. Brief comments on the basic concepts of IC invention documented by Kilby, Dummer, Johnson and Stewart given above 16. Concepts given by Saxena in 1954 17. Inputs for Noyce’s patent and investigation of Kilby’s patents 18. Other aspects which contributed to the invention and fantastic success of ICs 19. Answers to three questions raised in Section 11 20. For whom is the book intended and at what level?

6 8 13 13 14 15 16 17 18 19 19 23

25 27 27 28 28 29

Chapter 2: Discovery, Invention, Improvement, Patents and Publications 1. 2. 3. 4. 5. 6.

Discovery Invention Improvement Patents Publications Trade secrets

31 32 32 36 37 38 39

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Contents

Chapter 3: Evolution of Miniaturization in Electronics: ICs to VLSICs to ULSICs and Beyond in the Future

41

1. Present status of miniaturization 2. Need for miniaturization and its evolution

42 43

3. When an electronic circuit is an IC?

45

4. When does a hybrid-IC become a monolithic-IC?

46

5. Fast evolution from early ICs to VLSICs to ULSICs 6. Beyond ULSICs into the future

47 52

7. Some of the advantages of 3D-Si-ICs over conventional over 2D-Si-ICs 8. Some of the advantages of UPICs over conventional 2D-Si-ICs

55

9. Future

57

Chapter 4:

54

Monolithic vs. Hybrid Concepts in ICs

59

1. Hybrid-integrated circuits (hybrid-ICs)

60

2. Where do we draw the line in hybrid-ICs to define the onset of miniaturized Integrated Circuits? 3. Monolithic-integrated circuit (monolithic-IC)

62 65

Chapter 5: Summary of the IC Fabrication, Inventions, Relevant Patent Filings and Issue Dates, and Methodology of Analyses and Numbering

69

1. Summary of IC fabrication 2. Summary of the inventions of integrated circuit by Kilby and Noyce as documented in the literature

69

71

3. Sequence of relevant patent filings and issue dates

78

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4. Comparison of the sequence of relevant patent filing and issue dates given above with that given in the earlier NSTI paper 5. Key features of Saxena’s patent #3,687,722 on interconnects 6. Controversy over public disclosures and patent filing dates 7. Additional important facts from the published records 8. Figures from Kilby’s and Noyce’s patents and correspondence from USPTO 9. Methodology of Analyses of Patents and papers, and numbering of the Tables and Figures Chapter 6:

81 82 83 84 85 92

Hoerni and Lehovec Inventions

1. Importance of Hoerni and Lehovec inventions to the fundamental invention of ICs 2. Importance of choosing Si over Ge and other semiconductors

95

95 96

3. Sequence of important technical work and serendipity which led to the discovery of planar technology 97 4. Methodology to analyze Hoerni’s and Lehovec’s patents 103 5. Quotation of key points from Jean Hoerni’s patent no. 3,025,589, “Method Of Manufacturing Semiconductor Devices” 6. Quotation of key points from Jean Hoerni’s patent no. 3,064,167, “Semiconductor Device” 7. Quotation of key points from Kurt Lehovec’s patent no. 3,029,366, “Multiple Semiconductor Assembly”

104 105

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Contents

8. Copy of the original patent no. 3,025,589 of Jean Hoerni: “Method of Manufacturing Semiconductor Devices” 9. Copy of the original patent no. 3,064,167 of Jean Hoerni: “Semiconductor Device” 10. Copy of the original patent no. 3,029,366 of Kurt Lehovec: “Multiple Semiconductor Assembly” 11. Copy of Kurt Lehovec’s paper, “Invention of p-n Junction Isolation in Integrated Circuits” 12. Copy of the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec

107 113

119 123 124

Chapter 7: Kilby’s Invention of IC: Key Patents, Claims and Analyses 1. Introductory comments on Kilby’s invention

127

2. A few important facts and comments on the invention of ICs by Kilby 3. Original Patents

130 134

4. Summary of the invention 5. Key figures

134 134

6. Key claims 7. Reduction to practice

135 135

8. Choice of semiconductor 9. Fabrication method of devices

137 138

10. Insulating layers 11. Interconnects

138 139

12. Impact of 35 USC 112

139

13. Overall comments 14. Kilby’s OA (Original Application)

140 140

15. Kilby’s Patent No. 3,138,743 16. Kilby’s Patent No. 3,138,744

152 159

127

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17. Summary of comparisons between Kilby’s two IC Patent Nos. 3,138, 743 and 3,138,744, and a few additional comments

166

18. Detailed analyses of all the Claims of 3,138,744 19. Kilby’s Patent No. 3,261,081

169 179

20. Jack Kilby: Original Application no. 791,602, “Miniaturized Electronic Circuits and Method of Making” 21. Jack Kilby: US patent no., 3,138,743, “Miniaturized Electronic Circuits”

189

22. Jack Kilby: US patent no. 3,138,744, “Miniaturized Self-contained Circuit Modules and Method of Fabrication” 23. Jack Kilby: US patent no. 3,261,081, “Method of Making Miniaturized Electronic Circuits”

220

211

226

Chapter 8: Noyce’s Invention of IC: Key Patent, Claims, and Analyses

237

1. Original patent

237

2. Summary of the invention 3. Key figures

238 239

4. Key claims 5. Reduction to practice

239 241

6. Choice of semiconductor 7. Fabrication method of devices

241 242

8. Insulating layers 9. Isolation of devices

242 243

10. Interconnects 11. Impact of 35 USC 112

244 245

12. Overall comments 13. Detailed analyses of all the claims

245 246

14. Copy of the original Patent No. 2,981,877 of Bob Noyce: “Semiconductor Device-and-Lead Structure”

252

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Contents

Chapter 9: Other Efforts to Invent and/or Contribute to the Invention of ICs

261

1. Geoffrey Dummer

262

2. Harwick Johnson 3. Arjun Saxena

267 269

4. Richard Stewart 5. Jay Last

269 276

6. Reprint of the paper presented by Geoffrey Dummer, “Electronic Components in Great Britain” 7. Reprint of the paper by G. W. A. Dummer, “Integrated Electronics Development in the United Kingdom and Western Europe” 8. Harwick Johnson, “Semiconductor Phase Shift Oscillator and Device”, US Patent No. 2,816,228 9. Richard Stewart, “Integrated Semiconductor Circuit Device”, US Patent No. 3,138,747 10. J. T. Last, “Solid State Circuitry Having Discrete regions of Semi-Conductor Material Isolated by an Insulating Material”, US Patent No. 3,158,788

278

284

298 301

305

Chapter 10: Contributions of Kilby and Noyce beyond the Invention and to Next Generation ICs

313

1. Kilby

313

2. Noyce

317

Chapter 11:

Discussion

1. Noyce’s patent 2. Kilby’s original application (OA) and patents

321 321 322

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3. Reference to patent by Kilby in his latest paper in 1998 and comments on monolithic concept

323

4. Kilby’s filing dates and recent communications from USPTO 5. Monolithic concept

323 324

6. Monolithic interconnects

325

7. P-N junction isolation 8. Importance of keeping the filing date Feb. 6, 1959 by Kilby

325 325

9. Possible compromise of the laws of US Patent code 35 USC 112 and associated protocols

326

10. Stewart’s patent no. 3,138,747 11. Were any of Kilby’s patents ever used to manufacture ICs?

327

12. Four requirements to make monolithic-ICs 13. Noyce’s invention covered all criteria

327 328

327

14. Kilby’s invention(s) met only one out of four criteria 15. A recent report in 2007 by Moss for testing Kilby’s “solid circuits” in 1960

328

16. Issues intricately entwined technically, chronologically and patent wise 17. Noyce invented the monolithic-IC

329 329

18. Copy of the original article by Jeffrey Marque, “Getting History is an Important Matter” 19. Copy of Marvin J. Moss, “Present for the Birth of the Integrated Circuit” Chapter 12:

328

330 332

Award of the Nobel Prize

333

1. Excerpt from Nobel’s Will

334

2. Highlights of the updated Nobel Awards 3. Award of the Nobel Prize for inventing ICs

335 335

4. Excerpts from recent communications by Dr. MNC-1 with me

338

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Contents

5. Excerpts from recent communications by Dr. MNC-2 with me 6. Famous United States Patents Chapter 13:

339 339

Moore’s Law

341

Chapter 14: Growth of ICs and Impact on the Quality of Human Life

349

Chapter 15: Conclusions, Combined Summary, Historical Facts and Unanswered Questions

355

1. 2. 3. 4.

Conclusions Combined summary Historical facts Unanswered questions USPTO response: File History of Kilby’s patents is lost 5. Epilogue

355 358 362 368 370 374

Appendix 1: Developments in Physics, Microelectronics and a Few Other Technologies in The Past 55 Years — Dr. Arjun Saxena’s Contributions

379

Appendix 2: Saxena Documents Regarding IC Invention, Discussions and Patents in Devices, ULSICs and Beyond

395

Appendix 3: “Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce”

419

Appendix 4: “Fundamentals of the Invention and Impact on Future Developments of Integrated Circuits and Nano-optoelectronic Devices”

435

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Appendix 5: “Transistors to ICs to ULSICs and Beyond: Impact on Various Applications to Improve the Quality of Human Life”

451

Appendix 6: Alphabetical List of Acronyms and Abbreviations Used in This Book

461

Appendix 7: History of Nobel Prize in Physics and its Award to Alferov, Kroemer and Kilby in 2000

465

1. Introduction 2. Will of Alfred Nobel

465 468

3. Updated summary of the Nobel Prize award

473

4. The field of Engineering missing from the Nobel Award list

474

5. Difficult job of Nobel Committees; example of the Nobel Prize to Sir C. V. Raman 6. History of all the Nobel Awards in Physics from the very beginning in 1901 to 2007

475 476

7. The entire list of all Nobel Prize in Physics winners to 3-person awardees from the very beginning with their citations and distributions of the award money 8. Overall comments on the sequence of listing and the distribution of the financial amounts of 3-person awardees throughout the history of Nobel Awards

486

9. Discussion of the Sequence of Listing and the Distribution of the Financial amounts in the Nobel Prize Awarded in Physics in 2000 to Alferov, Kroemer and Kilby

487

10. Conclusion

480

492

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Contents

List of References, Tables, Figures and Documents

495

References

495

List of Tables List of Figures

504 506

List of Original Patents, Applications and Papers

508

Index

513

Acknowledgement to the Publishers

519

About the Author

523

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Chapter 1

Introduction

The story of the invention of integrated circuits (ICs) is like a mystery novel. Instead of waiting until the conclusion of this book to find out “Who done it? Did the butler do it?”, a style commonly used by fiction writers of mystery novels, the readers will be surprised with the facts given even briefly in this introduction. I hope to make the readers curious in the very beginning to ask, “How could this have happened? Why nobody questioned it all along?” This should help the readers to have an inquisitive frame of mind about the mystery of invention of ICs. The mystery lies in why many facts of the invention were either ignored or twisted by the powers to be? Further, why did they succeed to mislead and convince the entire community of technologists and scientists in the world, even the patent experts of the US Patent and Trademark Office (USPTO) that the inventors invented what they actually did not, and that the inventors had used the others’ inventions to make theirs possible without acknowledging them? Why did even the Nobel Committee, which was responsible for choosing a co-winner of the Nobel Prize in Physics in 2000, accepted an invention which never was, and published his citation which was vague and inconsistent with the purported Nobel award? Why was he awarded 1/2 of the Nobel prize money, and the other two co-winners were given 1/4 each? Additional facts are that why not any of those who have achieved high fame and made huge fortunes unparalleled in the history of business ever in the whole world, have spoken up, published and corrected the mistakes in the articles in popular and technical literature and patent claims of the IC inventions? A few are donating their fortune to give back to the society 1

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graciously and generously, the others are not. The readers are privy to read about both types of such individuals in the popular literature. Many of them were intimately involved from the very beginning in various aspects of the greatest invention of mankind even before the inventions actually took place. On ethical and moral grounds as well as professionally, if anybody who had the plenipotentiary strength to uphold the truth without the fear of jeopardizing their careers and jobs, would have been these select group of people. Why did they remain silent all along? Too busy amassing fame and fortune and soaring ever higher even though the fundamental facts of the IC inventions were on cloudy grounds? Maybe or maybe not; debatable? Sounds mysterious? Yes, it sure does. Is it all fiction? No, the mystery of the invention of ICs is based on well documented facts given in this book which nobody can deny. They are all available as public records. I shall summarize some of the facts and key information of the invention of ICs in this Introduction Chapter over and beyond those capsulized already in the Preface. Their details have been given in the subsequent chapters. They are also repeated in several portions of the book for the convenience of the readers. This presentation style has been followed not only for the sake of continuity of the discussions in those places, but also to help the readers to avoid going back and forth while reading the book, a popular style also followed by many biography authors of the titans of the 20th century scientists and engineers. At the outset, I wish to let all the readers know that I have had the highest regard for both late Jack Kilby and late Bob Noyce. I had known Bob Noyce both professionally and personally for about 30 years before he died from a heart attack in 1990. I had also known Jack Kilby professionally for several years, although we had met only a few times in person before he died in 2005. In my opinion, as it is also generally known, both men did make important contributions to the invention of ICs and to the field of microelectronics, and they were very caring and decent human beings too. Therefore any critique that I shall present in this book about their work, is only to uphold the truth of the science and engineering facts, with no disrespect whatsoever to them. My main aim and the only purpose in writing this book is to get the history right based on science and engineering facts, by putting all the available facts on record. I am doing this for the

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benefit of mankind, especially the younger generations who must be taught the facts to inspire them to achieve their own highest level of attainments in their professional and personal lives.

1. What is an IC? Why the invention of IC is so important has been given already in Section 2 of Preface. Before getting mired into the details of the inventions of IC by Kilby and Noyce, it will be helpful for the readers who may not be familiar with the IC, to know at the outset what is an IC? This has been capsulized in Section 3 of Preface, but I shall explain it a bit more and its development here. An IC is a circuit consisting of various active (transistors) and passive (resistors and capacitors, and recently, inductors) devices interconnected by single or multilevel metallizations on a piece of single crystal silicon (Si). It is referred to as a chip in popular language. The only kind of ICs sold widely from the very beginning have been the monolithic-ICs made from Si. We shall exclude in our defintion and in this book the hybrid ICs in every cell phone and other microwave ICs that contain several monolithic Si ICs and transistor chips made on compound semiconductors. Therefore throughout this book, the full expression monolithic-ICs or just ICs shall be used interchangeably; the former will be expressly used when the monolithic aspect is to be emphasized. The details of what are monolithicICs, how do they differ from the hybrid-ICs, how did they evolve from the earlier electronic circuits using vacuum tubes, shall be given in subsequent Chapters 3 and 4. Also, what did actually Kilby, Noyce and the others contribute to the invention of ICs shall be given in Chapters 7–9. The fast evolution of the ICs since their invention in 1959 to the current Ultra Large Scale ICs (ULSICs) is described in Section 5 of Chapter 3. The ICs sold for the first time in 1960 had only a few devices per chip fabricated with minimum geometries measured in mils (1 mil = 1/1000 inch, or one thousandth of an inch), and they were interconnected by a single level of metalization. Now a typical ULSIC has a few billion devices per chip fabricated with minimum geometries measured in nanometers (nm), and interconnected by 8 or more levels of metalizations. To give you an

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idea of the minimum geometries involved, 1 mil = 25.4 microns or µm; 1 µm = 1000 nm; 1 nm = 10 ˚ A (Angstrom); atomic diameter = 1 to 4 ˚ A; diameter of average human hair = 50 to 100 µm. Advancements in several multidisciplinary technologies have been made to enable large volume production of ULSICs with minimum geometries of 45 nm and decreasing. Comments on Moore’s Law which has predicted remarkably well the decrease in minimum geometries and increase of devices per chip for the past 40 years, and how long into the future the densities and complexities of the ICs shall continue to increase, are discussed in Chapters 13 and 14. 2. Key Requirements for making the IC and did Kilby and Noyce meet them? Before getting mired into the details of the inventions of Kilby and Noyce, it will be helpful for the readers to know at the outset of this Introduction chapter, that the only kind of ICs sold from the beginning have been the monolithic-ICs fabricated and manufactured in large volume on single-crystal silicon (Si), except the hybrid microwave IC’s containing several Silicon monolithic ICs and Compound semiconductor IC’s which are excluded in this book to focus on monolithic Si ICs. The precise definition of the word “monolithic” will be given in Chapter 4. Although it is not easy to coalesce all the information in one-sentence, the definition of monolithic-IC can be given as: “All the devices (transistors, resistors, capacitors, inductors) required for the IC, and their electrical interconnecting conductor lines deposited and etched in narrow lines adherent to the selected regions of the devices and insulator (e.g., silicon-di-oxide) surfaces, must be fabricated on a single crystal silicon chip as an integral solid unit which is protected from the influences of the ambient.” It is a mouthful to define in one sentence. But perhaps it may be a reasonable start for a lay-person to visualize that a monolithic-IC is a small piece of silicon with all the circuitry which if tossed around, neither the devices nor the interconnecting lines fall off the chip. They are all adherent to and embedded in the chip. Throughout this book, the full expression monolithic-ICs or just ICs shall be used interchangeably; the word monolithic will be expressly used when the monolithic aspect is to

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Chapter 1. Introduction Section 2. Key Requirements for making the IC

Table 1.1. Key requirements for making the monolithic-IC and whether or not they were met by Kilby and Noyce in their respective inventions. Key requirements for making the IC (Four key parts of the requirements) 1. All devices must be fabricated in the same substrate (e.g., single-crystal Ge, Si).

Kilby

Noyce

Yes

Yes

2. Planar technology must be No used to fabricate the above devices. (planar; Si) (mesa; Ge)

Yes (planar; Si)

3. All devices must be isolated from one another by an appropriate planar technology (e.g., p-n junction, LOCOS, trench).

No (mesa)

Yes (p-n junction)

4. All devices must be connected by planar interconnections adherent to oxide surface.

No Yes (Gold wire bonds) (Aluminum)

be emphasized. The details of what are monolithic-ICs, how do they differ from the hybrid-ICs, how did they evolve from the earlier electronic circuits using vacuum tubes shall be given in Chapters 3 and 4. However, it will be helpful for the readers to have a global view of the IC inventions of Kilby and Noyce before perusing through the rest of the book. Therefore I shall first summarize the key requirements for making the IC, i.e., monolithic-IC on Si, in Table 1.1, and answer in this table the questions on whether or not they were met by Kilby1 and Noyce2 in their respective inventions and patent claims. In their respective IC inventions as shown in Table 1.1, Kilby met only 1 out of 4 criteria, whereas Noyce met all the 4 criteria. Therefore, Noyce’s invention was for the monolithic-IC, and Kilby’s invention was not; it was for the hybrid-IC. Hybrid-ICs indeed are still used today in microwave-ICs (such as those in the cell phones), using evaporated metal films adherent to insulator substrates, but not like Kilby’s initial reduction to practice in 1958 shown in Figure 1.1. In this figure, wire bonded interconnects can be seen clearly going from one device to another. Figure 1.2 shows the reduction to practice of Noyce’s invention of IC. Planar interconnects can be seen clearly between the devices of the monolithic-IC. For a detailed listing and discussions of the various criteria and documented facts on the monlithic-IC versus the hybrid-IC, see Reference 12 and Chapter 4 of this book.

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Fig. 1.1.

Kilby’s reduction to practice of his invention of IC.

3. Sole credit to Kilby and Noyce The sole credit for the invention of ICs has been given to Kilby1 and Noyce2 in the literature since their inventions were disclosed in their respective patent filings in the USPTO ∼50 years ago in 1959. Unfortunately this recognition accorded to Kilby and Noyce is only partly correct and justified, and most if not all of the authors and hence the readers on this subject have failed to appreciate this fact. Kilby and Noyce did play key roles in the invention of ICs, but not quite the way they have been portrayed in the literature so far. They have been singled out as if they did it all by themselves in inventing the ICs. They have been given an iconic stature by the hero worshippers without knowing where the credits are actually due and for what? Also, hundreds of million dollars and some in the billions have been made as profits in their pockets by some of the contributors as well as non-contributors to the IC technology and related businesses, and by those business savvy wizards who happened to be at the right place, at the right time and with the right people. As a professional courtesy and propriety,

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Fig. 1.2.

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Reduction to practice of Noyce’s invention of IC.

I shall not mention the names of several of them whom I knew personally. This is also to avoid the appearance of a conflict of purpose by implication. My sole purpose is to help straighten out the true IC invention history. My presentations in this book are based on my own exhaustive research of the published literature and my own educational science and engineering backgrounds and job experiences (see Appendix 1). Only a very select few genuine contributors numbering less than the number of fingers on one hand, who have amassed huge fortunes, are giving back to the industry and the society. They are the very admirable few

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indeed who were lucky, smart and courageous too. Nevertheless, while they and the others have had dame luck smile on them, many other genuine contributors have been ignored by the society; not only by the laymen but also by their technological peers of the latter days including today. Moreover, some of the fundamental facts of the IC invention have either been overlooked or not understood at all by the previous authors on the history of IC. These facts have also been documented in this book. While not taking away the key contributions of Kilby and Noyce, these facts tell a different story about their actual contributions. The details can be found in the subsequent chapters of the book, but a few are summarized below to point out the mystery of the invention of ICs.

4. A few facts in the mystery of the invention of ICs 4.1. One fact is that Kilby did make a key contribution to the invention of ICs by disclosing that all the devices can be fabricated in a single piece of semiconductor. (See Jack Kilby, Fig. 1 in Wolff3 : “A page from Jack Kilby’s notebook of July 24, 1958, where he first recorded how resistors, capacitors, and transistors could be made on a single slice of silicon.” As it is clear from this Fig. 1, Kilby’s handwritten disclosure was not witnessed, as required by the Patent Law.) But this is only a small part of the complete information needed to make the monolithic-IC. Did he borrow this idea from and limited to the same technical constraints as Geoffrey Dummer4 in England, who had described the same key yet limited concepts earlier? This remains as yet an unresolved mystery. However the fact also is that Dummer’s publication (see Chapter 9) pre-dates Kilby’s disclosure handwritten in his notebook. It is also well known that Kilby had attended Dummer’s presentation of his paper in 1952 in Washington, DC. Essentially similar suggestions had also been made earlier than Kilby by Harwick Johnson5 of RCA and Richard Stewart6 also of Texas Instruments (as Kilby was also from TI but had joined TI later than Stewart). 4.2. Another important fact is that Kilby did not invent the silicon monolithic-ICs, the only kind sold from the beginning to this day (except the hybrid microwave ICs such as those in the cell phones). This fact has been confirmed by a member of the Nobel Committee (Dr. MNC-1) in his written communications with me recently (see Chapter 12). In the

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specifications of his invention, Kilby did not give the correct procedures for fabricating the devices and their electrical isolation. Moreover he missed completely giving the correct procedures to interconnect the devices (rectifying diodes, amplifying and switching transistors, resistors, and capacitors) in the chip, without which the IC is not complete and cannot function to process the electrical signals and information. These facts tell us that this is not a mystery; these were serious omissions by Kilby and not envisioned by Kilby at that time. But it is a mystery how all this important information was ignored and swept aside by the USPTO in granting the patents to Kilby, and by the key technical and patent personnel all over the world who simply accepted Kilby as the inventor of the IC. Moreover the authors of books on the invention of the transistor and of the IC, and also some who wrote their PhD theses in History on the science and technology of these inventions also ignored or did not understand this important information. 4.3 The quintessence of Nobel’s Will is that the Nobel Prizes shall be awarded to those irrespective of nationality who, during the preceding year have conferred the greatest benefit on mankind. Nobel Prize is not awarded in the field of Engineering. The invention of ICs belongs more to the field of engineering rather than any other basic field of science such as Physics, Chemistry, etc, in which the Nobel Prizes are awarded. Nevertheless the impact of the ICs on almost all the other basic sciences has been so huge in the last few decades that their invention definitely merited a Nobel Award. The ICs are indispensable to do almost any kind of standard and advanced work in all the fields included in the original Nobel Award list. The Nobel Prize in physics7 was awarded jointly to Alferov, Kroemer and Kilby, and listed in this order, in 2000. Noyce had died in 1990; the Nobel Prizes are not awarded posthumously. As best as I can judge, had Noyce not died, he would have been definitely included in this award. Perhaps then the entire Nobel Prize award would have been worded and even awarded differently. The inventions of Kilby and Noyce did not involve any basic contributions to physics. However, the work of Alferov and Kroemer did involve basic contribution to physics. The citation for the above Nobel award to the co-winners Alfred, Kroemer and Kilby was published as “for basic work on information and

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communication technology”. The part of the citation specific to Alferov and Kroemer was written as, “for developing semiconductor heterostructures used in high-speed- and opto-electronics”, and the part of the citation specific to Kilby was written as, “for his part in the invention of the integrated circuit”. The Nobel Prize money was distributed as 1/4 each to Alferov and Kroemer, but 1/2 to Kilby. The citation of the Nobel Award to Kilby did not explain what was his part to invent what kind of IC? Kilby’s citation in the Prize was incomplete and inconsistent with his contribution to the purported invention of monolithic-ICs for which he was given the Nobel award. No explanation has been offered so far by the Nobel Committee for the vague and imprecise citation of such an important world renowned Prize. Kilby’s demonstration of hybrid IC, subsequently used in microwave ICs to this day, such as the cell phone, was not recognized by the Nobel Committee, at least not explicitly. I had written communications in 2006 with two members of the Nobel Committee which was responsible for the Nobel award in Physics in 2000. For the sake of discretion, I have chosen to refer to them only as Dr. MNC-1 and Dr. MNC-2 (for details see Chapter 12). To the best of my knowledge, I was the first to raise the issue of the incomplete characterization in the citation of the award to Kilby. They had invoked Nobel’s Will, and declined to answer my questions. An aura of mystery was created in these communications because neither clarifications of Kilby’s invention nor any further recourse to get them were given. Any implication of Kilby’s hybrid demonstration of the IC now still used in microwave IC such as the cell phone could have been explicitly stated by the Nobel Committee without ambiguity, if the Nobel Committee had recognized and intended to award such an application of the hybrid IC. However, Kilby was not the first to demonstrate the concept of hybrid-ICs. The above mystery was heightened also by the refusal of Nobel Committee to offer explanation for an additional fact which struck me as unusual. This fact was that Kilby was given twice the amount of financial award, even though his contribution did not involve Physics, than to each of the other two co-recipients whose fundamental contributions did involve Physics. Such a monetary award was unlike the equal amounts given in the Nobel Prize in Physics awarded to Shockley, Bardeen and Brattain in 1956 for their invention of the transistor earlier.

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The winners in a 3-person Nobel Prize award are listed alphabetically most of the time, especially if the monetary part of the award is distributed equally. However this procedure was not followed in listing Shockley, Bardeen and Brattain in 1956. Alphabetical order was not followed either in the listing of Alferov, Kroemer and Kilby in 2000, and Kilby’s name was last in the sequence even though he was given twice the amount than given to each of the other two. It is generally known that the highly revered group of the Nobel Committee acts as a powerful closed institution which feels strongly that they do not owe any explanation to anyone regarding their choices and decisions. Without casting any aspersions on any party concerned, respectfully and punctiliously I only wish to state that the manner in which Kilby’s Nobel citation and award had been handled was quite inexplicable. My communications with the Nobel Committee and their refusal to shed light on both the citation of the award and the double amount of the financial award to Kilby, had created more intrigue to the mystery. Nevertheless one cannot obliterate the facts as published by the Nobel Committee itself and elsewhere in the literature. They are cast in concrete and therefore stated as such in this book. However I have done further research using the original Nobel website on the Nobel Awards in Physics throughout their entire history of existence. Based on my research, I can offer an explanation only for the sequence of listing of the names, and the unequal financial awards by the Nobel Committee to Alferov, Kroemer and Kilby. But I still cannot fathom the imprecise citation of the award and the choice of Kilby by the Nobel Committee, which remains a mystery. For details, see Appendix 7 and Chapter 12. 4.4. To repeat and elaborate further, Kilby’s reduction to practice of his invention was that of a hybrid-IC, not a monolithic-IC.12,13 He had used mesa technology to fabricate and isolate the devices in germanium (Ge), not silicon (Si), and he had used gold (Au) wires bonded to the device chips (transistors, diodes, resistors and capacitors) to connect them electrically. The gold wires flopped all over the chip from one device to another; they were not the monolithic IC interconnects in which evaporated-thin and etched-narrow aluminum films (adherent to the silicon-di-oxide films) to electrically interconnect the devices on a single silicon chip are used. This is not a mystery. It is a documented fact given in many publications (see

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Chapter 7). Figure 1.1 shows the photograph of Kilby’s reduction to practice of his invention. Wire bonded interconnects can be seen clearly going from one device to another flopping in air above each of the device chips. 4.5. Noyce’s invention2 gave the procedures to fabricate silicon monolithic-ICs which have been used for the past 50 years to this day (1959– 2009) in large volume manufacturing. But he had used planar technology invented by Hoerni8 and p-n junction isolation invented by Lehovec.9 The credit due both Hoerni and Lehovec for their crucial contribution to the invention of the IC had been overlooked and ignored in the entire technical literature, until my call.12 The credit at least due Hoerni was acknowledged recently by Riordan51 only after my paper12 had stated explicitly that the contributions from both Hoerni and Lehovec were indispensable, without which the monolithic-IC, as we know it today could not have been made. Another key contribution used in Hoerni’s invention at Fairchild Semiconductor R&D Laboratory was by Sah10 in 1958. He had given the experiments-based theoretical design curves for SiO2 layer thicknesses needed to mask against the dopant impurity for selective thermal diffusions in order to make planar junctions of desired geometries. This was a critical step in fabricating Hoerni’s planar transistors, not recognized by the others. Sah’s work was the enhancement of Frosch and Derrick’s11 work done earlier which had not given the design curves of the thickness of the SiO2 needed for masking against the high-temperature diffusion of the phosphorus impurity to make the n+/p junctions. For details, see Chapter 6. As it is well known that the thermal diffusions of phosphorus and boron were supplemented later by the ion implantation technology. Noyce did not acknowledge Hoerni8 and Lehovec9 in his key IC patent.2 Why? The reasons can be debated, nevertheless this is a fact whose mystery remains unexplained. The facts also tell us that the reduction to practice of his invention was a team effort who had used Noyce’s step-and-repeat lithography camera. The contributions were made by several key co-workers who had worked in the 100-person-strong Fairchild Semiconductor R&D Laboratory of which he was the Director of Research. Whether or not their indispensable contributions were ignored by Noyce’s patent lawyer intentionally, cannot be ascertained, but it was more likely that Noyce did not know who actually made the contributions and could not single out one person except those other single-inventor patents also filed during

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that period at Fairchild. However, it can be surmised that Noyce’s singleauthor IC patent may not have been the likely cause of the departure of several of his eight Fairchild co-founders as perceived by all subsequent semiconductor history authors. These departures may have been due to more lucrative opportunities elsewhere. As an example, Eugene Kleiner went on to found Kleiner-Perkins, the famous venture capital firm. They were all hired previously by Shockley as the core of the Shockley startup. This is a fact, not just a good story, which is likely to be pushed aside or fogotten by the subsequent sucesses of those who left for the greener pastures and personal professional interests of 1960’s. Additional patent-based key points of Kilby’s and Noyce’s inventions shall be given later in subsequent Chapters 7 and 8 in this book. However the few points listed above should serve as a good start to trigger and focus the readers’ curiosities to know about the mysteries and facts of the invention of ICs, the invention which is used in all electronic gadgets that impact every aspect of our life and existence, now and forever.

5. My qualifications The readers may be curious to know about who am I and what my qualifications are that could be adequate to point out the inconsistencies in the history of one of the most important inventions of mankind? I have already discussed these qualifications in the Preface, where the reasons for including my IC concepts briefly were also given. I have followed the advice given to me by Gordon Moore.55 In lieu of repeating in detail here, I ask you kindly to read Appendices 1 and 2 at the end of this book, my publications12,13 on the invention of ICs, and also the commentary given by Jeff Marque14 on my publication.12 They are copied in Appendices 3 and 4, and in Chapter 11.

6. Getting history right Getting history right is an important matter. It is in that spirit that I am writing this book about the invention of integrated circuits (ICs). The invention of ICs has been one of the most important inventions of the 20th century which has revolutionized mankind forever. They

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are used worldwide in many if not all fields and applications (partial list is given alphabetically): banking, biotechnology, communications, computers, education, entertainment, government, hospitals, internet, medicine, nanotechnology, research, travel, and others, and in every commercial, defense and industrial businesses. All the electronic systems in these applications use much more advanced ICs such as Ultra Large Scale ICs (ULSICs) than the ICs invented originally. However, the stems of all ULSICs are rooted in the basic invention of the ICs. The ULSIC business has now grown to multi-hundred billion dollars annually which is also the heart and soul of all electronic systems market of trillions of dollars per year. It appears that the future growth of ULSICs and its impact on newer businesses shall still be forever increasing. Therefore it is important to know what were these basic inventions of the ICs, who invented them and how. Getting history right is also a difficult task, especially if the subject matter is of a fundamental importance and its prevailing erroneous view has lasted for a long time, viz., a few decades. This is particularly difficult for the person setting the records straight if he/she, though qualified and having first hand knowledge, is not “famous” and also belongs to a minority group different than those of the majority whose history needs to be corrected. This problem gets exacerbated further when the persons of the majority have been regarded popularly as icons for decades.

7. The case of Einstein The case of Einstein will be cited here, not to set history right because there was nothing wrong with his work, but as an example of defending under difficult circumstances what was right for physics and humanity. Max von Laue had defended Einstein’s work which was being criticized as being Jewish in character by the others during the period Hitler’s power was ascending in Germany. Even though Laue belonged to the majority group and Einstein to the minority, it was not easy for Laue to stand up to the other well known physicists in the majority group who were trying to discredit and criticize Einstein unfairly. It took a few years for Laue to set the records straight about Einstein’s discoveries, but he succeeded eventually. Just imagine the compounding of the problem had the situation been reversed. Had Laue made the errors in his work and Einstein had

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corrected and tried to document them, this would have made Einstein a pariah being a member of the minority group. Even though Einstein’s main motive to do this would have been only to set history right, he would not have been given any kudos for this.

8. Why getting history right is important? Being cognizant of the yore, while forging ahead with the future by innovations is a prudent wisdom to follow, so that the past mistakes shall not be repeated. The adage “Those who do not learn from their past mistakes, are condemned to relive them” has been proven to be right over and again throughout the entire history of mankind including scientific research. The inspiration for the younger generation to innovate for the future is provided by the leaders of the past. If the past accomplishments are misrepresented by the spin meisters of the present, it negates this key process of progeny of innovation for the future. Therefore getting history right is very important. Society is comprised of a spectrum of human beings of different ages, backgrounds, education, careers, ethnicity etc all over the world. For it to function, survive and progress in a civilized manner, many prudent actions must be taken. To discuss all aspects of what they are is a daunting task well beyond the scope of this book. However, an undisputable and important task is that of getting history right for the society. While it is almost impossible to do this unequivocally in several fields affecting the society (e.g., politics), it is relatively an easier task in the fields of exact sciences and engineering. We shall narrow down from the morass of even these precision fields to focus only on the invention of ICs in this book. The invention of ICs has been one of the most important inventions of the 20th century which has revolutionized mankind forever. In some respects, the impact of this invention on mankind far exceeds that of Einstein’s discoveries made earlier. Nevertheless, the fundamental aspects of IC are rooted in Einstein’s contributions among other pioneering discoveries. To re-emphasize, ICs are used worldwide in many applications in various fields, and almost nothing is possible today without using the ICs and their associated technologies. As best as one can extrapolate into

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the future, their applications even in the uncharted territories yet to be dreamed of, shall forever increase. Therefore it is important to know what is true and what is not about the invention of ICs. Erroneous claims have been made and wrong conclusions have been drawn in the past regarding them in the literature. Both documented and undocumented facts have been used for such claims. While the latter may provide an intriguing and thought provoking type of a mystery novel, they do not quantify and prove beyond any reasonable doubt the truth of an invention. 9. Documented facts The documented facts are the only way to get history right especially in science and engineering. I concede, however, that even the documented facts in these fields of exact sciences and engineering may have resulted from intrigues and usurping other people’s rights and contributions. Such discussions are also debatable and beyond the scope of this book, although brief comments will be made only on a few relevant issues directly concerning the invention of ICs. Therefore the main focus of this book is to give and discuss the documented facts of IC invention. Even the documentations have left several key questions still unanswered after so many years regarding this important invention. They will be discussed briefly at the end in Chapter 15. Comments shall also be made on the support technologies key to the invention and progression of ICs, which have not been given their due recognition in the literature so far. To get history right is the responsibility of subject-qualified people, and such an important task should not be left solely to the so-called science history writers, many of whom have had little or no first hand knowledge and experience or college training in the field. I have been involved in science and technology from the early years before the ICs were invented, during their invention and their advancement to the current super chips, and their future directions. The IC inventions were discussed in the earlier papers12,13 in a comprehensive technical manner meant for the specialists in the IC field. Einstein’s answer to the question, “What should the younger generation be taught?” was a simple word, “History.” Another cliché ascribed to Einstein is, “Imagination is more important than knowledge. While the

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latter has limits, the former is limitless!” Even though these sentiments have been expressed by many over millennia, Einstein is credited with them as he has been better known in the modern era. A key implication derived from these comments of Einstein is to get history right. So this statement has been made here to reinforce the importance of getting history right, especially regarding the IC inventions by objective and thorough analyses of the documented facts.

10. What are documented facts? Similar to living in a “Fool’s paradise”, one is apt to misjudge what is right and what is wrong if it is not clearly understood what the documented facts are? Therefore at the outset, we shall describe what are they? Documented facts which are used in the scientific and technical world to assign an invention are the patents issued by a bona fide legal agency of a government such as the United States Patent and Trademark Office (USPTO) in the USA or similar agencies in other countries of the world, and the research publications, pre-publication and now also post-publication or post-public-disclosure, in peer reviewed professional journals. The latter have less clout than the former in legal contests. However for professional recognition as well as awards of prizes like Nobel Prize, research publications wield an equivalent clout if not higher than the issued patents. While this practice holds true most of the time, however, it was not the case in the recognition given to Kilby “for his part in the invention of the integrated circuit” cited by the Nobel award committee7 in 2000 (for details, see Chapter 12). Issued patents have sub-categories of requirements of the documents such as record of original concept (e.g., witnessed notebooks, patent disclosures), filing date, and reduction to practice of the invention. The last criterion is quite debatable as it has not been deemed to be absolutely essential in many cases to claim the invention and receive a patent. Writing of the patents itself is a highly specialized legal field in which its specifications (figures and the text) and the claims should be understood by any person conversant in the state of the art, and be able to reduce the

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invention to practice. All the claims of the patent must be supported clearly by its specifications. Documented facts as described above have been published and analyzed in the recent paper12 for the first time in the literature in a comprehensive manner to clearly characterize the inventions of ICs by Kilby1 and Noyce.2

11. All ICs sold from day one have been Si monolithic-ICs All the ICs manufactured and sold from the very beginning when they had only a few transistors on a silicon chip to those currently having several billion transistors per chip, have been the monolithic-ICs using silicon (Si). (As stated earlier, the bybrid microwave ICs, widely sold, such as in cell phone, are excluded from these deliberations.) As recently as in 2006, several research historians16,41 have erroneously heralded Kilby’s invention in 1958 as the advent of the monolithic era. Noyce’s invention as documented in his patent was simply to prescribe how a monolithic-IC was to be made using Si, but he did not reduce his concepts to practice. It was done by the others who were members of Noyce’s Research and Development Laboratory of which Noyce was the director at that time. Gordon Moore became its director later. The planar technology mandatory for fabrication and the electrical isolation of devices necessary in the ICs were respectively invented by Hoerni,8 a member of Noyce’s Laboratory, and Lehovec9 who was with Sprague Electric Company. However, even the invention of the planar technology ascribed to Hoerni can also be questioned. It was derived by Hoerni from a combination of associated technologies on which the key technical work was done earlier by several others (see Chapter 6 for details). What is the monolithic concept and how do the monolithic-ICs differ from the hybrid-ICs, has also not been understood or delineated properly in the literature so far. This will be explained in Chapter 4. Details of the facts of Kilby’s and Noyce’s inventions shall be given with proper documentations in Chapters 7 and 8 respectively. Neither Kilby nor Noyce contributed directly to the advanced technologies or concepts used currently to manufacture the Ultra Large Scale ICs (ULSICs) and those required for the future ICs, e.g., 3-dimensional-ICs (3D-ICs), Ultra Performance ICs (UPICs), and IC-based

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systems such as systems-on-a-chip (SOCs). Noyce, however, did make a very significant additional contribution to the entire field of microelectronics by co-founding Intel Corporation with Gordon Moore which has been the leading manufacturer of ULSICs in the world. A great majority of all the advanced technologies are developed and implemented in large volume manufacturing at Intel. Impact of the past and current inventions of ICs on Moore’s Law which has guided the entire microelectronics industry, and future directions, shall also be presented in Chapter 13.

12. Three questions need to be answered up front In addition to giving the background information about the invention of the ICs in this chapter on Introduction, three questions also need to be answered up front: 12.1 Why do we need to know the important facts and to get the clarifications now after the invention of ICs about 50 years ago (or 55 years depending on when you start counting)? 12.2 Why nobody else has clarified some of the key technical facts of their inventions by Kilby and Noyce so far? Did Kilby and Noyce borrow their ideas from the others? 12.3 What are the questions on the invention of ICs which are still unresolved, and why have they not been addressed so far? The answers to the above three questions are given in Section 18 below after discussing the relevant information in the following sections.

13. Victory/success and defeat/failure As it is well known, “Victory/success has many fathers, but defeat/failure is an orphan!” This fact has been expressed in many different parts of the world from ancient times to the present in respective languages and cultures in their own unique and inquisitive ways. The invention of the ICs has been perhaps the most successful event in the entire history of technology developments in the world which have contributed to so many

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fields of science and businesses, and revolutionized mankind. The acronym IC for integrated circuit has been used in the literature generically for any kind of integrated circuit, without explaining what specifically it is for. This has caused some confusion, because when it is used for a hybrid-IC also, the demarcation between it and a monolithic-IC is debatable and not unequivocally separated. However, as it will be explained in Chapter 4 of this book, the use of acronym IC is predominantly for, and from accuracy point of view should be restricted to, the monolithic-ICs only. From the very beginning to the present, all the integrated circuit products sold in the semiconductor industry have been monolithic-ICs. Despite the above well known adage regarding victory and defeat, it is interesting to note that not many “fathers” have come forward to claim the parentage of the invention of the ICs during the past 50 years. The two “fathers”, viz., Jack Kilby1 and Bob Noyce,2 have been regarded as the undisputed inventors of the ICs, except that a few key facts even about their inventions have not been scrutinized carefully so far in the literature. Several others also did make key contributions to make the monolithic-ICs a reality, which are the true ICs, not the hybrid-ICs, being manufactured all along in the past 50 years. These monolithic-ICs are the heart and soul of the multi-hundred-billion dollar per year IC industry, which is also the core of the multi-trillion dollar per year electronic systems industry. However, while a few have been recognized (cf. Rostky15 ) for their contributions to make monolithic-ICs a reality, others have been literally “walked over”. Was it due to the hero worship of Kilby and Noyce, and/or due to the lightening speed at which the technology and business developments with huge profits that took place, and that the timing was propitious for them to happen? These are debatable issues. The purpose of this book is not to address this complex subject which is hard to quantify, but to present several technical facts primarily about Kilby’s and Noyce’s inventions of ICs and key contributions of a few others which have not been clarified and documented before. Therefore, it is important to know the truth about who invented what and how, even after 50 years since the patenting process of these inventions was begun. A few authors such as Kilby1,19 (who is widely regarded as, and was, the co-inventor with Noyce2 of the ICs), Wolff,3 Rostky,15 Riordan & Hoddeson,16 Berlin,17 Reid,39 Lee,40 Brock,41 and Lojek42 have tried to

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tell the story of the invention of ICs in their respective ways. While Kilby21 himself has given a historical account of the invention of the ICs in 1976, however he addressed and discussed the technical aspects of his invention and the patent22 only recently19 in 1998, and made some comments also on Noyce’s invention and his basic IC patent.2 Noyce43 described the IC as conceived at Fairchild, and referred to the work of Kilby (ibid), Hoerni,8 Lehovec9 and others, but did not describe the technical details of their patents in his paper. The authors in references 15–17, 39, 41, 42 do not address the technical issues of Kilby’s and Noyce’s IC inventions and their patents, and they have ascribed Kilby’s invention incorrectly to be that of a monolithic-IC. Perhaps this may be due to their efforts more as science history writers, rather than as scientists and engineers who are educated and trained to have the technical precision and knowledge and contributed first hand to solid state devices and IC technologies. Even Kilby’s later comments19,44 are incomplete engineering physics at best. Wolff3 gives an early account of the genesis of IC including predictions of Dummer4 in England, efforts of Kilby23 at Texas Instruments (TI), Noyce2 at Fairchild, and Lehovec9 at Sprague. However, Wolff3 does not refer to the work of Johnson5 of RCA and Stewart6 of TI. While his descriptions of the work of Noyce and Lehovec are quite correct, but that of Kilby’s requires some clarification. The caption of Fig. 1 in Wolff’s paper reads, “A page from Jack Kilby’s notebook of July 24, 1958, where he first recorded how resistors, capacitors, and transistors could be made on a single slice of silicon.” This part of making the devices is aptly credited to Kilby, but it is only a small as well as incomplete part of fabricating devices for the chip; it does not even specify the need for interconnecting and isolating the devices. Also, these devices must be made with planar, not mesa technologies. Nowhere in his patents or papers Kilby mentions or uses planar technology; instead he uses mesa technology. Therefore, while Kilby’s enunciation of the concept to fabricate various devices on a single chip is to be recognized, his actual accomplishments were not for the correct monolithic fabrication of even just the devices used in the last 50 years since the beginning of manufacturing of the ICs. Also, the key role of interconnects to electrically connect these devices is not explained by Wolff3 who simply quotes from Kilby’s notebook as their fabrication with “conductive material evaporated to connect the transistor emitter and base to the circuit, or small wires might be attached by thermal bonding.” Kilby

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prescribes in his patents evaporation of metals through metal masks, and wire bonded interconnects which are not used in monolithic ICs. Until the monolithic interconnects are also fabricated, which must be adherent to the insulator layers without shorting to the regions adjacent to the devices and each other, monolithic IC is not complete and will not function. As a journalist, Reid39 has done a good job of writing the story of “The Chip”, however, it is meant for laypersons. While he does not give the technical details of the invention of ICs, he presents the various key issues quite well. Lee40 discusses mostly “The (Pre-) History of the ICs”, and gives only a capsule of Kilby and Noyce’s inventions at the end of his paper without analyzing their technical details. The recent book by Lojek42 gives an interesting and compelling account of the “History of Semiconductor Engineering”, covering several of the areas of semiconductor engineering as it developed from the early years. While it is almost impossible to give the technical details of every issue in its entire field, he has tried to give the essence of a few of them. He has provided an incredible amount of documentation, some of which is rather provocative and debatable. Regarding the invention of ICs, Lojek’s42 statements at the outset (p. X. lines 15–17) are quite correct: “Historians assigned the invention of integrated circuits to Jack Kilby and Robert N. Noyce. In this book I am arguing that the group of inventors was much bigger.” To emphasize, only these statements by Lojek are undisputable in my opinion. His description of the others in “the group of inventors” is debatable, incomplete, and controversial due to lack of proper documentation. Even though the internet and information technologies have enabled communications of all sorts better than ever in the history of mankind, the facts regarding one of the most important inventions, viz., the ICs, are still not known clearly to a majority of the people. This is true also even for many of the thousands of scientists and engineers working in the microelectronics field today. Similar to the statement above regarding victory/success and defeat/failure, it will behoove us to recognize also that many an invention is not without some controversy about who the original inventor(s) was (were). My intent is not to create any controversy, or in any way to diminish the pioneering contributions of Kilby and Noyce, but the key purpose of

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writing this book is to clarify and present the facts. Like celebrities, only those inventions are newsworthy and deserving of critical and thorough investigation, which make a major impact on the business and/or human life. “The Invention of ICs” is such an invention (see Saxena20 ). Therefore, its story merits a more thorough technical scrutiny than it has been done so far in the literature. 14. Disclosure of the basic concept for ICs by others earlier than Kilby Kilby’s suggestion to fabricate multiple devices within a single piece of semiconductor was of course a key contribution, but it was only a small as well as incomplete part of the total invention needed to fabricate the ICs. Independent of Kilby, similar suggestions had been made by other authors, e.g., Geoffrey Dummer4 in England, and by Harwick Johnson5 of RCA and Richard Stewart6 also of Texas Instruments (as Kilby was from there too but joined TI later) right here in the USA, earlier than Kilby. If we restrict to the concept of fabricating multiple devices in a single piece of semiconductor as the key invention of IC by Kilby, for which he was also awarded the Nobel Prize, then we must recognize the documented contributions of the others made earlier than Kilby. Why were they ignored? Did Kilby derive his key ideas from them but did not acknowledge them? Why could someone do that and be allowed by the peers and the professional societies to get away with it? For the sake of whetting the appetite of the reader at this point, I shall quote the key ideas of the IC invention described in their respective patents and paper by Kilby, Dummer, Johnson and Stewart briefly as follows: 14.1 Quotation of the basic concept of IC invention stated in Kilby’s patent1 no. 3,138,744, “Miniaturized Self-contained Circuit Modules and Method of Fabrication”; filed May 6, 1959; issued Jun. 23, 1964*; Column 1; Lines 55–62: “. . . To that end, I have proposed in my pending application for patent, Serial No. 791,602, filed February 6, 1959, that

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various circuit elements including diodes, transistors, and resistors all be formed within a single block of semiconductor material, thereby eliminating the necessity for separate fabrication of the semiconductor devices and the interconnections as mentioned above. . . . ” Kilby did not state the above concept in any of his other patents. 14.2 Quotation of the basic concept statement from Dummer’s paper,4 “Electronic Components in Great Britain,” Proc. Components Symp., Washington, DC, p. 15–20, May 6, 1952 (No patent filed by Dummer); second paragraph on p. 19: “At this stage, I would like to take a peep into the future. With the advent of the transistor and the work in semiconductors generally, it seems now possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating conducting, rectifying and amplifying materials, the electrical functions being connected directly by cutting out areas of the various layers.” 14.3 Quotation from Harwick Johnson’s patent5 no. 2,816,228, “Semiconductor Phase Shift Oscillator and Device”; Filed May 21, 1953; Serial no. 356,407; issued Dec. 10, 1957; Column-4; lines 62–67, Claim 4. “A semiconductor phase shift network comprising a unitary semiconductor body including a plurality of series-connected alternating elements of semiconductor material of one type of conductivity and P-N junction elements, and bias voltage means connected to said P-N junction elements for varying capacitance thereof.” 14.4 Quotation from Richard Stewart’s patent6 no. 3,138,747 — “Integrated Semiconductor Circuit Device”; filed Feb. 12, 1959; issued June 23, 1964*; Column 1; lines 29–42:

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“The invention improves over the prior art circuits in that the necessary circuit elements such as the load resistor may be made an integral part of the semiconductor element. One such semiconductor element according to the present invention replaces several transistors required in the circuits of the prior art performing the same function. T he interconnecting circuit wiring is thereby eliminated or reduced. Also the gates of the “nor” circuit of the present invention provide amplification in addition to performing a logical function and the gates are well matched since they are basically one transistor. The fact that the entire circuit is embodied in a single transistor element allows miniaturization of the circuit heretofore not realizable.”

15. Brief comments on the basic concepts of IC invention documented by Kilby, Dummer, Johnson and Stewart given above For the sake of continuity and the readers to get a sense of intrigue in the invention of ICs, brief comments on their respective versions of concepts quoted above, are given as follows. Detailed comments on the basic concepts of the IC invention as documented by Kilby, Dummer, Johnson and Stewart above in Section 14 are given in Chapter 9. 15.1 Kilby had filed his patent(s) in 1959; some were issued in 1964, and others later. However, Kilby’s key patent no. 3,138,744, the only patent in which he had stated his basic concept of IC invention, was filed on May 6, 1959, and was issued on Jun. 23, 1964*. Kilby had claimed priority of earlier filing on Feb. 6, 1959, of his original application (OA) but this was denied by the USPTO. Its filing date was recorded as May 6, 1959, or that no filing date was recorded at all. Nevertheless based on OA, patent no. 3,138,743 was also issued on the same date as 3,138,744, viz., on Jun. 23, 1964*. Strangely enough, Kilby kept on referring to his patent no. 3,138,743 in his later patents and papers, although he had not stated his basic IC concept in this patent. Both of these patents were assigned to Texas Instruments (TI). The asterisk on the issue dates for these two patents of Kilby (3,138,743* and 3,138,744*), as well as Stewart’s patent no.

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3,138,747* given below (see 15.4), is to draw the reader’s attention that they were all issued by the USPTO on the same date, and all were assigned to Texas Instruments (TI). This practice is not commonly done by USPTO. It is somewhat unusual that all three patents were issued on the same date, especially when the filing date of Kilby’s patent no. 3,138,743 was deemed controversial, the two Kilby’s patents were numbered consecutively, Stewart’s patent was numbered by 3 more in the sequence, and all were issued much after Noyce’s patent even though filed earlier than him. For details of filing and issue dates, and further comments, see Chapters 5, 7 and 9. 15.2 Dummer did not file for a patent. But he had first published his concept on May 6, 1952, almost as an afterthought for an IC, without defining what kind of IC could be fabricated: hybrid or monolithic? Kilby’s description in his patent no. 3,138,744 filed on May 6, 1959 was similar and limited to the same criteria as Dummer’s in 1952. Kilby had attended Dummer’s presentation in 1952, so it is likely that Kilby may have derived his ideas from Dummer. He seems to allude to it in his Nobel Lecture in 2000. However, this cannot be proven beyond any reasonable doubt. Nevertheless, despite their incompleteness and similarities, clearly Dummer’s documentation of the basic concept pre-dates Kilby’s. 15.3 Harwick Johnson gave essentially similar concept in his patent no. 2,816,228 to fabricate a “unitary body”. Johnson’s patent describes the concept of forming a transistor and another portion formed as a controllable phase shift network or delay line (for example, resistance-capacitance), the two portions being related and interconnected to provide the desired function in a unitary semiconductor body. This is similar to, if not more than, the monolithic concept described by Kilby. It describes the concept of fabricating transistor, resistor and capacitor in a unitary semiconductor body, but it also specifies interconnecting them for a desired function which was not given by Kilby. Johnson had filed his patent on May 21, 1953, and it was issued on Dec. 10, 1957. So clearly, Johnson patent also predates both in filing and issuing of Kilby’s patents. 15.4 Richard Stewart’s patent no. 3,138,747 was filed on Feb. 12, 1959, and it was issued on June 23, 1964*. The asterisk on the issue date of this patent and the two patents of Kilby (3,138,743* and 3,138,744*) given

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above, is to draw the reader’s attention that they were all issued by the USPTO on the same date, and assigned to Texas Instruments (TI). Stewart had been working at TI before Kilby had joined it in 1958. Why was Stewart ignored when he had given essentially similar concepts to Kilby’s, and all the kudos were being given to Kilby, is a mystery. Stewart’s disclosure of the basic concept in his patent filed ahead of Kilby’s patent no. 3,138,744 in which Kilby’s concept was stated, was quite similar. Stewart wrote, “. . . the necessary circuit elements such as the load resistor may be made an integral part of the semiconductor element. One such semiconductor element according to the present invention replaces several transistors required in the circuits of the prior art performing the same function. The interconnecting circuit wiring is thereby eliminated or reduced.” Filing of Stewart’s patent no. 3,138,747 predates the filing of Kilby’s patent no. 3,138,744. For detailed discussion, see Chapter 9. 16. Concepts given by Saxena in 1954 As already written in Section 8 of the Preface, even though I had published a paper in 1953 based on which I had also given the concepts for ICs independent of and earlier than Kilby and Noyce, I shall not discuss them in detail in the main text of this book. However, for the sake of completeness of historical record, I shall defer it to Appendix 2. 17. Inputs for Noyce’s patent and investigation of Kilby’s patents My technical inputs which had helped Noyce’s IC patent to be awarded in 1961 ahead of Kilby are documented in two papers.20,28 Basically, the key issue was of the interconnect metal to be adherent to the insulating film, SiO2 . My inputs were that aluminum (Al) specified by Noyce was correct, whereas gold (Au) or copper (Cu) by themselves for interconnects specified by Kilby were incorrect. For further discussions, see Chapter 8. While investigating the details of Kilby’s patents, I have received some new information about them (see Chapter 5) as recently as on September 26, 2005, and on November 02, 2005, from the US Patent Office (USPTO). They had not been reported in the literature previously until my papers12,13 were published. These papers also contain brief accounts of the key technical

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facts of Kilby’s and Noyce’s inventions which had not been published in the past.

18. Other aspects which contributed to the invention and fantastic success of ICs There are many other aspects of ICs, e.g., manufacturing equipment, materials, processes, design, packaging, applications in systems, etc, whose inventions and developments also need to be scrutinized carefully. They were, and still are, crucial to the fantastic success of the IC industry. However, this huge subject also shall not be discussed in this book. The main purpose of this book is to focus on only one aspect of the ICs: The Invention of ICs.

19. Answers to the three questions raised in Section 11 The information given above in sections 12 to 16 provides the answer to the first question raised in Section 11: “Why do we need to know the important facts and clarifications now after the invention of ICs 50 years ago (or 55 years depending on when you start counting)?” See also the next Chapter 2. All throughout this period of time, the important facts and clarifications of the invention of ICs have not been documented correctly. My attempt to write this book is to do just that. The second question, “Why nobody else has clarified some of the key technical facts of the inventions of ICs by Kilby and Noyce so far?” is not easy to answer. Nevertheless I have given in Chapters 7 and 8, these key technical facts and why they are important. Hundreds and thousands of qualified personnel (scientists, engineers and patent attorneys) all over the world must have noticed these technical facts. Why they did not address and document them so far is surprising indeed. The answers to the last question, “What are the unresolved questions still on the invention of ICs, and why have they not been addressed so far?” are also somewhat difficult. However, these questions and comments are given in Chapter 15.

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20. For whom is the book primarily intended and at what level? This book is primarily intended for all scientists, engineers and managers in the IC industry, as well as undergraduate, graduate students, professors in electrical engineering, physics, materials engineering and chemistry in universities, and not the least, the patent attorneys. The level addressed will be for a broad category of practicing engineers in industry, undergraduate and graduate students in academia, attorneys in law, and venture capitalists. However even the laypersons who may be interested in finding the truth about the invention of ICs, should be able to follow all the documented facts without getting mired in their technical details and jargons. They may skip reading the various original patents and the technical papers, which may be of interest only to the specialists in microelectronics. Many of the engineers and scientists, even those who are currently in the fields of microelectronics, computer and information and communication technologies (ICTs), have taken Ultra Large Scale Integrated Circuits (ULSICs) for granted. While some may know how these ULSICs came to be, and how they emerged from the original ICs to the super chips of today, many are probably too busily immersed in the narrow topic and task of developing their respective advanced technologies to meet the target dates demanded by their jobs. As it is well known, these billion-device super chips are used in many applications in various fields of education, research, medicine, government, and in the entire commercial, industrial and defense industries. Therefore, even though the number of engineers, scientists and other workers in these fields may be huge, those who really understand the overall facts regarding the invention of the original ICs may be rather small. In order to appreciate the mind boggling progress of the entire IC industry, it will be helpful to understand how did it all begin, and to know the facts about how the original ICs were invented and by whom? Knowing the true history of the invention of ICs and their development can only help in having a better insight into the future technologies needed for the even more advanced chips. This book may also be used as the key text book to establish graduate level courses on “The Invention of ICs which Revolutionized

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Mankind Forever” in universities. These courses may be established in various departments such as Physics, Chemistry, Electrical and Computer Engineering, ULSI Design, Materials Engineering, Mechanical Engineering (Design of Processing Equipment), Entrepreneurship and Innovation, Business School (Marketing and Management in High-Tech Industries), and Social Sciences (Impact of High-Tech Innovation on Quality of Human Life). The core material may be extracted from this book and augmented with additional advanced support material to establish such graduate level courses.

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Chapter 2

Discovery, Invention, Improvement, Patents and Publications

In order to appreciate why is it important to understand the inventions of the integrated circuits (ICs) even after more than four decades since the patents were issued to Kilby1 and Noyce,2 it will be helpful to understand the answers to the following questions:

What is a discovery? What is an invention? What is an improvement in product or process? What is the significance of getting patents? What is the importance of publications?

Books have been, and many more can be, written for the answers to the above questions. This is because they involve the inventions and inventors in many disciplines, scientists, policy makers in different governments, and the spin-meisters in the legal/patent fields all over the world. The answers arrived at to define an invention, for example, can also be debated forever in some cases. However, for the purpose of this book, we shall focus only on the invention of the ICs. All the ICs manufactured and sold from the very beginning when they had only a few transistors per chip to those currently having over a billion transistors per chip have been monolithicICs made with Si. But what is the monolithic concept which is mandatory for fabricating such ICs, and how do these ICs differ from the hybrid-ICs? This is explained in Chapter 4.

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The answers to the above questions pertinent to the invention of the ICs, which is the root of all microelectronics and its related scientific and technology fields, shall be given briefly as follows. Those who are interested in getting the rigorous details in each category described below should consult the respective specialists and read the respective books.

1. Discovery A discovery is finding an object, phenomenon or law experimentally or theoretically which was not known to exist before. A few examples of discovery relevant to microelectronics are electrons, holes, quantum mechanics, p–n junctions, elements such as silicon (Si), oxygen (O), aluminum (Al), etc.

2. Invention An invention, succinctly defining it, is the cessation of ignorance by creating a new object, phenomenon or law experimentally or theoretically which did not exist before by using the already known or discovered sub-counterparts. The expression “cessation of ignorance” ascribed to define an invention has been given by me because we are knowledgeable about the known discovered objects etc., which are already all around us. However, we are ignorant about using them in a unique way to create something new and useful products, and advance our knowledge. Whoever removes the ignorance is the inventor of that particular invention. A few examples of the invention in microelectronics are bipolar and MOS (metal-oxide-semiconductor) transistors, planar technology, p–n junction isolation, LOCOS (LOCal Oxidation of Silicon) isolation, ICs, microprocessors, multilevel interconnects, homo- and hetero-epitaxial single crystal films, etc. Two specific inventions relevant to ICs which are discussed in detail in this book are those covered by the patents issued to Kilby1 for the invention of IC, even though it was only for a hybrid-IC, and to Noyce2 for the invention of the monolithic-IC, even though it had used the concepts patented independently by Hoerni8 and Lehovec.9

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Having the concept of an invention is necessary and is a good start, but it is insufficient. It is akin to Einstein’s gedanken experiments to initiate the innovative thought processes. Theoretical and experimental verifications of the new ideas must be made to substantiate their purported outcomes. For Kilby to only write in his notebook in 1958 (summarized as Fig. 1 in Wolff3 ), that the various devices (transistors, diodes, resistors, capacitors and inductors) can be made in the same piece of semiconductor, is just the beginning of the dream of a concept. Moreover, this was only a small part of the total concept needed for the invention of ICs. Even within this part, how to fabricate such devices which can be used for making the ICs needs to be defined clearly. This was not done correctly by Kilby; he had described mesa technology. The key technology mandatory for the fabrication of devices in ICs was the planar technology, which was invented by Hoerni.8 But Kilby never specified it even in his later patents. Noyce used it but did not refer to it in his patent.2 In Kilby’s 1958 handwritten disclosure3 in his notebook, the additional technologies of device fabrication, isolation and monolithic interconnections, without which ICs cannot be fabricated, were not specified correctly or not at all. A noteworthy fact is that Kilby’s part of the fundamental concept to fabricate various devices in the same piece of semiconductor, for which he was recognized with the Nobel award, had a striking similarity with and the limitations of almost exactly the same part and the idea disclosed earlier by Dummer.4 Kilby19,21 did quote Dummer’s statements verbatim in his papers in 1976 and 1998, and acknowledged them in his Nobel speech7 in 2000. But he made no mention of Dummer in the patent1 awarded in 1964. However in this patent, Kilby did write his own version of the same part of the fundamental concept, whose striking similarity could be construed as paraphrasing Dummer’s earlier statement. The controversy whether or not Kilby’s concept, for which he was recognized as the inventor of the ICs, was actually derived from Dummer has still not been resolved. Strangely enough, Kilby continued to ignore this patent1 (in which the part of the concept was written) in favor of his patent22 claimed to have been filed earlier (in which the part of the concept was not written). For details, see Reference 12 and Chapter 7. Also see Reference 20 for discussions of various developments beginning from pre-IC era to the invention of ICs, their advancements to current ULSICs and beyond, and their impact on the quality of human life (QHL).

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In lengthy and costly patent interference proceedings between Kilby and Noyce, the decision by The Board of Patent Interference of USPTO was that both Kilby and Noyce patents were necessary for the fabrication of ICs. In essence, Noyce was given the credit for his part to fabricate monolithic interconnects adherent to the oxide, and Kilby for his part to fabricate the necessary devices in a single chip. This was despite the fact that Kilby’s specifications for device fabrication in a single chip were incorrect, and both Kilby’s and Noyce’s patents ignored acknowledging planar technology invented by Hoerni8 and p-n junction isolation invented by Lehovec9 which were mandatory for the fabrication of ICs. Still another noteworthy fact is that Kilby19 continued to question the monolithic concept and regarded it controversial as late as in 1998, which was only two years before he was awarded the Nobel Prize in physics in 2000. If anybody who should have understood clearly the monolithic concept should have been Kilby because the company he was working for, Texas Instruments (TI) was manufacturing silicon monolithic-ICs ever since the early 1960s. Other serious matters which also should be noted are the confused record keeping by the USPTO regarding the filing and issuing of Kilby’s patents, and possible compromise of the laws of US Patent code 35 USC 112 and associated protocols. For details, see Reference 12 and Chapter 7. As summarized in Table 1.1 in Chapter 1, Noyce’s invention met all of the criteria of fabricating silicon monolithic-IC, Kilby’s met only 1 out of 4 requirements. Therefore on a relative basis, Noyce deserves more credit than Kilby for the IC invention. However, important contributions from the other key inventors and participants were ignored by both Kilby and Noyce. It is difficult sometimes to decide where to draw the line in sharing the credit of an invention with the other contributors. A realistic though somewhat facetious example to illustrate this point is the role of a junior technician who may have helped to fabricate the devices only by performing a part of simple yet crucial processing. Should that technician be included as a co-inventor? The obvious answer would be “No”. Should the bosses of the technician such as the Director or Manager or the key engineers who had made the invention possible be given the credit? The answer to this

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question can be debatable depending on how innovative and crucial their contributions were, and the subjective decision by the inventor whether or not their contributions were indispensable for the invention. Nevertheless, giving the credit for inventing the ICs solely to Kilby and Noyce appears to be somewhat misplaced. Particularly in Kilby’s case, it is like someone making the following statements, and be given the credit and Nobel award for inventing the respective inventions below. A few examples in various fields are given in a condensed manner to which most of the readers can relate. 2.1. Cancer can be cured by stopping the uncontrolled mitosis in the affected regions. [The exact proven methods and techniques are not given how to do this.] 2.2. Horrific diseases such as ALS (paralyzing nervous system disorder), Alzheimer’s, Parkinson’s, autoimmune disease, mental sickness (e.g., bipolar disorder, clinical depression), etc., can be cured by stem cells. [The open question of why the cells died or mutated in the first place, and exactly how the stem cell therapies are to be customized and used for curing are not specified.] 2.3. We can go to the moon and return by using rockets and space vehicles. [The exact proven methods and designs are not given.] 2.4. ICs can also be made from semiconductors other than Si by using appropriate surface passivation, planar, and interconnect technologies. [The exact proven details are not given.] 2.5. Vision can be improved, and blindness can be overcome, by implanting an array of nano-electro-optical detectors in the eye whose electrical outputs communicate with the visual cortex in the brain, and display the images similar to those produced by the natural rods and cones cells in the retina of human eyes. [The details of the devices, proven methods and techniques are not given how to do this.] 2.6. The energy crisis can be solved by using alternate energy sources instead of gasoline. [The exact proven details of the choice of alternate energy source(s) and their methods and techniques are not given.]

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Similar examples can be given and the respective inventions claimed in many different areas. Noyce’s invention and his patent2 could also be questioned about their uniqueness deserving the sole credit. As discussed above, Noyce’s invention was based only on the disclosure in his notebook which was not even witnessed. It had used Hoerni’s8 and Lehovec’s9 inventions, without which Noyce’s invention would not have been feasible. Its reduction to practice was not done by Noyce; it was done by others several of whom claim that had it not been for their key contributions, Noyce’s invention would not have worked. The above conclusions are not meant to tarnish the iconic images of Kilby and Noyce, but the documented facts have been given here to get the history right. I have had, and still do have, the highest respect for both Kilby and Noyce. The leadership qualities of Noyce are well known. Noyce went on after co-founding Fairchild to co-found Intel Corporation with Gordon Moore which is the top most IC manufacturer in the world today. At Intel, the most advanced IC technologies are being developed and used in large volume manufacturing. Kilby also made other important contributions to TI and the microelectronics industry. But the documented facts about their respective inventions of ICs tell a different story than it has been generally accepted so far for the past five decades regarding the credits accorded to them.

3. Improvement An improvement in a product or a process is its enhancement from the already known discoveries and inventions. This is an extremely debatable area in which the rulings of the US Patent & Trademark Office (USPTO) are generally regarded as final from a legal point of view in the USA. However, they can be quite controversial at times. An improvement may be allowed as an invention, thus a patent can be granted for it. Similarly other improvements can be denied as inventions, thus patents for them will be denied. A few examples are the innumerable patents for Ultra Large Scale ICs (ULSICs), ion implantation, low-pressure chemical vapor deposition (LPCVD), sputtering, reactive ion etching (RIE), planarization

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of metal and dielectric films, enhanced manufacturing equipment for larger size wafers, yield improvement products, etc. 4. Patents The essence of a patent is that it expressly guarantees the inventor the right to exclude others from — making, — using, or — selling the invention. To get a patent, the inventor must provide written description, and the method of fabricating and using the invention in — — — —

full, clear, concise & exact terms.

After getting the patent, the inventor can license it to the others to use the invention for fees which are acceptable mutually. (Such fees can amount to millions of dollars.) A patent’s claims should never be judged by how they are projected forward and used in the present, but only if they would be non-obvious to people who understood the then current state of the art. This is the proper legal definition. So, the fact that Kilby did not use planar technology, which is used everywhere in present day is not necessarily a detraction to his patent, claims or overall inventorship. However, as it will become clear later in Chapter 7, Kilby’s patents are limited in their scope of the ICs invented by him. The major credit accorded to Jack Kilby was for proposing that multiple active and passive devices can be fabricated in a single piece of semiconductor required for an integrated circuit. Whether or not this contribution of Kilby’s can really be termed as “major” is debatable, and whether it was derived from the others has not yet been resolved as discussed in Chapter 9. More important in addition, he missed specifying

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in his invention several key technologies correctly which are mandatory for the IC to be completed and function properly: monolithic interconnects adherent to the surface of the insulating film to connect all the devices; planar technology for fabricating the devices; monolithic isolation between the devices. During the time of Kilby’s invention, each solid state device had very poor yield and it was definitely not obvious to one in the state of the art that the overall yield for multiple devices on a single chip could be brought up to an acceptable level. Jack Morton, Head of Bell Labs at that time didn’t put any of his team’s effort into ICs because of his confidence that the overall yield of an IC would be disastrous. No one would have expected that the inclusion of multiple resistors or capacitors could have had a poor yield, so the additional inclusion of a multiplicity of resistors and capacitors may not have been an issue for the Patent Department judges at the time.

5. Publications Research publications to describe an invention or any of its variations in peer reviewed journals are almost as important as getting the patents. The former are regarded as very important in getting professional recognition and awards (including the Nobel Prize), but the latter are more important in legal matters concerning the invention, e.g., mandating and enforcing the collection of royalties from the users of the patents. Although it is not common, but it does happen in certain cases when an entrenched group of powerful reviewers and editors who disagree with an invention or a new result, can delay or even prevent publishing a paper. Sometimes the professional ethics and the academic freedom conflict with the responsibility of the reviewers to prevent junk and fraud from being published in reputable journals. This is somewhat similar to granting the patents when only genuine inventions should be allowed, and the junk should be rejected. More often than not, this is a highly debatable area in which the powerful with deep pockets and key connections are likely to prevail. This is unfortunate, but that is the reality that some authors and inventors do face and consequently lose due credit and recognition. A few examples of the deep pockets and key connections related to the invention

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of ICs are the patents and the papers by Jack Kilby (see Chapter 7) which got issued and published despite their questionable and/or limited merit. Sometimes it is easier and more helpful to document a new result without giving away the key patentable ideas, and to publish them in trade journals, magazines and newspapers. Such publications do not receive the scrutiny given to publications in peer reviewed journals, so they can usually be published faster too. Nevertheless, because of the fear of tarnishing their reputation, and not to make enemies of the powerful, even these non-peerreviewed journals, magazines and newspapers sometimes refuse to publish the new results. With the advent of the internet, however, this scenario is changing; any appearance in the public domain excludes its sole ownership and patentability. 6. Trade secrets Still another way to protect one’s proprietary idea is to use the “Trade Secret” route. A famous example for this is the Coca Cola formula, which has never been patented. However in short, this route is not easy to protect one’s key technologies for the ICs and ULSICs, although several corporations have invoked “Proprietary Information” as the reason for not divulging them in conferences and publications.

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Chapter 3

Evolution of Miniaturization in Electronics: ICs to VLSICs to ULSICs and Beyond in the Future To re-emphasize, my main objective to write this book is to get history right and set the records straight of the invention of integrated circuits (ICs). Therefore the entire book is devoted primarily to this important task. Nevertheless, I shall give in this chapter a brief description of electronics on both sides of the IC invention, viz., what was the status of electronics before, how this field changed after the invention rapidly to its Very Large Scale Integration (VLSI) level of integration, and subsequently advanced even faster to its current nano-version of Ultra Large Scale Integrated Circuits (ULSICs) having several billion transistors per chip. I shall also give insight into where and how we can progress beyond ULSICs in the future. Obviously I cannot do justice to this latter huge and important subject also in this chapter and the book. However I shall try to capsulate a few key items and refer the readers to pursue them elsewhere. In order to understand who did what to invent what kind of integrated circuit, i.e., whether it was a hybrid-IC or a monolithic-IC, it will be helpful to follow the evolution of miniaturization itself of the electronic circuits leading to the present ULSICs. How do the hybrid-ICs differ from monolithic-ICs shall be discussed in detail in the next Chapter 4. However before doing that, we need to address briefly the following questions: — Why miniaturization is needed? — What is the evolution of miniaturization? 41

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— When do we call an electronic circuit an integrated circuit? — Where do we draw the line in hybrid-ICs to define the onset of miniaturized monolithic-ICs?

1. Present status of miniaturization One of the best ways to appreciate the evolution of anything is to recognize in the very beginning what is its status at present. Most of the advanced “miniaturized electronic circuits” currently are the Ultra Large Scale Integrated Circuits (ULSICs) made from single crystals of Si. For a recent paper on the evolution of “Transistors to ICs to ULSICs and Beyond”, and for the details of 3D-ICs and Ultra Performance ICs (UPICs), see Saxena.20 For convenience, a copy of this original paper is given in Appendix 5. CMOS has established itself as the predominant ULSIC technology. Figure 3.1 shows a typical cross section of twin-tub CMOS structure20,27

Fig. 3.1.

A typical cross section of twin-tub CMOS structure (not drawn to scale).

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(not drawn to scale). A typical ULSIC chip now contains hundreds of millions to billions of devices which are fabricated monolithically in Si using planar and appropriate isolation and multilevel interconnect technologies. These devices are connected by the 1st layer interconnect making ohmic contacts to the various devices, going over and adherent to the SiO2 film without shorting the junctions, and by multilevel interconnects using metals/alloys and inter-layer dielectrics (ILDs), which are contiguous to the single crystal Si substrate. Those conversant in the state of the art know that a variety of advanced technologies such as photolithography, reactive ion etching (RIE), ion implantation, low pressure chemical vapor deposition (LPCVD), planarization via chemical mechanical etchingpolishing, sputtering, cleaning, etc., are used to manufacture such ULSICs. However, it is important to remember that in each chip, not only the devices are monolithic in Si, but all the different multilevel interconnects and the passivation layers are also contiguous, adherent and monolithic. To emphasize, the entire ULSIC chip is monolithic, i.e., the entire structure is one solid block, and there are no dangling wires bonded between the devices to connect them and to perform the necessary functions expected from the computer-aided-design of the electronic circuit in the chip. 2. Need for miniaturization and its evolution In order to understand how the miniaturization of electronic circuits began and how the invention of ICs played a pivotal role in their evolution to the ULSICs of today, it will be important to review the progression of miniaturization itself briefly. For ease of discussions in the subsequent sections, and not divert from the main focus on the invention of integrated circuits, the evolution of miniaturization will be defined here only in two categories: 2.1. Hybrid-Integrated Circuits (Hybrid-ICs), and 2.2. Monolithic-Integrated Circuits (Monolithic-ICs). The demarcation between some of the stages within the evolution of hybrid-ICs is not sharp and precise, so they will not be elaborated. However, the hybrid-ICs will be defined and how the monolithic-ICs differ from them unequivocally. This is discussed in detail in the next Chapter 4.

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We shall begin with the starting stage of an electronic circuit having devices for functions like amplification, switching, rectification, etc. It consisted of vacuum tubes as the active devices, and resistors, capacitors and inductors as the passive devices. They were all mounted mostly in a chassis of some sort, and were connected by appropriate soldering, alloying or bonding of the wires according to a desired circuit design. Such electronic circuits consumed a lot of electrical power, produced considerable heat, were bulky, and prone to unreliable operation due to the limited life of the vacuum tubes. During the 2nd world war and thereafter during the cold war, buildup of the missiles and defense systems, as well as the onset of the space age and global communications, it became clear that the miniaturization of electronic circuits was of paramount importance. Some of the factors motivating miniaturization were reliability, low power consumption, portability, performance and cost. The discovery of the transistor effect at Bell Labs in 1947, and the rapid developments of advanced versions of the transistor from the transistor effect thereafter, provided the natural entrée to the miniaturization of the electronic circuits. The formation of resistors, capacitors and interconnects by various deposition techniques (such as vacuum evaporation, silk screening, plating, etc.) on ceramic, glass and plastic substrates were already being pursued. Printed circuit boards (PCBs) were being developed and used already for manufacturing low cost radios and several other electronic products sold in the market place. The era of miniaturization of the electronic circuits was initiated when the solid state devices such as transistors and diodes replaced the vacuum tubes, and were used in conjunction with the passive components such as resistors and capacitors. The use of the term “Integrated Circuits” for such miniaturized circuits shall be enforced here, although its actual use was initiated in practice during the later stages of their evolution. From a pedantic point of view of the English language, the term “Integrated Circuits” could also be applied to the earlier circuits using vacuum tubes. Since all the components in such circuits were connected together and integrated to perform the electronic functions, they could also be characterized as an early version of “Integrated Circuits”. But as it has been the practice in the entire literature and the industry, the electronic circuits with vacuum tubes shall not be referred to as “Integrated Circuits” in this book.

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3. When an electronic circuit is an IC? When solid state active devices such as transistors and diodes replaced the vacuum tubes, and were used in conjunction with the passive components such as resistors and capacitors in a chassis or on a PCB, the resulting electronic circuit was a sort of integrated circuit. As explained in the next Chapter 4, such circuits are called hybrid-ICs. However, to further clarify their evolution and differentiate between those hybrid-ICs fabricated initially with “Packaged Chips” and later with “Unpackaged Chips”, I shall introduce a new terminology as follows. 3.1. Hybrid-ICs fabricated with Packaged Chips = Hybrid-PC-ICs. 3.2. Hybrid-ICs fabricated with Unpackaged Chips = Hybrid-UC-ICs. None of the IC products initially sold had all the devices monolithic within one Si chip. They were individual devices which were wire-bonded between the various active and passive devices to connect them to form the desired circuit. Such products were not monolithic-ICs; they were hybridICs. In hybrid-ICs, the entire structure of the circuit on the chip is not monolithic, because the bonded wires go from one device to another, up above the Si chip, and/or to the pre-metallized interconnects on the ceramic or other substrates. The reduction to practice by Kilby for his invention was a hybrid-IC in which mesa (defined by chemically etching) devices were fabricated in Ge pieces or chips, each glued to a common glass substrate, and the devices on each of the chips were interconnected by gold (Au) wire bonds flopping over the devices. This is described briefly in Chapter 1 and in detail in Chapter 7. From the above discussions, it is clear that there is little difference between the type of hybrid-IC demonstrated by Kilby and the other types using PCBs or silk-screened ceramic substrates which contained thin and narrow conducting stripes adherent to the substrates which interconnect the devices on the chips. In the latter type of hybrid-ICs, however, mostly already packaged devices were used initially, although unpackaged components were also used later, directly soldered to the metallic conducting stripes. Both types of hybrid-ICs give miniaturization of electronic circuits, yielding miniaturized integrated circuits. However, to differentiate between the

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hybrid-ICs with packaged devices wire-bonded together and to the other components, and those hybrid-ICs with unpackaged devices wire-bonded or connected together with metal stripes and to the other components, the miniaturization of the electronic circuits would be achieved better with the latter approach than with the former. If the former approach with packaged devices is accepted as the definition of the onset of miniaturized integrated circuits, then many a scientist and engineer would need to be recognized as the inventors of the ICs. Many of the older readers of this book will remember the days of assembling radios, amplifiers and other circuits with transistors, diodes, etc., using “Heathkits” and other electronic kits sold by several manufacturers in the 1950s and 1960s. Already packaged solid state devices with PCBs or other substrates having some of the interconnections were supplied with the kits, along with the circuit diagrams and instructions on how to assemble them. Such kits represented circuits which were miniature hybrid-PC-ICs. So we shall not use this example for the onset of miniaturized integrated circuits, otherwise we will have an onslaught from many a “father” claiming to have invented the ICs after having bought the Heathkits for themselves and/or their kids. The solar cells also are not characterized as miniature ICs, because their p–n junctions and interconnections are huge in size as compared to those fabricated in transistors or even hybrid-ICs. However, since the early workers in this field did use Si for the solar cells inter-connected with Al adherent to the oxide films, even though their technology relatively speaking was crude, some of them may feel entitled to be credited with the invention of the integrated circuit (e.g., see Queisser24 ). Therefore, any person who has constructed such solar cells earlier could also claim recognition as an inventor of the IC. But this has not been practiced in the literature so far, or given recognition by the Nobel Committee either, so we shall not deviate from this practice as well. 4. When does a hybrid-IC become a monolithic-IC? A hybrid-IC becomes a monolithic-IC when all the active and passive devices are fabricated, isolated and interconnected monolithically in a single piece of semiconductor. A popular term for such a monolithic-IC

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in a single piece of semiconductor is called a “chip”. For details, see Chapter 4. Not only the state of the art ULSIC chips, but from the very beginning of manufacturing and selling the ICs about 48 years ago, all the IC products sold have used monolithic chips of single crystal Si, although the monolithic Si and compound-semiconductor chips may be connected by wires to form a larger hybrid IC product. Such monolithic Si chips are fabricated in single crystal Si substrates, and the planar technology is mandatory for the fabrication of the devices in them. Each chip is one solid block of Si single crystal substrate in which the various devices are fabricated and isolated monolithically, and they are connected with single and multilevel interconnects adherent to SiO2 films and contiguous to the Si substrate. Within a package containing a die-attached (or chip-attached) monolithicIC chip, a few wires which are not monolithic are only those bonded from the pads on the chip to the external leads of the package, to communicate with the outside circuits external to the chip. These wires do not dangle loose and flop around above and in between the devices of the chip in the package, but the two respective ends of each wire are securely bonded. Thus all the IC products manufactured and sold from day one of the IC industry contained Si chips which were entirely monolithic. The practice of referring to these products has been to call them simply in short the ICs, and not to elaborate them as the monolithic-ICs. The above important distinctions are crucial to unequivocally assign and credit the inventor(s) of the ICs properly. It is quite surprising that these important distinctions between Kilby’s and Noyce’s IC inventions have not been documented and clarified in the literature earlier. It is also surprising that after all these years, about half a century or 50 years, since his invention in 1959, Kilby19 himself as recently as in 1998 left the question of monolithic-ICs ambiguous and unanswered by concluding, “Despite these introductions, the monolithic concept remained controversial.” 5. Fast evolution from early ICs to VLSICs to ULSICs Figure 3.2 shows the roadmap of the evolution of ICs.20,27 Figure 3.3 is the same with additional comments on the role of scaling (viz. shrinking

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Fig. 3.2.

Roadmap of ICs.20,27

the device and interconnect dimensions), multilevel interconnections, and the device integration regimes. The largest segment of the present ULSIC business of multi-hundred-billion dollar volume is the Si CMOS. To describe it very briefly, it is a two-MOSFET (Metal-Oxide-Silicon-Field-EffectTransistor) or two-MOST (Metal-Oxide-Silicon-Transistor) signal inversion circuit known as the inverter. It is a circuit as defined by the IEEE SolidState-Circuit-Society, not a device which implies a single device component or single transistor (not two interconnected). This is well established by now from the dollar volume and the number sold as the most important and dominant product in the entire semiconductor industry (see Table 13.1 in Chapter 13). Therefore it is important to remember that the Si CMOS has established itself as the predominant ULSIC technology. For an excellent review of the evolution of the MOS transistor into ULSICs based solely on patent applications and issue dates similar to this book that I am writing, see the 1988 invited review in the IEEE Proceedings given by Sah.56

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Fig. 3.3. Roadmap of ICs.20,27 Same as Fig. 3.2, but it also gives additional comments on the role of scaling, multilevel interconnections, and the device integration regimes. The largest segment of the present ULSIC business of multi-hundred dollar volume is Si CMOS.

Another critical technology development was the Si-gate technology which enabled the faster generation of CMOS devices with low threshold voltages. It launched CMOS rapidly into the major technology in the entire industry, when it was applied to the successful new class of products known as the microprocessors, popularly termed as the computer on a chip. Faggin, Hoff Jr., Mazor and Shima61 were instrumental in initiating and developing the microprocessors. Faggin led the team which demonstrated the world’s first microprocessor, and the other advanced microprocessors at Intel and elsewhere. These key developments were undoubtedly responsible for spawning many corporations worldwide catering to new businesses using microprocessors and microcontrollers. It is beyond the scope of this book to give also a history of this exciting part of the development of ULSICs emanating from the invention of the ICs. However, to give a taste of how important a development it is, I shall borrow a few sentences from

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Faggin’s classic editorial comments61 and his paper co-authored with several colleagues as follows: “Few inventions in the history of technology, during their first 25 years of existence, had a faster, deeper, and more widespread impact on society than the microprocessor. . . . the microprocessor industry has grown to such an extent that nearly 70% of all semiconductors sold worldwide are either microprocessors, microcontrollers, or other components used in conjunction with them, such as memory and I/O devices. . . . The market value of all the products incorporating microprocessors is many times that figure, of course — a truly staggering amount. . . .” Since the total world semiconductor market in 2007 was about $250 billion, the market directly related to the microprocessor was $175 billion approximately. The total systems market using them was over $1 trillion annually. (See Chapters 13 and 15.) A very important fact the reader must also realize is that all these microprocessors and other advanced chips are all 2D-Si-ULSICs. To explain it briefly, such 2D (2-Dimensional) chips have all the devices laid out in the 2-dimensional silicon surface layer of the Si wafer, and the 3rddimension is used primarily for the multilevel interconnects above the 2-D silicon surface layer. Some thin-film devices, such as resistors and capacitors, may be fabricated in multiple levels in the 3rd dimension above the main level, the 2-D silicon surface layer level, of the single crystal Si wafer. But these thin-film devices are not fabricated from single crystal Si films. However, almost all the ULSIC materials and device technologies are reaching their engineering if not also fundamental limits that prevent their further performance improvements as well as higher functional packing density for further microminiaturization. To understand these limitations, one has to dig deep into various aspects of reaching these limits. Only a brief list of the rather broad topics is given below without giving their details. 5.1. Materials. 5.2. Equipment. 5.3. Processing. 5.4. Diagnostics/Monitoring.

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5.5. Test. 5.6. Reliability. 5.7. Design. 5.8. Applications/Marketing. The immensity of the above topics is quite overwhelming. That is why hundreds and thousands of scientists and engineers are working all over the world to push the limits of the above, and billions of dollars are being invested annually in just the R&D (Research and Development) of such efforts. Judging from the time when ICs were invented, their advancements to where we have progressed today as ULSICs have been absolutely mind boggling. Just imagine further advancements when paradigm shifts in the materials and technologies are introduced when the 3D-Si-ULSICs and UPICs become realities.20,37,38 The incessant desire to have an ever increasing number of electrical signal processing functions on a chip requires ever increasing number of devices per chip in 2D-Si-ULSICs. This can be achieved only by reducing the dimensions of the devices and interconnects to increase their packing density, and by increasing the chip size and the number of levels of interconnects. From the point of view of the economics of manufacturing, the wafer sizes need to be increased too. The historical trends and their forecast into the future were recently reviewed and updated by Gordon Moore45,46 which has been known in the industry as the Moore’s Law (see Chapter 13). The debate has gone on regarding how small dimensions of the devices and interconnects can be achieved and manufactured economically and profitably in large volume. There are various aspects of this debate which are also beyond the scope of this book. The current status of the practical limit of the small dimensions is expected to reach at about 0.018 µm (or 18 nm). This regime is referred to as the nano-scale CMOS technology, because the dimensions have been shrunk from one-tenth of micron (0.1 µm or 100 nanometer) to the tens of nanometer (nm) range. The latter range is also referred to as the nano-technology encompassing a wide variety of disciplines including nano-tubes made of molecular-size carbon fibers.

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Since CMOS has such a strong history behind its development and in large volume manufacturing, the natural question arises what can be done to milk its attributes further before its limit is reached. Many excellent papers have been written to address this. The challenges and issues of the nanoscale Si CMOS have been reviewed and analyzed. Various technologies and device structures discussed include different types of Sion-insulator (SOI), double-gate-field-effect-transistor (DG-FET), stacked FET, strained-Si FET, SiGe, high-k gate-dielectrics, low-k inter-layerdielectrics, metal gate electrode, and carbon nanotube FET (CNFET). Also new device geometries at even smaller dimensions to provide higher function density such as the recent discovery (March 2007) by Sah and Jie63 on the simultaneous presence of electron and hole surface channels and currents in the experimental data of the nanometer double-gate thinbase MOSFETs, would immediately double the function density of the CMOS ICs without change in the dimensions used in the current nanometer technology. Already, SiGe, high-k gate-dielectrics and metal gates are being implemented in production. Although the proprietary details are not known, a high-k gate-dielectric material of choice is based on Hafnium Oxide (HfO2 ). Its dielectric constant has been reported recently as about 20. It is interesting to note that it is quite close to the value reported by me and Mittal57 about 33 years ago. We had calculated it from the accurate film thickness measurements by ellipsometry. Earlier, the dielectric constant of HfO2 was claimed to be about 3 times larger by a few other investigators, who had made errors in the film thickness measurements of HfO2 . The bottom line is that economics will dictate the continued use of conventional Si devices and related materials, until they become obsolete to deliver cost effective performance. However, paradigm shifts in the technologies are needed to extend the validity of Moore’s Law and introduce new products.48

6. Beyond ULSICs into the future The needs in the future monolithic-ICs require an ever increasing number and types of functions on a chip. This forces us to look beyond the limits of the validity of Moore’s Law. It also implies providing both the electrical and optical functions on a monolithic chip, instead of being

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limited to the electrical functions only as in the present ULSICs. These newer technologies will produce chips heretofore not manufactured, which will enable more complex circuit functions per chip, and they would represent additional huge markets. Essentially, such chips will be advanced systems-on-a-chip (SOC). Some of the market segments, which will have unique advantages with these SOCs, are: Advanced Microprocessors and Microcontrollers; Image Processors; Network/Internet Systems on a Chip; Intelligent Robots; Body Net Systems (vision, speech, hearing, monitoring, etc.); Giga/Terra Memories (all types); Security/Defense. The roadmap of future monolithic ICs has been given above in Section 5. Figure 3.2 shows the roadmap of the evolution of ICs.20,27 It shows two roads to achieve the ultimate in ICs, which are defined as Ultra Performance ICs (UPICs). Figure 3.3 is the same with additional comments on the role of scaling, multilevel interconnections, and the device integration regimes. The users of ICs, such as the designers of computers and almost all the other systems in a large variety of applications, do not care if a particular chip is made of a CMOS, bipolar or BiCMOS technology, or how large is the number of devices on the chip. Its speed performance of complex functions, power consumption, cost, reliability, and a few other external and application factors are more or most important to the users. Therefore, UPICs are needed, in which the active devices like transistors, etc., are fabricated in single crystal Si and in single crystal compound semiconductor films in the 3rd dimension, also grown in the third dimension on the desired respective regions of amorphous insulator films above the Si wafer. The single crystal Si films are used for devices performing the conventional electrical functions. The single crystal compound semiconductor films are used for devices performing optical functions and for faster electrical functions, e.g., in the microwave regime, beyond the limit of Si. Thus, electronic and optical functions can be integrated monolithically on UPICs, whose performance will be superior to that of ULSICs and compound semiconductor ICs in a hybrid package. All the processes developed for the above 3D-Si-ICs and UPICs should be applicable for large volume manufacturing. See recent patents.37,38 Even before considering the UPICs, all-Si 3D-ICs should also be scrutinized carefully since Si is the most used and well established material

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in large volume manufacturing. True 3D-Si-ICs are needed, in which the active devices like transistors, etc., are fabricated in single crystal layers of Si in the 3rd dimension grown on amorphous insulator films on top of the Si wafers. Some ICs currently use amorphous Si films to fabricate devices in the 3rd dimension. However, they are not high performance devices, and their characteristics are not uniform. With the true 3D-SiICs, the number of devices, consequently the number of functions per chip can continue to increase even with normal critical dimensions (CDs), i.e., CDs > 0.10 µm, without pushing the limit of the CDs < 0.018 µm. This is possible because the devices can be stacked in the 3rd dimension at various levels in single crystal layers grown on insulator films in the upper levels in the 3rd dimension also. Thus the 3D-Si-IC technology can then continue to provide at least the same rate of increase of the number of devices per chip, as predicted by Moore’s Law, if not exceed it. The crucial technologies for fabricating all-Si 3D-ICs as well as UPICs are covered by the Saxena patents.37,38 7. Some of the advantages of 3D-Si-ICs over conventional 2D-Si-ICs 1. The mandatory necessity for continued device and interconnect scaling, and to keep on pushing the manufacturing technologies to the limit, for increasing the number of devices per chip with time according to Moore’s Law, is obviated by 3D-Si-ICs. 2. With 3D-Si-ICs, the design rules can be relaxed. This means that the minimum geometries and the alignment tolerances used in the conventional 65 nm when the new 3D-Si-IC technology is used. Relatively speaking, the former requires more stringent manufacturing technologies than the latter. It is important to note that the criterion of the number of devices per chip, or the device density, is not compromised by going to the more relaxed design rules with 3D-Si-ICs. The device density achieved with a conventional 65 nm 3D-Si-IC technology. Moreover, the chip size with the latter having wider CDs can be smaller than with the former having smaller CDs. This is due to the layout advantages of the new >65 nm 3D-Si-IC technology. Such layout advantages are even more striking when an apple-to-apple

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comparison is made for the wider CD (e.g., 65–90 nm) technologies. The chips with the 3D-Si-IC technology can be about 50% smaller, and have less metal and improved performance than those with the conventional 2D-Si-IC technology. The reliability of the 3D-Si-ICs having wider CDs will also be better than that of conventional 2D-Si-ICs with smaller CDs. Thus, several aspects of manufacturing technologies, such as photolithography, reactive ion etching (RIE) and multilevel metallizations should be easier for the 3D-Si-ICs than those needed for the conventional 2D-Si-IC technologies for chips having the same device densities. 3. The reliability of the 3D-Si-ICs will be superior because of the shorter and less metal interconnects. Further, the electromigration lifetimes of the interconnects with wider CDs in 3D-Si-ICs are greater than those with smaller CDs used in the conventional 2D-Si-ICs. 4. Some of the additional advantages of 3D-Si-ICs can be summarized as: fabrication of DG-FETs; many of the device physics problems are minimized; smaller chip size; higher functionality; higher yield; lower cost per function; allows easier parallel processing and architectures to enhance speed for a given design rule. Figure 3.4 shows the cross section of an UPIC chip using both Si and compound semiconductors.38 It shows an example of four layers of devices fabricated on single crystal films of Si and compound semiconductors, and connected to each other with multilevel interconnects. Only the ohmic contact technologies in UPICs will require different metals for Si and compound semiconductors. However, the multilevel interconnects are essentially the same as in the 3D-Si-ICs. The thermal budget requirements in both UPICs and 3D-Si-ICs have to be considered carefully because of the growth of the single crystal Si and compound semiconductor films, and metallizations thereafter. 8. Some of the advantages of UPICs over conventional 2D-Si-ICs 1. All the advantages of the 3D-Si-ICs discussed above, apply to the UPICs. Furthermore, even before attempting to push the technologies into the sub-18 nm regime, or even in the sub-65 nm regime, many unique UPIC

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Fig. 3.4. Cross section of an UPIC chip38 using both Si and compound semiconductors. It shows four layers of devices fabricated on single crystal films of Si and compound semiconductors, and connected to each other with multilevel interconnects.

chips can be produced by using the conventional 65–90 nm technologies. They will make inroads into the market because of several factors discussed below. 2. The UPICs offer the unique capability of combining electrical and optical functions, all on the same monolithic chip. This will open a new vista of single chip systems. UPICs can allow communicating with other electrooptical systems without requiring electrical interconnects/wiring between the two. As an example, robots can be controlled remotely by electro-optical systems. Some of the other examples of UPICs include single chips for smart security, body net, defense, satellite and medical systems. 3. Existing 6 (150 mm) and 8 (200 mm) fabs can be used for manufacturing the 3D-Si-ICs and UPICs, with essentially the same equipment, except for a few changes in the epitaxial growth, ion implantation and metallization equipment. The process integration will

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need to be adjusted for the new process flow. Other key processes such as photolithography, RIE, multilevel metallizations and planarizations shall remain essentially the same. 4. The present trend to increase the wafer size from 8 (200 mm) to 12 (300 mm) and beyond to 16 (450 mm), thereby escalating the wafer fab cost from about 5 billion dollars to colossal larger amounts, and to require equipment migration to ever larger sizes can be stemmed by the 3D-Si-IC and UPIC technologies. In fact these new technologies offer a significant advantage to extend the life of the older 6 (150 mm), current 8 (200 mm) and 12 (300 mm) fabs. The main reason for this advantage is that they allow unique custom chips with high profit margins, which cannot be produced with the current 2D-Si-IC manufacturing technologies and fabs.

5. Other possible impact of the 3D-Si-IC and UPIC technologies could be to replace the bulk single crystal start materials, thereby reducing the demand and the cost of the latter. As an example, single crystal Si films of desired orientations and thicknesses can be grown with these technologies on bulk amorphous quartz substrates of large sizes. These can then replace the bulk single crystals of Si used currently. This feature allows more efficient use of Si, and at a cost potentially lower than the current start materials. Its importance can further be appreciated, when it is realized that the new start material shall have single crystal Si of a desired orientation and thickness only where it is needed. This can simplify the isolation technologies and the entire process integration also. 6. The new 3D-Si-IC and UPIC technologies will also have a significant impact on the large area flat panel displays, TVs and other unique applications. The former has been already in the large volume production which has driven the price of the LCD TV down by about factor of two annually. However this technology does not employ the single crystal Si films, which are described in the recent patents.37,38 9. Future Obviously the economics will be dominant in determining which new technologies will ever come to fruition and become a reality to prevail.

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This implies large volume manufacturing, meeting and exceeding the needs and lowering the cost of existing applications, creating new applications, acceptance by the political and social changes, marketing and distribution. Despite some promising new technologies, there is plenty of room still for advancing the current well established CMOS technologies. Nevertheless, paradigm shifts in technologies need to be explored in the future. As an example, a technology will be very welcome to have a silicon light emitter with sufficient optical efficiency at low power dissipation, compatibility with existing processes, and economic manufacturing. A few advanced research labs have claimed that they are close to achieving this, but it has not yet been proven in manufacturing. Not only existing product designs can be implemented with these new technologies to produce improved and more profitable chips, but newer chips with unique capabilities heretofore not possible to serve the markets can be manufactured. Thus, the future of the microelectronics industry is quite promising indeed.

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Chapter 4

Monolithic vs. Hybrid Concepts in ICs

At the outset, we shall clarify the meaning of the word “monolithic” itself, and then we shall explain how it has been and is used in the entire microelectronics industry. It is important to understand this, because its use has not been consistent in the literature. Even Kilby, who was awarded the Nobel Prize in Physics7 in 2000 “for his part in the invention of the integrated circuit”, and was a person of giant stature in many ways, wrote17 as recently as in 1998 that “Despite these introductions, the monolithic concept remained controversial.” Riordan and Hoddeson16 gave historical account of the era from the birth of the transistor to the beginning of integrated circuits. Their last chapter is on “The Monolithic Idea”, as they gave their concluding remarks in their book on the advent of integrated circuits. However, they ascribed erroneously the accomplishment of Kilby’s reduction to practice as “The monolithic idea was finally a reality.” It was not a reality in totality, but only a partial reality, and that too in only a small way. That is because Kilby’s reduction to practice was a hybrid-IC, not a monolithic-IC (see Chapter 7 for details). Briefly, Kilby had used mesa devices fabricated monolithically in Ge, but they were interconnected by wire-bonding; none of these are used to fabricate monolithic-ICs. In the English language, “Monolithic” is the adjective of the noun, “Monolith”. The meaning of “Monolith” in dictionary is given by three expressions. 1. A single block of stone especially shaped into a pillar

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or monument. 2. A person or thing like a monolith in being massive, immovable, or solidly uniform. 3. A large block of concrete. None of the above meanings of monolithic convey its usage in electronics quite accurately, either literally or in spirit, except perhaps for its reference to a “solidly uniform” thing. Far from being “massive” and “immovable”, the semiconductor based microelectronics circuitry has been able to achieve almost the ultimate in miniaturization by using the monolithic-ICs, which are not massive; they are movable and portable. However, the “solidly uniform” thing has to be scrutinized carefully. The basic monolithic structure may be “solidly uniform”, but the sub-structures at different levels may neither be “solidly uniform”, nor contiguous to the entire surface of the base. A few examples are: the polycide Si-gate metalizations, planarized contacts to salicided source/drains of CMOS transistors, and vias of multilevel interconnects. However, a monolithic-IC chip is one whole solid piece with different materials on a piece of single crystal Si. It does not have the mesa structures for the devices or any dangling wires bonded to connect them, even when the separate devices may have been fabricated by using planar technology in one solid block of Si. For the ease of discussion, and to conform to the general usage of the terms in practice, only two stages (Hybrid and Monolithic) of miniaturization shall be described below.

1. Hybrid-integrated circuits (hybrid-ICs) In hybrid-ICs, the active devices (e.g., transistors, diodes) are fabricated singly or collectively on or from suitable semiconductors (e.g., Ge or Si). The other passive devices (e.g., resistors and capacitors) could be fabricated from the same semiconductors, and/or from different materials. Inductors shall be ignored in all of these discussions, because they are not used in monolithic-ICs, which are the main focus of this book. Inductors are used in r.f. hybrid-ICs which are fabricated with evaporated and etched metal films on insulating substrate, on which a compound semiconductor chip for r.f. power generation is also attached by soldering. This is similar to the silicon CMOS digital chip soldered down on the substrate for digital processing of the digitally converted r.f. signal.

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The above active and passive devices, unpackaged or packaged are mounted on or inserted in the substrates having interconnects already formed in them (e.g., PCBs, silk-screened ceramic substrates, glass, highresistivity semiconductors, plastic, etc.), and additional wire bonding is then followed as required between the various electrical contact regions of the devices and the interconnects of the circuit. Such circuits are called hybrid-ICs. However as discussed briefly in the previous Chapter 3, to clarify their evolution and to differentiate between those hybridICs fabricated with “Packaged Chips” or “Unpackaged Chips”, I have introduced a new terminology as follows. 1.1. Hybrid-ICs fabricated with Packaged Chips = Hybrid-PC-ICs. 1.2. Hybrid-ICs fabricated with Unpackaged Chips = Hybrid-UC-ICs. Neither of the above two types of hybrid-ICs necessarily has all the active and passive devices fabricated within or on the same piece of the semiconductor. Moreover, these devices and the wire-bonded interconnects in such hybrid-ICs are not contiguous to a single surface, be it may of the substrate or the semiconductor. Hybrid-PC-ICs are self-explanatory. Essentially a circuit constructed with vacuum tubes was miniaturized by replacing them with the packaged solid state devices initially sold in the market. As an example, Sony sold miniaturized radios starting in the mid-1960. They were not only smaller than those having the vacuum tubes, but they were cheaper, better performing, more reliable and portable. Hybrid-UC-ICs went through various stages of development. In one stage, it used circuit elements, which had some of the devices fabricated monolithically (viz., all in one block; explained in detail in the next section) within a semiconductor (e.g., Ge or Si). As an example, several transistors and diodes were fabricated in one piece of the semiconductor, and the resistors and capacitors in another piece. These semiconductor pieces were glued, attached or bonded to a suitable insulating substrate like glass, ceramic or PCBs, and the devices were connected by wire-bonding or alloying according to the circuit design, dangling in air above the substrate, not contiguous or adherent to its surface. Such a circuit may have had pieces with devices fabricated monolithic to each piece, but the interconnections

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between the devices and the semiconductor pieces were not monolithic to the entire circuit. Thus such a circuit was not one whole block of a solid unit. Therefore, it was a hybrid-IC, not a monolithic-IC. Precisely speaking, this is exactly how Kilby had reduced his invention to practice using Ge mesa devices and wire bonded gold (Au) interconnects to connect the devices, viz., Kilby’s reduction to practice was a hybrid-UC-IC. In another development of the hybrid-UC-ICs, all of the active and passive devices were fabricated monolithically within or on a single piece of the semiconductor. Such a piece of semiconductor was glued, attached or bonded to a suitable insulating substrate like glass, ceramic, PCBs or high resistivity semiconductor, and the devices were connected by wire bonding or alloying according to the circuit design, dangling in air above the substrate, not contiguous or adherent to its surface. Such a circuit was also not one whole block of a solid unit. Therefore, it was also a hybrid-IC, not a monolithic-IC. Several permutations and combinations of the above type of fabrication of integrated circuits were used. However, none of them were one whole block of a solid unit. Thus, they were all hybrid-ICs of one kind or another. Even the IBM360 mainframe computer was built with such so-called “Solid Modules” on a ceramic substrate with evaporated-etched-defined interconnects to connect the individual chips that were soldered onto the lines on the substrate. They did not use the dangling interconnecting wires for interconnects, as were used by Kilby in the reduction to practice of his invention of a hybrid-IC in 1958. The “Solid Modules” approach made it possible to completely automate all the manufacturing steps of all the modules with different circuit functions needed for a mainframe computer. They were produced efficiently and economically at an automated chip factory, the IBM silicon IC factory in East Fishkill, New York, which was the first automated factory in the entire industry. However, it was still a hybrid-IC approach for the computer, not a monolithic-IC such as the microprocessor. 2. Where do we draw the line in hybrid-ICs to define the onset of miniaturized Integrated Circuits? As described above, the term “Integrated Circuits” is restricted to the miniaturized electronic circuits using solid state devices, such as

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semiconductor transistors, diodes, resistors and capacitors on a chip. The miniaturization of electronic circuits began with the advent of hybridICs. The ultimate in miniaturization occurs in a monolithic-IC (described below in Section 4.3), for which the acronym IC is used. The answer to the question “Where do we draw the line in hybrid-ICs to define the onset of miniaturized Integrated Circuits?” is somewhat arbitrary, because of the permutations and combinations of their fabrication referred to above. Kilby’s invention of the ICs, for which he was awarded the Nobel Prize in Physics in 2000, was a hybrid-IC, perhaps more hybrid than all the subsequent hybrids. (See above Section 1, and Chapters 7 and 12.) The reduction to practice, i.e., demonstration of his invention, was not one whole block of solid unit, so it was not monolithic-IC (see above Section 1). To give some details, Kilby’s first demonstration device was a phase-shift oscillator which used only one mesa transistor fabricated in a piece of Ge. Kilby’s second demonstration device was a multivibrator which used two mesa transistors fabricated in a piece of Ge. The resistor(s) and capacitor(s) were fabricated in another piece of Ge. Each respective Ge piece was glued to a substrate such as glass slide. The transistors in one piece of Ge were wire-bonded to the resistors and capacitors on another piece of Ge, which was also glued to the same substrate glass slide. Thus, Kilby’s invention more precisely was for a hybrid-UC-IC, not a monolithic-IC. The IBM silicon Solid-Module for the IBM360 mainframe was perhaps the closest to Kilby’s invention of hybrid-UC-IC. Instead of using dangling gold wires a la Kilby, IBM replaced them by evaporated aluminum films, patterned by etching into narrow aluminum metal lines, and interconnected several single-device chips of bipolar silicon transistors, silicon p/n junction diodes, and resistors. A few of the workers in this field of microelectronics, who have contributed not only to hybrid-ICs, but also to the planar and other advanced technologies for the monolithic-ICs, could then qualify more to be credited as the inventors of the ICs than Kilby and Noyce. Going one step further, if a select fewer workers went on to contribute to the next generation monolithic 3D-ICs and UPICs also, for sure they should then qualify even more for the recognition and appreciation than those whose contributions were limited to the stage of hybrid-ICs only. While these criteria appear to be quite logical, no priority has been assigned preferentially

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to such accomplishments so far to be given recognition also for the invention of ICs. However, the answer to the question “Where do we draw the line in hybrid-ICs to define the onset of miniaturized Integrated Circuits?” can be derived from the actual invention of ICs by Kilby, as well as the recognition given to him by the Nobel Committee. Even though as explained above in detail, Kilby’s invention was only a hybrid-UC-IC (and not a monolithicIC; see next Section 3), the line to be drawn in favor of Kilby and answer the above question is as follows: 2.1. The active devices are fabricated (e.g., using mesa technology used by Kilby, but not restricted to it) singly or collectively in a piece of semiconductor (e.g., Ge used by Kilby, but not restricted to it). 2.2. The passive devices are fabricated (e.g., using mesa technology used by Kilby, but not restricted to it) singly or collectively in the same or another piece of semiconductor (e.g., Ge used by Kilby, but not restricted to it). 2.3. Single or multiple pieces of the semiconductor (e.g., Ge used by Kilby, but not restricted to it) with unpackaged devices are glued, cemented or attached (e.g., glued used by Kilby, but not restricted to it) to an insulating substrate (e.g., glass slide used by Kilby, but not restricted to it). 2.4. Devices are connected by wire-bonding (e.g., Au wires used by Kilby, but not restricted to it) going from one device or region to another, the wires being neither contiguous nor adherent to either the semiconductor or the insulating substrate. 2.5. The entire circuit constructed as above (by Kilby) was a hybridUC-IC, not a monolithic-IC (explained in detail in sections 1 and 2 above, and below in Section 3). In addition to the above facts, the readers should keep in mind that huge numbers of IBM360 mainframes were produced in which the Solid Modules were used. It is well known that IBM360s dominated all the computer applications at that time. The concept and the use of Solid

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Modules was just one step beyond Kilby’s hybrid-UC-IC “obvious to those familiar with the art”. Thus from now on in this book, hybrid-UC-ICs with unpackaged devices wire-bonded together shall be used to define the onset of miniaturized Integrated Circuits a la Kilby’s invention of the ICs.

3. Monolithic-integrated circuit (monolithic-IC) In monolithic-ICs, all the active and passive devices are formed and fabricated in and on the surface of a single piece (chip) of a single crystal semiconductor, e.g., Si, wafer (substrate). But correct technologies for forming and fabricating the devices must be used. Mesa technology specified and used by Kilby for his invention is wrong. It will not work for monolithic-ICs; the planar technology must be used as was done in Noyce’s invention. Also, fabrication alone of the active and passive devices in the same chip in one block (monolith idea) is not enough, because they must be interconnected contiguous and adherent to the insulating layer over the same body of the semiconductor to produce a monolithic-IC. If the devices are fabricated within the same body of the semiconductor, but they are interconnected by bonding wires dangling over the chip, such an IC is not a monolithic-IC anymore; it is then a hybrid-UC-IC. This is explained in detail in the previous Section 1. To re-emphasize, only after all the steps of fabrication and isolation of devices within the same semiconductor body (chip) with the correct technology, and their interconnections contiguous and adherent to the insulating layer over the semiconductor surface are completed, only then a monolithic-IC is produced. In practice, each wafer has a large number of chips laid out in arrays. In monolithic-ICs, each fabrication step is done on the wafer as a whole, i.e., simultaneously on every chip on the wafer. The only exception to this is in photolithography with the advent of steppers a few decades ago, when each die is aligned and exposed individually on the wafer. However, the associated processes of applying and developing the photoresist are done simultaneously at each level over the entire wafer. Each respective process step of depositions and/or growth of the various films/layers are done contiguous to the entire surface of the wafers, and the respective

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post-exposure photolithographic masking and etching processes are used to delineate the patterns of the ICs simultaneously over the entire array of chips on each wafer. All the devices in each chip of the monolithic-ICs are interconnected by suitable multilevel metallizations (e.g., Al) as needed by the circuit design, contiguous and adherent to the insulating layers over the entire surface of the wafer. (The materials for contacts and interconnects are not evaporated through masks in monolithic-ICs, which were specified by Kilby1,23 for his invention.) This necessitates that all the interconnects must go over the insulating layers (e.g., SiO2 ) from one device to another, as well as from one interconnect level to another in each chip. The p–n junction edges must be covered in-situ during their fabrication by the insulating layers, so that the interconnects do not short the junctions with the adjacent regions. This is the fundamental invention of planar technology (Hoerni8 ). Moreover, appropriate isolation techniques are also used for the electrical isolation of devices and circuit elements within each chip (Lehovec9 ; Kooi25 ). The entire surface of a completed monolithicIC chip is contiguous to the surface of the single crystal semiconductor substrate. The monolithic-IC chip is one solid body, and it does not have any dangling wires bonded to different devices and regions, as it does in the hybrid-UC-ICs. To do all of the above and manufacture monolithic-ICs, the use of planar technology (Hoerni8 ) for fabricating various devices, such as transistors and diodes, in a single piece of semiconductor is mandatory. Mesa technology and wire-bonding (used by Kilby1,22 ) for fabricating and interconnecting the devices will be extremely difficult if not impossible to use for manufacturing monolithic-ICs, especially at the integration levels of today. The above explanations prove unequivocally that Kilby’s invention of the integrated circuit was a hybrid-UC-IC, not a monolithic-IC. Noyce’s invention of the integrated circuit was a monolithic-IC, not a hybrid-UCIC. Kilby demonstrated his invention by using Ge mesa transistors glued to a glass slide, and the devices were wire-bonded to interconnect them. These are not used in manufacturing the ICs.

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Noyce did not reduce to practice his invention, which was written but un-witnessed in his lab notebook. However, he had specified Si planar technology, Al interconnects adherent to and going over SiO2 layers without shorting p–n junctions, photolithography and etching techniques which are all used in manufacturing the ICs. Turning Noyce’s invention into reality was done by several other people. Kilby made no contributions to the Si planar technologies even after it was well established that they were mandatory for the manufacturing of the monolithic-ICs. Kilby’s specifications of the interconnect materials and processes in his patents are also unusable in manufacturing the monolithicICs. Kilby did not make further contributions to the monolithic-ICs after his invention of hybrid-UC-IC. Kilby must have known from the early years, as did the corporation he worked for, viz., Texas Instruments, and the entire microelectronics industry, that the planar and other technologies mandatory for monolithic-ICs were invented by several other people, e.g., Hoerni,8 Lehovec,9 and Noyce.2 Even though Noyce received a few patents after his basic IC patent, and had published a few papers, he made no direct contributions to the advanced or the next generation ICs himself. However, Noyce made major contributions to the entire field when he co-founded Intel Corporation with Moore where many of the most advanced USICs have been developed, and is now the leading IC manufacturer in the world. Finally, the application of these silicon monolithic ICs in the mainframe was again at IBM first in the IBM370 series, which were the next generation mainframes following the IBM360.

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Chapter 5

Summary of the IC Fabrication, Inventions, Relevant Patent Filings and Issue Dates, and Methodology of Analyses and Numbering

1. Summary of IC fabrication In order to understand the IC inventions of Kilby, Noyce and the others, their relevant patent filings and issue dates given in this chapter, I shall give at the outset the fundamentals of how a monolithic-IC is fabricated. As emphasized in the earlier chapters, this is the only kind of IC that is important to know all about, as it is the only kind sold in the market from the inception of the chip industry onwards. To clarify and re-emphasize this statement further, from the standpoint of chips, only the monolithic-ICs in packaged as well as unpackaged forms were sold from the very beginning in the industry. The unpackaged forms of the monolithic-IC chips were sold in the beginning to IBM for the “Solid Modules” used in their IBM370 mainframes, which were at that time the next generation mainframes to their IBM360. Later on the “Solid Modules” were replaced by using allpackaged monolithic-ICs in the IBM mainframes, and in those by other manufacturers. (See also Sections 1 and 2 in Chapter 4.) How do the monolithic-ICs differ from the other types of ICs such as hybrid-IC, has been explained in Section 3 of Chapter 4. The key steps for its fabrication and whether or not they were met by Kilby and Noyce in their respective inventions have also been given in Table 1.1 in Chapter 1. But I shall re-state them with a few additional comments

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as follows: 1.1. All devices must be fabricated in the same single crystal Si substrate. Other semiconductors (like Ge used by Kilby) do not lend themselves to their use in planar technology (see next step). 1.2. Planar technology must be used to fabricate the above devices. This technology protects the edges of the junctions from being shorted by the contact and interconnect metallizations. (Mesa technology used by Kilby exposes the junction edges to metallizations causing shorting and leakages.) Hoerni8 has been credited in the literature with the invention of planar technology. However, as it has been documented in the next Chapter 6, Hoerni did not invent the planar technology all by himself; it was built upon a combination of important discoveries of a few other people earlier, the crucial work done by Sah,10 and key inputs from the test engineer(s) doing the electrical characterizations of the transistors. 1.3. All the devices must be isolated from one another by an appropriate planar technology (e.g., p–n junction, LOCOS, trench). The most important technique to isolate the devices initially was invented by Lehovec9 by using the p–n junctions. It was soon replaced almost completely by the LOCOS technique invented by Kooi25 and the trench isolation invented by several technologists later. (See next Chapter 6). Nevertheless, it must be remembered that Lehovec’s invention was crucial for the invention of ICs. 1.4. All the devices must be connected by planar interconnections adherent to oxide surface. Kilby did not accomplish this, and he had used bonded gold wires flopping over the chip from one device to another. This factor was a key part of Noyce’s invention, and cost Kilby the sole ownership of the IC invention. Therefore keeping the above four steps in mind as the readers proceed in this chapter and subsequently, it will be easier to understand the important facts of the IC inventions of Kilby and Noyce. They are given in Table 5.1 below. Since the IC inventions of Kilby and Noyce are the main focus of this book, the reader will benefit by knowing these important facts also ahead of time before reading the detailed analyses of Kilby’s and Noyce’s patents in Chapters 7 and 8 respectively. It is easy to get bogged down in the details as evidenced by the lack of actions on the part of most if not all the senior

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most technologists, scientists and patent attorneys of the world. As I have already pointed out in my paper,12 all the issues of the IC inventions are inextricably entwined technically, chronologically, and legally patent wise. Therefore it is better to stay focused on the important facts rather than get mired with the rest of the details. Everything is given for the sake of completeness, so the readers can guide themselves from different angles on the key issues and facts. Next in this chapter, I shall give the updated Table 5.2 to summarize the relevant patent filings and their issue dates, and earlier unpatented but documented work, of Kilby, Noyce and several other key contributors. All the references of the documents have been given, so that any reader(s) can follow up for details of the information given by me. For the sake of comparison with a similar table published by me in the earlier NSTI paper,12 I shall also list them in Table 5.3. The NSTI paper was limited in scope due to the length limitation of the conference proceedings. The listings are chronological according to patent filing and publication dates. As it is well known, listing patent filing dates and public disclosures chronologically documents the origin and sequence of conception of an invention, which is not reflected by the issue dates of the patents. The issue dates were the only public-domain dates, unlike the repeatedly changed, modified, and updated, copyright law of today. The process in between the filing and the issue dates of the patent during the older days, as well as what each inventor did beyond his respective invention to advance its technology to what it is today, are also important to acknowledge and critique the features of each contribution. It shall be noted that Kilby’s patents and claims are rather controversial because of the dubiously glaring patent issuing dates and the subsequent cited patent numbers and dates by Kilby in his own journal articles recollecting the history. For the detailed discussion of Kilby’s patents, see Chapter 7. 2. Summary of the inventions of integrated circuit by Kilby and Noyce as documented in the literature Summary of the inventions of integrated circuit by Kilby and Noyce as documented in the literature is given in Table 5.1.

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Table 5.1. Important Facts 1. What was the basic concept of the invention as written in their key patents: Kilby’s 3,138,744; Noyce’s 2,981,877? Note: Kilby did not refer to 3,138,744 in his 1998 paper19 ; instead he chose to refer to 3,138,743 in which the concept of monolithic-ICs was not mentioned at all in its text or claims. Controversy is glaring also over application no. 791,602 claimed by Kilby to be filed on Feb. 6, 1959 for patent no. 3,138,743. (See Chapter 8, Section 15.)

Summary of IC inventions by Kilby and Noyce. Kilby

“. . . .various circuit elements including diodes, transistors, and resistors all be formed within a single block of semiconductor material, thereby eliminating the necessity for separate fabrication of the semiconductor devices and the interconnections as mentioned above.” (cf: Kilby1 : column 1, lines 58–62; it is not written in Kilby22 ). The basic concept stated above in Kilby’s 3,138,744 was only partly consistent with the concept of monolithic-ICs, and that too in a limited way. Kilby did not state nor specify how these devices formed within a single block of semiconductor were to be interconnected within the same block of semiconductor for a given IC function, and Kilby did not assure that the interconnects and the devices were properly isolated electrically. Also regarding the fabrication of the devices within a single block of semiconductor, Kilby did not suggest, even mention the need of the correct fabrication procedures or sequence in his issued patent 1 to accomplish what he had proposed or invented. The reduction to practice, and the materials and technologies specified by Kilby in his patent 1 and in

Noyce “. . . .the present invention utilizes dished junctions extending to the surface of a body of extrinsic semiconductor, an insulating surface layer consisting essentially of oxide of the same semiconductor extending across the junctions, and leads in the form of vacuum-deposited or otherwise formed metal strips extending over and adherent to the insulating oxide layer for making electrical connections to and between various regions of the semiconductor body without shorting the junctions.” (cf: Noyce2 : column 1, lines 24–32). From this paragraph above, it should be obvious to the readers that Noyce stated it all in the very first paragraph of his patent. In fact, this is essentially how the monolithic-ICs were made then, all throughout the past 40 years, and even today.

(Continued )

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Table 5.1. Important Facts

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(Continued )

Kilby

Noyce

the original application 23 to fabricate the devices and the interconnects were not consistent with the monolithic-ICs. Hybrid-IC with mesa devices, not planar devices; wire-bonding of devices, not monolithic interconnects (cf: Figs. 3 & 4 of patent1 ; Figs. 4,5,6 & 8 of original application23 ). Application serial no. 811,486 filed on May 6, 1959 for patent no. 3,138,744. (Controversy over application serial no. 791,602 claimed by Kilby to be filed on Feb. 6, 1959 for patent no. 3,138,743. See Chapter 8, Section 15.)

Monolithic-IC.

4. Test circuit(s) defined.

Yes (phase-shift oscillator; multivibrator)

No (but defined by others under the direction and management of Noyce as the Director of the Fairchild R&D Laboratory).

5. Reduction to practice of original invention.

Yes; Phase-shift oscillator — used a single Ge mesa transistor (not used in ICs), glued Ge to glass slide (not used in ICs), wire-bonded (not used in monolithic ICs; used only in hybrid ICs such as those in the IBM360 mainframe and in the current wireless phones and other high-transmitter-power applications) to 2 resistors and a capacitor; Multivibrator — used 2 Ge mesa transistors, glued Ge to glass slide, wire-bonded to 6 resistors and 2 capacitors.

Yes (but with the others using Si planar technology, and Al interconnects adherent and contiguous to SiO2 , which are used in all monolithic ICs fabricated or manufactured to-date).

2. What was actually invented as described in the issued patents?

3. First public disclosure of the inventions.

US patent filed on July 30, 1959. (Note that this was after Kilby’s filed on May 6, 1959.) There was no controversy regarding Noyce’s filing date.

(Continued )

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Table 5.1. Important Facts

(Continued )

Kilby

Noyce

6. Proof of the original invention.

US Patent nos. 3,138,743 and 3,138,744 (note their nos. differ by only one) issued on the same date Jun. 23, 1964; contested in courts for their delayed issue 3 yrs after Noyce’s patent; Kilby’s suit was lost partially because it was resolved that both Noyce’s and Kilby’s patents were essential for ICs; Kilby’s suit against Lehovec9,26 for p–n junction isolation was also lost (see Chapter 9).

US Patent no. 2,981,877 issued on Apr. 25, 1961. (Note that this was much earlier than Kilby’s patent issued on June 23, 1964.)

7. Contributions to planar and monolithic-IC technologies?

No

Yes; 4 US Patents since the above IC patent was issued, a most essential virtue expected of a genuine inventor by the community and practice of patent law.

8. Contributions to other advanced IC technologies, 3D-ICs and UPICs?20,27,28

No

Yes. While filing the IC patents, also led and personally (hands-on) developed the industrial first step-and-repeat camera for Fairchild which was used for manufacturing the first generation double-diffused silicon bipolar transistors and logic integrated circuits. About ten years later, also co-founded Intel Corporation, authored the first silicon gate article in the electronics journal, and in addition, directed the entire team at Intel who has led the world in inventing and putting into manufacturing the new technologies.

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2.1. Kilby’s strong and weak points; important original figures STRONG: 1. Kilby’s basic concept as stated for integrated circuit could be stretched to give a monolithic-IC (but Kilby did not even suggest the correct procedures to accomplish what he had stated). Whether Kilby’s basic concept was derived from Dummer’s cannot be ascertained. Nevertheless, Kilby’s bonded and dangling wires were so “obvious to those familiar with the art” that required only one-step-advancement in the manufacturing art by the IBM engineers to mass produce the so-called “Solid Modules” for the IBM360 Mainframe computer. It was the first automated factory of its kind in which billions of ceramic substrates with customized interconnected devices for the Solid Modules were manufactured. They were similar to Kilby’s hybrid-IC, except that the dangling wires were replaced by evaporated thin aluminum films on ceramic substrates, which were chemically etched to narrow lines for interconnecting the device chips. This then led to the next generation of IBM360, viz., IBM370 in which “Solid Modules” with Noyce’s true monolithic-ICs were used. However from a pedantic point of view, the “Solid Modules” were hybrid-ICs in which manytransistor silicon chips for different functions were still soldereddown to the interconnecting-metal-lined ceramic chips. They were really just larger-size and higher-function hybrid-ICs. 2. Kilby reduced to practice his concept of integrated circuit, at least as a hybrid-IC (but not as a monolithic-IC).

WEAK: 1. Kilby’s reduction to practice of his invention was that of a hybrid-IC, not a monolithic-IC which is the only type that are fabricated and sold in the entire IC market. 2. Kilby used Ge which is not used for any Si monolithic-ICs sold currently. 3. Kilby used mesa technology for devices which is not used for any recent or past monolithic-ICs which depended on the “planar” process invented by Hoerni (see Chapter 6).

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4. Kilby glued Ge pieces to glass slide which is not used for monolithic-ICs (if we exclude the large area glass-substrate used by the flat-panel LCD monitors). 5. Kilby used wire-bonding for interconnects, which is not used for monolithic-ICs. 6. Kilby’s patent was filed earlier than Noyce’s, but it was awarded after Noyce’s. 7. Kilby made no contributions to planar and monolithic-IC technologies after his invention, even though it was known that they were mandatory for the monolithic-ICs. 8. Kilby made no contributions to advanced IC technologies, or 3D-ICs, or UPICs after his invention.

IMPORTANT ORIGINAL FIGURES: 1. Figure 6.1 shows Figs. 1–4 copied from Kilby’s1 patent no. 3,138,744. Note the mesa structures in Kilby’s Figs. 3 & 4 (instead of the planar structures which are necessary in monolithic-ICs). Mesa technology was invented at Bell Telephone Laboratories and first used in mass-produced silicon transistors by Fairchild Semiconductor which actually used also Hoerni’s planar process to define the emitter of the first commercial silicon n/p/n and p/n/p double diffused silicon transistors. 2. Figure 6.2 shows Figs. 1-5 copied from Kilby’s23 patent application no. 03/791,602. Note the mesa structures in Kilby’s Figs. 4 & 5 (instead of the planar structures which are necessary in monolithic-ICs). 3. Figure 6.3 shows Figs. 6 & 8 copied from Kilby’s23 patent application no. 03/791,602. Note the wire-bonding in Kilby’s Figs. 6 & 8 (instead of the monolithic interconnects which are necessary in monolithic-ICs).

2.2. Noyce’s strong and weak points; important original figures STRONG: 1. Noyce’s concept for ICs was for monolithic-ICs, which are the only type manufactured and sold in the IC market from the

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very beginning (not counting the hybrid-IC used by the IBM360 which was not sold as stand-alone hybrid-ICs, only as part of the IBM360 mainframe computer). 2. Noyce specified Si which is used for monolithic-ICs. 3. Noyce specified planar technology for devices which is used for monolithic-ICs. 4. Noyce specified Al interconnects which are adherent and contiguous to the SiO2 surface, and are used for monolithicICs. 5. Noyce’s patent was filed a little after Kilby’s, but it was awarded much earlier than Kilby’s. 6. Noyce made some contributions to the monolithic-IC technologies after his invention.

WEAK: 1. Noyce’s IC concepts, though correct, were written in his notebook at Fairchild, but they were not witnessed by anyone with signature as far as we can determine. However, it can be anticipated that his ideas were disclosed at least to several cofounders of Fairchild, and managers and engineers under his command in the Fairchild R&D Laboratory for which he was the first Director of Research. 2. Noyce did not reduce to practice his invention; it was done by the others in the Fairchild R&D Laboratory. 3. Noyce made little or no direct contributions to the advanced IC technologies, 3D-ICs, or UPICs after his invention, although he did co-found Intel Corporation where most of the advanced technologies were and are still being developed and put into manufacturing first.

IMPORTANT ORIGINAL FIGURES: 1. Figure 6.4 shows Figs. 3, 4 & 5 copied from Noyce’s2 patent no. 2,981,877. Note the planar structures and monolithic interconnects in Noyce’s Figs. 3 and 4 (instead of the mesa structures and wire-bonding). Figure 5 just shows the circuit diagram of Noyce’s invention.

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3. Sequence of relevant patent filing and issue dates In order to understand the facts about the invention of the ICs, it is important for us to know the filing and the issue dates of a few relevant patents, and earlier unpatented but documented work. The sequence of the filing and issue dates of Kilby’s and Noyce’s patents are listed in Table 5.2. The same are included only for a few of my patents and documents also Table 5.2. Filing and issue dates of patents and publications relevant to IC inventions (Updated version for this book). Patent no.

Filing date/ Publication date

Issue date

Dummer4

None filed

May 6, 1952

(Technical paper)

• Johnson5 • SaxenaApp.2

2,816,228 None filed

May 21, 1953 July, 1953

Dec. 10, 1957 See Appendix 2 (Technical paper)

• Kilby22 (ICs)

3,138,743 Application Serial No.23 03/791,602.

Claimed by Kilby to be Feb. 6, 1959. (No official record30 of this filing date. Official records show only May 6, 1959, as the filing date.29 See Fig. 6.5 and Fig. 6.6)

June 23, 1964*

• Stewart6

3,138,747

Feb. 12, 1959 No controversy about this filing date, unlike the one above for Kilby’s OA and patent no. 3,138,743.

June 23, 1964* Note its patent no. differs by 4 from Kilby’s patent 3,138,743, and by 3 from Kilby’s patent 3,138,744, all awarded on the same date and assigned to the same company, TI.

• Lehovec9 (Isolation)

3,029,366

Apr. 22, 1959

April 10, 1962

• Hoerni8 (Planar Tech.)

3,025,589 3,064,167

May 1, 1959 May 1, 1959

Mar. 20, 1962 Nov. 13, 1962

• Kilby31

3,072,832

May 6, 1959

Jan. 8, 1963

• Kilby32

3.115,581

May 6, 1959

Dec. 24, 1963

•

(Continued )

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Chapter 5. Summary of the IC Fabrication, Inventions, Relevant Patent Filings Section 3. Sequence of relevant patent filing and issue dates

Table 5.2.

79

(Continued )

Patent no.


• Kilby1 (ICs)

3,138,744

May 6, 1959

Jun. 23, 1964* (Key patent) Note its patent no. differs by only 1 from his patent 3,138,743, and by 3 from Stewart’s patent 3,138747, all awarded on the same date and assigned to TI.

• Noyce2 (ICs)

2,981,877

Jul. 30, 1959

Apr. 25, 1961 (Key patent) See Fig. 6.4.

• Last33 (Isolation)

3,158,788

Aug. 15, 1960

Nov. 24, 1964

• Kilby34

3,261,081 Ser. No. 352,380

Original appl. as Feb. 6, 1959; this appl. Mar. 16, 1964.

July 19, 1966

• Last35 (Isolation)

3,313,013

Original appl. as Aug. 15, 1960; this appl. Nov. 24, 1964.

Apr. 11, 1967

• Dummer4.2

None filed (Technical paper)

December, 1964

(Technical paper)

• Kooi25 (LOCOS)

3,970,486 3,752,711

Oct. 3, 1966 Jun. 4, 1970

Jul. 20, 1976 Aug. 14, 1973

• Saxena36 (Interconnect)

3,687,722

Mar. 10, 1971

Aug. 29, 1972

• Kilby21

None filed July, 1976 (Review (Review paper) paper) [Gave historical review of his IC invention.]

• Kilby19

None filed Mar. 31, 1998 (Technical (Technical paper) paper) [Made comments on his and Noyce’s original patents1,2 , “monolithic ICs”, and Dummer’s4 approach to “. . . envisage electronic equipment in a solid block with no connecting wires.”]

Issue date

(Continued )

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Table 5.2.

(Continued )

Patent no.


Issue date

• Saxena37 (3D-ICs & UPICs)

6,110,278

Aug. 10, 1998

Aug. 29, 2000


6,392,253

Aug. 6, 1999

May 21, 2002

Note: The asterisk * in Table 5.2 is to draw attention to the same date on which Kilby’s patents 3,138,743 and 3,138,744, and Stewart’s patent 3,138,747 were awarded, all assigned to Texas Instruments. Note also that Kilby’s patent numbers differ by only 1, and Stewart’s patent differs from Kilby’s by 4 and 3 respectively.

in this table for the sake of continuity and sequencing, although their details and other documents relevant to the IC invention are given in Appendix 2. The patents and earlier unpatented but documented work are listed chronologically with patent filing dates and public disclosures from publications. To emphasize, listing patent filing dates and public disclosures chronologically is important because it documents the origin and sequence of conception of an invention, which is not reflected by the issue dates of the patents. The process in between the filing and the issue dates of the patent, as well as what each inventor did beyond his respective invention to advance its technology to what it is today, are also important to acknowledge and when critiquing each contribution. For Kilby and Noyce, they are discussed in detail in Chapters 7 and 8 respectively, whereas for the others, they are given in Chapter 9. In addition to the key documents and patents of Kilby and Noyce on the invention of ICs, only a few patents of Lehovec, Hoerni, Kooi and mine are also listed in Table 5.2 above, because of their relevance to the invention of the original and the next generation ICs. For details of my patents and documents, see Appendix 2. The acronym 3D-ICs refers to 3-dimensional ICs, in which the active devices are also fabricated on a chip in the 3rd dimension above the surface of the single crystal Si wafer (henceforth referred to only as Si wafer), in addition to those fabricated in 2-dimensions on and near the surface of the Si wafer. The latter is done in all types of ULSICs being manufactured today. These ULSICs are all 2D-ICs, and only the interconnections are fabricated in the 3rd dimension in these ULSICs to interconnect the devices via

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multilevel interconnections. Moore’s Law is applicable only for the ULSICs, viz., for 2D-ICs.20 The acronym UPICs refers to Ultra Performance ICs,27 in which the active devices are fabricated on a chip using single crystals of Si and other semiconductors such as GaAs, GaAlAs, GaN, GaP, etc, in the 3rd dimension also above the surface of the Si wafer, in addition to those fabricated in 2dimensions on and near the surface of the Si wafer. All the devices in UPICs are interconnected via multilevel interconnections. In UPICs, both electrical and optical functions can be integrated monolithically.13,20

4. Comparison of the sequence of relevant patent filing and issue dates given above with that given in the earlier NSTI paper12 For the sake of comparison of the sequence of relevant patent filing and issue dates given above in Table 5.2 with that given in the earlier NSTI paper,12 Table 5.3 is copied below from this paper. Please note that the references in this Table 5.3 correspond to those in my NSTI paper.12 Table 5.2 gives a more complete list than what could be given in Table 5.3 due to the length limitation of the paper for inclusion in the conference proceedings. Table 5.3. Filing and issue dates of patents and publications relevant to IC inventions (Copied from the earlier NSTI paper12 for the sake of comparison with the above Table 5.2. The references in the following table correspond to those in the NSTI paper.12 ).

•

Kilby16

(ICs)

• Lehovec3 (Isolation)

Patent#

Filing date

Issue date

3,138,743 Application Serial No. 03/791,602.

Claimed by Kilby to be Feb. 6, 1959. (No official record15 of this filing date. Official records show only May 6, 1959, as the filing date.14 See Figs. 5,6.)

June 23, 1964*

3,029,366

Apr. 22, 1959

April 10, 1962 (Continued )

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Table 5.3.

• Hoerni4 (Planar Tech.)

(Continued )

Patent#

Filing date

Issue date

3,025,589 3,064,167

May 1, 1959 May 1, 1959

Mar. 20, 1962 Nov. 13, 1962

• Kilby

3,072,832

May 6, 1959

Jan. 8, 1963

• Kilby

3,115,581

May 6, 1959

Dec. 24, 1963

• Kilby1 (ICs)

3,138,744

May 6, 1959

Jun. 23, 1964* (Key patent)

• Noyce2 (ICs)

2,981,877

Jul. 30, 1959

Apr. 25, 1961 (Key patent) See Fig. 4.

• Kilby

3,261,081 Ser. No. 352,380

July 19, 1966

• Kooi5 (LOCOS)

3,970,486 3,752,711

Original appl. as Feb. 6, 1959; this appl. Mar. 16, 1964. Oct. 3, 1966 Jun. 4, 1970

• Saxena20 (Interconnect)

3,687,722

Mar. 10, 1971

Aug. 29, 1972

• Kilby11

None filed July, 1976 (Review paper) (Review paper) [Gave historical review of his IC invention.]

• Kilby12

None filed Mar. 31, 1998 (Technical paper) (Technical paper) [Made comments on his and Noyce’s original patents1,2 , “monolithic ICs”, and Dummer’s21 approach to “. . . envisage electronic equipment in a solid block with no connecting wires.”]


6,110,278

Aug. 10, 1998

Aug. 29, 2000


6,392,253

Aug. 6, 1999

May 21, 2002

Jul. 20, 1976 Aug. 14, 1973

For discussions of the above list in Table 5.3, see Saxena.12

5. Key features of Saxena’s patent # 3,687,722 on interconnects36 The key invention of this patent was to form the well-defined patterns of interconnects and contacts selectively without doing any etching of the metal films. The main purpose of listing this patent here is to give example

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of the continuity of my work on interconnects and ICs from the early years to the present, a credible feature for valid ownership of patents. Please note that this patent of mine was filed on March 10, 1971, which was after Kooi’s25 patents on Local Oxidation of Silicon (LOCOS) which were filed on Oct. 3, 1966, and Jun. 4, 1970. But it was granted on Aug. 29, 1972, which was before both patents of Kooi were granted (July 20, 1976; August 14, 1973, respectively). Prior to Kooi’s patents25 on LOCOS process, which is used for the isolation of devices in ICs, Lehovec9 had been awarded the patent for the p–n junction isolation of devices in ICs. Lehovec’s patent was important and crucial to isolate the devices in the invention of monolithic-IC by Noyce.2 Kooi’s patent, while not crucial for the invention of ICs, was important for IC manufacturing for many years until it was also replaced by trench isolations in advanced ULSICs.

6. Controversy over public disclosures and patent filing dates There is no controversy over public disclosures and the patent filing dates of all of the authors listed in Table 5.2, except in the case of Kilby.1,23 In his patent no. 3,138,744, Kilby writes (cf: column 1, lines 55–57), “To that end, I have proposed in my pending application for patent, Serial No. 791,602, filed February 6, 1959, . . . ” Saxena, while obtaining a copy of Kilby’s23 Application Serial No. 791,602, “Miniaturized Electronic Circuits and Method of Making” from the United States Patent and Trademark Office (USPTO), received the following two official responses recently: 6.1. E. Bornett,29 Certifying Officer, USPTO, wrote to Dr. Arjun N. Saxena, “This is to certify that annexed hereto is a true copy from the records of the United States Patent and Trademark Office of those papers of the below identified patent application that met the requirements to be granted a filing date under 35USC111. Application: No. 03/791,602; Filing date: May 06, 1959.” This was sent by USPTO to Saxena on September 26, 2005. (See Fig. 5.5) 6.2. Customer Service Department,30 USPTO, wrote to Dr. Arjun N. Saxena, “The product or service you requested cannot be fulfilled because

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the application #03/791,602 does not have an official filing date.” This was sent by USPTO to Saxena on November 02, 2005. (See Fig. 5.6) The above contradictory responses from the USPTO cannot be explained. No matter what may be the problem of keeping records accurately and consistently at the USPTO, one fact is clear from the above responses that the official filing date of Kilby’s Application No. 03/791,602 was not February 6, 1959, as claimed by Kilby1 ; instead it was May 06, 1959, which was also the filing date of Kilby’s issued patent no. 3,138,744, and the other two TI patents listed in Table 5.2. It is also important to note (see Table 5.2) that according to the public records, no further action was taken either by Kilby or by the USPTO on Kilby’s Application No. 03/791,602, and no patent was ever issued for this application. Even though Kilby’s patent no. 3,138,743 was based on his Original Application No. 03/791,602, which was never patented, their claims were quite different. No patent per se was issued directly on 03/791,602, as confirmed by USPTO during communications over telephone (with “Chris” of Electronic Business Support, USPTO; April 11, 2007). Several technology related matters in Kilby’s Application No. 03/791,602, such as “shaping” or “mesa” techniques prescribed in it for the fabrication and isolation of transistors and other devices, gold for interconnects, gold and aluminum evaporated through masks for ohmic contacts shall not be reviewed in detail in this book. As it is well known to those conversant in the state of the art, these technologies are not used and will not work in manufacturing the monolithic-ICs.

7. Additional important facts from the published records Additional important fact proven by the published records is that neither Dummer4 nor Johnson5 or Stewart6 had pursued the development of ICs further after disclosing their respective versions of the original concepts. Still another important fact is that after receiving his patents on ICs, Kilby19 continued to regard the monolithic concept as controversial and made little if any contributions to the monolithic-ICs. The Nobel Prize

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awarded to Kilby and cited “for his part in the invention of the integrated circuit” in physics in 2000 is rife with controversy regarding what was his part in inventing which kind of IC. Kilby was also awarded double the financial amount than to his co-winners Allferov and Kroemer. My direct written communications with two members of the Nobel committee (Dr. MNC-1 and Dr. MNC-2) did not result in clarifying either the official citation of the award to Kilby or the unequal financial awards to him and the other co-recipients. However, after I did my own research into the matter using the Nobel website for the documented facts, I can explain the unequal financial awards but not the citation of the award. This unusual fact remains a mystery. For details, see Section 6.8 of Preface, and Chapter 12. 8. Figures from Kilby’s and Noyce’s patents and correspondence from USPTO The following figures are given from Kilby’s and Noyce’s patents, and correspondence from USPTO, with brief comments on them. 1. Figure 5.1: Figs. 1–4 copied from Kilby’s1 patent no. 3,138,744. Note the mesa structures in Kilby’s Figs. 3 & 4 (instead of the planar structures which are necessary in monolithic-ICs). 2. Figure 5.2 shows Figs. 1–5 copied from Kilby’s23 patent application no. 03/791,602. Note the mesa structures in Kilby’s Figs. 4 & 5 (instead of the planar structures which are necessary in monolithic-ICs). 3. Figure 5.3: Figs. 6 & 8 copied from Kilby’s23 patent application no. 03/791,602. Note the wire-bonding in Kilby’s Figs. 6 & 8 (instead of the monolithic interconnects which are necessary in monolithic-ICs). 4. Figure 5.4: Figs. 3, 4 & 5 copied from Noyce’s2 patent no. 2,981,877. Note the planar structures and monolithic interconnects in Noyce’s Figs. 3 and 4 (instead of the mesa structures and wire-bonding). Fig. 5 just shows the circuit diagram of Noyce’s invention. 5. Figure 5.5 Response from E. Bornett,29 Certifying Officer, USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on September 26, 2005, regarding its filing date. 6. Figure 5.6 Response from Customer Service Department,30 USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on November 02, 2005, regarding its filing date.

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Fig. 5.1. Figures 1–4 copied from Kilby’s1 patent no. 3,138,744. Note the mesa structures in Kilby’s Figs. 3 & 4 (instead of the planar structures which are necessary in monolithic-ICs).

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Fig. 5.2. Figures 1–5 copied from Kilby’s23 patent application no. 03/791,602. Note the mesa structures in Kilby’s Figs. 4 & 5 (instead of the planar structures which are necessary in monolithic-ICs).

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Fig. 5.3. Figures 6 & 8 copied from Kilby’s23 patent application no. 03/791,602. Note the wire-bonding in Kilby’s Figs. 6 & 8 (instead of the monolithic interconnects which are necessary in monolithic-ICs).

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Fig. 5.4. Figures 3, 4 & 5 copied from Noyce’s2 patent no. 2,981,877. Note the planar structures and monolithic interconnects in Noyce’s Figs. 3 and 4 (instead of the mesa structures and wire-bonding). Fig. 5 shows the circuit diagram of Noyce’s invention.

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Fig. 5.5. Response from E. Bornett,29 Certifying Officer, USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on September 26, 2005, regarding its filing date to be May 6, 1959 (NOT Feb. 06, 1959) cliamed by Kilby.1,19,23

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Fig. 5.6. Response from Customer Service Department,30 USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on November 02, 2005, stating that it “does not have an official filing date.”

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9. Methodology of Analyses of Patents and Papers, and Numbering of the Tables and Figures 9.1. Methodology The methodology of analyses of patents and papers by various inventors and authors that I have used in this book is as follows. A. Quotations from the original patents (text and claims) and papers are given in ITALICIZED FONT. B. Important points in the above quotations are highlighted in BOLD ITALICIZED FONT. C. My comments on any of the above are given in NORMAL FONT. D. Important points in the above comments given by me are highlighted in BOLD NORMAL FONT. The above methodology makes it easier for the reader to recognize when certain material is being quoted from the original document, and what portion of the quote is actually important. The same comment applies to my comments on the original documents. Next the above methodology used to analyze various patents in the book is further elaborated as follows.

1. ORIGINAL PATENT: A copy of the original patent as issued by the USPTO is given for every patent analyzed. 2. SUMMARY OF THE INVENTION: A brief description of the invention given in the text of the patent is summarized. 3. KEY FIGURES: Comments on the figures of the patent which are key to the invention are given. 4. KEY CLAIMS: Comments on the claims of the patent which are key to the invention are given. 5. REDUCTION TO PRACTICE: Comments are given on the reduction to practice of the invention over and beyond what may have been given in the patent. 6. CHOICE OF SEMICONDUCTOR: Comments are given on the choice of the semiconductor by the inventor for the invention over and beyond what may have been given in the patent.

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7. FABRICATION METHOD OF DEVICES: Comments are given on the fabrication method described by the inventor in the patent. 8. INSULATING LAYERS: Comments are given on the insulating layers described by the inventor in the patent. 9. ISOLATION OF DEVICES: Comments are given on the isolation of devices described by the inventor in the patent. 10. INTERCONNECTS: Comments are given on the interconnects used to connect the devices described by the inventor in the patent. 11. IMPACT OF 35 USC 112: Where applicable to certain patents, the impact of US Patent Code 35 USC 112 is discussed. 12. OVERALL COMMENTS: 13. DETAILED ANALYSES OF ALL THE CLAIMS: For pedantic reasons, detailed analyses of all the claims of only a few important patents are given.

9.2. Numbering The numbering of the tables and figures in each chapter follows the convention defined below. (Table or Figure)–(Chapter no.)–(Numerical sequence). For example, Table 1.1 is the 1st table in Chapter 1. Table 6.2 is the 2nd table in Chapter 6. Similarly, Fig. 1.2 is the 2nd figure in Chapter 1. Fig. –6.3 is the 3rd figure in Chapter 6.

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Chapter 6

Hoerni and Lehovec Inventions 1. Importance of Hoerni and Lehovec inventions to the fundamental invention of ICs The inventions of Jean Hoerni8 (Si planar technology) and Kurt Lehovec9 (p–n junction isolation) are ancillary to the fundamental inventions of the integrated circuits (ICs) by Jack Kilby1 and Bob Noyce.2 The latter are the main subject of this book; therefore they have been discussed in detail in Chapters 7 and 8 respectively. To state up front, the planar technology invented by Hoerni will work only with Si (used by Noyce), not with Ge (used by Kilby). However, the invention by Hoerni was based on a series of important investigations done by several others prior to him, as it will become clear from the discussions below. Even though the details of Kilby’s invention are given in Chapter 7, briefly stating, its reduction to practice was that of a hybrid-UC-IC. It had used Ge mesa technology for the fabrication and isolation of devices, and they were interconnected by gold (Au) wire bonds flopping above and between two pieces of Ge. Kilby’s invention was not of a Si monolithic-IC and did not use Hoerni’s and Lehovec’s inventions. The details of Bob Noyce’s invention are given in Chapter 8. Briefly, its reduction to practice was that of a Si monolithic-IC. It was done by a few others working under Noyce, not by Noyce himself. It used Si, Hoerni’s planar technology, Lehovec’s p–n junction isolation of planar devices, and they were interconnected monolithically by thin, narrow Al conductors deposited by thermal evaporation of Al and patterned by wet chemical etch. These Al conductors were adherent to the thermally grown SiO2 film 95

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on the Si surface. The inventions of both Hoerni and Lehovec were crucial to make Noyce’s invention of the monolithic-IC to function properly.

2. Importance of choosing Si over Ge and other semiconductors Many scientists all over the USA and the rest of the world were working with Germanium (Ge), Silicon (Si) and other semiconductors to make solid state devices. The original credit for choosing Si over Ge for making the devices belongs to William Shockley.55 The reasons for this choice were primarily technical, not technological. The insight and the genius of Shockley as well as some of his preferences and personality traits have been recognized already in the literature. They are not the subject of this book. Nevertheless, without shortchanging the former qualities, it is fair to say that Shockley’s acumen did not follow through a rigorous technology development of the potential of high quality silicon-dioxide (SiO2 ) films that could be grown on Si at high temperatures. These temperatures were in the 1000 degree centigrade (C◦ ) range, such as those used for the diffusion of n- and p-type dopants in Si. The SiO2 films protect and passivate the p/n junctions (needed to fabricate diodes and transistors) electrically and from the surrounding ambient on the Si surface. This important quality of the SiO2 films to preserve the electrical characteristics of the p–n junctions, and prevent these electrical characteristics from deteriorating by the gaseous ambient environment was discovered by Atalla at Bell Laboratories.64,65 As it will become clear from the following discussions, Atalla’s important finding would have led to the invention of the planar technology by Hoerni while working at the Shockley Transistor Corporation instead of at a new company in 1959, the Fairchild Semiconductor Corporation. As it is well known, Hoerni and his seven colleagues (including Noyce and the others — see Preface, Section 10) had worked together at Shockley, left and cofounded Fairchild. The choice of silicon (Si) over the other semiconductors was fortuitous and timely because the oxide film (SiO2 ) that could be grown on it was an excellent insulator film. Appreciation of this important property47,55 was due to a combination of knowledge, serendipity, luck, timing, ingenious contributions of various process and test engineers, and quick turn around

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times to produce measurable, meaningful, and reproducible results. Even though many scientists and technologists deserve to be recognized, but the results of such combination usually leads to propping up the “geniuses”. Various such “geniuses” can be named, but to apply the “Law of the Famous,”62 only a select few qualify genuinely for such an honor.

3. Sequence of important technical work and serendipity which led to the discovery of planar technology Atalla and his group at Bell Laboratories were the first to show in 1959 that high quality insulator films of SiO2 could be grown thermally on the Si surface to protect the underlying Si p/n junction diodes and transistors.56,64,65 Frosh and Derrick11 were the first to show in 1958 that the thermally grown SiO2 films on Si can mask against the diffusion of the vapor of the p-type acceptor impurities (Boron, Gallium, Indium) and n-type donor impurities (Phosphorus, Arsenic, Antimony) into Si. These results were extended quantitatively for practical engineering use in processing by Sah10 in 1958 first at Shockley Transistor Corporation. Later they were further enhanced by Sah and other colleagues at Fairchild.56 They modeled the processes mathematically, and designed the experiments and fabrication processes necessary for the selective diffusions for p/n junction diodes and transistors passivated by the SiO2 films on the surface of Si. In 1959, Jean Hoerni8 combined these discoveries of the unique properties of the thermally grown Si-dioxide (SiO2 ) film on Si. They had been reported and published earlier by Atalla,64 Frosch and Derrick,11 engineering design data of Sah,10 and Sah with his co-workers.56 Hoerni also seized on the key inputs from the electrical test engineering group at Fairchild (which have never been described before in the literature; see discussions given below). With the knowledge of all this combined important information, Hoerni8 filed for patents on what is now known as the famous planar technology (see also Table 5.2 in Chapter 5). Before documenting the sequence of important technical work in detail, I shall describe the input(s) which came as serendipity from the electrical test engineering group at Fairchild. Since I have focused to use documented facts primarily in my papers, I have been somewhat reluctant in the past to cite another important trigger point which I believe was also crucial

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for the brain-wave in Hoerni’s mind regarding the invention of the planar technology. I have used some inputs related to the invention of ICs from a few reliable sources elsewhere in this book, for which I cannot provide published documents. But I have quoted and referred to them as personal communications. I have also stated up front that I have used my professional discretion and courtesy to refrain from divulging the names in a few cases. I was privy to and participated in several events that I have discussed in this book. In the same spirit, I shall refer to the following inputs66 on the additional sequence of events which were important in the evolution of planar technology at Fairchild. Therefore I feel compelled to describe them below in this book. They have never been reported before in the literature. At the review meetings of early Si transistor development at Fairchild, a test engineer and a technician who were assigned to measure the electrical characteristics of these transistors, used to complain about the I-V (currentvoltage) results. Among those attending these review meetings were several other engineers, and Vic Grinich. The readers will remember from section 10 of Preface that Grinich was also a co-founder of Fairchild, thus a colleague of Hoerni, Noyce, and Moore et al. As best as I can remember, there were no precise titles given at that time as V.P. of this or that in Fairchild. Everybody did during those days what had to be done, even across the lines of management and responsibility. The esprit de corps was such that things were done fast and well in coordinated but unrestrictive roles. Nevertheless, Grinich had a title of something like Head of Applications Engineering which included electrical testing and characterizations at Fairchild. The complaint referred to above can be summarized as follows: The engineer and the technician had difficulty in measuring the collector-base junction properties due to its breakdown creep and instabilities of the transistors. But they had no such problems with the emitter-base junctions of the same transistors. Such electrical behavior was repeated consistently over several batches of transistors from different processing runs (commonly used to identify different processing batches). All the attendees of the review meetings were made aware of the processes used for the above batches of transistors. During the

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early attempts to develop the processes for fabricating these batches of transistors, planar technology was used for the selective diffusions for emitters and bases through the openings in the oxide films. The oxide was left to cover the emitter-base junctions, thus their edges were protected by the oxide film in these processes. However, the base-collector junctions were delineated by the mesa process, i.e., the surface oxide was removed as the base-collectors were etched as mesas. Consequently the edges of the base-collector junctions were exposed to the ambient. Therefore, the effect of the variations in the ambient would manifest in the I-V variations of the base-collector junctions, but not in the emitter-base junctions. As it is well known now, the latter were passivated by the oxide but the former were not. During one of these meetings, one of the test engineers suggested why don’t we leave the oxide on the base-collector junctions too, and do not etch them as mesas? Some discussions went on regarding the possible lowering of the junction breakdown voltages when the oxide was left on to cover the junctions. This would have been due to the “dish” shape of the junctions protected by the oxide films. In any event, the engineer’s suggestion was implemented, and in a couple of months, “new” transistors with the entire surface of the Si wafer with all the junctions covered with the oxide films were produced. All the junctions were planar which came up to the surface, and were protected by the oxide films. All the electrical characteristics of these transistors were found to be stable. They were reportedly named later by Noyce as the “Planar transistors”, and the fabrication process as the “Planar process”. There was great excitement; Hoerni filed two patents8 for the planar technology and the semiconductor device, and presented his paper67 in the Electron Device meeting in 1960. The rest is history. I shall now recapitulate and document the precise historical sequence56 of the four sets of pioneering experiments that led Hoerni to the development of the planar technology: 3.1. First was the 1954 work of Fuller and Ditzenberger68 on the diffusion of boron and phosphorus impurities into silicon. 3.2. Second was the 1957 work of Frosh and Derrick11 on the surface protection and selective masking during diffusion of dopants into silicon.

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3.3. Third was the 1958 work of Sah10 at the Shockley Semiconductor Laboratory and Shockley Transistor Corporation, (in the six months during summer 1958 to spring 1959) with the help of Doug Tremere in the second half of the nearly 100 experiments for diffusion masking by the oxide. Sah had developed severe allergy to the P2 O5 vapors, and reported it in the full report of the Shockley Semiconductor Laboratory Technical Memorandum Series, No. 61, dated 2 March 1959. All the results were presented by Sah to the Fairchild engineers and Hoerni during Sah’s job interview arranged by Noyce at Fairchild during the following week in March 1959. This was also the exact manuscript submitted on June 17, 1959 and published10 in September 1959 after Sah had left Shockley and joined Noyce at Fairchild. The manuscript and the final journal article (since there were no revisions and changes) were given to Hoerni during Sah’s job interview at Fairchild. This paper10 provided the experiment-based theoretical design equations and the complete family of engineering design curves for the necessary oxide film thicknesses needed to mask against phosphorus impurity diffusion into the Si underneath which oxide masking was not possible as stated in the original paper by Frosh and Derrick.11 The above information was absolutely crucial to process and fabricate successfully the double-diffused planar transistors. It enabled Hoerni to grow the necessary oxide thicknesses to mask against phosphorus diffusion, and fabricate the n+emitter/p-base region of the n+/p/n double-diffused silicon bipolar transistor. With this process, the entire n+/p/n transistor had the planar structure in which all the junctions coming up to the surface (referred to as dish junctions by Noyce2 ) were protected by the SiO2 films. Hoerni disclosed all this in his patent application8 filed on May 1, 1959. The 1957 experimental conditions of Frosch and Derrick11 did not reach the oxide thicknesses necessary to mask against phosphorus diffusion. Thus inadequate oxide thicknesses had caused them to conclude that the oxide film would not mask against phosphorus diffusion, like they had found against boron diffusion. Therefore Frosch and Derrick’s results prevented Hoerni to fabricate successfully the planar n+/p/n double diffused and oxide protected silicon bipolar transistor. However after Sah had given Hoerni a copy of Sah’s 2-March-1959 TM61 after the jobinterview presentation in March 1959, Hoerni did succeed to fabricate

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the planar n+/p/n double diffused and oxide protected silicon bipolar transistors. The diligence of Sah’s work on engineering based technology of oxide masking against dopant diffusion was recorded by a series of experiments published56 in the Journal of the Applied Physics in 1964 and 1965 by Sah and his co-workers at Fairchild Semiconductor Research and Development Laboratory. These experiments were designed to give the oxide film thickness curves against diffusion of the other donor and acceptor impurities also into Si. 3.4. Fourth was the 1959 work of Atalla, Tanenbaum and Scheibner64 on the stabilization of silicon surface by thermally grown oxide. 3.5. Finally, the combination of the above four items reported in the 1959–1960 work of Hoerni8,67 was first disclosed to the public in 1960 at the December 1960 IEDM.67 In this presentation, Hoerni coined the combination (or borrowed from Noyce’s expression) as the planar process pursuant to benefiting from the work of ALL the prior scientists and engineers. Once again, the advantages of the Si planar technology can be summarized as follows. For illustrations of the important properties of the planar technology, see Figs. 1–10 of Hoerni’s patent No. 3,025,589 given at the end of this chapter. 3.6. Excellent planar p–n junctions could be fabricated whose peripheries came up to the Si surface underneath the SiO2 films. 3.7. The p–n junctions and their peripheries were sealed at the edges at the surface by the SiO2 films, thus they were protected from the variations in the ambient above the films. This enabled the p–n junctions to be very stable with low leakage currents. 3.8. Because of the point No. 3.7 above, the metal contacts to the p–n junctions made in their centers did not short the junction edges. 3.9. The n- and p-type dopants could be masked by appropriate thicknesses of SiO2 films allowing selective thermal diffusions to make well defined junctions for the transistor geometries. As discussed above, this property of the SiO2 films was described originally by Frosch and

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Derrick.11 Sah10 gave experiments-based theoretical design curves for SiO2 layer thicknesses needed to mask against the dopant impurities for selective thermal diffusions in order to make planar junctions of the desired geometries. Sah’s work was motivated by the failure of Frosch and Derrick in not being able to mask against the key n-type impurity, phosphorus, at the very high phosphorus vapor pressure (at the diffusion temperature) by even the thick thermally grown oxide, and it played a key role in the success of Hoerni’s planar invention. Hoerni got the patents8 for the planar technology essentially covering the key points 3.6, 3.7 and 3.8 given above. Hoerni’s patents were singleinventor patents commanded by the Fairchild Patent Attorney’s concern on the validity and/or the strength of multi-inventors in a patent. It is unlikely that the criterion of single-inventor was enforced by the senior attorney, John Ralls (who had died after filing for the IC patent of Bob Noyce2 ). However it may have been insisted upon later, as an example, for the patent on the CMOS inverter circuit by Wanlass. Point no. 3.9 was the necessity that was built-in in Hoerni’s innovative combination of 3.1, 3.2, 3.3 and 3.4. As discussed above, they were obvious to those familiar with all the work done previously. However Hoerni was at the right place and time to combine all this prior knowledge and invent the planar technology. It worked successfully and produced the original Si planar transistor, and provided Noyce to take the next obvious step, i.e., to put two and two together and invent the monolithic-IC. The continued use of the planar technology from the inception to the ULSICs of today attests to the fact that it is indispensable to the entire microelectronics field. However, despite all the technical and technological factors, it must also be recognized that the Nature’s gift to mankind of high quality SiO2 films that can be grown on Si with a reliable and stable interface reproducibly, was and is absolutely crucial. The credit due to both Hoerni and Lehovec for their fundamental contributions to the invention of the IC had been essentially ignored, or certainly not recognized in the entire literature so far, until my paper12 was published. Nevertheless, their innovations did not fall like manna from the sky, but they were based on the four indispensible prior arts and the knowledge gained by the tedious and long experiments listed in 3.1, 3.2,

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3.3 and 3.4. The historical fact cannot be denied that Sah was the first to design and perform the crucial experiments which enabled Hoerni to accomplish “fait accompli”, and they were described by Sah in 1988.10 The credit at least due Hoerni was acknowledged recently by Riordan51 after my paper12 had stated it explicitly for the contributions from both Hoerni and Lehovec. But nobody has recognized the importance of the engineering-designed prior arts described in 3.1 to 3.4, and the key input from an electrical test engineer, that were the seeds sowed in Hoerni’s mind to combine them to blossom into the ubiquitous planar process of the IC industry. As the readers can now appreciate that the Si planar process was built upon the key contributions of many, but it is referred to as Hoerni’s planar process. This may also be due to the fact that the basic patents for this process were filed and awarded to Hoerni8 (two years ahead of Kilby’s patent, and one year after Noyce’s patent; see Table 5.2, Chapter 5). Hoerni’s planar process is still indispensable today even though the IC technology has now advanced to the ULSIC stage having several billion devices per chip, and will advance to the next generation 3D-ICs and UPICs.37,38 Lehovec’s invention has been mostly replaced by Kooi’s25 LOCOS isolation, and by the reactive ion etched (RIE) trench-isolation technologies invented by several others (see Section 7). 4. Methodology to analyze Hoerni’s and Lehovec’s patents Instead of analyzing Hoerni’s key patent Nos. 3,025,589 and 3,064,167, and Lehovec’s key patent No. 3,029,366 in detail, as I have done for the inventors of ICs per se, e.g., Kilby, Noyce, Johnson and Stewart (see Chapters 7, 8 and 9), I shall give only the gist of Hoerni’s and Lehovec’s inventions in this chapter. I shall quote the relevant portions from their patents and comment on their respective inventions. However, for those who may be interested in scrutinizing them further, I shall provide their original patents issued by the USPTO, Lehovec’s 1978 IEEE-TED paper26 and the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec, at the end of this chapter. See also reference 8 in Lehovec’s paper.26 It refers to the “Decision of the Board of Interferences in the patent interference Kilby vs. Lehovec,” No. 93612, April 5, 1966.

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5. Quotation of key points from Jean Hoerni’s patent no. 3,025,589, “Method of Manufacturing Semiconductor Devices”, filed May 1, 1959; ser. no. 810,388; issued March 20, 1962. Column 7; Lines 2–18: “The method of making semiconductor devices, comprising the following steps: (a) forming a non-conducting coating on a surface of a semiconductor body; (b) opening a hole through the coating, thereby exposing a limited surface area of the semiconductor; (c) diffusing into the semiconductor, through such hole, an impurity forming within the semiconductor, beneath the hole, a P–N junction extending to the semiconductor surface underneath said coating; (d) re-forming a non-conducting coating on the semiconductor surface within such hole; (e) and opening a new hole through the last-mentioned coating to the semiconductor surface, while leaving permanently in place the coating covering all parts of the P–N junction that extend to the semiconductor surface.” Hoerni describes the essence of planar technology that combined the knowledge from the prior arts described in 3.1 to 3.4 above; their combination is the key of his invention. The edges of the p–n junctions are planar and covered with the oxide on the surface of the semiconductor. This is the deterministic difference between this planar and the mesa technology. In the latter, the p–n junction sticks out like a mesa (in a mountain range), and the periphery of its junction is exposed to the ambient. Therefore the exposed mesa p–n junctions in the early years had high and variable leakage currents which were dependent on the ambient. After the invention of planar technology, the planar p–n junctions have very low leakage currents independent of the ambient because the edges of the junctions are sealed by the SiO2 films. Consequently the junctions are protected from the variations in the ambient. In the recent trench isolation technologies, the etching of the

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trenches (grooves) in the bulk Si wafer is covered and filled with deposited oxide. Thus any junctions if delineated in the trenches due to etching are covered by the oxide layers, thus they are protected from ambient effects also.

6. Quotation of key points from Jean Hoerni’s patent no. 3,064,167, “Semiconductor Device”; filed May 1, 1959; ser. no. 810,388. Divided and this application May 19, 1960, ser. no. 30,256; issued Nov. 13, 1962. Column 6; Lines 26–42: “An improved double-diffused transistor structure comprising a thin wafer having a plane upper surface, said wafer being mostly of a first conductive type of semiconductor, a first thin layer of opposite conductive type semiconductor diffused into only part of the upper surface of said wafer, a second layer of first conductive type semiconductor diffused into only part of the upper surface of said first layer closer to one edge thereof than to the other so that a substantial are of said first layer appears at the upper surface of the wafer, a protective adherent nonconducting coating upon the upper surface of the wafer and having openings therethrough to said second layer and wafer, as well as to said first layer only at the substantial surface area of the latter, and electrical leads extending through said openings into contact with said wafer and first and second layers at the upper surface of said wafer.” Hoerni describes a planar double-diffused transistor whose surface is planar, and the peripheries of the two p/n junctions (the emitter and the collector p/n junctions) are protected by the oxide, leading thus to high quality stable planar transistors in large volume manufacturing with high yields of good devices.

7. Quotation of key points from Kurt Lehovec’s patent no. 3,029,366, “Multiple Semiconductor Assembly”; filed April 22, 1959; ser. no. 805,249; issued April 10, 1962. Column 6; Lines 37–45: “1. A multiple semiconductor assembly comprising a semiconductor slice having a plurality of regions of alternating

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p and n conductivity types to thereby provide a plurality of p–n junctions, at least two semiconducting components assembled each on one of said regions of said slice, said components being separated by plurality of said regions so as to provide therebetween at least two p–n junctions thereby achieving electric insulation of said components through said slice by the impedance of said p–n junctions.” Lehovec specifies the use of p–n junction isolation of devices in ICs. This is Lehovec’s key invention. Nevertheless, this specification is too general and not valid under all conditions. It only works to electrically isolate if the p/n junction is not strongly forward biased, i.e., VPN is less than about +300 mV, above which it will not isolate effectively. Therefore, in such cases Lehovec’s patent is not valid, and his claims cannot be allowed. Lehovec wrote a rejoinder to Kilby’s paper21 of 1976, because according to Lehovec, Kilby had misquoted his p–n junction claims. Hence Lehovec corrected it in the letter to the editor published in IEEE Trans. ED26 given in Section 10 at the end of this chapter. It should also be evident to anyone familiar with the state of the art why Bob Noyce may have chosen not to specify p/n junction for isolating the transistors on a piece of silicon. Noyce probably knew the trouble due to the p/n/p/n switch back, which was not obvious to anyone else at that time, that for certain conventional circuit designs and operations Lehovec’s simple p/n junction isolation scheme will not work. This limitation can be obviated substantially when additional circuit elements are added to the original circuit. This has been done in the scaling of CMOS ICs, but it adds complications to the design. Therefore, Lehovec’s invention of p–n junction isolation is at a disadvantage for widespread use in ICs, in particular CMOS ICs. Consequently it has been replaced by Kooi’s25 and trench isolation inventions. It is another example of why just a theoretical idea of an invention without meaningful reduction to practice and detailed scrutiny is usually inadequate. The technical reasons have been given above why Noyce may have chosen not to file claims for p–n junction isolation, and also not to acknowledge Lehovec in his patent. Please note the word “may” that I have used in the previous sentence, which I have done to give the benefit of

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the doubt in Noyce’s favor. I am making this qualifying disclaimer because the technical reasons are more apropos for the CMOS circuit designs, which comprise the largest segment of the entire chip business today. The concept of CMOS did not even exist in 1959 when Noyce’s patent was filed. Nevertheless, while no claims were filed by Noyce, the p–n junction isolation was mentioned but not described properly in Noyce’s patent to “teach one of ordinary skill in the art how to construct the device”. However, Noyce did acknowledge Lehovec’s isolation patent later in his paper43 in 1977. I did not have a chance to review personally the above with Noyce before he died in 1990. Nevertheless based on my technical reviews with Sah,69 I have given the most likely technical reasons in the previous paragraphs above why Noyce may have chosen not to claim the p–n junction isolation in his IC patent2 because of the circuit design issues and the pnpn switch back which Noyce was very familiar with while working at Shockley Laboratory on the pnpn diode switch for telephone switching office. Lehovec sent me a personal copy of the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec. It is given in Section 11 at the end of this chapter. See also Reference 8 of Lehovec’s paper.26 It refers to “Decision of the Board of Interferences in the patent interference Kilby vs. Lehovec,” No. 93,612, April 5, 1966. Quote from last but one paragraph of Lehovec’s paper26 is as follows: “To quote from the decision by the Board of Interferences [8]: ‘We have carefully examined Patent 3,138,743’ [7] ‘but nowhere can we find support for the subject matter of the counts . . .. Since Kilby has no reduction to practice prior to the filing date of Lehovec, . . . priority of counts 1–5 is awarded to Kurt Lehovec, the senior party.’ The counts of interference are the claims of the Lehovec patent [2].”

8. Copy of the original patent no. 3,025,589 of Jean Hoerni: “Method of Manufacturing Semiconductor Devices”, filed May 1, 1959; ser. no. 810,388; issued March 20, 1962.

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9. Copy of the original patent no. 3,064,167 of Jean Hoerni: “Semiconductor Device”; filed May 1, 1959; ser. no. 810,388. Divided and this application May 19, 1960, ser. no. 30,256; issued Nov. 13, 1962.

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10. Copy of the original patent no. 3,029,366 of Kurt Lehovec: “Multiple Semiconductor Assembly”, filed April 22, 1959; ser. no. 805,249; issued April 10, 1962.

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11. Copy of Kurt Lehovec’s paper,26 “Invention of p–n Junction Isolation in Integrated Circuits”, p. 495–496, IEEE transactions on electron devices, Vol. ED-25, no. 4, April, 1978.

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12. Copy of the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec. See reference 8 of Lehovec’s paper,26 given as “Decision of the Board of Interferences in the Patent Interference Kilby vs. Lehovec,” no. 93612, April 5, 1966. Quote from last but one paragraph of Lehovec’s paper is as follows: To quote from the decision by the Board of Interferences [8]: “We have carefully examined Patent 3,138,743” [7] “but nowhere can we find support for the subject matter of the counts . . .. Since Kilby has no reduction to practice prior to the filing date of Lehovec, . . . priority of counts 1–5 is

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awarded to Kurt Lehovec, the senior party.” The counts of interference are the claims of the Lehovec patent [2]. The references given above within brackets [. . . ] correspond to those given in Lehovec’s paper.26

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Chapter 7

Kilby’s Invention of IC: Key Patents, Claims and Analyses 1. Introductory comments on Kilby’s invention Kilby’s invention of the IC is more complicated to analyze than that of Bob Noyce (see next Chapter 8). While Noyce’s invention is covered by only one patent (US patent no. 2,981,877), Kilby’s invention is covered by the Original Application (OA) and three patents listed below. They are somewhat controversial also and are shrouded in mystery as discussed in the subsequent sections of this chapter. To facilitate in understanding Kilby’s IC invention, a cumulative summary of the analyses of OA and the three patents is coalesced in the beginning of this chapter. However for completeness, copies of Kilby’s OA and these three patents as recorded by the USPTO, as well as detailed analyses by me on all the claims are given in the end of this chapter. For those who are interested in the rigorous details can read all the individual patents and their analyses at the end of this chapter. Kilby’s Original Application (OA) and the three patents for his IC invention that are discussed in this chapter are as follows. 1.1. Original Application (OA) no. 791,602, “Miniaturized Electronic Circuits and Method of Making”; claimed to have been filed on February 6, 1959, but the filing date recorded by USPTO was May 6, 1959. No patent action was taken and no patent was issued on this application per se. (See Saxena29,30 ; Chapter 5, Section 6.)

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1.2. US patent no. 3,138,743,22 “Miniaturized Electronic Circuits”; filed February 6, 1959; serial no. 791,602; issued June 23, 1964. This filing date is controversial because this patent was based on the OA in 1.1 whose filing date was May 6, 1959 as recorded by USPTO, not February 6, 1959. 1.3. US patent no. 3,138,744,1 “Miniaturized Self-contained Circuit Modules and Method of Fabrication”; filed May 6, 1959; serial no. 811,486; issued June 23, 1964. Note that the number of this patent is sequentially only one more than the above patent no. 3,138,743, and both were awarded on the same date, viz. June 23, 1964. Note that the filing date of this finally issued patent, May 6, 1959, was also exactly the filing date of the OA (see 1.1) that had a different title than this issued patent. Also it is important to note that even though Kilby had filed his OA (see 1.1) about two months and three weeks ahead of Noyce, Noyce was awarded his patent no. 2,981,877, three years and two months earlier than Kilby. This was due to the incompleteness and deficiencies of Kilby’s invention. It could have been probably due to other reasons also, including possibly intentional delay. The latter was reported to be a tactic used later by TI on the sensing circuits of the DRAM, which had derived a fortune of annual royalties to TI from the Japanese manufacturers on silicon integrated circuits. Another important point regarding Kilby’s patent no. 3,138,744 lost in the details and apparently omitted by the USPTO, was put on record by Lehovec.26 Ref. no. 6 in Lehovec’s paper states, “J. S. Kilby, US Application 811-476 filed on May 6, 1959; re-filed as US Application 218-206 on Aug. 16, 1962.” Application 811,476 filed on May 6, 1959 is the key patent no. 3,138,744 of Kilby. The USPTO did not record the re-filing in 3,138,744 as US Application 218-206 on Aug. 16, 1962. Therefore either there is a conflict between Lehovec’s and USPTO’s records of events, or nothing happened on its re-filing as Application 218,206 on Aug. 16, 1962. Why had it to be re-filed anyway? Was it due to the ongoing actions of the Board of Patent Interferences after Noyce’s patent was issued ahead of Kilby in 1961, and before finalizing their decision later to issue Kilby’s patents in 1964? The mystery of various actions of USPTO, Board of Patent Interferences (which ruled in favor of TI), Court of Customs and Patent Appeals (CCPA — which overturned the decision of BPI, and ruled in favor of Fairchild and Noyce), and TI itself, is too complex to be resolved, and as yet it has not been resolved. I have ordered case history files of TI patents from USPTO recently, but USPTO has failed to complete my order citing that they

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have been lost! I am still pursuing this matter with higher authorities at USPTO, but I have had no satisfactory response from them so far. (See Section 1.5). 1.4. US patent no. 3,261,081,34 “Method of Making Miniaturized Electronic Circuits”; USPTO wrote on the front page of the patent, “Original Filed Feb. 6, 1959”, and “July 19, 1966” as the patented date. On inside above column 1, the USPTO wrote “Original application February 6, 1959, Ser. No. 791,602, now Patent No. 3,138,743, dated June 23, 1964.” As stated above in Section 1.1, the filing date of the OA was not recorded by the USPTO to be Feb. 6, 1959. Therefore it is rather strange that the USPTO printed “Original Filed Feb. 6, 1959” on the front page of US patent no. 3,261,081, and wrote on the inside front page the confused or grammatically erroneous English “Divided and this application Mar. 16, 1964, Ser. No. 352,380”. The issue date of this patent is July 19, 1966, which represents a delay of about 2 years longer than the other two patents purported to have been filed on Feb. 6, 1959 also. The confused published facts of the filing and issue dates of Kilby’s patents appear quite circumspect indeed. Since the above four documents of Kilby’s IC invention need to be discussed in this chapter, their analyses shall essentially follow the methodology sequence given in Chapter 5, but modified to give a cumulative report first in the next Section 2. This will help the reader to grasp the totality of Kilby’s IC invention easily at the outset, and then follow the detailed analysis of the texts and claims of each document individually. 1.5. Why the facts of the filing date of Kilby’s OA (which was so important to claim the earliest filing date of the IC invention by Kilby) were not ascertained correctly earlier? It appears still to be in a state of confusion at USPTO as evidenced by their written communications29,30 with me in 2005. As of writing this book, my attempts to obtain the “Certified Copy each of the File History of patent numbers 3,138,743 and 3,138,744, both being based on the original application number 03,791,603” from the USPTO have not been successful. For detailed discussions, see Section 4.2 in Chapter 15. The response from the USPTO is given in Figure 15.1 at the end of Chapter 15. It states, “We are unable to fill your order because the files for the above patent numbers are unavailable due to being in the

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lost category. . . .” I have initiated further inquiry to find out why such important files have been “lost” by the USPTO. So far I have not received any reply from the USPTO. If the files of “Certified Copy each of the File History of patent numbers 3,138,743 and 3,138,744, both being based on the original application number 03,791,603” ordered and paid for by me were not “lost” by the USPTO, they would have helped to clarify at least two mysteries: 1.5.1. The mystery of the filing date of Kilby’s OA no. 03,791,603. 1.5.2. The mystery of various actions of USPTO, Board of Patent Interferences (which ruled in favor of TI), and of the Court of Customs and Patent Appeals (CCPA — which overturned the decision of BPI, and ruled in favor of Fairchild).

2. A few important facts and comments on the invention of ICs by Kilby Given and discussed below are a few important facts and comments to help the readers in appreciating the details of Kilby’s invention. Some of these facts and comments may be repeated throughout the book for the sake of continuity and emphasizing their relevance to the discussion at a given point. 2.1. Kilby became aware of Dummer’s concepts of ICs given in 1952, when he had attended and listened to Dummer’s paper at the symposium4.1 in Washington, DC. 2.2. Kilby joined TI in 1958, wrote and demonstrated his invention of ICs only as hybrid-ICs, not as monolithic-IC, using Ge mesa devices and wire-bonded interconnects. They are never used to make the monolithicICs. (Stewart6 had been working at TI even before Kilby had joined it in 1958; see Chapter 10. Even though their patents were issued on the same date assigned to TI, and had similar disclosures for fabricating devices in the same piece of semiconductor, they did not refer to each other’s patents.)

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2.3. Kilby wrote his original patent application (OA) and claimed to have filed it with USPTO on Feb. 6, 1959. However, the USPTO recorded it as filed on May 6, 1959, as documented in recent communications with me,29 or that it “does not have an official filing date.”30 These conflicting responses from the USPTO cannot be explained. A staff member “Chris” of USPTO told me over telephone that, “If an application does not have an official filing date, then no action was taken by USPTO on it, and no patent was awarded for it.” Kilby wrote repeatedly in the text of his issued patents and in his subsequent papers that his patent was filed on Feb. 6, 1959. Kilby’s most recent paper19 was published in 1998, which was only two years before he was awarded the Nobel Prize in 2000. 2.4. Kilby wrote the concepts (strikingly similar to Dummer’s4.1 ) which were only partly consistent with monolithic-ICs in the beginning of only one of his patents.1 But its entire text and all the claims were for producing hybrid-ICs. He did not give materials and processes in his patent correctly for producing monolithic-ICs. 2.5. Kilby received his IC patents1,22 in 1964 after Noyce’s patent2 was issued in 1961, even though he had filed earlier than Noyce. 2.6. Kilby lost his patent interferences against Noyce (for monolithic interconnects) and against Lehovec (for p–n junction isolation in ICs). These rulings by USPTO clearly suggest that Kilby did not qualify for the Nobel Prize, especially as it was cited by the Nobel Committee for his award. They also provide evidence that the Nobel committee had not done a thorough job of evaluating the contributions of Kilby for the Nobel award (see Chapter 12 and Appendix 7). 2.7. Kilby continued to regard the monolithic concept as controversial since the early years until later in his paper19 in 1998. He cited in this paper only his patent no. 3,138,743 as he reviewed his and Noyce’s IC inventions. Kilby had not written his IC concepts in this patent. No other patents were cited by him, including his patent no. 3,138,744 in which he did write his IC concepts. 2.8. Kilby made no contributions to monolithic-IC technologies even after patents were awarded for his version of the IC invention, though it

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was well known that the planar technology and other advanced technologies were essential to fabricate them. 2.9. Kilby was awarded the Nobel Prize7 in 2000 “for his part in the invention of the ICs”. But what was his part in the invention of what kind of ICs was not specified by the Nobel Committee. His invention was only for hybrid-ICs with Ge mesa transistors and wire-bonded interconnects which are not manufactured and sold because they are not monolithic-ICs. Also it is inexplicable why Kilby was given twice the financial award than to each of the other two co-recipients of the Nobel Prize (for details, see Chapter 12). 2.10. Kilby’s patent no. 3,138,743, serial no. 791,602 was issued on June 23, 1964, the same date on which his patent no. 3,138,744 (note the difference in the patent nos. sequentially by only 1), serial no. 811,486 was issued. Also 3,138,743 was issued by USPTO, and wrote on this patent as filed on Feb. 6, 1959. This filing date is same as that of original application (OA) no. 791,602 claimed by Kilby, although this filing date was not confirmed by USPTO.29,30 Another patent 3,261,081 was also filed on Feb. 6, 1959 (see Section 1.4). The texts and figures of OA, 3,138,743 and 3,261,081 were exactly the same in all three, but their claims were entirely different. Huge differences in their claims can be read in the discussions in Sections 15.2, 16 and 20 in this chapter. The original copies of OA, 3,138,743, 3,138,744 and 3,261,081 are given at the end of this chapter. They all contain the same sets of figures and texts. The claims of 3,138,743 and 3,261,081 revised from the OA did not support the text and the figures, so this violates the US patent code of Section 35 USC112. But still the USPTO allowed these patents. All of these facts are quite unusual and highly circumspect legal procedures of USPTO. Those readers who are interested in the details should read and compare the original documents given at the end of this chapter. 2.11. To inform the reader briefly, Section 35 USC 112 requires that: 2.11.1. The new claims must be enabled. 2.11.2. The new claims have their best mode disclosed.

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2.11.3. The written description must prove that the inventor (e.g., Jack Kilby) was in appreciative possession of the later claimed subject matter as of his original filing date. Under Section 35 USC 112, one is allowed to re-write the claims entirely while keeping the text the same, as long as the specification (text and drawings) provides full support for the new set of claims and one is not double patenting (claiming the same thing twice). The US patent statute was significantly re-written in 1952. However since Kilby’s patent filings were made after the 1952 Act was passed, Section 112 applies to Kilby’s patents. 2.12. In his ECS paper19 of 1998, Kilby referred to 3,138,743, not to 3,138,744, and not to any other patents of his. This also re-confirms that he did not get any patents in the future on ICs to claim and reinforce his invention, and that he did not make any contributions to or invent anything further for monolithic-ICs. To refer to 3,138,743, and not to 3,138,744, was not a good decision by Kilby. Or perhaps it was poor advice that he may have been given by TI’s patent attorneys in 1998 to go backward in time to claim the earlier filing date, which was not even confirmed by USPTO.29,30 At least in 3,138,744, Kilby had stated his concept of the invention, though it was only partially correct. In 3,138,743, his concept of the invention was not stated at all anywhere in the text. One could also suspect that the one digit difference between “3” and “4” could be a typographical error or even a negligence of the editor of the ECS paper via global replacement of a typographical error. But, there was no erratum later on this ECS paper that we were able to locate in the open literature or in a later issue of ECS. 2.13. In addition to patent no. 3,138,743, another patent no. 3,261,081 was awarded to Kilby on ICs based on the original application (OA) serial no. 791,602 claimed to have been filed on Feb. 6, 1959. Patent no 3,138,744 was awarded to Kilby based on serial no. 811,486 filed on May 6, 1959. However he did refer to the OA in this patent in column 1, lines 55–57, “. . . To that end, I have proposed in my pending application for patent, Serial No. 791,602, filed February 6, 1959, . . . .” To repeat once again, the

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filing date of OA serial no. 791,602 claimed by Kilby as February 6, 1959, has not been confirmed by USPTO.29,30 3. Original patents As listed in Section 1, Kilby’s Original Application no. 791,602, and the three patents derived from it, are nos. 3,138,743, 3,138,744 and 3,261,081. As it has been explained and documented in Chapter 5, Section 6, the filing date of OA claimed by Kilby February 6, 1959, is controversial. The recent correspondence of the USPTO with me29,30 has confirmed that there is no such filing date in their records for this OA; either it was May 6, 1959, or it did not have any filing date assigned to it. The texts and figures of OA, 3,138,743 and 3,261,081 were exactly the same in all three, but their claims were entirely different. Kilby did not write his version of the monolithic concept in any of these three, except that he did write it in 3,138,744. In my opinion, Kilby’s strongest document among the four (OA; 3,138,743; 3,138,744; and 3,261,081) is 3,138,744. Therefore the coalesced analyses of Kilby’s patents given below shall focus on 3,138,744, although the important points from the other three shall also be included. 4. Summary of the invention Kilby’s invention of IC was only of a hybrid-IC, not a monolithic-IC, using Ge mesa devices which were isolated also by mesa technology, and connected electrically by wire-bonded interconnects. Neither these devices nor such technologies are ever used to make the monolithic-ICs. 5. Key figures The figures are same in all three documents: 791,602; 3,138,743; 3,261,081. A few key points from the figures are: 1. Figures 1–5 show mesa structures. 2. Figures 6 and 8 show wire-bonded interconnects. In patent no. 3,138,744, Figs. 1 and 2 show the top view and the circuit diagram of the test device, and Figs. 3 and 4 show the mesa structures.

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Neither mesa structures nor wire-bonded interconnects are ever used in monolithic ICs.

6. Key claims Entirely different in all three: 791,602; 3,138,743; 3,261,081. But they are all for the same invention. Moreover they are not supported by the texts and figures. For possible violation of 35 USC 112, see Sections 2.10 and 2.11.

7. Reduction to practice Kilby1 did implement the “reduction to practice” of his invention before filing his OA and the IC patents. Kilby17 had “put one transistor and a few other components on a piece of germanium 7/16 × 1/16 in. glued to a glass slide”. These devices were connected by wire bonding to complete his IC (see Chapter 1, Fig. 1.1; Chapter 5, Fig. 5.3). The resulting product was only a hybrid-UC-IC using Ge, not a monolithic-IC. Almost all of the previous authors and historians have overlooked this key fact, and heralded erroneously Kilby’s effort as the one to have produced the first IC, implying the first monolithic-IC. However, they did not explicitly state the monolithic aspect either. If they implicitly meant IC as hybrid-IC without knowing the difference between a hybrid-IC and a monolithic cannot be ascertained. Braun18 described the procedure used by Kilby, as follows: “In his lab, Kilby put one transistor and a few other components on a piece of germanium 7/16×1/16 in. glued to a glass slide, creating the first electronic circuit in which all components — active and passive — were fabricated on a single slice of semiconductor material. The development came to be called the integrated circuit, and it laid the conceptual and technical foundation for all of modern microelectronics. . . . Look around world, look around . . . you’ll see Jack Kilby everywhere.” The last two sentences from this quote do not quite convey the message accurately. This sentiment is also echoed by Berlin17 (see below), when she writes about Kilby’s circuit as, “. . . his was undoubtedly an integrated

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circuit of sorts.” From the characterization “of sorts”, it can be inferred that Kilby’s circuit of his invention was not the IC as it has been and is manufactured in the industry. Kilby’s key patent1 may be considered to lay only partially the conceptual, but not the technical foundation for all of modern microelectronics. Kilby’s invention of the IC as specified in his patent,1 and as demonstrated in his reduction to practice samples, was that of hybrid-UC-IC. Therefore it cannot be claimed that it accounts for the omnipresence of the monolithic-ICs today or from the inception of the IC industry. Not to take away the credit entirely from Kilby, perhaps it will be more accurate to re-phrase Braun’s last sentence as “. . . Look around world look around . . . you’ll see Jack Kilby and Bob Noyce everywhere.” Or perhaps even more accurate expression could be “. . . you’ll see Jack Kilby, Bob Noyce, Jean Hoerni, Kurt Lehovec, Gordon Moore, and a few more key inventors/scientists/engineers everywhere.” Moore’s name has been included among the original inventors because of his key contributions also beyond the invention of ICs to their present advanced state of omnipresence. From the original photograph15 of Kilby’s invention in 1958 (see Chapter 1, Fig. 1.1) it is clear that wire bonding between various devices in Ge was used. In fact, two separate pieces of Ge (not identified in the photo, but they can be seen clearly) were glued to a glass slide. Various regions of the devices were wire-bonded to the electrodes from these two Ge pieces. The interconnections between these regions were not monolithic on, and not contiguous to, the surfaces of the germanium pieces. Berlin17 also writes: “In the fall of 1958, a young Texas Instruments researcher named Jack Kilby set out to build an integrated circuit. By early 1959, he had built a complete circuit on a single germanium substrate. Kilby’s circuit was meticulously hand assembled with a network of gold wires connecting the components to each other. The wires precluded the device from being manufacturable in any quantity, a fact of which Kilby was well aware, but his was undoubtedly an integrated circuit of sorts.” This also confirms the wire bonding used by Kilby. A recent report by Moss49 who was a University of Florida college co-op student assigned to work with Kilby at TI in the summer of 1960,

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also confirms the wire bonding used by Kilby. Moss had tested the “solid circuit” flip-flop (7 resistors, 2 capacitors, 2 transistors, “interconnected with very fine wires”) given to him in 1960 by Kilby. For details, see Chapter 11. In 1998, Kilby19 refers only to his patent no. 3,138,743 in his discussions on the invention of ICs, not to any other patent of his. Kilby writes,19 “To demonstrate the feasibility of the idea, germanium wafers which had previously been diffused for transistors were selected. These were cut and masked with wax to form the necessary circuit elements for a simple phase shift oscillator. It was operated successfully on September 12, 1958. Within a few weeks a similar process was used to produce a flip-flop circuit. A patent application covering both germanium and silicon was prepared and filed in February, 1959.” As explained above, Kilby’s invention was not a monolithic-IC, i.e., it was not an IC, but it was a hybrid-UC-IC. Also as documented in direct communications between USPTO and me,29,30 Kilby’s23 application no. 03/791,602 was not filed on February 6, 1959, as claimed by Kilby repeatedly in his various patents as well as in his recent paper19 in 1998. It was recorded by USPTO to have been filed instead on May 06, 1959, or that it had no filing date at all. For details, see Chapter 5, Section 6.

8. Choice of semiconductor Kilby1 had used Ge to demonstrate his concept, which is not used in the monolithic ICs. Kilby wrote in his patent1 : Column 1; Lines 38–44: “. . . problems have arisen when it has been attempted to employ such techniques in the forming of semiconductor devices, such as diodes and transistors, for conventional semiconductor material such as germanium or silicon, do not lend themselves to evaporation or other methods heretofore employed for the application of passive elements . . . .” Kilby was referring to the prior art of circuit packaging techniques. However, throughout the patent1 except in Column 1 Line 41, including

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all the claims, Kilby writes only “semiconductor material” and does not specify the semiconductor to be either Ge or Si. 9. Fabrication method of devices Kilby wrote in his patent1 : Column 3; Lines 23–25 & 28–34: “Initially, a block of semiconductor material is procured and doped either in its entirety or over an area in which an active element is to be formed. . . . Thus impurities may be diffused in successive layers into the surface of the semiconductor block to form the emitter, base and collector regions. (Para) After doping has been accomplished, upper layer areas other than those required for the active circuit elements may be eliminated by etching, thereby leaving only those desired . . . .” Kilby is specifying the formation of mesa transistor. The mesa structure is also visible clearly both in Figs. 3 and 4 of Kilby’s patent no. 3,138,744, and in Figs. 4 and 5 of his application no. 03/791 and patents 3,138,743 and 3,261,081. The isolation of devices used by Kilby in his reduction to practice and as described in his patents used mesa etching of devices for isolation. This is never used in the fabrication of monolithic-ICs. 10. Insulating layers Kilby wrote in his patent1 : Column 2; Lines 70, 71; Column 3; Lines 1– 4: “Immediately over film 8 is located a dielectric film 7 which may be of any suitable material, such as silicon monoxide; and immediately above film 7 is positioned relatively low resistance film 6, which as heretofore mentioned, comprises the upper conducting film of the capacitor C.” (Underlining of silicon monoxide done by me here to draw attention to it, and emphasize that it was not silicon dioxide.) Kilby did not write how silicon monoxide was deposited or grown. It cannot be grown easily, because the grown film is normally silicon dioxide. So, it is implied that it was a deposited film. Vacuum evaporation was one of the commonly used processes to deposit silicon monoxide films during those years, and it is used even currently in a few non-IC processes. Also, silicon monoxide was used by Kilby in his patent1 as the dielectric for the

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capacitor, not for covering the junctions of the transistor as it is done in planar technology.

11. Interconnects As discussed already in Section 7 above, Kilby1,15,16 had used Au wirebonding between the devices to demonstrate the feasibility of his concept. This is done in hybrid-ICs, not in monolithic-ICs. Kilby wrote in his patent1 : Column 4; Lines 12–21 and 38–44: “. . . Thus, for example, if an NPN-type transistor is being formed, a mask might be used to cover all of the surface except the emitter and collector recesses, and antimony-doped gold or other suitable material could be evaporated or otherwise deposited through the mask into the recesses. Thereafter, the entire surface of the member 1 could be masked except for the base recess, into which a suitable ohmic-contact-making material such as aluminum might be evaporated or otherwise deposited . . . . Next, any suitable highly conductive material, such as copper or gold, is applied by vacuum deposition technique . . . . A relatively thick film is applied to the indicated areas in order that the resistance thereof maybe made low.” Kilby proposed to use Sb-doped Au for ohmic contacts to N-type emitter and collector, and Al for ohmic contact to P-type base, of the n–p– n transistor, and he specified thick films of either Cu or Au by themselves for the interconnects. He had also proposed that these “or other suitable material could be evaporated or otherwise deposited through the mask into the recesses”. As it is well known, evaporation or deposition through a mask is not done in the monolithic-ICs. However, Al and Cu are used but with appropriate modifications as well as barrier and cap layers, and photolithographic and etching techniques are used to define the interconnect patterns. Even with the barrier and cap layers, the use of Au interconnects in ICs has been discontinued for a long time (although they had been used earlier in the beam-lead technology).

12. Impact of 35 USC 112 The impact of US Patent Code 35 USC 112 has already been discussed above in Sections 2.10 and 2.11.

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13. Overall comments The bottom line of Kilby’s patent is that it claims an integrated device consisting of a mesa transistor, whose emitter, base and collector regions are connected to passive components such as resistors and capacitors by interconnects of copper or gold over an insulating layer such as silicon monoxide. Copper and gold interconnects by themselves do not adhere to the insulating layers, silicon monoxide and mesa transistors are not used in the ICs. So, at best, Kilby’s invention in his patent is an integrated circuit having a mesa transistor, and the interconnects as specified will be non-adherent and non-functional. In the famous slide showing Kilby’s first integrated circuit (see Chapter 1, Fig. 1.1), transistors and passive components in two separate pieces are glued to a glass slide, and the different regions of the transistors, capacitors and resistors are shown interconnected by dangling wires bonded to them. Thus, Kilby’s first integrated circuit was a hybrid-integrated circuit, not the forerunner of the monolithic ICs of today. 14. Kilby’s OA (Original Application) No. 791,602, “Miniaturized Electronic Circuits and Method of Making”, (Claimed to have been filed on Feb. 6, 1959, but recorded filing date was May 6, 1959; no patent action taken and no Patent was issued on this application) This is the original application on which Kilby’s patents (nos. 3,138,743, 3,138,744 and 3,261,081) are based. Therefore its review is important to understand the basic invention of Kilby. 14.1. Key items of OA No. 791,602 Important items of Kilby’s Original Application No. 791,602, analyses and comments on related patents based on it are given below in Table 7.1. 14.2 Detailed analyses of all the claims of Kilby’s OA no. 791,602 For pedantic reasons, detailed analyses of all the claims of Kilby’s OA No. 791,602 are given.

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Chapter 7. Kilby’s Invention of IC: Key Patents, Claims and Analyses Section 14. Kilby’s OA No. 791,602

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Table 7.1. Important items of Kilby’s Original Application No. 791,602, analyses and comments on related patents based on it. Key items

Analyses and comments

1. Original application no. 2. Filing date. Responses by USPTO to Saxena in 2005

791,602 Feb. 6, 1959 (Claimed by Kilby.) While obtaining a copy of Kilby’s Application Serial No. 791,602, “Miniaturized Electronic Circuits and Method of Making” from the US Patent Office (USPTO), I received the following two official responses recently: 2.1 E. Bornett,29 Certifying Officer, USPTO, to Dr. Arjun N. Saxena, “This is to certify that annexed hereto is a true copy from the records of the United States Patent and Trademark Office of those papers of the below identified patent application that met the requirements to be granted a filing date under 35USC111. Application: No. 03/791,602; Filing date: May 06, 1959.” Sent by USPTO to me on September 26, 2005. (See Fig. 5.5.) 2.2 Customer Service Department,30 USPTO, to Dr. Arjun N. Saxena, “The product or service you requested cannot be fulfilled because the application #03/791,602 does not have an official filing date.” Sent by USPTO to me on November 02, 2005. (See Fig. 5.6.) The above seemingly contradictory responses cannot be explained. No matter what may be the problem of keeping records accurately at the USPTO, one fact is clear from the above that the official filing date of Kilby’s Application No. 03/791,602 was NOT February 6, 1959, as claimed by Kilby22 ; instead it was May 06, 1959, which was also the filing date of Kilby’s issued patent no. 3,138,744. It is also important to note that no further action was taken either by Kilby or by the USPTO, and no patent was ever issued, on Kilby’s Application No. 03/791,602 per se. Patent no. 3,138,743 with “Filed Feb. 6, 1959”; Ser. No. 791,602 [This is the only Kilby patent referred to in Kilby’s 1998 paper before he received the Nobel Prize in 2000.]

3. Patent issued anyway with OA 791,602 filed Feb. 6, 1959.

(Continued)

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Table 7.1.

(Continued )

Key items


4. Another patent issued anyway with OA 791,602, but with “Divided and this application Mar. 16, 1964, Ser. No. 352,380.” 5. Texts in OA & the patents.

Patent no. 3,261,081 with “Original Field Feb. 6, 1959”; with OA “791,602”, but with “Divided and this application Mar. 16, 1964, Ser. No. 352,380.”

6. All Figs. 1–8.

7. Claims.

Same in all three: 791,602; 3,138,743; 3,261,081. None of these three state the monolithic concept even partly as was done by Dummer in 1952 (although Kilby gives it only partly in his patent no. 3,138,744). A few key points described in the texts of these three patents are: 1. Shaping for isolation between components; 2. Shaped “mesas” for transistors, diodes, and capacitors; 3. Evaporated Si-oxide for dielectric layer for capacitors; 4. Au-plated Kovar leads “attached by alloying”; 5. Au evaporated through a mask to make ohmic contact with n-regions; 6. Al evaporated through mask to provide emitter areas; 7. Au wires thermally bonded; 8. Au “laid down on the insulating material” for interconnects. None of these are ever used in Si monolithic-ICs. Kilby also states on p. 7 of this application, “. . . examples of suitable semiconductor materials Ge, Si, intermetallic alloys such as GaAs, AlSb, InSb, as well as others.” Technologies need for Ge, GaAs, AlSb, InSb, etc are not the same as those used in Si monolithic-ICs. Exactly same in all three: 791,602; 3,138,743; 3,261,081. A few key points from the figures are: 1. Figures 1–5 show mesa structures; 2. Figures 6 and 8 show wire-bonded interconnects. None of these are ever used in monolithic ICs. Entirely different in all three: 791,602; 3,138,743; 3,261,081. But they are all for the same invention. Moreover they are not supported by the texts and figures. For possible violation of 35 USC 112, see next item below. (Continued)

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Table 7.1.

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(Continued )

Key items


8. Possible violation and irregular use of the patent law?

1. Patent no. 3,138,743: Under 35 USC 112, re-writing the entire set of claims in 3,138,743 which are completely different from 791,602 was not allowable, because they do not support the specifications of the text and the figures. But this was allowed by the USPTO. Why? 2. Patent no. 3,261,081: Even though all the texts and Figs. In 3,261,081, OA 791,602 and 3,138,743 are the same, and their claims are entirely different, if this patent 3,261,081 was filed as Ser. No. 352,380 on Mar. 16, 1964, then the patent law 35 USC 112 would not have been violated in issuing this patent. However, the revised filing date Mar. 16, 1964 was not written on the front pages of 3,261,081; instead “Original filed Feb. 6, 1959” was written. This appears rather strange action by USPTO. All of the above actions were very unusual, and difficult to understand now as we know the laws under 35 USC 111 and 35 USC 112 to be. During 1959–1964, the field of planar transistors, devices and monolithic ICs were in its infancy as compared to what we know now in 2008. Therefore lack of appropriate expertise in USPTO examiners may have contributed to the unusual decisions made by them when confronted by teams of aggressive patent attorneys trying to secure the maximum for their clients’ patents. 3,138,743 and 3,138,744 (note that they differ in number by only 1, i.e., they were successive patents) were issued on the same date June 23, 1964. Note the following points: 1. USPTO took over 5 years to review both of these patents since their filing in 1959 and finally issued them on the same date June 23, 1964.

9. Significance of the same issue date of 3,138,743 and 3,138,744.

(Continued)

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Table 7.1. Key items

(Continued )

Analyses and comments 2. Noyce’s patent 2,981,877 had already been issued on Apr. 25, 1961, which had described the monolithic ICs. The patent interference between Kilby and Noyce for the earlier award of patent to Noyce was settled as a compromise that both Noyce’s and Kilby’s patents were considered necessary to manufacture ICs (even though Kilby’s invention was not for monolithic ICs). 3. Lehovec’s patent 3,029,366 had already been issued on Apr. 10, 1962, which had described the p–n junction isolation for ICs. The lawsuit between Kilby and Lehovec was pending, which was decided by the Board of Patent Interference later to be in favor of Lehovec. One key issue of Kilby’s lawsuit was to gain priority over Lehovec’s filing (April 22, 1959). But Kilby’s attempts to keep the filing date of OA 791,602 to be Feb. 6, 1959, were unsuccessful as decided by the US Board of Patent Interference #93.612 after a final hearing on March 16, 1966. Why did USPTO still keep the filing date of 3,138,743 to be Feb. 6, 1959 is a mystery. 4. Kilby’s patent 3,138,744 (Ser. no. 811,486, Filed May 6, 1959) was re-filed as US Application Ser. No. 218,206 on Aug. 16, 1962, according to Lehovec.26 But this re-filing action was not published in Kilby’s patent 3,138,744. This is the only patent of Kilby which at least states the basic concept of monolithic ICs, though only partly correct. Kilby did not even suggest, what to say of giving, the correct procedures to accomplish what he had stated. 5. With Kilby’s patent interferences against Noyce and Lehovec ongoing, it appears that there were desperate attempts to reach a compromise with USPTO, which allowed issuing both 3,138,743 and 3,138,744 successively on the same date (Continued)

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10. Monolithic concept as controversial?

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(Continued )

Analyses and comments June 23, 1964, allowed 3,138,743 to keep its original serial no. 791,602 and filing date of Feb. 6, 1959, and allowed 3,138,744 to keep its original serial no. 811,476 filed May 6, 1959 (and to ignore its re-filing as serial no. 218,206 filed Aug. 16, 1962). These desperate attempts to get the two patents out of the way appear to be unusual if not irregular practice by USPTO. Kilby continued to regard the monolithic concept as controversial until as late as in 1998, according to published records.19 The patent no. 3,138,744 is the only patent of Kilby which at least states the basic concept of monolithic ICs, though only partly correct in a limited manner. However, Kilby chose to refer to his patent no 3,138,743 instead of 3,138,744 in his 1998 paper.19 3,138,743 does not mention monolithic concept at all. The two possible advantages of 3,138,743 over 3,138,744 were: 1. Earlier filing date claimed as Feb. 6, 1959 (instead of May 6, 1959). 2. Revised entire set of claims (which were in possible violation and irregular use of the patent law?). The definition of the monolithic concept has not been clear in Kilby’s writings from the very beginning. Let me itemize three technical points as follows to illustrate this. 3.1 Kilby defines the fabrication of all the devices in a semiconductor piece by itself as monolithic, without specifying the processes for their fabrication, interconnection and isolation. His definition is incomplete. 3.2 Kilby does not specify the correct process to fabricate even just the devices in the semiconductor in his patents. The correct process must be the planar process, and the semiconductor must be silicon. Kilby had used mesa technology for devices and had used germanium. (Continued)

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(Continued )

Analyses and comments 3.3 Kilby does not give the correct process and materials to interconnect the devices monolithically in the piece of semiconductor. The CCPA (Court of Customs and Patent Appeals) had ruled against Kilby, and ruled in favor of Noyce. Kilby had used bonded gold wires to connect the devices flopping in the air. From the above three key technical points, it can be inferred that the monolithic concept remained controversial for Kilby because he failed to give them correctly. However, if anybody who should have known about the monolithic concept correctly should have been Kilby himself, because the company he worked for, i. e., TI, was one of the first company selling Si monolithic-ICs from 1960 onwards. In addition to the monolithic concept, the factors of yield, optimum use of proper materials, and ability to change designs were not proven to be advantageous for Kilby’s invention. While these factors needed further evaluation by cost analysis and large volume manufacturing data, the three key technical points needed no debate whatsoever. As mentioned in comment 3.3 above, it is quite inexplicable that all the offices and highly qualified personnel involved (e. g, USPTO, The Board of Interference of the Patent Office, CCPA, all the technical and legal personnel at least in TI and Fairchild) did not seem to scrutinize and take appropriate actions for all these years.

Claim 1. “A circuit device comprising a body of single crystal material of one type conductivity containing a diffused layer of opposite type conductivity which defines with said body a diffused p–n junction, said body defining in one region thereof a circuit element selected from the class consisting of active circuit elements and passive circuit elements,

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and said body defining in a contiguous region thereof a passive circuit element.” Comments on Claim 1: Note that the claimed device is “A circuit device”, not “Integrated circuit” as Kilby did in 3,138,743. “Single crystal material” not specified. The description of one region with active devices and passive devices, “and said body defining in a contiguous region thereof a passive circuit element” is O’K. Claim 2. “A circuit device comprising a body of single crystal material of one type conductivity containing a diffused layer of opposite type conductivity which defines with the said body a diffused p–n junction, said body defining in contiguous regions thereof different circuit elements.” Comments on Claim 2: Re-hash of words in Claim 1; additional “defines with the said body a diffused p–n junction.” Claim 3. “A circuit device comprising a body of single crystal semiconductor material of one type conductivity containing a diffused layer of opposite type conductivity which defines with said body a diffused p–n junction, said body defining in one region thereof an active circuit element, said body defining in a contiguous region thereof a passive circuit element, and contact means attached to said body remote from said active circuit element.” Comments on Claim 3: Re-hash of words in Claim 2; additional “contact means attached to said body remote from said active circuit element.” Contact means not defined, and how they were fabricated. Claim 4. “A circuit device comprising a body of single crystal semiconductor material of one type conductivity containing a diffused layer of opposite type conductivity which defines with said body a diffused p–n junction, said body defining in one region thereof s transistor, said body defining in a contiguous region a passive circuit element, and contact means to said body remote from said transistor.” Comments on Claim 4: Re-hash of words in Claim 3; additional “defining in one region thereof a transistor .”

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Claim 5. “A circuit device comprising a body of single crystal semiconductor material of one type conductivity containing a diffused layer of opposite type conductivity which defines with said body a diffused p–n junction, said body defining in one region thereof a diode, said body defining in a contiguous region thereof a passive circuit element, and contact means attached to said body remote from said diode.” Comments on Claim 5: Re-hash of words in Claim 4; additional “defining in one region thereof a diode.” Claim 6. “A circuit device comprising a body of single crystal semiconductor material of one type conductivity containing a diffused layer of opposite type conductivity which defines with said body a diffused p–n junction, said body defining in one region thereof a passive circuit element and said body defining in a contiguous region thereof another passive circuit element.” Comments on Claim 6: Re-hash of words in Claim 5; additional “defining in one region thereof a passive circuit element and said body defining in a contiguous region thereof another passive circuit element.” Claim 7. “A circuit device as defined in Claim 1 wherein said circuit element is a transistor and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 7: Re-hash of words in Claim 1; additional “circuit element is a transistor and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Claim 8. “A circuit device as defined in Claim 1 wherein said circuit element is a light sensitive device and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 8: Re-hash of words in Claim 7; additional “circuit element is a light sensitive device.”

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Claim 9. “A circuit device as defined in Claim 1 wherein said circuit element is a power generator means and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 9: Re-hash of words in Claim 8; additional “circuit element is a power generator means.” Claim 10. “A circuit device as defined in Claim 1 wherein said circuit element is a resistor and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 10: Re-hash of words in Claim 9; additional “circuit element is a resistor .” Claim 11. “A circuit device as defined in Claim 1 wherein said circuit element is a capacitor and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 11: Re-hash of words in Claim 10; additional “circuit element is a capacitor .” Claim 12. “A circuit device as defined in Claim 1 wherein said circuit element is an inductor and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 12: Re-hash of words in Claim 11; additional “circuit element is an inductor .” Claim 13. “A circuit device as defined in Claim 1 wherein said circuit element is a diode and said passive circuit element last mentioned is selected from the group consisting of resistors, capacitors, inductors and diodes.” Comments on Claim 13: Re-hash of words in Claim 12; additional “circuit element is a diode.”

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Claim 14. “A method of producing miniaturized electronic circuits comprising the steps of obtaining a wafer of single crystal semiconductor material of one conductivity type, diffusing desired amounts of conductivity type determining impurities into said wafer to create therein components selected from the group consisting of active and passive electrical circuit components, shaping said wafer to obtain isolation between said components and to define the areas utilized by said components in said wafer, and providing internal electrical connections to complete said circuit.” Comments on Claim 14: 14.1 “Single crystal material ” not specified. “. . . shaping said wafer to obtain isolation between said components and to define the areas utilized by said components in said wafer, and providing internal electrical connections to complete said circuit.” Shaping not defined here in the claim, but defined in the text and shown in figures as mesa etching. 14.2 “Providing internal electrical connections” not defined here in the claim, but defined in the text and shown in figures as wire bonds. Claim 15. “A capacitor comprising a body of single crystal semiconductor material, a dielectric layer formed on said body, and a layer of conductive material substantially covering said dielectric layer.” Comments on Claim 15: Formation of a capacitor; “dielectric layer formed on said body” is not defined; evaporation of dielectric layer specified in the text; same comment for the conductive material. Claim 16. “A capacitor as defined in Claim 15 wherein said semiconductor body is silicon and said dielectric layer is an oxide of silicon.” Comments on Claim 16: Rehash of words in Claim 15, but specifies Si and “oxide of Si ”. Whether it is a mono-oxide or di-oxide of silicon is not specified. Claim 17. “A capacitor as defined in Claim 15 wherein said semiconductor body is of n-type conductivity.” Comments on Claim 17: Rehash of words in Claim 16, but specifies n-type Si.

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Claim 18. “A capacitor as defined in Claim 15 wherein said semiconductor body is of p-type conductivity.” Comments on Claim 18: Rehash of words in Claim 17, but specifies p-type Si. Claim 19. “A resistor comprising a body of single crystal semiconductor material containing a p–n junction, said p–n junction defining a boundary for said resistor.” Comments on Claim 19: Formation of a resistor with a p–n junction. Claim 20. “A resistor comprising a body of single crystal semiconductor material of one conductivity type, a region produced in said body by diffusion of impurity of conductivity determining type opposite to said one conductivity type defining thereby a p–n junction in said body, said diffused region comprising the current path of said resistor, and ohmic contacts to said diffused region.” Comments on Claim 20: Rehash of words in Claim 19; a bit more specific description of the resistor. Claim 21. “A method of forming a resistor comprising the steps of obtaining s body of single crystal semiconductor material of one conductivity type, diffusing into said body impurity of a conductivity type opposite to said one conductivity type thereby to define a p–n junction in said body, and determining the resistance and temperature coefficient properties of said resistor by varying the impurity concentration in said diffused region.” Comments on Claim 21: Rehash of words in Claim 20; a bit more specific description of the resistor. Claim 22. “Each and every novel aspect of the invention disclosed hereby.” Comments on Claim 22: It is just a global expression to claim everything.

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15. Kilby’s Patent No. 3,138,743, “Miniaturized Electronic Circuits”; filed Feb. 6, 1959; Serial No. 791,602; issued June 23, 1964 As mentioned in Section 15.1 above, the texts and figures in Kilby’s OA and the two patents of Kilby, viz., 791,602; 3,138,743; 3,261,081, are all the same, but their claims are very different. Therefore only the analyses of all the claims of Kilby’s patent no. 3,138,743 shall be given in this section. As a reminder to the readers, Kilby did not disclose the concept of his IC invention in this patent. Nevertheless, he kept on referring to this patent in his subsequent papers in order to claim its earlier filing date of Feb. 6, 1959. This filing date, however, was not recorded by the USPTO; instead of Feb. 6, 1959, they had recorded it as May 6, 1959, or that it had no filing date at all. Claim 1. “In an integrated circuit having a plurality of electrical circuit components in a wafer of single-crystal semiconductor material , a plurality of junction transistors defined in the wafer, each transistor including thin layers of semiconductor material of opposite conductivity-types adjacent one major face of the wafer providing a base and an emitter region which overlie a collector region, the base-emitter and base-collector junctions of each of said transistors extending wholly to said one major face, a plurality of thin elongated regions of the wafer exhibiting substantial resistance to provide semiconductor resistors, the elongated regions being spaced on said one major face from the transistors, and conductive means connecting selected ones of the elongated regions to regions of selected ones of the transistors.” Comments on Claim 1: The expression “integrated circuit” is used in this patent. It lists its original application (OA) no. 791,602 filed on Feb. 6, 1959. The text and the figures of OA no. 791,602, patent no. 3,138,743 and 3,262,081 are the same, but their claims are different. “Single-crystal semiconductor material” not identified; fabrication of junction transistors (mesa or planar) not given; “conductive means” not given. Claim 2. “In a semiconductor device which includes a single-crystal semiconductor wafer: a junction transistor provided adjacent one major

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face of the wafer by thin layers of semiconductor material of opposite conductivity types overlying one another and extending to said one major face with the emitter-base and base-collector junctions of the transistor extending wholly to said one major face; and a resistor provided in the wafer by a discrete elongated region of the semiconductor material which is spaced from the transistor on said one major face.” Comments on Claim 2: Rehash of words in Claim 1, except a “resistor” provided. Claim 3. “An integrated circuit comprising a wafer of semiconductor material containing a plurality of electrical components including at least one active circuit component and at least one passive circuit component, the active circuit component including at least two thin layers of semiconductor material of opposite conductivity-types extending to one major face of the wafer with p–n junctions of the active circuit component extending wholly to said one major face, the passive circuit component including at least one discrete region of the semiconductor material of the wafer which is spaced on said one major face away from the thin layers of the active component, substantial electrical impedance being exhibited between the semiconductor material contiguous to the at least one discrete region of the passive component and semiconductor material immediately underlying said thin layers of the active component.” Comments on Claim 3: Fabrication method not given, but claims that “p–n junctions of the active circuit component extending wholly to said one major face,” and “substantial electrical impedance” is exhibited. These are NOT supported by the figures or the text. Claim 4. “An integrated circuit according to Claim 3 wherein said active circuit component is a junction transistor, said passive circuit component is an elongated resistor region, and said semiconductor material immediately underlying said thin layers of the active component defines the collector region of the junction transistor.” Comments on Claim 4: Rehash of words in Claim 3; junction transistor and resistor are specified. These are NOT supported by the figures or the text.

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Claim 5. “An integrated circuit according to Claim 3 which further comprises: at least one other active circuit component provided in the wafer and including at least two thin layers of semiconductor material of opposite conductivity-types extending to said one major face with p–n junctions of such other active circuit component extending wholly to said one major face; and at least one other passive circuit component provided in the wafer and including at least one discrete region of the semiconductor material which is spaced on said one major face away from the thin layers of the at least one other active component.” Comments on Claim 5: Rehash of words in Claim 3. These are NOT supported by the figures or the text. Claim 6. “An integrated circuit according to Claim 5 wherein said discrete regions of said passive circuit components include thin surfaceadjacent regions at said one major face of the wafer.” Comments on Claim 6: Rehash of words in Claim 5. These are NOT supported by the figures or the text. Claim 7. “An integrated circuit according to Claim 3 wherein the at least one discrete region of the passive circuit component includes a thin surface-adjacent layer of semiconductor material.” Comments on Claim 7: Rehash of words in Claim 3. These are NOT supported by the figures or the text. Claim 8. “An integrated circuit according to Claim 7 wherein the passive circuit component is a resistor .” Comments on Claim 8: Rehash of words in Claim 7; resistor specified. These are NOT supported by the figures or the text. Claim 9. “An integrated circuit according to Claim 3 wherein at least one of said circuit components includes a thin layer of dielectric material overlying said one major face of the wafer with a thin layer of conductive material overlying the dielectric material .” Comments on Claim 9: Capacitor formation.

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Claim 10. “A semiconductor device comprising a body of single-crystal material; an active circuit component provided adjacent one major face of the body and including thin regions of the semiconductor material which extend to said one major face, each of such regions being of different conductivity than adjoining semiconductor material with the interface between each such region and other of the semiconductor material of the body extending wholly to said one major face; a passive circuit component provided in the body by a discrete portion of the semiconductor material which is spaced from the active circuit component on said one major face, substantial electrical impedance existing through the body between said thin regions of the active circuit component and the discrete portion of the passive circuit component.” Comments on Claim 10: Rehash of words in Claim 3. These are NOT supported by the figures or the text. Claim 11. “A semiconductor device according to Claim 10 wherein at least part of said substantial electrical impedance is exhibited by at least one p–n junction within the wafer.” Comments on Claim 11: Rehash of words in Claim 10; claims p–n junction isolation (but this was overruled by the Board of Patent Interference later). These are NOT supported by the figures or the text. Claim 12. “An integrated circuit comprising a wafer of single-crystal semiconductor material having a plurality of electrical circuit components therein, the components including an active circuit component which comprises thin regions of semiconductor material of opposite conductivitytypes closely adjacent one major face of the wafer with p–n junctions between such thin regions extending wholly to said one major face, the components further including a semiconductor resistor provided by a discrete elongated region of the wafer which is spaced on said one major face from the active circuit component, and a conductive lead connecting an end of the elongated region to one of the thin regions of the active circuit component.” Comments on Claim 12: What is the conductive lead and how is it fabricated? Not given. NOT supported by the figures or the text.

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Claim 13. “In an integrated circuit having a plurality of circuit components in a wafer of single-crystal semiconductor material, a pair of junction transistors defined in the wafer with each transistor including thin layers of alternate conductivity type adjacent one major face of the wafer providing a base and an emitter region which overlie a collector region, the base-emitter and collector-base junctions of each of said transistors extending wholly to said one major face, elongated semiconductor means defined in the wafer and exhibiting substantial resistance to provide load resistor means for the pair of transistors, first conductive means connected to the collector region of one of the transistors and to an end of the elongated semiconductor means, second conductive means connected to the collector region of the other one of the transistors and to an end of the elongated semiconductor means, means including contacts to the emitter regions of the transistors and to the elongated semiconductor means for applying operating bias to the transistors and means including separate contacts on said base regions for applying inputs to said pair of transistors.” Comments on Claim 13: What are the conductive means and how are they fabricated? Not given. NOT supported by the figures or the text. Claim 14. “In an integrated circuit according to Claim 13 first and second elongated semiconductor regions defined in the wafer and exhibiting substantial resistance to provide base resistors for the pair of transistors, and conductive means separately connecting an end of the first elongated region to the base region of one of the transistors and an end of the second elongated region to the base region of the other of the transistors.” Comments on Claim 14: What is the conductive means and how is it fabricated? Not given. NOT supported by the figures or the text. Claim 15. “An integrated circuit having a plurality of electrical circuit components in a wafer of single-crystal semiconductor material, at least one of the components being an active circuit component which includes thin layers of semiconductor material of alternate conductivity types defined in the wafer adjacent one major face thereof with p–n junctions of such active circuit component extending wholly to said one major face,

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at least one of the components being a passive circuit component which includes at least one discrete region defined in the wafer, the passive circuit component being spaced on said one major face from the active circuit component, substantial electrical impedance being exhibited through the wafer between the active circuit component and the passive circuit component, a plurality of interconnections between selected circuit components, the circuit components and interconnections being so arranged and constructed as to allow, upon the application of electrical power, the performance within the structure of an electrical function equivalent to the function performed by a plural element electrical network.” Comments on Claim 15: What are the plurality of interconnections and how are they fabricated? Not given. NOT supported by the figures or the text. Claim 16. “An integrated circuit comprising a wafer of singlecrystal semiconductor material containing a plurality of electrical circuit components defined in the wafer, the circuit components including an active circuit component which comprises at least two thin regions of the wafer of opposite conductivity-types each extending to one major face with the junction between each such thin region and other semiconductor material of the wafer extending to said one major face, the circuit components further including a passive circuit component which comprises at least one discrete region of the semiconductor material, the discrete region being spaced on said one major face from the thin regions of the active circuit component, non-common regions of the active and passive circuit components being interconnected to for at least part of an electrical circuit.” Comments on Claim 16: How and with what materials “being interconnected”? Not given. NOT supported by the figures or the text. Claim 17. “In a semiconductor device according to Claim 2, said thin layers of said junction transistor being portions of a raised mesashaped part of said one major face.” Comments on Claim 17: Junction transistor being portions of a raised mesa-shaped part — MESA technology specified. Claim 18. “An integrated circuit according to Claim 3 wherein said active circuit component is a junction transistor with said two thin layers

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being the base and the emitter regions of said junction transistor,the emitter region being substantially smaller than the base region on said one major face, a base contact being positioned on said base region spaced from the emitter region.” Comments on Claim 18: Nothing new. Claim 19. “An integrated circuit according to Claim 18 wherein said discrete region of the passive circuit component includes a thin surfaceadjacent layer of semiconductor material of conductivity-type opposite that of subjacent semiconductor material, an ohmic contact is provided on said surface-adjacent layer, and a conductive lead connects such ohmic contact to said base contact.” Comments on Claim 19: What is the conductive lead which connects such ohmic contact to base contact, and how is it fabricated? NOT supported by the figures or the text. Claim 20. “A semiconductor device according to Claim 10 wherein said passive circuit component provided in the body by said discrete portion of the semiconductor material includes a thin surface-adjacent portion of the semiconductor material at said one major face of the body, such thin portion being of conductivity differing from subjacent semiconductor material .” Comments on Claim 20: Nothing new. Claim 21. “A semiconductor device according to Claim 20 wherein separate electrical contacts are provide on at least two of said thin regions of the active circuit component on said one major face, wherein a contact is provided on said thin surface-adjacent portion on said one major face, and wherein conductive means interconnects said contact on said surface-adjacent portion with one of said contacts on said thin regions of the active circuit component .” Comments on Claim 21: NOT supported by the figures or the text. Claim 22. “In an integrated circuit according to Claim 13 said elongated semiconductor means being a single elongated region of the

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semiconductor material with said first and second conductive means being separately connected to opposite ends of such elongated region and with said means for applying operating bias being connected to a centrally located portion of such elongated region.” Comments on Claim 22: Nothing new. Claim 23. “In an integrated circuit according to Claim 13 said means for applying inputs to said pair of transistors includes separate coupling means connecting the first conductive means to the contact on the base region of said one of the transistors and connecting the second conductive means to the contact on the base region of said other one of the transistors.” Comments on Claim 23: What are the 1st and 2nd conductive means which connect the bases of the two transistors, and how are they fabricated? NOT supported by the figures or the text. Claim 24. “An integrated circuit according to Claim 16 wherein said discrete region of the passive circuit component includes a thin surfaceadjacent region of conductivity type opposite to that of subjacent semiconductor material .” Comments on Claim 24: Nothing new. Claim 25. “An integrated circuit according to Claim 24 wherein said passive circuit component is a P–N junction capacitor .” Comments on Claim 25: Specifying P–N junction capacitor.

16. Kilby’s Patent No. 3,138,744 “Miniaturize Self-Contained Circuit Modules and Method of Fabrication”, filed May 6, 1959; Serial No. 811,486; issued June 23, 1964 Kilby’s patent no. 3,138,744 is the only patent in which he had stated the monolithic concept, although it was only partly correct. As discussed

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earlier, it is Kilby’s key patent which will be analyzed in detail in this section. As we remember that this patent no. 3,138,744 of Kilby’s was filed on May 6, 1959, before Bob Noyce had filed for his patent no. 2,981,877 on July 30, 1959. However, Kilby’s patent was issued on June 23, 1964, which was after Noyce was issued on April 25, 1961. Kilby had to revise his original patent application, and he also refers to Lehovec’s patent no. 3,029,366 (filed on April 22, 1959; issued on April 10, 1962). 16.1. Summary of the Invention Basic concept of Kilby’s invention: Column 1; Lines 55–62: “. . . To that end, I have proposed in my pending application for patent, Serial No. 791,602, filed February 6, 1959, that various circuit elements including diodes, transistors, and resistors all be formed within a single block of semiconductor material, thereby eliminating the necessity for separate fabrication of the semiconductor devices and the interconnections as mentioned above. . . .”; Column 2; Lines 1–5: “. . . Consequently, it is an object of this present invention to provide in a package of miniature size, electronic circuits which include not only active elements such as transistors or diodes but, in addition, passive elements of great stability.” Kilby’s basic concept stated above is partially consistent with monolithic-ICs and that too in a limited way. He does not specify how these circuit elements will be “formed within a single block of semiconductor material ” (viz., what technology shall be used? — he did not ever specify planar technology which is mandatory; he had used mesa technology which is the wrong technology and specified it in the claims of his patent.), and how they will be isolated and interconnected. The materials and technologies given in his patent and his original application are not consistent with monolithic-ICs. The materials and technologies specified by KiIlby will not produce monolithic-ICs. Planar technology and interconnects going over and adherent to the insulating films are essential to fabricate monolithic-ICs.

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It is easy to state an important goal correctly. But to achieve that goal, innovative materials and techniques are of paramount importance which must be invented and proven that they work. It is like someone making the following statements, and be given credit and Nobel award for inventing the respective inventions below. A few examples in various fields are given in a condensed manner to which most of the readers can relate. 1. Cancer can be cured by stopping the uncontrolled mitosis in the affected regions. [The exact proven methods and techniques are not given how to do this.] 2. Horrific diseases such as ALS (amyotrophic lateral sclerosis — a treatment resistant paralyzing nervous system disorder), Alzheimer’s, Parkinson’s, autoimmune diseases, mental sickness (e.g., bipolar disorder, clinical depression, etc.), can be cured by stem cells. [The open question of why the cells died or mutated in the first place, and exactly how the stem cell therapies are to be customized and used for curing are not specified.] 3. We can go to the moon and return by using rockets and space vehicles. [The exact proven methods and designs are not given.] 4. ICs can also be made from semiconductors other than Si by using appropriate surface passivation, planar, and interconnect technologies. [The exact proven details are not given.] 5. Vision can be improved, and blindness can be overcome, by implanting an array of nano-electro-optical detectors in the eye whose electrical outputs communicate with the visual cortex in the brain, and display the images similar to those produced by the natural rods and cones cells in the retina of human eyes. [The details of the devices, proven methods and techniques are not given how to do this.] 6. The energy crisis can be solved by using alternate energy sources instead of gasoline. [The exact proven details of the choice of alternate energy source(s) and their methods and techniques are not given.]

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Similar examples can be given and the respective inventions claimed in many different areas. Again as above, the statement of a goal alone is necessary but not sufficient. Thus Kilby’s statement alone of his concepts, and that too partially, of monolithic-ICs is not enough to credit him with their invention. Most of the materials and technologies written by him in his patent #3,138,744 and original application #03/791,602, are not suitable for the fabrication of monolithic-ICs. Planar technology and interconnects going over and adherent to the insulating films are essential to fabricate monolithic-ICs. 16.2. Key Figures Key figures from Kilby’s patent no. 3,138,744 are Figs. 3 & 4. They show clearly mesa structures of the transistor. 16.3. Key Claims Comments on the claims of the patent which are important for Kilby’s invention are as follows. Claim 1 (First claim) of 3,138,744: Column 5; Lines 29–35: “The method of making an electronic device comprising the steps of forming a transistor in a limited-area portion of one face of a wafer of semiconductor material, applying an insulating layer upon one face of said wafer of semiconductor material and forming upon said layer adjacent said transistor a passive electrical circuit component.” Comments on Claim 1: The semiconductor material is not specified as to what it is. The insulating layer is applied, not grown. Kilby specifies evaporation of silicon-mono-oxide in the text of patent. The SiO2 film used in monolithic-ICs is grown, not applied by evaporation. Kilby also specifies that the passive device is formed upon said layer, not in the semiconductor material. Resistors and capacitors are also fabricated within Si in monolithic ICs. Claim 22 (Last claim) of 3,138,744: Column 10; Lines 4–21: “An integrated circuit device comprising a wafer of semiconductor material, a semiconductor circuit element adjacent one face of the wafer and including

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a plurality of surface-adjacent regions of the wafer of opposite conductivity types with P–N junctions between said regions extending to said one face, an insulating coating on said one face of the wafer extending across at least portions of said junctions, a plurality of passive circuit components formed on said one face of the wafer overlying said insulating coating at positions spaced from said regions, said passive circuit components comprising thin deposited layers of material adherent to the insulating coating, and means electrically connecting at least one of said passive circuit components to at least one of said regions comprising thin elongated conductive film on said one face of the wafer overlying and adherent to said insulating coating and extending over said junctions but being insulated therefrom.” Comments on Claim 22: 22.1. “. . . a semiconductor circuit element . . . ”: What type of circuit element is it? Transistor, diode, resistor, capacitor or inductor (not used in ICs)? Is it only of one kind, or different types, with “surface-adjacent regions of the wafer of opposite conductivity types with P–N junctions between said regions extending to said one face”? 22.2. Not supported by figures and text. 16.4. Reduction to Practice This has already been discussed above in section 7. Further quotes and comments are: Column 3; Lines 23–25 & 28–34: “Initially, a block of semiconductor material is procured and doped either in its entirety or over an area in which an active element is to be formed. . . . Thus impurities may be diffused in successive layers into the surface of the semiconductor block to form the emitter, base and collector regions. (Para) After doping has been accomplished, upper layer areas other than those required for the active circuit elements may be eliminated by etching, thereby leaving only those desired.” Kilby is specifying formation of mesa transistor. The mesa structure is also visible clearly in Figs. 3 and 4 of Kilby’s patent no. 3,138,744, and in Figs. 4 and 5 of his application no. 03/791,602.

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16.5. Choice of Semiconductor This has been already discussed above in section 8. Further quotes and comments are: Column 1; Lines 38–44: “. . . Problems have arisen when it has been attempted to employ such techniques in the forming of semiconductor devices, such as diodes and transistors, for conventional semiconductor material such as germanium or silicon, do not lend themselves to evaporation or other methods heretofore employed for the application of passive elements . . . ” Throughout the patent, Kilby writes semiconductor material, and does not specify the semiconductor to be either Ge or Si. 16.6. Fabrication Method of Devices Already discussed in section 9. 16.7. Insulating Layers Already discussed in section 10. Further quotes and comments are: Column 2; Lines 70, 71; Column 3; Lines 1–4: “Immediately over film 8 is located a dielectric film 7 which may be of any suitable material, such as silicon monoxide; and immediately above film 7 is positioned relatively low resistance film 6, which as heretofore mentioned, comprises the upper conducting film of the capacitor C.” Kilby does not write how silicon monoxide is deposited or grown. It cannot be grown easily, because the grown film is normally silicon dioxide. So, it is implied that it was deposited. Also, it is used by Kilby as the dielectric for the capacitor, not for planar use for covering the junctions of the transistor. 16.8. Isolation of Devices Already discussed in Section 11.

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16.9. Interconnects Already discussed in Section 12. Further quotes and comments are: Column 4; Lines 12–21 and 38–44: “. . . Thus, for example, if an NPN-type transistor is being formed, a mask might be used to cover all of the surface except the emitter and collector recesses, and antimony-doped gold or other suitable material could be evaporated or otherwise deposited through the mask into the recesses. Thereafter, the entire surface of the member 1 could be masked except for the base recess, into which a suitable ohmic-contact-making material such as aluminum might be evaporated or otherwise deposited . . . Next, any suitable highly conductive material, such as copper or gold, is applied by vacuum deposition technique . . . A relatively thick film is applied to the indicated areas in order that the resistance thereof maybe made low.” Kilby proposes to use Sb-doped Au for ohmic contacts to emitter and collector, and Al for ohmic contact to base, of the n–p–n transistor; also he uses thick films of either Cu or Au by themselves for interconnect. He also proposed evaporation or “otherwise deposited” through a mask. As it is well known, these are not done in the monolithic ICs. 16.10. Impact of 35 USC 112 Already discussed in Sections 2.10 and 2.11. 16.11. Overall Comments The bottom line is that Kilby’s integrated device consists of a mesa transistor, whose emitter, base and collector regions are connected to passive components such as resistors and capacitors by interconnects of Cu or Au over an insulating layer such as silicon monoxide. Cu and Au interconnects by themselves do not adhere to insulating layers, and silicon monoxide and mesa transistors are not used in the ICs. So at best, Kilby’s invention is an integrated circuit having a mesa transistor, and the interconnects will be non-adherent and non-functional. In the famous slide showing Kilby’s first integrated circuit, transistor and passive components in two separate pieces of Ge are glued to a glass slide, and the different

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regions of the transistor, capacitor and resistor are shown interconnected by dangling wire bonded to them. Thus Kilby’s integrated circuit was a hybrid-integrated circuit, not the monolithic-IC.

17. Summary of Comparisons between Kilby’s two IC Patent Nos. 3,138,743 and 3,138,744, and a few additional comments The summary of comparisons between Kilby’s two IC patent nos. 3,138,743 and 3,138,744, and a few additional comments are given below in Table 7.2. Table 7.2. Summary of comparisons between Kilby’s two IC patent nos. 3,138,743 and 3,138,744, and a few additional comments. Key items

Patent no. 3,138,744


1. Serial nos. 2. Filing dates.

811,486 May 6, 1959 According to Lehovec,26.2 it was re-filed as Serial no. 218,206 on Aug. 16, 1962. But this is not indicated on 3,138,744.

791,602 Originally claimed by Kilby to be Feb. 6, 1959. USPTO wrote to Saxena29 on Sep. 26, 2005, that 791,602 which “met the requirements to be granted a filing date under 35 USC 111”, the filing date was May 6, 1959. USPTO also wrote30 on Nov. 2, 2005 that it does not have an official filing date. The above contradictory documents from USPTO cannot be explained. But the latter document was used by the Customer Service Department to convey that no further action was taken, and no patent was issued for the serial no. 791,602 by USPTO. Kilby’s patent no. 3,138,743 was issued under very unusual and questionable circumstances. (See item no. 3 below.) Its filing date was kept as Feb. 6, 1959, and not given as May 6, 1959, specified above. (Continued)

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Chapter 7. Kilby’s Invention of IC: Key Patents, Claims and Analyses Section 17. Summary of Comparisons

Table 7.2.

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(Continued)

Key items


3. Issue dates

June 23, 1964 June 23, 1964 Note that these two patents differ in number by only 1 (3,138,744 and 3,138,743), and both were issued on the same date (June 23, 1964), which was about 3 years and 2 months after Noyce was awarded his patent no. 2,981,877 on April 25, 1961. Note also that it took USPTO more than 5 years to review these two patents since they were filed, and to issue them. Noyce’s patent had already specified the monolithic-IC concept in 1961. During this 5 year period, Kilby had also filed interference proceedings against Noyce and Lehovec and lost. One key issue was to gain priority over Lehovec’s filing (April 22, 1959). But Kilby’s attempts to keep the filing date of OA 791,602 to be Feb. 6, 1959, was unsuccessful, as decided by the US Board of Patent Interference case no. 93.612 after a final hearing on March 16, 1966.26 Why did USPTO still keep the filing date of 3,138,743 to be Feb. 6, 1959 on this patent is a mystery? Refers to original Texts of original application (OA) application (OA) no. 791,602 and patent no. no. 791,602; materials 3,138,743 are exactly the same. and technologies The materials and technologies specified are never specified are never used in ICs, used in ICs; and prescribed mesa technology. prescribed mesa technology. States procedures only No statement for monolithic concept partly correct in a given in the text. small way; striking similarity with Dummer’s description given in 1952; Kilby was aware of this. Clearly show mesa Clearly show mesa devices with wire devices with bonded bonded interconnects; interconnects; hybrid-ICs. All figures are hybrid-ICs. exactly the same in OA no. 791,602 and 3,138,743. Total no. of claims = 22. Total no. of claims in OA They are not for 791,602 = 22. Total no. of claims monolithic ICs. in 3,138,743 = 25. The claims of 3,138,743 were rewritten entirely. When was this done cannot be ascertained at this time, but it appears that it was done after

4. Texts of the patents; monolithic concept?

5. Figures

6. Claims


(Continued)

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7. Patent referred to in Kilby’s 1998 paper (2 years before the Nobel award in 2000). 8. Monolithic concept as controversial. 9. Interference suits against Lehovec and Noyce. 10. Ever used to manufacture ICs?

(Continued)


No. This was strange because the monolithic concept was at least stated partly in this patent.

Patent no. 3,138,743 Noyce’s patent on monolithic ICs was issued on April 25, 1961. These two sets of claims are entirely different from each other, even though their texts and figures are exactly the same. While these two sets of claims are not double-patenting, they do not support the specifications (texts and drawings). Therefore, issuing 3,138,743 was in violation of patent law 35 USC 112. The applicability of these claims to monolithic-ICs is questionable also. How the entire re-written claims of 3,138,743 and original filing date of Feb. 6, 1959, of OA 791,602, while their texts and figures could not be changed, were pushed through USPTO by TI is a mystery. This mystery is enhanced even more when we realize that both 3,138,743 and 3,138,744 differ in number by only 1, and they were issued on the same date June 23, 1964. Yes. This was strange because in this patent the monolithic concept was not stated even partly.

Yes, Kilby19 continued to regard the monolithic concept as controversial until as late as in 1998, according to published records. Kilby lost against Lehovec for p–n junction isolation, and lost partially against Noyce for monolithic-ICs using Al interconnects and Si planar technology. (See also item no. 3 above.) No.

No.

(Continued)

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Chapter 7. Kilby’s Invention of IC: Key Patents, Claims and Analyses Section 18. Detailed analyses of all the Claims of 3,138,744

Table 7.2.

169

(Continued)

Key items



11. Did they ever affect the millions of dollars in royalties between TI, Fairchild, etc.? 12. Did Kilby receive more patents beyond these two which were related to ICs?

Yes.

Yes.

13. Did Kilby make contributions to the technologies being used today in ULSICs?

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Yes, but only 2 or 3 as best as one can tell from the published patents Kilby received which were related to ICs. But none of them were relevant to monolithic ICs as we know them from day one. This is also clear from the fact (see item no. 7 of this table) that Kilby refers only to one patent (3,138,743) in his last major technical paper in 1998 before receiving the Nobel Prize in 2000. Had he contributed to the IC technologies after the above two and subsequent 2 or 3 patents, it is obvious that he would have referred to them in 1998. He did receive many more patents in other important areas, but not of any direct significance to ICs. Based on item no. 12 above and on published literature the answer is “No”.

18. Detailed analyses of all the Claims of 3,138,744 All the claims of Jack Kilby’s patent no. 3,138,744 (filed May 6, 1959; issued June 23, 1964) and their detailed analyses are given below. Claim 1. “The method of making an electronic device comprising the steps of forming a transistor in a limited-area portion of one face of a wafer of semiconductor material, applying an insulating layer upon said one face of said wafer of semiconductor material and forming upon said layer adjacent said transistor a passive electrical circuit component.” Comments on Claim 1: The semiconductor material is not specified as to what it is. The insulating layer is applied, not grown. Kilby

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specifies evaporation of silicon-mono-oxide in the text of patent. SiO2 used in monolithic-ICs is grown, not applied by evaporation. Kilby also specifies that the passive device is formed upon said layer, not in the semiconductor material. Resistors and capacitors are also fabricated within Si in monolithic ICs. Claim 2. “The method of making an electronic device comprising the steps of forming a transistor in a limited-area portion of one face of a wafer of semiconductor material, applying am insulating layer upon said one face of said wafer of semiconductor material, and forming upon said layer adjacent said transistor a passive electrical element selected from the class consisting of resistors and capacitors.” Comments on Claim 2: This is essentially the same claim as Claim 1, but this claim specifies the passive device to be resistor and capacitor. Claim 3. “The method of making an electronic device comprising the steps of forming PN junction in a wafer of semiconductor material closely adjacent one face thereof with the area occupied by the junction being much less than the total area of said one face, applying an insulating layer upon said one face of the wafer of semiconductor material, and forming upon said layer at a position spaced on said one face from said PN junction a passive electrical circuit component.” Comments on Claim 3: This is essentially the same claim as Claim 1, and just a re-hash with words; nothing new. Claim 4. “The method of making an electronic device comprising the steps of forming PN junction in a wafer of semiconductor material closely adjacent one face thereof with the area occupied by the junction being much less than the total area of said one face, applying an insulating layer upon said one face of the wafer of semiconductor material, and forming upon said one face over said insulating layer spaced from said PN junction a passive electrical element selected from the class consisting of resistors and capacitors.” Comments on Claim 4: This is essentially the same claim as Claims 1and 3, and just a re-hash with words; nothing new.

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Claim 5. “The method of making an electronic device comprising the steps of forming a transistor within one face of a wafer of semiconductor material, removing a portion of said one face from said wafer of semiconductor material to limit the area occupied by said transistor, applying an insulating layer upon said one face of said wafer of semiconductor material and forming upon said insulating layer adjacent transistor a passive electrical circuit component.” Comments on Claim 5: This claim specifies the formation of mesa transistor, on top of which an insulating layer is “applied”, not grown. The passive device is formed upon the insulating layer adjacent to transistor. Claim 6. “The method of making an electronic device comprising the steps of forming a PN junction within one face of a wafer of semiconductor material, removing a portion of said PN junction from said one face of said wafer of semiconductor material, applying an insulating layer upon said one face of said wafer of semiconductor material, and forming upon said insulating layer adjacent PN junction a passive electrical circuit component.” Comments on Claim 6: This claim is exactly the same as Claim 5 specifying mesa transistor except that it substitutes PN junction for transistor. Claim 7. “The method of making an electronic device comprising the steps of forming a PN junction within one face of a wafer of semiconductor material, removing a portion of said PN junction from said one face of said wafer of semiconductor material, applying an insulating layer upon said one face of said wafer of semiconductor material, and forming upon said insulating layer adjacent PN junction a passive electrical element selected from the class consisting of resistors, capacitors, and inductors.” Comments on Claim 7: This claim is exactly the same as Claim 6 specifying mesa transistor, except that it adds element selected from the class consisting of resistors, capacitors, and inductors.

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Claim 8. “The method of making an electronic device comprising the steps of forming a PN junction in a block of semiconductor material, forming in said block of semiconductor material, forming in said block of semiconductor material an area of high resistivity immediately adjacent and in ohmic contact with one of the P and N regions in said PN junction, applying an insulating layer upon said block of semiconductor material, forming apertures through said insulating layer at the other one of the P and N regions of said PN junction and at said area of high resistivity, making electrical contacts with said other of the P and N regions of said PN junction and said area of high resistivity through said apertures, and forming upon said insulating layer adjacent PN junction a passive electrical circuit component.” Comments on Claim 8: This claim is trying to specify how the electrical contact is made to the PN junction. I shall break it up into 4 parts as follows: 8.1. “an area of high resistivity immediately adjacent and in ohmic contact with one of the P and N regions in said PN junction”: It does not give the method as how to form the “area of high resistivity . . . adjacent . . . in ohmic contact . . . .”. The text of the patent also does not specify this, and what is the purpose of the area of high resistivity? 8.2. “applying an insulating layer upon said block of semiconductor material ”: Applying an insulating layer means depositing or evaporating, NOT grown. 8.3. “forming apertures through said insulating layer at the other one of the P and N regions of said PN junction and at said area of high resistivity ”: Holes through the insulating layer to make electrical contacts. 8.4. “making electrical contacts with said other of the P and N regions of said PN junction and said area of high resistivity through said apertures”: Does not specify the materials needed for such electrical contacts. The text gives Sb-doped-Au for N regions and Al for P regions; the interconnects were specified in the text to be Cu and Au by themselves.

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Claim 9. “The method defined by Claim 8 in which said passive electrical element formed upon said insulating layer adjacent said PN junction comprises a member selected from the class consisting of resistors, capacitors, and inductors.” Comments on Claim 9: This claim is just re-hashing to specify the passive components, which were specified earlier anyway in Claim 7. Claim 10. “The method of making an electronic device comprising the steps of forming a PN junction in a block of semiconductor material, forming in said block of semiconductor material a capacitor adjacent and in ohmic contact with one of the P and N regions in said PN junction, applying an insulating layer upon said block of semiconductor material, forming apertures through said insulating layer at the other one of the P and N regions of said PN junction and at said capacitor, making electrical contacts through said apertures with said other of the P and N regions of said PN junction and said capacitor, and forming upon said insulating layer adjacent PN junction a passive electrical circuit component.” Comments on Claim 10: Nothing new. Claim 11. “The method of making an electronic device comprising the steps of forming a PN junction in a block of semiconductor material, forming in said block of semiconductor material an area of high resistivity and an area of distributed capacitance, both said area of high resistivity and said area of distributed capacitance lying adjacent to and in ohmic contact with one of the P and N regions in said PN junction, applying an insulating layer upon said block of semiconductor material, forming apertures through said insulating layer at the other one of the P and N regions of said PN junction, at said area of high resistivity and at said area of distributed capacitance, making electrical contacts through said apertures with said other of the P and N regions of said PN junction, with said area of high resistivity and with said area of distributed capacitance and forming upon said insulating layer adjacent PN junction a passive electrical circuit component.” Comments on Claim 11: Nothing new.

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Claim 12. “The method of making an electronic device comprising the steps of forming a PN junction in a block of semiconductor material, forming in said block of semiconductor material an area of high resistivity and an area of distributed capacitance, both said area of high resistivity and said area of distributed capacitance being adjacent to and in ohmic contact with one of the P and N regions in said PN junction, applying an insulating layer upon said block of semiconductor material, forming apertures through said insulating layer at the other one of the P and N regions of said PN junction, at said area of high resistivity, and at said area of distributed capacitance, making electrical contacts through said apertures with said other of the P and N regions of said PN junction, said area of high resistivity, and said area of distributed capacitance, and forming upon said insulating layer adjacent said PN junction a passive electrical element selected from the class consisting of resistors, capacitors, and inductors.” Comments on Claim 12: How are the electrical contacts made through said apertures? Not specified. Claim 13. “A semiconductor device comprising a body of singlecrystal semiconductor material, a P–N junction being defined in said body adjacent one face thereof by contiguous regions of opposite conductivity types extending to said one face, an insulating layer on said one face overlying said P–N junction and being contiguous thereto, conductive means including a thin elongated strip of resistive material overlying said insulating layer and being contiguous thereto, said conductive means extending over said P–N junction, one end of said conductive means being electrically connected to one of said regions of said body .” Comments on Claim 13: What are the conductive means, how are they deposited and etched to define conductive patterns? Claim 14. “A semiconductor device comprising a wafer of singlecrystal semiconductor material, a P–N junction being defined in said wafer adjacent one face thereof by contiguous regions of opposite conductivity types extending to said one face, an insulating layer on said one face covering at least a portion of said wafer including said P–N junction and being contiguous thereto, conductive means including a thin

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elongated strip of resistive material overlying said insulating layer and being contiguous thereto, one end of said conductive means being electrically connected to one of said regions of said wafer, means for applying a bias voltage between the other end of said conductive means and the other of said regions of said wafer, and means including a thin conductive strip adherent to said insulating layer connected to said conductive means closely adjacent said one region deriving an output from said device.” Comments on Claim 14: What are the conductive means, how are they deposited and etched to define conductive patterns? Re-hash of Claim 13; minor addition of “applying a bias voltage”. Claim 15. “A semiconductor device comprising a wafer of monocrystalline semiconductor material, at least a portion of said wafer adjacent one surface thereof being of one conductivity type, a first region of said wafer of opposite conductivity type contiguous to said portion, a second region of said wafer of said one conductivity type contiguous to said first region and spaced from said portion, an insulating layer covering at least said one surface of said wafer and being contiguous to at least parts of said portion and said first and second regions, a plurality of conductive means contacting each of said portion and first and second regions separately, and a thin elongated layer of resistive material overlying said insulating layer and being contiguous thereto, one end of said elongated layer being connected to one of said conductive means by a conductive strip which overlies said insulating layer.” Comments on Claim 15: Nothing new. Claim 16. “An electronic device comprising a wafer of monocrystalline semiconductor material, at least a portion adjacent one surface of said wafer being of one conductivity type, a first region of said wafer of opposite conductivity type contiguous to said portion, a second region of said wafer of said one conductivity type contiguous to said first region and spaced from said portion, an insulating layer covering at least said one surface of said wafer and being contiguous to at least parts of said portion and said first and second regions, a plurality of conductive means contacting each of said portion and first and second regions separately, and a thin elongated layer of resistive material overlying said insulating layer and contiguous

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thereto, one end of said elongated layer being electrically connected to one of said conductive means by a conductive strip overlying said insulating layer and being contiguous thereto, one end of said conductive strip contacting said one of said conductive means, the conductive strip extending over said portion and one of said regions.” Comments on Claim 16: Nothing new. Claim 17. “A semiconductor device comprising a body of semiconductor material, a first region of one conductivity type defined in said body, a second region of opposite conductivity type defined in said body contiguous to said first region and adjacent one surface thereof, a third region of said one conductivity type defined in said body contiguous to said second region and spaced from said first region, an insulating layer covering at least said one surface of said body and being contiguous to said first, second, and third regions, first conductive means contacting first region adjacent said one surface, second conductive means contacting said second region, third conductive means contacting said third region, each of said conductive means being positioned in areas free of said insulating layer, an elongated layer of resistive material overlaying said insulating and contiguous thereto, one end of said elongated layer being electrically connected to said first conductive means, means for applying a bias voltage between said third conductive means and the other end of said elongated layer and for applying a bias voltage to said second conductive means, and output means connected to said first conductive means.” Comments on Claim 17: Nothing new. Claim 18. “A semiconductor device comprising a wafer of singlecrystal semiconductor material, a first region of one conductivity type defined by the major portion of said wafer, a second region of opposite conductivity type defined in said wafer contiguous to said first region and adjacent one surface thereof, a third region of said one conductivity type defined in said wafer contiguous to and overlaying said second region and spaced from said first region, an insulating layer covering at least said one surface of said wafer and being contiguous to said first, second and third regions, first conductive means contacting said first region adjacent said one surface, second conductive means contacting said second region

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adjacent said one surface, third conductive means contacting said third region adjacent said one surface, each of said conductive means being positioned in areas free of said insulating layer, an elongated layer of resistive material overlaying said insulating layer and being contiguous thereto, one end of said elongated layer being electrically connected to said first conductive means, means for applying a bias voltage between said third conductive means and the other end of said elongated layer, means for applying an electrical potential to said second conductive means, and output means connected to said first conductive means and comprising a thin conductive strip adherent to said insulating layer .” Comments on Claim 18: Nothing new. Not supported by figures and text. Also overruled by the Board of Patent Interference. Claim 19. “An electronic device comprising a body of single-crystal semiconductor material, a first region of one conductivity type defined in said body adjacent one surface thereof. A second region of opposite conductivity type defined in said body adjacent said one surface thereof contiguous to said first region, a third region of said one conductivity type defined in said body adjacent said one surface thereof contiguous to said second region and spaced from said first region, an insulating layer overlaying said one surface of said body and being contiguous thereto, first conductive means including a first elongated resistive strip positioned on said body overlaying said insulating layer and contiguous thereto, one end of said first conductive means being electrically connected to said first region, second conductive means including a second elongated conductive resistive strip positioned on said body overlaying said insulating layer and contiguous thereto, one end of said second conductive means being electrically connected to said third region, and capacitive means positioned on said body overlaying said insulating layer and electrically connected to said second region.” Comments on Claim 19: Nothing new. Not supported by figures and text. Claim 20. “A semiconductor device adapted for amplifying signals and comprising a wafer of single-crystal semiconductor material, a first region of one conductivity type defined in said wafer adjacent one surface thereof, a second region of opposite conductivity type defined in said wafer contiguous to and overlaying said first region, a third region of said

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one conductivity type defined in said wafer contiguous to and overlaying said second region and spaced from said first region, an insulating layer overlying said one surface of said wafer and being contiguous thereto, first conductive means adjacent said surface and contacting said first region, second conductive means adjacent said surface and contacting said second region, third conductive means adjacent said surface and contacting said third region, an elongated resistive strip positioned on said wafer overlying said insulating layer and contiguous thereto, one end of said resistive strip being electrically connected to one of said first and third conductive means, capacitive means positioned on said wafer overlying said insulating layer and comprising a pair of conductive layers separated by a dielectric layer, the lower one of said conductive layers being connected to said to second conductive means, means for applying signals to the upper one of said conductive layers, means for coupling out put signals from said one of said first and third conductive means, and means for applying a bias voltage between the other end of said resistive strip and the other of said first and third conductive means.” Comments on Claim 20: Nothing new. Not supported by figures and text. Claim 21. “A semiconductor device comprising a wafer of semiconductor material, a region defined in the wafer adjacent one face thereof composed of semiconductor material of conductivity-type opposite to that immediately underlying such region, an interface between said region and contiguous semiconductor material providing a P–N junction which extends wholly to said one face and there defines an enclosed surface area which is much smaller than the total area of said one face, said region and junction providing at least a part of a semiconductor circuit element, an insulating coating on said one face of the wafer extending across a portion of said junction, an elongated strip of resistive material overlying said insulating coating and being contiguous thereto, and a thin strip of conductive material on said one face overlying said insulating coating, one end of the thin strip of conductive material contacting the resistive strip and the other end extending across said portion of said junction and being electrically connected to said region.” Comments on Claim 21: Nothing new. Not supported by figures and text.

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Claim 22. “An integrated circuit device comprising a wafer of semiconductor material, a semiconductor circuit element adjacent one face of the wafer and including a plurality of surface-adjacent regions of the wafer of opposite conductivity types with P–N junctions between said regions extending to said one face, an insulating coating on said one face of the wafer extending across at least portions of said junctions, a plurality of passive circuit components formed on said one face of the wafer overlying said insulating coating at positions spaced from said regions, said passive circuit components comprising thin deposited layers of material adherent to the insulating coating, and means electrically connecting at least one of said passive circuit components to at least one of said regions comprising thin elongated conductive film on said one face of the wafer overlying and adherent to said insulating coating and extending over said junctions but being insulated therefrom.” Comments on Claim 22: 22.1. “. . . a semiconductor circuit element. . . ”: What type of circuit element is it? Transistor, diode, resistor, capacitor or inductor (not used in ICs)? Is it only of one kind, or different types, with “surface-adjacent regions of the wafer of opposite conductivity types with P–N junctions between said regions extending to said one face”? 22.2. Not supported by figures and text.

19. Kilby’s Patent No. 3,261,081, “Method of Making Miniaturized Electronic Circuits”, (“Original Application Feb. 6, 1959, Ser. No. 791,602, now Patent No. 3,138,743, dated June 23, 1964. Divided and this Application Mar. 16, 1964, Ser. No. 352,380; 21 Claims.”; issued July 19, 1966) As mentioned in Section 15.1 above, the texts and figures in all three documents (OA and two patents) of Kilby, viz., 791,602; 3,138,743; 3,261,081, are the same, but their claims are very different. Therefore only the analyses of all the claims of Kilby’s patent no. 3,261,081 are given in this section.

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19.1 Detailed Analyses of all the Claims Claim 1. “In a method of manufacturing an integrated circuit of the type having a plurality of separate transistors and a plurality of separate passive circuit components including elongated semiconductor resistors in a semiconductor body, the steps of diffusing conductivitydetermining impurity material into one face of the body to convert the conductivity-type of semiconductor material adjacent said one face to form what in the completed integrated circuit functions as the base regions of said plurality of transistors and to form at the same time what in the completed integrated circuit functions as at least parts of said passive circuit components, applying contacts to a face of the body at opposite ends of said elongated semiconductor resistors, and applying interconnections to connect selected ones of the passive circuit components including said semiconductor resistors to selected ones of the transistors, the method including the steps of treating the body to electrically isolate said base regions from one another and form said parts of the passive circuit components.” Comments on Claim 1: Describes the formation of resistors during the base diffusions of the transistors; applying interconnections (how and with which materials not specified) to connect selected parts of resistors and transistors; treating (but not given how) to isolate base regions as well as form parts of passive circuit components? Claim 2. “The method of fabricating an integrated circuit comprising the steps of: diffusing conductivity-determining impurities into a first area of a semiconductor body adjacent a major face of said body to form a region of an active element, while simultaneously therewith diffusing conductivitydetermining impurities into another area of the body adjacent to said one major face but spaced on said one face from said first area to form a region which provides at least a part of a passive circuit element, and applying electrical connecting means on said one face to provide in the completed device an integrated electronic circuit which includes said active and passive circuit elements, said method including the step of processing the body to provide substantial electrical impedance between said areas whereby substantial electrical isolation is obtained .” Comments on Claim 2: Rehash of words in Claim 1.

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Claim 3. “A method of fabricating an integrated circuit comprising introducing into the surface of a major face of a body of semiconductor material conductivity-determining impurities at spaced apart locations on said one face to form simultaneously like regions of a plurality of junction transistors and like regions of a plurality of passive electronic elements, and securing to said major face a plurality of electrically conductive means external to the semiconductor material to interconnect selected ones of the transistors and selected ones of the passive circuit elements, said method including the steps of processing the body to provide substantial electrical isolation between spaced apart locations.” Comments on Claim 3: Rehash of words in Claim 1, and to include plurality of transistors, passive elements and interconnections. Claim 4. “A method of fabricating an integrated circuit as in claim 3 wherein said processing include shaping by physical removal of at least some of the semiconductor material of the body .” Comments on Claim 4: As it states, this is Claim 3 with the addition of “shaping by physical removal of at least some of the semiconductor material of the body.” This is used in mesa technology to shape the junctions and diffused regions. Claim 5. “A method according to Claim 4 wherein unwanted semiconductor material is completely removed through the body from one major face to the opposite major face.” Comments on Claim 5: As it states, this is Claim 4 with the addition of “wherein unwanted semiconductor material is completely removed through the body from one major face to the opposite major face.” The method suggested by this claim, without giving the process to remove completely, was hardly ever used successfully in manufacturing. However, both the method and the process were covered in Jay Last’s patents, 3,158,788 and 3,313,013; both filed Aug. 15, 1960, but issued on Nov. 24, 1964 and April 11, 1967 respectively. Claim 6. “In a method of manufacturing an integrated circuit device of the type having a plurality of separate active circuit components and a

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plurality of separate passive circuit components in a semiconductor body, the steps of providing a wafer of extrinsic semiconductor material, diffusing into one face of the body conductivity-determining impurity material to form surface-adjacent areas which in the completed device provide separate like regions of the active circuit components and to form at the same time areas which in the completed device provide separate like regions of the passive circuit components, and applying contacts and interconnections to said one face of the wafer to connect selected ones of said regions of the passive circuit components to selected ones of the active circuit components, said method including the step of treating said one face of the wafer to provide electrical isolation between said regions of the active circuit components and said regions of the passive circuit components.” Comments on Claim 6: It can be construed as a sort of p–n junction isolation, in which the plurality of diffused regions are used to fabricate separate active and passive circuit components of an integrated circuit; contacts and interconnects are made to complete the circuit. However, the materials and how “applying contacts and interconnections” are done, are not specified. Claim 7. “In a method according to Claim 6, said step of treating said one face of the wafer to provide electrical isolation between said regions of the active circuit components and said regions of the passive circuit components including removing semiconductor material of the wafer from one major face to the opposite major face.” Comments on Claim 7: Same as Claim 6, but includes the additional step of removing the semiconductor material as in Claim 5. Claim 8. “In a method according to Claim 6, said step of treating comprising removing selected portions of said one face of the wafer after said step of diffusing to leave raised mesas on said one face.” Comments on Claim 8: Same as Claim 6, but specifies further to leave raised mesas after removal of selected portions of the semiconductor.

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Claim 9. “In a method of manufacturing an integrated circuit of the type having a plurality of separate active circuit components and a plurality of separate passive circuit components including elongated semiconductor resistors in a semiconductor body, the steps of diffusing conductivitydetermining impurity material into one face of the body to convert the conductivity-type of semiconductor material adjacent said one face to form what in the completed integrated circuit functions as separate regions of said plurality of active circuit components and to form at the same time what in the completed integrated circuit functions as at least parts of said passive circuit components, and applying contacts to a face of the wafer at opposite ends of said elongated semiconductor resistors and to selected portions of said active circuit components at said one face and applying interconnections to connect selected ones of the passive circuit components including said semiconductor resistors to selected ones of the active circuit components, said method including the step of processing the body to provide electrical isolation between the active and passive circuit components.” Comments on Claim 9: It is essentially a rehash of Claim 1. Interconnect materials not specified. Claim 10. “In a method of fabricating a semiconductor device of the type having at least one active circuit element and at least one passive circuit element in a wafer of semiconductor material adjacent a major face thereof, the steps of forming in the wafer one region of said active circuit element, with such region being of conductivity-type opposite to subjacent semiconductor material, by introducing conductivity-type determining material into said region, forming in the wafer at a position spaced on said one face from the active circuit element an elongated surfaceadjacent region which is at least part of said passive circuit element, with the region being of conductivity-type opposite to subjacent semiconductor material, by introducing conductivity-type determining material into said elongated region, and securing electrical connecting means to said one face of the wafer, external of the wafer, to interconnect said active circuit element with said passive circuit element, said method including the step of treating the wafer to obtain isolation through the wafer between wafer portions which in the completed device for said active and passive circuit elements.”

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Comments on Claim 10: Same as Claim 9, but adds the isolation through the wafer between portions with active and passive circuit elements. Interconnect materials not specified. Claim 11. “A method of producing miniaturized electronic circuits comprising the steps of: (a) obtaining a wafer of single crystal semiconductor material of one conductivity type, (b) diffusing desired amounts of conductivity type determining impurities into said wafer to create therein an active component and a passive component, (c) shaping such wafer to obtain isolation between said components and to define areas utilized by said components in said wafer, (d) and providing electrical connections to complete the circuit.” Comments on Claim 11: Rehash of Claim 4. Claim 12. “The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of: (a) forming a wafer of semiconductor material doped with one type conductivity-producing ingredient, (b) forming in one part of said wafer a portion predominantly doped with an opposite type conductivity-producing ingredient to produce a transistor region selected from the class of emitter, base and collector, (c) concurrently forming in another part of said wafer a portion predominantly doped with said opposite type conductivity-producing ingredient to produce one region of said passive element, (d) and securing to the wafer electrically conductive means to connect said elements into an electronic circuit,

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said method including the step of treating the wafer toprovide electrical isolation between said active and passive elements.” Comments on Claim 12: Rehash of Claim 9. Claim 13. “The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of: (a) forming in a wafer of doped semiconductor material one transistor region selected from the regions of emitter, base and collector, (b) while concurrently forming in said wafer a region of said passive element, (c) and securing to the wafer electrically conductive means to connect the active and passive elements into an electric circuit, said method including the step of processing the wafer to obtain electrical separation through the wafer between wafer portions which in the completed device form said active and passive circuit elements.” Comments on Claim 13: Rehash of Claim 10. Claim 14. “The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of: (a) forming a wafer of semiconductor material doped with one type conductivity-producing ingredient, (b) diffusing into one area of said wafer an opposite type conductivityproducing ingredient to form a transistor region selected from the class of emitter, base and collector, (c) while concurrently diffusing an ingredient of said opposite type conductivity into another separate region of said wafer to form one region of said passive element,

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(d) and applying to the wafer electrically conductive means to connect the active and passive elements into an electronic circuit, said method including the step of treating the wafer to provide electrical isolation between active and passive circuit elements.” Comments on Claim 14: Rehash of Claim 9. Claim 15. “The method of fabricating a solid state circuit device having at least one active element and one passive element comprising the steps of: (a) masking a wafer of doped semiconductor material with masking means to expose preselected areas of said wafer, (b) and diffusing through said masking means a selected conductivitytype ingredient to form at least a part of said elements, (c) applying to the wafer electrically conductivity means to connect the active and passive elements into an electronic circuit, said method including the step of treating the wafer to provide electrical separation between the active and passive elements.” Comments on Claim 15: Rehash of Claim 9. Claim 16. “The method of fabricating a solid state embodiment of an entire electronic circuit having at least one transistor, one resistor, and one capacitor, comprising the steps of: (a) forming a doped wafer of semiconductor material, (b) introducing an ingredient of opposite type conductivity into at least a part of said wafer to form one region of said transistor and at least a part of one of said resistor and capacitor, (c) introducing at least one additional conductivity-producing ingredient in said wafer to form an additional portion of said transistor, (d) and applying to the wafer electrically conductive means to connect the transistor, resistor and capacitor in an electronic circuit,

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said method including the step of treating the wafer to provide electrical isolation between the transistor and the resistor and capacitor .” Comments on Claim 16: Rehash of Claim 9. Claim 17. “The method of fabricating a solid state embodiment of a complete electronic circuit comprising at least one transistor, a resistor, and a capacitor comprising the steps of: (a) forming a wafer of doped semiconductor material, (b) introducing into at least one region of said wafer an impurity ingredient of opposite conductivity type to form concurrently at least one portion of each of said transistor, resistor, and capacitor, (c) securing to the wafer electrically conductive means to connect the transistor, resistor and capacitor in an electronic circuit, said method including the step of treating the wafer to obtain electrical separation between the transistor and the resistor and capacitor .” Comments on Claim 17: Rehash of Claim 9. Claim 18. “The method of fabricating a solid state circuit device having a diode and an inductor comprising the steps of: (a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said diode, (b) introducing into another part of said doped semiconductor wafer an ingredient to form one region of said inductor, (c) and applying to the wafer electrically conductive means to connect said diode and inductor in an electronic circuit, said method including the step of treating the wafer to provide electrical isolation between the diode and the inductor .” Comments on Claim 18: Rehash of Claim 9, but inductors are not used in ICs.

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Claim 19. “The method of fabricating a solid state circuit device having a diode and an inductor comprising the steps of: (a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said diode, (b) shaping another part of said wafer to form one region of said inductor, (c) and applying to the wafer electrically conductive means to connect said diode and inductor in an electronic circuit.” Comments on Claim 19: Rehash of Claim 9, but inductors are not used in ICs. Claim 20. “The method of fabricating a solid state circuit device having a transistor and an inductor comprising the steps of: (a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said transistor, (b) introducing into another part of said doped semiconductor wafer an ingredient to form one region of said inductor, (c) and applying to the wafer electrically conductive means to connect said transistor and inductor in an electronic circuit, said method including the step of treating the wafer to provide electrical isolation between the transistor and the inductor .” Comments on Claim 20: Rehash of Claim 9, but inductors are not used in ICs. Claim 21. “The method of fabricating a solid state circuit device having a transistor and a resistor comprising the steps of: (a) introducing into one part of a doped semiconductor wafer an ingredient to form one region of said transistor,

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Chapter 7. Kilby’s Invention of IC: Key Patents, Claims and Analyses Section 20. Jack Kilby: Original Application no. 791,602

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(b) diffusing an ingredient into another part of said doped semiconductor wafer to form at least a part of said resistor, (c) and applying to the wafer electrically conductive means to the wafer to connect the transistor and the resistor in a circuit, said method including the step of processing the wafer to provide electrical separation through the wafer between said parts of said wafer.” Comments on Claim 21: Rehash of Claim 9. 20. Jack Kilby: Original Application no. 791,602, “Miniaturized Electronic Circuits and Method of Making”; claimed to have been filed on February 6, 1959, but the recorded filing date by USPTO was May 6, 1959. No patent action was taken and no patent was issued on this application per se. (See Saxena.29,30 ) A copy of the original application filed by Jack Kilby with the USPTO TO is given below.

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21. Jack Kilby: US patent no. 3,138,743, “Miniaturized Electronic Circuits”; filed February 6, 1959; serial no. 791,602; issued June 23, 1964. This filing date is controversial because this patent was based on the OA whose filing date was not recorded to be on February 6, 1959. A copy of the original patent 3,138,743 issued by the USPTO TO Jack Kilby is given below.

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22. Jack Kilby: US patent no. 3,138,744, “Miniaturized Self-contained Circuit Modules and Method of Fabrication”; filed May 6, 1959; serial no. 811,486; issued June 23, 1964. A copy of the original patent 3,138,744 issued by the USPTO TO Jack Kilby is given below.

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23. Jack Kilby: US patent no. 3,261,081, “Method of Making Miniaturized Electronic Circuits”; USPTO wrote on the front page of the patent, “Original Filed Feb. 6, 1959”, and “July 19, 1966” as the patented date. On inside above column 1, the USPTO wrote “Original application February 6, 1959, Ser. No. 791,602, now Patent No. 3,138,743, dated June 23, 1964. Divided and this application Mar. 16, 1964, Ser. No. 352,380”, for which this patent no. 3,261,081 was issued on July 19, 1966. As stated in section 1.1, the filing date of the OA was not recorded by the USPTO to be Feb. 6, 1959. A copy of the original patent 3,261,081 issued by the USPTO TO Jack Kilby is given below.

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Chapter 8

Noyce’s Invention of IC: Key Patent, Claims, and Analyses Bob Noyce’s invention of the monolithic-IC is given in his patent no. 2,981,877 (filed July 30, 1959; issued April 25, 1961), which was the only patent awarded to him for this invention. Despite the interference proceedings filed by Jack Kilby, Noyce was awarded this patent 3 years and 2 months earlier than Kilby although Kilby had filed his patents ahead of Noyce. (See Chapters 5 and 7 for details.) My technical inputs which had helped Noyce’s IC patent to be awarded in 1961 ahead of Kilby are documented in two papers.20,28 Basically, the key issue was of the interconnect metal to be adherent to the insulating film SiO2 . My inputs were that aluminum (Al) specified by Noyce was correct, whereas gold (Au) or copper (Cu) by themselves for interconnects specified by Kilby were incorrect. For further discussions, see Chapter 11. A detailed discussion of Noyce’s patent no. 2,981,877 as well as a copy of the original patent is given in this chapter. As a reminder to the reader, the methodology of analyses follows the sequence given in Chapter 5.

1. Original patent A copy of the original patent 2,981,877 issued by the USPTO to Bob Noyce is given in Section 14 at the end of this chapter. This has been done for the convenience of the readers as it may not be easily accessible to them. The subsequent sections in this chapter give the discussions and analyses of the Noyce patent in a self-contained manner so that those conversant in the 237

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state of the art may not need to read the original patent at the outset. The key points are given succinctly which can be grasped easily. Nevertheless, the original patent has been given for the sake of record, and for those who may be interested in the technical and legal details of Noyce’s IC invention. The original patent also documents how Noyce and his patent attorneys chose to describe and claim the invention.

2. Summary of the invention A brief description of the invention given in the text of the patent is summarized. 2.1. Quotations from the original patent: Column 1; Lines 15–32: “This invention relates to electrical structures incorporating semiconductor devices. Its principal objects are these: to provide improved device-and-lead structures for making electrical connections to the various semiconductor regions; to make unitary circuit structures more compact and more easily fabricated in small sizes than has heretofore been feasible; and to facilitate the inclusion of numerous semiconductor devices within a single body of material. In brief, the present invention utilizes dished junctions extending to the surface of a body of extrinsic semiconductor, an insulating surface layer consisting essentially of oxide of the same semiconductor extending across the junctions, and leads in the form of vacuum-deposited or otherwise formed metal strips extending over and adherent to the insulating oxide layer for making electrical connections to and between various regions of the semiconductor body without shorting the junctions.” 2.2. My comments on the above quotations: Bob Noyce says it all in the very first paragraph of his patent. This is essentially how the present monolithic ICs are made. Of course many advances of the various required technologies, e.g., photolithography, reactive ion etching (RIE), ion implantation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, multilevel metallizations, planarization, etc, have been made in the past four decades

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which are used in the Ultra Large Scale ICs (ULSICs). The progress of each has been absolutely mind boggling.

3. Key figures Comments on the figures of the patent which illustrate the key points of the invention are given below. Figure 1 shows the top view, and Fig.2 shows a cross section of a double diffused transistor. The ohmic contact metalizations to emitter and base regions going over the oxide layers across the respective junction edges are also shown. The junctions and their edges are passivated and protected by the oxide layer. Only the contacts are made in the center away from the edges of the junctions. Therefore the leakage currents of the junctions are low and not affected by the ambient. This is the essence of Hoerni’s invention of planar technology. The junction edges in mesa technology used by Kilby are exposed to the ambient, therefore the leakage currents of the junctions are high, unstable, and vary as the ambient conditions change. Figures 3, 4 and 5 show the circuit used by Noyce for his invention. Figure 3 shows the top view, Fig. 4 shows the cross section of the structure, and Fig. 5 shows the circuit diagram. The key things to note are that the “dished” planar junctions extend beyond the opening in the oxide whose edges are all protected by the oxide layer, and the metalizations make contacts to the junctions away from their edges, and these metalizations adherent to the oxide layer go over and across the junctions without shorting them to complete the circuit. The “discoid” shaped metalizations are just the shapes of the interconnects used at that time by Noyce for his invention. Figures 6 and 7 show an example in which the emitter and base contacts are parallel strips.

4. Key claims As it is well known, all the claims of a patent are considered as important because they cover essentially all aspects of the invention

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described in the patent. However, one or two are usually the key claims of the invention, and the rest of the claims are written to cover the various ramifications and subsets of the invention. In my opinion, Claims 1 and 9 are the key claims of Noyce’s patent. Even though all the claims have been analyzed in detail in Section 13 below, Claims 1 and 9 shall be repeated as follows: Claim 1. “A semiconductor device comprising a body of semiconductor having a surface, said body containing adjacent P-type and N-type regions with a junction therebetween extending to said surface, two closely spaced contacts a adherent to said surface upon opposite sides of and adjacent to one portion of said junction, an insulating layer consisting essentially of oxide of said semiconductor on and adherent to said surface, said layer extending across a different portion of said junction, and an electrical connection to one of said contacts comprising a conductor adherent to said layer, said conductor extending from said one contact over said layer across said different portion of the junction, thereby providing electrical connections to both of the closely spaced contacts.” Comments on Claim 1: The claim 1 and the subsequent claims are essentially legalese way of saying what Column 1, Lines 15–32 give clearly in plain English all about Noyce’s invention. Bob Noyce says it all in the very first paragraph of this patent. This is essentially how the present monolithic ICs are made. Claim 9. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing a plurality of dished, P–N junctions each having an edge extending to said surface and there surrounding and defining an enclosed region of said semiconductor, a plurality of metal contacts adherent to said surface in electrical connection with respective ones of said enclosed regions, an insulating layer consisting essentially of oxide of said semiconductor on said surface, said layer being congenitally united with said body and extending across a plurality of said junctions, and electrical interconnections between said contacts comprising metal strips adherent to said

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layer and extending over said layer across a plurality of said junctions.” Comments on Claim 9: Essentially similar to Claim 1, but gives some specifications of the oxide of semiconductor, and interconnections between several contacts, with “. . . metal strips adherent to said layer and extending over said layer across a plurality of said junctions.” 5. Reduction to practice Comments are given on the reduction to practice of the invention over and beyond what have been given in the patent. The reduction to practice was led by Noyce; it included not only Noyce’s step-and-repeat lithography camera but also the contributions made by the others. Several of them claim that had it not been for their key contributions, Noyce’s invention would not have worked. This may have been true, but Noyce’s own lithography contributions were crucial too. Keeping in mind that the various technologies used in 1959 to reduce the invention to practice were rather primitive by today’s standards, however, they are summarized as follows: The oxide layers were grown by thermal oxidation; masking was initially done by contact printing; buffered HF was used to etch patterns in oxides; patterns were defined by photolithography; thermal diffusions of boron and phosphorus through patterns etched in the oxides were accomplished to dope selectively the desired areas of silicon to give the p- and n-type junctions respectively, and the rest of the regions were masked from diffusions by the oxide layers of appropriate thicknesses; metallizations were done by evaporating aluminum which was adherent to the oxide layers; metal patterns were delineated in aluminum by contact masking and wet chemical etching. 6. Choice of semiconductor Many scientists all over the USA and the rest of the world were working on Germanium, Silicon and compound semiconductors. However, Noyce used Si. The choice of Silicon over others was fortuitous because the oxide

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film that could be grown on it was an excellent insulator film. For details of the various factors resulting in this choice, see Chapter 6.

7. Fabrication method of devices The fabrication method of devices used for Noyce’s invention was a double-diffused planar transistor technology of Hoerni.8 The key features of this technology and how was it invented by Hoerni by combining important work of the others earlier than him, were described in Chapter 6. Fabricating more than one device in one chip is only a part of the monolithic-IC. Only this part was described by Kilby for which he was given the credit for “the invention of integrated circuit”. But this part was insufficient by itself to fabricate a complete monolithic-IC. Additional parts were needed, but not described correctly by Kilby. They were the technologies needed for the fabrication of the devices, viz., the planar technology, and the devices had to be interconnected by monolithic interconnections adherent to the insulator films, and isolated electrically from each other (see Table 1.1 in Chapter 1). Noyce’s invention2 gave the correct procedures to fabricate silicon monolithic-ICs. However, he used the planar technology invented by Hoerni8 to fabricate the devices, and p-n junction isolation technology invented by Lehovec,9 but the credit due to both Hoerni and Lehovec for their crucial contribution to the invention of the IC had been essentially ignored in the entire literature so far, until my paper12 was published. The credit due Hoerni was acknowledged only recently by Riordan51 also after my paper12 had stated it explicitly for both Hoerni and Lehovec (for additional details, see Chapter 6).

8. Insulating layers Comments are given on the insulating layers described by the inventor in the patent. Column 2; lines 19–28: “. . . at elevated temperature in an oxidizing atmosphere, the surface of silicon oxidizes and forms an oxide layer 5, often one micron or more in thickness, congenitally united with and

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covering surface 2. This layer may consist chiefly of silicon dioxide, or of disproportionated silicon suboxide, depending upon the temperature and conditions of formation. In any event, the oxide surface layer is durable and firmly adherent to the semiconductor body, and furthermore it is a good electrical insulator.” The above lines clearly state that the insulating layer used in Noyce’s invention is SiO2 film which is thermally grown on silicon substrate. For pedantic reasons during 1959 when Noyce’s application was filed, “disproportionated silicon suboxide” was also included in Noyce’s description to cover all possible aspects of thermally grown oxide. Also, deposited silicon oxide films were not mentioned because the “semiconductor device” being claimed then was a single-level metallization device, not a multi-level metallization device as produced thereafter. As it is well known now, after the 1st-level insulator film of SiO2 is thermally grown, insulator films of doped and undoped Siv Ox Py Bz films are deposited above thermal oxide and at higher-levels by various processes such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc, to be used as inter-layer dielectrics (ILDs). Planarization of these films has also been used in most of the advanced technologies to reduce the interconnect delays and the steps of thinner interconnect metal giving higher resistance and current density leading to higher failure rate due to electromigration.56

9. Isolation of devices Comments are given on the isolation of devices described by the inventor in the patent. The statement in Claim 1, “. . . said body containing adjacent P-type and N-type regions with a junction therebetween extending to said surface . . . ” implies isolation of devices in the invention, which was the invention of Lehovec. Why isolation was not claimed by Noyce in his invention, and why Lehovec’s invention was not cited and acknowledged in Noyce’s patent filing even though it was crucial to his invention, has been explained in Chapter 6.

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In the reduction to practice of Noyce’s invention, and during the early years of IC fabrication, the devices were isolated by forming deep p-n junctions obtained by long thermal diffusions. However this problem was solved later by the use of thin epitaxial layers through which the isolation diffusions could be accomplished in much shorter times. As the technology developed further, for the electrical design considerations of the ICs, Local Oxidation of Silicon (LOCOS) was used for many years, and even it has been replaced by trench isolation technologies in advanced ULSICs. 10. Interconnects Comments are given on the interconnects used to connect the devices described by the inventor in the patent. Column 3; Lines 20–29: “Various methods may be employed for forming the base and emitter contacts and leads. By way of example, the contacts and leads can be deposited in the configuration shown by direct vacuum evaporation of aluminum, or other suitable contact metal, through a mask of suitable size and shape. Alternatively, a metal coating may be deposited over the entire upper surface of the composite structure, and the unwanted metal then removed by known photoengraving techniques to leave only the contact-and-lead configuration shown . . . ” Column 3; Lines 69–75: “Furthermore, leads 7 and 9 can be made as large as may be desired at the point where wires or other circuit elements are to be attached; and such attachments can be made at a distance from the active elements of the transistor proper, so that chances of damage to the transistor are significantly reduced.” Column 5; Lines 36–38 and 42–44: “. . . by the vacuum deposition of an aluminum film covering both the cleared and oxide-coated areas . . . The circuit structure is completed by providing metal strips extending over and adherent to the insulating oxide layer 27 and making electrical connections to and between the various contacts heretofore described . . . .” Noyce specifies the use of Al and the essence of planar technology.

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11. Impact of 35 USC 112 Noyce had been awarded several patents in IC technology. But only one patent was awarded to him for the invention of IC, viz., no. 2,981,877. Therefore, there could not be a potential violation of the US Patent Code 35 USC 112. However such violation could be suspected in the patents awarded to Kilby for his invention of the IC as described in detail by me in the previous chapter, Chapter 7. 12. Overall comments A few important facts other than the technical details and comments on the invention of ICs by Noyce are as follows. 12.1. Noyce became aware of Hoerni’s planar process in 1958, wrote his concepts for monolithic-ICs in his notebook at Fairchild in 1959 which was not even witnessed by anyone. However, he must have disclosed his concepts at least to some of his seven co-founders at Fairchild Semiconductor and his key managers during that time. Proof of such disclosure by Noyce has not been available, although several of the seven co-founders are still professionally active at this moment. Thus, existence of such disclosures by Noyce during 1958–1959 is debatable at best, until one or some of the key contributors would step forward. 12.2. Noyce filed for his IC patent on July 30, 1959; was awarded his patent on April 25, 1961, which was ahead of Kilby’s. 12.3. Noyce made no patentable (except perhaps trade secrets such as the lithography camera) contributions to advanced monolithic-IC technologies and beyond, as evidenced by the lack of patents issued to Noyce for them. But Noyce made another major contribution to the IC industry after inventing the monolithic-IC, viz., he co-founded Intel with Gordon Moore. The engineers at Intel have been and still are leading the world in inventing and putting into manufacturing practice the advanced technologies that provided the multiple CPU chips to give the ultra-fast laptop and desktop personal computers and workstations we are using, such as the writing of this book using a laptop PC containing the latest dual core processor with significantly lower power dissipation and longer battery life than the preceding dual core generation.

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12.4. Noyce did not receive the Nobel Prize in 2000 because he had died in 1990. The Nobel Prizes are not awarded posthumously. (For details of the Nobel Prize, see Chapter 12 and Appendix 7.) 13. Detailed analyses of all the claims For pedantic purposes, detailed analyses of ALL the claims of Bob Noyce’s patent no. 2,981,877 (filed July 30, 1959; issued April 25, 1961) are given below, including those key claims just analyzed already in the preceding Section 12. Claim 1. “A semiconductor device comprising a body of semiconductor having a surface, said body containing adjacent P-type and N-type regions with a junction therebetween extending to said surface, two closely spaced contacts a adherent to said surface upon opposite sides of and adjacent to one portion of said junction, an insulating layer consisting essentially of oxide of said semiconductor on and adherent to said surface, said layer extending across a different portion of said junction, and an electrical connection to one of said contacts comprising a conductor adherent to said layer, said conductor extending from said one contact over said layer across said different portion of the junction, thereby providing electrical connections to both of the closely spaced contacts.” Comments on Claim 1: The claim 1 and the subsequent claims are essentially legalese way of saying what Column 1; Lines 15–32 state clearly in plain English all about Noyce’s invention. For convenience in reading all the claims, these lines are copied again below. Column 1; Lines 15–32: “This invention relates to electrical structures incorporating semiconductor devices. Its principal objects are these: to provide improved device-and-lead structures for making electrical connections to the various semiconductor regions; to make unitary circuit structures more compact and more easily fabricated in small sizes than has heretofore been feasible; and to facilitate the inclusion of numerous semiconductor devices within a single body of material. In brief, the present invention utilizes dished junctions extending to the surface of a body of extrinsic semiconductor, an insulating

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surface layer consisting essentially of oxide of the same semiconductor extending across the junctions, and leads in the form of vacuumdeposited or otherwise formed metal strips extending over and adherent to the insulating oxide layer for making electrical connections to and between various regions of the semiconductor body without shorting the junctions.” Bob Noyce says it all in the very first paragraph of this patent. This is essentially how the present monolithic ICs are made. P- and N-type regions “extending to said surface” and “an insulating layer consisting essentially of oxide of said semiconductor on and adherent to said surface, said layer extending across a different portion of said junction” are essentially derived from Hoerni’s invention of planar technology. Noyce’s key invention lies in “comprising a conductor adherent to said layer, said conductor extending from said one contact over said layer across said different portion of the junction”, in particular the adherence of the conductor to the insulator films. The key issue of monolithic interconnects adherent to oxide was settled by the decision of the CCPA, the highest appeals court to hear the case, that Kilby did not disclose the adherent interconnects.19 (To clarify the legal aspects of patent interference proceedings, it is an adjudicative hearing within the auspices of an administrative agency, the US Patent Office. It is run like a mini-trial, but technically speaking it is not occurring in a court of law. It is occurring before the Board of Appeals of the USPTO.26 Why Hoerni’s invention was not cited and acknowledged in Noyce’s patent filing even though it was crucial to his invention, is not easy to explain now. Nevertheless, see Chapters 6 and 11 for discussions. The statement in Claim 1, “. . . said body containing adjacent P-type and N-type regions with a junction therebetween extending to said surface . . . ” implies isolation of devices in the invention, which was the invention of Lehovec. Why isolation was not claimed by Noyce in his invention, and why Lehovec’s invention was not cited and acknowledged in Noyce’s patent filing even though it was crucial to his invention, is not easy to explain completely. Nevertheless, using electrical engineering for the design of the ICs, reasonable explanations have been given in Chapters 6 and 11.

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A typographical error appears to be in Claim 1, Column 7, line 28 of the patent, and line 3 in the above text, “. . . closely spaced contacts a adherent to said surface”, where the letter “a” between “contacts” and “adherent” is not needed and it should be deleted. Also none of the Figs. 1–7 identify any contact with the letter “a”. Claim 2. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing adjacent P-type and N-type regions, one overlaying the other, with a junction therebetween extending to said surface and there completely encircling said overlying region, the underlying one of said regions extending to said surface and there surrounding said junction, a first metal contact adherent to said surface in ohmic electrical connection with said overlying region, an insulating layer consisting essentially of oxide of said semiconductor united with said surface and extending across said junction, a metal strip adherent to said layer , said strip being electrically connected to said first contact and extending therefrom over said layer across said junction, and a second metal contact adherent to said surface in ohmic electrical connection with said underlying region, said second contact substantially encircling said junction from one side of said strip to the other.” Comments on Claim 2: Essentially similar to Claim 1; additional specifications of ohmic electrical connections and layout. Claim 3. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing adjacent P-type and N-type regions with a dished junction therebetween having a substantially circular edge at said surface, a discoid metal contact adherent to said surface wholly within and substantially concentric with said edge, a Cshaped metal contact adherent to said surface and substantially concentric with said discoid contact, said C-shaped contact being wholly outside of and substantially encircling said edge, said C-shaped contact having two ends defining a gap therebetween, an insulating layer consisting of oxide of said semiconductor on said surface extending through said gap and across said junction, and a metal strip over and adherent to said layer extending through said gap and across said junction to said discoid contact, said contacts being in direct electrical connection with respective ones of said regions, and said metal strip being in direct electrical connection with said

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discoid contact but spaced and insulated from the ends of said C-shaped contact.” Comments on Claim 3: Essentially similar to Claim 1; additional specifications of discoid and C-shaped contacts and layout. Claim 4. “A diffused junction transistor comprising a body of extrinsic silicon having a surface, said body containing adjacent base and emitter regions, with a discoid emitter junction therebetween having a substantially circular edge at said surface encircling said emitter region, a discoid metal contact to said emitter region adherent to said surface wholly within said edge, a C-shaped metal contact to said base region adherent to said surface and substantially encircling said edge, said C-shaped contact having two ends defining a gap therebetween, an insulating layer of oxidized silicon on said surface, said layer being congenitally united with said body and extending across said junction, and a metal strip adherent to said layer , said strip extending from said discoid contact over said layer across said junction and between said ends forming an electrical connection to said emitter region.” Comments on Claim 4: Description of planar diffused junction transistor and its contacts. Claim 5. “A semiconductor device comprising a single-crystal body of semiconductor material having a surface, said body containing a highresistivity region and extrinsic P-type and extrinsic N-type regions with a P-N junction therebetween extending to said surface, a metal contact to one of said extrinsic regions adherent to said surface, an insulating layer consisting essentially of oxide of said material on said surface, said layer being congenitally united with said body and extending across said junction, and an electrical connection to said contact comprising a metal strip adherent to said layer , said strip extending from said contact over said layer across said junction, said high-resistivity region underlying a portion of said strip, reducing the shunt capacitance between said strip and said body.” Comments on Claim 5: Essentially similar to Claim 1; additional specifications of P–N junction isolation and “. . . an insulating layer consisting essentially of oxide of said material on said surface,

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said layer being congenitally united with said body and extending across said junction, and an electrical connection to said contact comprising a metal strip adherent to said layer . . . ” Why was P-N junction isolation, which was awarded to Lehovec (who had filed earlier but awarded his patent later than Noyce — see Chapter 6, Table 6.2) was not claimed per se by Noyce? See my comments in Claim 1 above. Claim 6. “A semiconductor device comprising a body of semiconductor having a surface, said body containing adjacent P-type and N-type regions, one overlaying the other, with a junction therebetween extending to said surface, a first metal contact adherent to said surface in electrical connection to said overlaying region, a second metal contact in electrical connection with the underlying one of said regions, an insulating layer consisting essentially of oxide of said semiconductor on said surface, said layer being congenitally united with said body and extending across said junction, an electrical connection to said first contact comprising a metal strip adherent to said layer , said strip extending from said first contact over said layer across said junction, and circuit means for applying between said strip and second contact a D.C voltage of the polarity that reverse-biases said junction, so that said junction acts as a capacitor connected between said strip and said second contact.” Comments on Claim 6: Essentially similar to Claim 5, but additional specifications of junction acting as a capacitor. Claim 7. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing adjacent, first, second and third regions, one overlying the other, P-type and N-type alternately, with a first, dished, P–N junction between said first and second regions having an edge extending to said surface and there surrounding said first region, and a second, dished, P-N junction between said second and third regions extending to said surface and there surrounding said second region, a first metal contact adherent to said surface in electrical connection with said first region, a second metal contact adherent to said surface in electrical connection with said second region, a third metal contact in electrical connection with said third region, an insulating layer consisting essentially of an oxide of said semiconductor on said surface, said layer being congenitally untied with said body and

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extending across both of said junctions, an electrical connection to said first contact comprising a first metal strip adherent to said layer , said first strip extending from said first contact over said layer across both of said junctions, and an electrical connection to said second contact comprising a second metal strip adherent to said layer, said second strip extending from said second contact over said layer across said second junction.” Comments on Claim 7: Essentially similar to Claim 1, but giving some specifications of making contacts to more than one contact with metal strip adherent to the insulating layer and going over such layer. Claim 8. “A semiconductor device as in claim 7, wherein said second contact is a C-shaped metal strip substantially encircling said first junction, and said third contact is a larger C-shaped metal strip adherent to said surface and substantially encircling said second junction.” Comments on Claim 8: Essentially similar to Claim 1, but giving some specifications of C-shaped metal strip. Claim 9. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing a plurality of dished, P–N junctions each having an edge extending to said surface and there surrounding and defining an enclosed region of said semiconductor, a plurality of metal contacts adherent to said surface in electrical connection with respective ones of said enclosed regions, an insulating layer consisting essentially of oxide of said semiconductor on said surface, said layer being congenitally united with said body and extending across a plurality of said junctions, and electrical interconnections between said contacts comprising metal strips adherent to said layer and extending over said layer across a plurality of said junctions.” Comments on Claim 9: Essentially similar to Claim 1, but giving some specifications of oxide of semiconductor and interconnections between several contacts with “. . . metal strips adherent to said layer and extending over said layer across a plurality of said junctions.”

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Claim 10. “A semiconductor device comprising a body of extrinsic semiconductor having a surface, said body containing adjacent P-type and N-type regions with a dished junction therebetween, said junction having an edge that extends to said surface and there forms an elongated, closed figure, first and second contacts in the form of parallel metal strips adherent to said surface, said first contact being wholly within and said second contact wholly without said edge of the junction, an insulating layer consisting of oxide of said semiconductor on said surface and extending across said junction, and a metal strip adherent to said insulating layer and extending there-over across said junction to connect physically and electrically with said first contact.” Comments on Claim 10: Essentially similar to Claim 9. 14. Copy of the original Patent No. 2,981,877 of Bob Noyce: “Semiconductor Device-and-Lead Structure”, filed July 30, 1959; serial no. 830,507; issued April 25, 1961.

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Chapter 9

Other Efforts to Invent and/or Contribute to the Invention of ICs Besides Kilby and Noyce being recognized in the entire literature as the sole inventors of the ICs, the only other name occasionally associated with the invention has been that of Dummer. But this is restricted primarily only to the technical literature, because Kilby had referred to and quoted Dummer in his papers and in his Nobel speech. Kilby did not make any reference to Dummer in any of his patents but instead, Kilby gave his own version of the IC concepts in only one of his patents. These concepts given by Kilby were strikingly similar and limited to the same constraints as those given earlier by Dummer. Noyce did not refer to nor quote Dummer at all in his papers and patent, perhaps because Noyce did not regard Dummer’s concepts to be worth quoting or Noyce may not have been aware of Dummer’s article. Regardless, it is proven by me in the preceding descriptions that Dummer’s descriptions were irrelevant to the concept of monolithic-ICs given by Noyce. There were others too who had given the concepts for the ICs earlier than Kilby and Noyce and contributed to the IC inventions. But why were they ignored? The answers to this question are still elusive. Nevertheless for the sake of putting everything on record, the efforts other than those of Kilby1,23 and Noyce2 to invent and/or contribute to the invention of ICs, or even the reduction to practice, in addition to Hoerni which I have already described in the previous chapters, were those of Dummer,4 Johnson,5 Saxena,App.2 Stewart,6 and Last.33,35 They shall be documented and discussed in this chapter.

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The work done by Geoffrey Dummer4 of Royal Radar Establishment (RRE) in England, is discussed below in Section 1. The work done by the groups under the direction of Ian Ross at Bell Labs16 will be mentioned here only for the sake of completeness of record. But neither RRE by itself nor Bell Labs have been listed in the Table 5.2 of Chapter 5 for the chronological account of the invention of the ICs. Dummer has been listed, but RRE has not been listed. The reasons are obvious from the following brief comments on RRE and Bell Labs. RRE had pursued grown junction technology for the transistors, which was extremely difficult to control and make contacts to the necessary layers of devices. At Bell Labs, the focus was on finding clever ways to eliminate as many components and interconnections as possible, and to fabricate functional blocks using mesa technologies for the transistors and diodes. Mesa technology had been known by that time before the planar technology was invented by Hoerni. So mesa technology was chosen by Bell Labs. The results at both RRE and Bell Labs were dismal failures to invent the ICs. While their efforts can be termed as gallant, they “were barking up the wrong tree.”16 Even to this day, the technologies initially pursued to invent the ICs, both at RRE and Bell Labs, have made no contributions to the invention, or to the advancement of ICs, and they are not used to manufacture them. However, Bell Labs did make outstanding contributions to several technologies beyond the IC invention, which are well known and documented in the literature. Similarly, key contributions to several technologies for and beyond the IC invention were made in the universities and research labs of various corporations not only within the US, but also in other countries and regions of the world (a partial alphabetical list includes Belgium, Canada, England, France, West Germany, India, Israel, Italy, South Korea, Japan, Singapore, Taiwan, The Netherlands).

1. Geoffrey Dummer The concepts for an IC were given by Dummer in the conclusion of his paper that he had presented in 1952. They are quoted from it and described below. Also, to compare them with those given by Kilby, and document the similarities and the limitations between them, several criteria

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have been defined. These criteria used for such comparison, and whether or not Dummer and Kilby met them are summarized in Table 9.1. The concepts of IC given by Dummer4.1 have been copied below from the second paragraph on p. 19 of his paper, “Electronic Components in Great Britain”, Proc. Components Symp., Washington, DC, p. 15–20, May 6, 1952. A complete reprint of this paper is given in Section 6 of this chapter.

Table 9.1.

Similarity between and limitations in both Dummer’s and Kilby’s concepts. Dummer4.1

Kilby1

1952

1958/59

Yes

Yes

Yes

Yes

No

No

No

No

No

No

No

Yes

N/A N/A N/A N/A

Ge Mesa Gold wire bonds. No

8. Did they file for a patent for their concepts?

No

9. Did they obtain patents for their concepts?

No No

Yes, but controversial filing date.23 Yes, but not valid for monolithic-IC. No

No

No

Criteria 1. The year when they first disclosed their concepts? 2. Did they give the concept that all devices can be formed in a single block of semiconductor? 3. Did they give the concept that no separate fabrication of devices and interconnections would be needed? 4. Did they give the processes needed for device fabrication? 5. Did they give processes and materials for interconnections? 6. Did they specify electrical isolation of devices, and give processes for achieving this isolation? 7. Did they reduce their concepts to practice? 7.1. 7.2. 7.3. 7.4.

Semiconductor used? Process for device fabrication? Process for interconnects? Did they demonstrate monolithic-IC?

10. Did they ever follow up their work to include planar technology, adherent interconnects and isolations needed for monolithic-ICs, the only kind sold in the market from the very beginning? 11. Did they make contributions to ULSICs?

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“At this stage, I would like to take a peep into the future. With the advent of the transistor and the work in semiconductors generally, it seems now possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating conducting, rectifying and amplifying materials, the electrical functions being connected directly by cutting out areas of the various layers.” Dummer4 did not file for a patent. But he had first published his monolithic concepts in 1952, although they were incomplete to enable the fabrication of the monolithic-IC. He had written that he was taking “a peep into the future” at the very end of his paper. This was akin to wishful thinking or the increasingly popular science and technology fictions such as those presented in the TV programs and popular science fiction articles and books, about the new things that could be achieved because the transistor had become a reality. Dummer had only “envisaged” but did not give any details of the materials and technologies needed in reality to fabricate the “electronic equipment in a solid block with no connecting wires.” The three sentences of Dummer quoted above were like dreaming or thinking out aloud of the new possibilities. But they had many shortcomings and limitations, and the details were missing to specify clearly how a monolithic-IC could be fabricated following his concepts. Kilby’s description in his patent1 filed in 1959 was similar and limited to the same shortcomings as Dummer’s in 1952. Kilby had attended Dummer’s presentation in 1952, so it is possible to assume that Kilby may have derived his ideas from Dummer. He seems to allude to that in his Nobel Lecture in 2000. However, this cannot be proven beyond any reasonable doubt. (See comments in Chapter 7, Section 17.1.) For a comparative study of the concepts given by Dummer in 1952 with those given by Kilby in 1959, the basic concept of Kilby’s invention is copied from his patent1 no. 3,138,744: Column 1; Lines 55–62: “. . . To that end, I have proposed in my pending application for patent, Serial No. 791,602, filed February 6, 1959, that various circuit elements including diodes, transistors, and resistors all be formed within a single block of semiconductor material, thereby eliminating the necessity for separate fabrication of the semiconductor devices and the interconnections as mentioned above. . . .”

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The criteria used to compare Dummer’s and Kilby’s concepts as quoted above and the similarity between and limitations in both are summarized in Table 9.1. Dummer had also quoted his concepts4.1 in a later paper that he had published in 1964.4.2 A complete reprint of this paper is also given in Section 7. However for readers’ convenience, portions relevant to Dummer’s concepts and the work on integrated electronics in England are copied below from this paper. Copy of the Early British Work on Integrated Electronics from p. 1415 of Dummer4.2 - “Integrated Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, P. 1412–1425, December, 1964: “Early British Work on Integrated Electronics As far as can be seen, the first published reference to the integrated electronics concept was made in a paper on ‘Component Development in the United Kingdom,’ presented at the Electronic Components Symposium by the author in Washington, D. C., on May 6, 1952. With the advent of the transistor and the work in semiconductors generally, it seems now possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating conducting, rectifying and amplifying materials, the electrical functions being connected directly by cutting out areas of the various layers. This concept has since been referred to in several review papers published in the U.S.1,2

1. P. J. Franklin and E. F. Horsey, Materials and techniques for microelectronics — Part I,” Elec. Mfg., pp. 275–280; May, 1960. See p. 275. 2. W. A. Adcock, ‘A Survey of the Future of Microcircuitry,’ Proc. NEC, October 12–16, 1959.

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Towards the end of 1956 the use of silicon as a resistor was investigated and resistors of approximately 1000 ohms were made from sliced crystals, about 2 cm long × 1/2 mm square. A contract was placed with the Plessey Company Research Labs. In April, 1957, for the development of semiconductor integrated circuits on the lines indicated by the author. A model demonstrating the technique of shaping the silicon crystals to control semiconductor properties was shown at the International Components Symposium at the RRE in September, 1957, as an illustration of the possibilities of semiconductor integrated circuit techniques. The model represented a flip-flop circuit approximately 0.25 × 0.25 × 0.125 inch with emitter follower outputs. It was known as a “solid circuit”3 and represented a small block of semiconductor material specially doped and shaped to form the four transistors. Four fixed resistors were depicted as bridges of semiconductor material (silicon) with deposited films of conductive, resistive, and dielectric materials to represent a complete functional circuit. 3. ‘Solid Circuits — glimpses into the future at Malvern components symposium,’ Wireless World, vol. 63, pp. 516–517; November, 1957. Early in 1958, work was begun in the RRE labs. on the development of complex thin-film circuits using resistive, capacitive, and conductive films. It was envisaged that the transistors would be inserted separately. The aspect of reliability was considered to be important, and therefore inorganic materials were considered essential for the required high standard. A major problem which necessitated a decision was whether to develop all-chemical processes or all evaporation processes, or a mixture of both. Tin and antimony oxide resistors had been fabricated in the laboratories in 1954, and meander resistor patterns on flat glass plates had been made. However, the basic principle adopted was to use the best known material and process for each passive component, i.e., nickel chromium for resistors, silicon monoxide for capacitors, and gold (with chromium keying to the glass base) for conductors, and a circuit was constructed on these lines on a half inch square glass substrate. The circuit ceased to operate after a relatively short period, due to instability of the magnesium fluoride dielectric. This

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material was chosen initially because of the ease with which it could be evaporated. However, by the time of the circuit failure, silicon monoxide was being satisfactorily evaporated and this was used in future work. In order to aid the production of thin-film circuits on a practical basis, it was clear that considerable fundamental studies must be made on the problems of nucleation, stabilization, leakage, breakdown, and long period stability of dielectric and metallic films. This was undertaken in the first instance in RRE labs., in which the possibility of a process was established, and was then supplemented by a number of contracts for research in universities, research institutes, and in private industry. A summary of the over-all position on integrated electronics in the United Kingdom, which may be interest, was made by the author in May, 1959, and is given in Table II (next page). It will be seen that by this time all the main areas of work had been covered, either by work in RRE labs. or by research and development contracts with universities, research associations and industry.”

2. Harwick Johnson Johnson5 had filed his patent in 1953, and it was issued in 1957. A complete copy of this patent is given in Section 8 at the end of this chapter. Kilby1,23 had filed his patent(s) in 1959, and they were issued in 1964 and later. So clearly, Johnson patent predates Kilby’s patents. 2.1. Quotes from Harwick Johnson’s patent5 no. 2,816,228: “Semiconductor Phase Shift Oscillator and Device”; portions relevant to the IC invention have been highlighted in bold font:

1. Filed May 21, 1953; Serial no. 356,407; issued Dec. 10, 1957; assigned to RCA. 2. Column-1; lines 15–17: “This invention pertains to semiconductor devices and particularly to semiconductor phase-shift oscillators and devices.” 3. Column-1; lines 18–22: “One basic form of semiconductor device is known as a P–N junction transistor and comprises a body of

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4.

5. 6.

7.

8.

9.

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semiconductor material of one type of conductivity having two zones of opposite conductivity material formed therein and separated therefrom by rectifying barriers. . . .” Column-1; lines 42–45: “Also in accordance with a preferred embodiment of the invention, a semiconductor phase-shift oscillator is incorporated in a unitary body whereby much of the circuitry of the conventional phase-shift oscillator is eliminated.” Column-1; lines 52–53: “A further object is to provide a novel phase-shift oscillator in a unitary semiconductor body.” Column-1; lines 54–60: “In general, the purposes and objects of this invention are accomplished by providing a semiconductor body having a portion thereof formed as a transistor and another portion formed as a controllable phase shift (for example, resistance-capacitance) network or delay line, the two portions being related and interconnected to provide the desired function.” Column-2; lines 3–6: “Referring to Fig. 1, a semiconductor device 10 according to the invention comprises a body 12 of semiconductor material of germanium, silicon or the like of N-type or P-type conductivity. . . . ” Column-2; lines 13–17: “Contiguous or integral with the N-type body portion 16, according to the invention, is a portion 22 of semiconductor material which is formed and operated as a resistance-capacitance phase shift network or delay line. . . . ” Column-4; lines 62–67: Claim 4. “A semiconductor phase shift network comprising a unitary semiconductor body including a plurality of series-connected alternating elements of semiconductor material of one type of conductivity and P–N junction elements, and bias voltage means connected to said P–N junction elements for varying capacitance thereof.”

2.2. My comments: This patent describes the concept of forming a transistor and another portion formed as a controllable phase shift (for example, resistance-capacitance) network or delay line, the two portions being related and interconnected to provide the desired function in a unitary semiconductor body. This is similar to, if not more than, the monolithic concept described by Kilby.1 Johnson’s patent5 not only describes the concept of fabricating transistor,

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resistor and capacitor in a unitary semiconductor body, but it also specifies interconnecting them for a desired function which was not given by Kilby.1

3. Arjun Saxena As already written in Section 7 of the Preface, even though I had published a paper in 1953 based on which I had also given the concepts for ICs independent of and earlier than Kilby and Noyce, I have chosen not to discuss them in the main text of this book. Therefore I shall not discuss them in this section. However, for the sake of completeness of historical record I shall defer it to Appendix 2. It provides the available documents and discusses briefly what actually my contributions were. I have also addressed the “job” assigned to me by Gordon Moore55 in his advice to me (see also Preface and Appendix–2), by giving a comparative summary to distinguish my concepts from the others in Appendix–2. Appendix–1 gives a summary of my contributions and patents in various fields of physics and microelectronics from 1953 onwards on and beyond the invention of ICs. They will serve also as a background to list my experiences as qualifications to write this book, in contrast to other authors who did not have the hands-on experiences so very important to the understanding to analyze the details of each parts of such a complex electron device, the integrated circuit.

4. Richard Stewart Key points on and from Richard Stewart’s patent no. 3,138,747, “Integrated Semiconductor Circuit Device”; (filed February 12, 1959; Ser. No. 792,840; 6 Claims; issued June 23, 1964), are given in this section. A complete copy of this patent is given in Section 9 at the end of this chapter. The methodology of analyses of the patents given in Chapter 5 shall be modified in the analyses of the various patents of the others in this chapter. Nevertheless the essence of the various inventions and contributions shall be summarized to convey the important points.

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4.1. Summary of the Invention A brief description of the invention given in the text of the patent is summarized. Column 1; lines 29–42: “The invention improves over the prior art circuits in that the necessary circuit elements such as the load resistor may be made an integral part of the semiconductor element. One such semiconductor element according to the present invention replaces several transistors required in the circuits of the prior art performing the same function. The interconnecting circuit wiring is thereby eliminated or reduced. Also the gates of the ‘nor’ circuit of the present invention provide amplification in addition to performing a logical function and the gates are well matched since they are basically one transistor. The fact that the entire circuit is embodied in a single transistor element allows miniaturization of the circuit heretofore not realizable.” Stewart’s invention describes the concepts of an IC in which “. . . the necessary circuit elements such as the load resistor may be made an integral part of the semiconductor element . . . ”, and “. . . The interconnecting circuit wiring is thereby eliminated or reduced. . . .” This disclosure is similar to if not more than Kilby’s. It is surprising that both Stewart and Kilby had worked at TI when their patents were filed with the USPTO, and these patents were issued on the same day (see Chapter 5), but they never referred to each other’s work and invention. I had speculated the possible causes in the previous chapter. 4.2. Comments on key figures and claims, reduction to practice, choice of semiconductor, fabrication method of devices, insulating layers, isolation of devices, interconnects, and impact of 35 USC 112. They shall not be elaborated here. Such intricate details are deemed unnecessary for these patents regarding the invention of ICs.

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4.3. Overall Comments Why was this patent of Stewart not referred to in any of Kilby’s papers and patents? It claims an integrated circuit with a plurality of transistors, resistors, isolation by P–N junction, and interconnections by conductive means. 4.4 Analyses of all the relevant Claims to ICs Analyses of all the relevant claims to ICs in the patent are given; others are coalesced. Claim-1: “A semiconductor device comprising an emitter layer, a base layer, and a collector layer, a plurality of base layer contacts passing through said emitter layer, said base layer having sufficient sheet resistance to make the operation of each of said base contacts substantially independent of each other, a portion of said emitter and base layers cut away to expose an additional surface on said collector layer, a first collector contact on said additional surface, a second collector contact on the surface opposite said additional surface, said collector layer having a shape that the conductive path from the boundary between said base layer and said collector layer through said collector layer to said second collector contact is substantially greater than the conductive path from said boundary through said collector layer to said first collector contact.” Comments on Claim-1: This claim essentially describes the fabrication of an integrated circuit. Claim-2: “A semiconductor device comprising an emitter layer, a base layer, and a collector layer, a plurality of contacts each passing through said emitter layer making rectifying contact therewith, said base layer having sufficient sheet resistance to make the operation of each of said contacts when biased as a base contact substantially independent of each other, any one of said contacts functioning as the emitter contact when biased properly, a portion of said emitter and base layers cut away to expose an additional surface on said collector layer, a first collector contact on said additional surface, and a second collector contact on the surface opposite said additional surface.”

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Comments on Claim-2: This claim essentially describes the fabrication of an integrated circuit with minor variation from Claim-1. Claim-3: “An integrated circuit device comprising: (a) a thin wafer of monocrystalline extrinsic semiconductor material, (b) first crystal means of one conductivity-type included in said wafer providing collectors for a plurality of transistors, (c) second crystal means of the opposite conductivity-type included in said wafer adjacent a major face thereof. The second crystal means being very thin relative to lateral dimensions thereof and relative to the thickness of the wafer, the second crystal means providing bases for a plurality of transistors, the lateral area occupied by the second crystal means adjacent said major face being much less than the total surface area of said major face, (d) third crystal means of said one conductivity-type included in said wafer adjacent said major face, the third crystal means being very thin relative to the thickness of the wafer, the third crystal means providing emitters for a plurality of transistors, the surface area occupied by the third crystal means on said major face being much less than the total surface area of said major face, (e) a plurality of transistors provided by the first, second and third crystal means, each transistor being defined in a separate small portion of the wafer adjacent said major face, the small portions being laterally spaced from one another on said major face, diffusion of minority carriers being effective in each small portion through only a part of the second crystal means to only a part of the first crystal means, the total lateral area of the small portions adjacent said major face being much less than the total surface area of said major face, and less than the lateral area of the second crystal mean adjacent said major face, (f ) first contact means engaging said small portions of the wafer on said one major face, said first contact means being connected to said third crystal means and effective in operation to provide substantially ohmic connections to the emitters of the plurality of transistors,

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(g) a plurality of second contacts to the wafer on said one major face ohmically engaging the second crystal means at said small portions so that the second contacts will provide separate inputs to the bases of the transistors, (h) conductive means on said one major face ohmically engaging said first crystal means at positions closely adjacent said small portions of the wafer to provide collector contacts for the plurality of transistors, (i) a resistor region defined within the wafer effective to provide a common collector load resistor for at least two of the plurality of transistors, the resistor region being ohmically engaged at one end by said conductive means on said one major face of the wafer, the resistor region being electrically isolated from the second and third crystal means by P–N junction means, (j) third contact means engaging the wafer on a major face thereof ohmically contacting the other end of the resistor region, the third contact means being spaced from the parts of the first crystal means which function as the collectors of the transistors by distances much greater than the spacing between such parts and the positions where the conductive means engage the first crystal means, (k) and means for applying operating bias voltage to the first and third contact means.” Comments on Claim-3: It claims an integrated circuit with a plurality of transistors, resistors, isolation by P–N junction, and interconnections by conductive means. Claim-4: “A semiconductor integrated device comprising: (a) a wafer of monocrystalline semiconductor material; (b) a plurality of junction transistors defined in the wafer adjacent one major face thereof by thin layers of semiconductor material of alternate conductivity types closely adjacent said one major face, each transistor having a collector, a base region and an emitter region separated

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from one another by a collector-base junction and an emitter-base junction, the transistors being laterally spaced along said one major face; (c) a semiconductor resistor region provided within the wafer; (d) a plurality of electrically conductive means engaging the surface of the wafer; (e) a first of said conductive means making non-rectifying electrical connection on said one major face to the collector regions of each of the transistors and to one end of the resistor region; (f ) a second of said conductive means making non-rectifying electrical connection to the other end of the resistor region, the resistance through the resistor region from the first to the second conductive means being much greater than the resistance between the collector-base junction of each transistor and the first conductive means; (g) a third of said conductive means making electrical connection on said one major face to the emitter regions pf each of the transistors; (h) means for applying operating bias potential across said second and third conductive means to reverse bias the collector-base junction of each of the transistors, the resistor region thereby providing a collector load resistor; (i) and a plurality of base contacts making separate electrical connection on said one major face to the base regions of each of the transistors so that the emitter-base junction of each of the transistors may be separately forward biased by potentials applied to such base contacts.” Comment on Claim-4: Same as in Claim-3. Claim-5: “An integrated circuit comprising a wafer of single crystal semiconductor material with a plurality of junction transistors provided within the wafer adjacent one face thereof by regions of opposite conductivity-types overlaying one another, each transistor including a collector, a base, and an emitter; a portion of the wafer providing the electrical properties of a resistor ; conductive means secured to

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said one face making low resistance ohmic contact to one end of said resistor portion and to the collectors of the plurality of transistors so that the collectors are effectively connected together ; separate electrical connections including contacts on said one face to the bases of the transistors; conductive means engaging said one face contacting the emitters of the transistors; and an electrical connection to the other end of said resistor portion.” Comment on Claim-5: This claim of Stewart is similar to the concepts given by Dummer and Kilby, in that it also does not specify the processes needed to fabricate the transistors, resistors and interconnects. Dummer did not show any drawing of his structure; Kilby’s drawing showed mesa transistors and bonded gold wire interconnects. Stewart’s drawings also do not show the correct planar technology for devices and interconnects, which has the same limitations as Dummer and Kilby. However, Stewart’s claims have the additional concept of electrical connections by conductive means, and lack only capacitor in the integrated circuit. Claim-6: “An integrated circuit comprising a wafer of single crystal semiconductor material with regions of alternate conductivity-type defined in the wafer overlaying one another adjacent one face thereof to provide a pair of transistors with each transistor including a collector, a base, and an emitter, a semiconductor resistor region provided in the wafer , conductive means engaging said one face of the wafer contacting one end of the resistor region and also contacting the collectors of the pair of transistors so that the collectors are effectively connected together, a pair of base contacts on said one face with each separately engaging the base of different one of the transistors, conductive means engaging said one face contacting the emitters of the transistors, and an electrical connection to the other end of the resistor region.” Comment on Claim-6: Same as in Claim-5. This claim of Stewart is similar to the concepts given by Dummer and Kilby, in that it also does not specify the processes needed to fabricate the transistors, resistors and interconnects. Dummer did not show any drawing of his structure; Kilby’s drawing showed mesa transistors and bonded gold wire interconnects.

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Stewart’s drawings also do not show the correct planar technology for devices and interconnects, which has the same limitations as Dummer and Kilby. However, Stewart’s claims have the additional concept of electrical connections by conductive means, and lack only capacitor in the integrated circuit.

5. Jay Last 5.1. Comments on J. T. Last,33 “Solid State Circuitry Having Discrete Regions of Semi-Conductor Material isolated by an Insulating Material”, US Patent no. 3,158,788, filed Aug. 15, 1960, issued Nov. 24, 1964. A complete copy of this patent is given in section 10 at the end of this chapter. 1. Column 1; lines 54–66: “The present invention provides for the establishment in a single, solid-state unit of a plurality of electronic components, in accordance with known transistor manufacturing procedures, followed by the establishment of requisite electrical connections to such electronic components, and between individual portions thereof as required for attainment of a desired circuit configuration. This accomplished with the circuit components relatively unisolated in the crystal wafer. The invention hereof then provides for the electrical isolation or insulation between the circuit components without disturbing the components themselves or the electrical connections therebetween.” 2. Claim 1: “An improved solid-state electronic circuit comprising: a body having a plurality of separate regions of semiconductor material, said regions having semiconductor devices formed therein, each region having a face which is coplanar with the other regions, said coplanar faces forming one face of said body; an integral insulating coating upon said one face of said body, said coating having openings exposing selected portions of said devices for electrical connections; a region of solid insulating material, at least a part of which is a different material from said body extending

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between said regions of semiconductor material to electrically isolate said semiconductor regions from each other, said insulating material being bonded to said semiconductor regions, said insulating and semiconductor regions collectively forming a single integral body containing a plurality of semiconductor devices; and connecting means on said coating electrically connecting said separated semiconductor devices together to form said electrical circuit.” 3. Claim 2: “An improved unitary electronic circuit comprising a body having a plurality of zones or semiconductor material separated from each other by insulating material which extends completely through the body in bonded contact with said zones; circuit components in said zones; a protective insulating coating over said body; and electrical connections overlaying said coating and extending through said coating into selective contact with said circuit components in different ones of said zones, thereby electrically connecting same together to form said unitary electronic circuit.” 4. Key summary: Silicon is etched in between the devices all the way through, and the space opened up is filled with a bonded insulating material such as epoxy resin to isolate the devices and maintain the integrity of the wafer. 5.2. Comments on J. T. Last,35 “Method of Making Solid State Circuitry”, US Patent no. 3,313,013, Original filed Aug. 15, 1960; Divided and this application Oct. 5, 1964; issued April 11, 1967. Attorneys: Roger S. Borovoy; Original attorneys (not stated here) were Lippincott, Ralls and Hendricson; Ralls had died around 1960, so Roger Borovoy had taken over the case, as he had done for Bob Noyce’s patent no. 2,918,877. Borovoy has been and is still professionally active, but has had no longer any interest in semiconductor technology, as stated by him in a personal visit last year I had with him at his home office. This patent is substantially the same as Last’s previous patent no. 3,158,788 issued on Nov. 24, 1964. Therefore, its analysis is not needed. Consequently a complete copy of this patent has not been given.

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6. Reprint of the paper presented by Geoffrey Dummer,4.1 “Electronic Components in Great Britain”, Proc. Components Symp., Washington, DC, p. 15–20, May 6, 1952.

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7. Reprint of the paper by G. W. A. Dummer,4.2 “Integrated Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, p. 1412–1425, December, 1964.

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8. Harwick Johnson,5 “Semiconductor Phase Shift Oscillator and Device”, U.S. Patent No. 2,816,228, filed on may 21, 1953, Serial No. 356,407; issued on December 10, 1957.

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9. Richard Stewart,6 “Integrated Semiconductor Circuit Device”, U.S. Patent No. 3,138,747; filed on February 12, 1959; Serial No. 792,840; issued on June 23, 1964. A copy of the original patent 3,138,747 issued by the USPTO TO Richard Stewart is given below.

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Chapter 9. Other Efforts to Invent and/or Contribute to the Invention of ICs Section 10. J. T. Last

10. J. T. Last,33 “Solid State Circuitry Having Discrete regions of Semi-Conductor Material Isolated by an Insulating Material”, US Patent no. 3,158,788, filed Aug. 15, 1960, Serial No. 49,717, issued Nov. 24, 1964.

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Chapter 10

Contributions of Kilby and Noyce Beyond the Invention and to Next Generation ICs 1. Kilby 1.1. Award of the post-planar technology IC patents After Kilby1,23 was awarded the IC patent nos. 3,138,743 and 3,138,744, a few other patents were also awarded to him (see Chapter 7 and Table 10.1 below). However none of these, and no additional patents were awarded to him which had described the Si planar technology and interconnects that were adherent to SiO2 . It had been well established that they were mandatory for fabricating the monolithic ICs. Kilby did not make any contributions later to the planar and other technologies which were, and are, essential to manufacture the conventional and advanced monolithicICs. The subsequent patents that he did obtain were on miniature electronic calculators and in other fields which were important contributions in their own right, but not to the invention and further development of ICs. Nevertheless, Kilby was given the recognition of being the co-inventor with Bob Noyce of ICs based solely on perhaps two patents, viz., nos. 3,138,743 and 3,138,744. As mentioned also in Chapter 7, even Kilby19 refers only to his patent23 no. 3,138,743 in his paper in 1998 on “Origins of the Integrated Circuit”, and not to any other patent of his, when he was critically reviewing his and Noyce’s fundamental inventions of the integrated circuit. 1.2. List of patents of Jack Kilby on and beyond the invention of ICs

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Table 10.1.

List of patents of Jack Kilby on and beyond the invention of ICs. Patent#

•Kilby22 (ICs)

•Kilby31 •Kilby32 •Kilby1 (ICs)

•Kilby34

Filing date

3,138,743 Claimed by Kilby to Application be Feb. 6, 1959. Serial (No official No.23 record30 of this 03/791,602. filing date. Official records show only May 6, 1959, as the filing date.29 See Fig. 6.5 and Fig. 6.6) 3,072,832 May 6, 1959 3,115,581 May 6, 1959 3,138,744 May 6, 1959

3,261,081 Ser. No. 352,380

Issue date June 23, 1964*

Jan. 8, 1963 Dec. 24, 1963 Jun. 23, 1964* (Key patent) Note that patent no. differs by only 1 from his patent ‘743’ and by 3 from Stewart’s patent ‘747’ all awarded on the same date, and all assigned to TI. July 19, 1966

Original appl. as Feb. 6, 1959; this appl. Mar. 16, 1964. •Kilby 4,042,948 May 6, 1959 Aug. 16, 1977 •Kilby 3,643,138 Jan. 29, 1962 Feb. 15, 1972 •Kilby 3,643,232 Jun. 5, 1967 Feb. 15, 1972 •Kilby 3,698,082 Feb. 25, 1971 Oct. 17, 1972 •Kilby 3,819,921 Sep. 29, 1967 Jun. 25, 1974 (Calculators) (abandoned) Dec. 21, 1972 •Kilby Only the numbers of some of the subsequent patents on calculators are given here without giving the other details: 3,991,305; 3,900,722; 3,987,416; 3,892,957; 4,074,351.

List of patents of Jack Kilby on and beyond the invention of ICs is given in Table 10.1. Kilby was also awarded patents later in various other fields, e.g., packaging, light energy conversion, crystal growth, thermal recording head

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for printers, teaching system, telephone answering system, etc. But they are not listed above because they are not pertinent to the IC invention. 1.3 Dialectic approach for possible explanation why Kilby made little or no contributions to IC technologies beyond his original invention With all due respect to Kilby, it is surprising to note that he made little or no contributions to the development and the advancement of IC technologies beyond his original invention after his patent nos. 3,138,743 and 3,138,744 were issued in 1964. It is surprising that in his later work, he did not even seem to acknowledge the planar technology, which is essential to fabricate and manufacture any kind of monolithic-ICs whether they were conventional or advanced ICs. Kilby neither contributed to the planar technology, nor to its advancements which led to the present day ULSICs. As discussed in Chapter 7, Kilby19 was quite defensive about his original ideas of ICs covered by his patent no. 3,138,743 in his paper in 1998 on the “Origins of the Integrated Circuit”, before he died in 2005. The obvious question is why Kilby did not refer to any of the other patents when he reviewed critically the “Origins of the Integrated Circuit” in his paper19 in 1998 after 34 years of receiving his patent no. 3,138,743? The commonsense type of obvious answer is that since he did not receive any other patent relevant to the IC invention, that is why he did not or even could not refer to any patent other than no. 3,138,743 in his paper19 in 1998. Kilby19 left the question of monolithic-ICs ambiguous and unanswered by concluding that “Despite these introductions, the monolithic concept remained controversial.” The fact that he chose to refer to 3,138,743 and not to 3,138,744, even though he had at least stated the concept partially for the monolithic-IC in the latter, was probably due to the earlier filing date Kilby had claimed for the former. This was rather unfortunate indeed because his claim for the earlier filing date for the former was not confirmed by the USPTO.29,30 Another scenario, I suggested in the previous chapter, could be a typographical error in the patent number during editing the 1998 article. From all the accounts by many people, including my brief personal meetings with Kilby, it is unquestionable that Kilby was an affable and a

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brilliant gentleman. Why was he so recalcitrant about monolithic-ICs being the mainstream of all the ICs, and why did he stop contributing to their development after his invention in 1958, which had used mesa instead of planar technology and wire-bonding for interconnects (see Chapter 7)? It will only be a speculation now to offer any explanation for Kilby’s actions or lack thereof. Nevertheless, using dialectic approach based on the available facts given below, a possible explanation emerges even though it may be regarded as just a conjecture. It appears that perhaps the circumstances faced by Kilby at Texas Instruments from 1970 on were not conducive for him to make such contributions. Kilby writes in his paper19 referring to his application no. 03/791,602, that, “A patent application covering both germanium and silicon was prepared and filed in February, 1959.” However, the official record at the USPTO given in Chapter 7 shows that that filing date recorded by the USPTO29,30 instead was on May 06, 1959, or that no filing date was recorded at all for this patent application. For this error in the filing date to be repeated even after 34 years by Kilby, is quite surprising. It will be normal and logical to expect that at least Kilby’s patent attorneys would have informed him of the correct filing date recorded officially by the USPTO. The fact that apparently he was not advised of this, raises doubt on Kilby’s assertion (cf: Kilby’s Nobel Autobiography7) that he had “maintained a significant involvement with the company that continues to this day”, i.e., until 2000 when he had received the Nobel Prize in Physics. Kilby took a leave of absence7 from Texas Instruments (TI) in 1970 to do some independent work. From 1978 to 1984, he spent much of his time as a Distinguished Professor of Electrical Engineering at Texas A & M University. Kilby retired officially7 from TI in the 1980’s. It appears that Kilby did not receive much administrative help from TI in 1998. That would have helped to verify the filing date of his original application and made sure that all the information given in it was correct in his manuscript.19 Usually a committee in a company like TI reviews and approves a paper before it is allowed to be published. But in 1998, Kilby was no longer employed by TI, having retired from TI a decade earlier. Whether or not this was done in the case of Kilby19 is hard to prove now. Nevertheless according to the normal procedures, someone should have caught the errors and statements like, “Despite these introductions, the monolithic concept

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remained controversial.” Similar statement can be made for Kilby’s Nobel Lecture,7 in which three references, viz., nos. 5, 6 and 9 were exactly the same, but they were given different nos. for some unexplained reason. This is difficult to understand and not expected to occur in a published Nobel Lecture.7 Because of these published facts available to anybody having access to the literature and internet, such errors and omissions can be attributed respectively to Kilby, TI and the Nobel Committee. The above facts seem to negate the assertion that Kilby had “maintained a significant involvement with the company that continues to this day”, i.e., until 2000 when the Nobel Prize was awarded to him. These facts are not crucial for the discussion on the invention of ICs in this book. However, for the sake of completeness of reviewing critically perhaps the world’s most important invention ever, the above facts have to be documented based on the analyses I have given. One may infer from them that after Kilby took a leave of absence7 from TI in 1970 “to do some independent work” on photovoltaics, printers etc, he was not involved actively with the ICs and their associated technologies anymore. In defense of Kilby and to give credence to his busy schedule with other activities, these facts may explain why Kilby did not, or could not, make any contributions to ICs and their technologies after his initial patents were granted in 1964.

2. Noyce 2.1. Award of the post-planar technology IC patents After Noyce2 was awarded the IC patent no. 2,981,877, a few more patents were awarded to him on other process and design related issues of ICs. They are listed in Table 10.2 below. But no further patents were awarded to him that went beyond the present 2D-ICs, only for which Moore’s Law holds (Moore45,46 ; Saxena12,13,20,48 ). For example, Noyce did not invent 3D-ICs or UPICs having materials and technologies for devices in addition to Si, and for interconnects in addition to Al, which are used today in many of the advanced ULSICs which are all 2D-ICs. Examples of these are the use of Cu interconnects with appropriate barrier and cap layers, W (tungsten) for contact and via filling, planarization of dielectric and metal films, RIE, LPCVD, etc. The limitations of Moore’s Law for the

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Table 10.2.

List of patents of Bob Noyce on and beyond the invention of ICs. Patent#

Filing date

Issue date

•Noyce (ICs) •Noyce

2,981,877 3,108,359

Jul. 30, 1959 Jun. 30, 1959

•Noyce •Noyce •Noyce

3,150,299 3,117,260 3,325,787

Sep. 11, 1959 Sep. 11, 1959 Oct. 19, 1964

Apr. 25, 1961 (Key patent) Oct., 29, 1963 (Co-inventor with Gordon Moore) Sep. 22, 1964 Jan. 7, 1964 June 13, 1967 (2 co-inventors)

2D-ICs, however, can be removed by invoking the 3D-ICs and UPICs. This is discussed in two memos of Saxena48 given to Gordon Moore at Intel. See also two recent patents of Saxena37,38 and three recent papers.12,13,20 (See Chapter 13.) 2.2. List of patents of Bob Noyce on and beyond the invention of ICs List of patents of Bob Noyce on and beyond the invention of ICs is given in Table 10.2. As it can be noted in Table 10.2, Noyce obtained only four more patents after his key IC patent was issued in 1961. He had obtained other patents earlier. The total number of US patents awarded to Bob Noyce was 17. Except for the crucial 8-mask step-and-repeat lithography camera which impacted the evolution of the technology, he did not contribute further to the inventions of several advanced technologies which are essential to manufacture the ULSICs today, and to the next generation 3D-ICs and UPICs. However he made a major contribution to the entire microelectronics industry, which was the co-founding of Intel Corporation. Intel has become and has been the leading semiconductor manufacturer in the world, where most of the advanced technologies are developed and implemented in large volume manufacturing. Getting patents for inventions, publishing fundamental papers, and receiving important awards, on a relative basis, are far easier than implementing one’s unique knowledge and talent to create a successful high technology business. It is far more crucial to make it in the real world and change it forever, affecting the lives of almost every human being on earth. Along with Bob Noyce, it is also important to recognize the contributions of Gordon Moore and their entire team(s) to make Intel a great success.

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2.3. Dialectic approach for possible explanation why Noyce made little or no contributions to advanced and next generation ICs beyond his original invention Noyce was a compulsive idea generator.17 Also, he was a charismatic leader as well as a team player with a hands-off management style. So the obvious question arises, why did he not generate subsequent ideas on several advanced technologies and the next generation ICs beyond his original invention? Why did he not innovate further and patent at least some of the technologies needed for ULSICs, many of which have become the mainstay of the microelectronics business today and to the forthcoming next generation 3D-ICs and UPICs? In the case of Noyce, the answers to the above questions are difficult to arrive at even with the dialectic approach. Perhaps the simplest answer can be the “trade secret”, a practice which actually Intel was following at those initial formative times, years, well-known to most and proven by patent filing history. Without any doubt, Noyce was the key idea generator (inventor) of the monolithic-ICs, although many others did also make key contributions to make them a reality as well as to the advancements of the technologies and design of the ULSICs. Being a charismatic leader as well as a team player with a hands-off management style, can be viewed as somewhat contradictory. If the above observations are correct, then Noyce could have coinvented, if not claimed to have solely invented, several advanced IC technologies, since he would have had easy access to many of their key developments. But he did not do that. If anything, Noyce was too generous to give his ideas freely to the others. Was he over-reacting to the criticism that he had usurped the IC invention from the others, and that is why he was being too generous after that? It is hard to tell. It is well known though that Noyce was deeply involved in starting, managing and running Fairchild and Intel. These activities would have forced Noyce not to be able to use his creativity and contribute first hand to the ULSICs and beyond. However, he did interact with several other scientists, engineers and entrepreneurs in various technical fields, and helped them to start their own companies. So there are no easy answers for Noyce’s lack of further direct contributions and innovations in the IC field, despite the dialectic reasoning given above.

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In my personal opinion, Noyce was brilliant, enterprising and a generous man willing to take risk on a promising new idea. I am privileged to have known Bob Noyce personally for many years, benefited immensely from Noyce’s advice and help, and I am grateful to him. Bob Noyce died young at the age of 62 years and 5 months. Bob was undergoing certain severe stresses especially during later years in his life, which may have precipitated his heart attack on June 3, 1990.

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Chapter 11

Discussion

Key observations on various patents relevant to the invention of ICs are summarized below. Their discussion is adapted mostly from my recent papers.12,13 Some important additional information has been given, as well as some has been repeated to facilitate in unraveling their intricate issues entwined technically, chronologically and patent wise. See also a commentary by Jeff Marque14 on my paper.12 For convenience of the readers, the original copy of my paper12 is given in Appendix 3, and that of Marque is given at the end of this chapter. 1. Noyce’s patent — Noyce patent2 2,981,877 (filed on Jul. 30, 1959; issued on Apr. 25, 1961): This was the only patent awarded to Noyce for the invention of IC. It states and claims the monolithic concept clearly using planar technology and monolithic interconnects adherent to the insulator layers, and without shorting to the regions adjacent to the devices (see Chapter 8 for details). Even though the ICs have advanced to the current ULSICs in which more than 2 billion transistors per chip with 45 nm dimensions and more than 8 levels of metallizations are used, Noyce’s invention is still fundamental to them. Outstanding advancements of processes and materials have been made to enable such ULSICs in large volume production, but Si as the start material and Noyce’s invention remain the core. Important reminders to the reader are that all the ULSICs being sold in the market are 2D-Si-ULSICs, and only electrical functions can be performed in them. They have all the devices laid out in the 2-dimensions of the Si wafer, and the 3rd-dimension is used primarily for the multilevel 321

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interconnects. Some thin-film devices may be fabricated in levels above the main level of the Si wafer. Moore’s Law applies only to such 2D-Si-ULSICs. It is reaching limits of its continued validity due to the fundamental limits of materials and technologies, and paradigm shifts in the architectures of new microprocessors. However, other technologies can be invoked to extend its validity. For details, see Chapter 13. 2. Kilby’s original application (OA) and patents: Two patents 3,138,743 and 3,261,081 were awarded to Kilby23,34 which were based on his OA 03/791,602. A third patent 3,138,744 was also awarded to Kilby1 which refers to OA 03/791,602, but its serial no. was 811,486. [Lehovec9 writes in his Ref. 6, “Application 811,476 filed on May 6, 1959; re-filed as US Application 218,206 on Aug. 16, 1962”. Lehovec only writes “Application 811,476 filed on May 6, 1959”, and does not write directly that patent no. 3,138,744 was issued on this Application. From the documents listed in Chapters 6 and 7, there is little doubt that Lehovec refers to Kilby’s 811,486 for which patent no. 3,138,744 was issued.] It is important to note that all the figures in OA 791,602, patent numbers 3,138,743 and 3,261,081 were exactly the same, and their entire texts were also similar except for some minor variations. But the three sets of claims (OA 03/791,602; 3,138,743 and 3,261,081) were different and they were not entirely supported by the specifications (texts and figures). 2.1. If the claims of the OA were supported by the specifications (i.e., texts and figures), and USPTO was satisfied, a patent with those claims would have been issued reasonably promptly instead of having to review for over 5 years and then award 3,138,743 with the new set of claims on June 23, 1964. 2.2. Next, if the claims of 3,138,743 were sufficient to get the patent on the OA filed on Feb. 6, 1959, then why 3,261,081, which also originated from the same OA and same specifications on the same filing date, was re-filed and new set of claims were necessary? See Section 4 for its revised filing date Mar. 16, 1964 and serial no. 352,380; it was awarded on July 19, 1966. Obviously its issue date was about 2 years after that of 3,138,743 issued on June 23, 1964. In addition, the fact that it did not provide any new information, this may have been the

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reason also why Kilby did not refer to 3,261,081 also in his 1998 paper19 (see Section 3 below). 2.3. The quote from Lehovec9 in his Ref. 6, “Application 811,476 filed on May 6, 1959; re-filed as US Application 218,206 on Aug. 16, 1962”must be legitimate. However, Lehovec does not give any details about why this re-filing of Kilby’s Application was made? Also the USPTO did not document its re-filing as US Application 218,206 on Aug. 16, 1962, on the patent no. 3,138,744 issued on June 23, 1964. Why the re-filing number and date were not published on 3,138,744, has not been explained by the USPTO. Was this done to hide the facts from the public record of the issued patent, and maintain the earlier filing date of Kilby? Since nobody knows why such procedures were allowed by the USPTO, they appear to be circumspect. Maintaining the priority of filing dates was one of the key objectives of Kilby during his interference proceedings independently each with Lehovec and with Noyce. This also reflected in Kilby’s continued referral to his OA being filed on Feb. 6, 1959, as recently as in 1998, but this filing date was rejected by the USPTO (see Section 4 below and Chapters 5 and 7). 3. Reference to patent by Kilby in his latest paper in 1998 and comments on monolithic concept: Kilby19 refers only to 3,138,743 with serial no 791,602 and the filing date Feb. 6, 1959 in his 1998 paper. Kilby19 does not refer to his second patent 3,261,081 nor to 3,138,744 (filing date May 6, 1959; serial no. 811,486) in his 1998 paper. Kilby also writes in this paper, “Despite these introductions, the monolithic concept remained controversial.” In my opinion, Kilby’s patent no. 3,138,744 was his KEY PATENT because it was the ONLY patent of Kilby in which he had at least stated the monolithic concept though partially correct and only partly consistent in its text. 4. Kilby’s filing dates and recent communications from USPTO: Kilby’s23 OA 791,602 and corresponding patent23 3,138,743 were claimed to have been filed on Feb. 6, 1959. But recent USPTO

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communications to Saxena29,30 in 2005 (see Chapter 5, Figs. 5.5 and 5.6) regarding serial no. 791,602 sent two conflicting responses: 4.1. Its filing date29 was May 6, 1959. 4.2. It did not have an official filing date.30 Why did USPTO still keep the filing date of 3,138,743 to be Feb. 6, 1959 is a mystery? The filing date of the second patent 3,261,081 is written in its Column 1, lines 6–9 as “Original application Feb 6, 1959, Ser. No. 791,602, now Patent No. 3,138,743, dated June 23, 1964. Divided and this application Mar. 16, 1964, Ser. No. 352,380; 21 Claims, (Cl. 29–155.5).” The wording in this patent, “Divided and this application Mar. 16, 1964, Ser. No. 352,380” seems strange, but it is clear that revised filing date was Mar. 16, 1964, and its serial no. was 352,380. As written in Section 2 above, the claims of this patent 3,261,081 were also not supported by its specifications (texts and the figures). As of writing this book, my attempts to obtain the “Certified Copy each of the File History of patent numbers 3,138,743 and 3,138,744, both being based on the original application number 03,791,603” from the USPTO have not been successful. The response from the USPTO is given in Fig. 15.1 at the end of Chapter 15. It states, “We are unable to fill your order because the files for the above patent numbers above are unavailable due to being in the lost category. . . .” 5. Monolithic concept: Noyce’s patent states and claims the monolithic concept clearly using planar technology and monolithic interconnects adherent to the insulator layers, and without shorting to the regions adjacent to the devices (see Section 6 below). Kilby19 wrote in his 1998 paper, “Despite these introductions, the monolithic concept remained controversial” implying that he did not agree with the monolithic concept described by Noyce. Kilby did not refer in this paper to his patent 3,138,744 which at least stated the monolithic concept though partially correct and only partly consistent in its text. Instead, he chose to refer only to 3,138,743 which did not even mention the monolithic concept. Kilby had filed a patent interference against Noyce for earlier award, and claiming priority that the monolithic interconnects

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were already anticipated by him in his OA 791,602. The patent interference was settled as a compromise that both the patents of Noyce and Kilby were deemed necessary to fabricate monolithic ICs. Except in Kilby’s 3,138,744, none of his other patents (especially the patent application OA 791,602, patent 3,138,743, and patent 3,261,081), state the monolithic concept in their specifications or claims. 6. Monolithic interconnects: None of Kilby’s patents, especially the patent application OA 791,602, patent 3,138,743, patent 3,261,081, and 3,138,744 state correctly how to achieve monolithic interconnects adherent and contiguous to the insulator layers, and without shorting to the regions adjacent to the devices. 7. P–N junction isolation: Lehovec9 had filed his P–N junction isolation invention on this on Apr. 22, 1959, and was awarded patent no. 3,029,366 on April 10, 1962. Kilby had filed a patent interference against Lehovec claiming priority that the P-N junction isolation technique was already anticipated by him in his OA 791,602, which was claimed to have been filed earlier on Feb. 6, 1959. Kilby lost the patent interference because of the decision by the Board of Patent Interference on this priority sought by Kilby over Lehovec’s p–n-junction isolation technique.9,26..2 Briefly, the Board ruled “We have carefully examined Patent 3,138,743 but nowhere can we find support for the subject matter of the counts . . . Since Kilby has no reduction to practice prior to the filing date of Lehovec, . . . priority of counts 1–5 is awarded to Kurt Lehovec, the senior party.” (See also Chapter 6.) 8. Importance of keeping the filing date Feb. 6, 1959 by Kilby: Because of the patent interferences (see Sections 5 and 7 above), it was quite important for Kilby to insist on keeping the filing date Feb. 6, 1959 as valid. See Section 4 above for details regarding Feb. 6, 1959. The communications from USPTO to Saxena29,30 in 2005 negate this validity. However it is difficult to explain why this filing date Feb. 6, 1959 was allowed to be kept in Kilby’s patent 3,138,743, and its claims to be rewritten though still inconsistent with monolithic-ICs, which was in the review process for over 5 years by USPTO. During this period, Noyce’s

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patent for monolithic ICs had been issued, i.e., its contents were public knowledge, and Kilby’s patent interferences against Noyce and Lehovec were ongoing. The re-written claims of 3,138,743 and 3,261,081 which were quite different from those in OA 791,602 seem to have been influenced by the then public knowledge of Noyce’s patent 2,981,877 and Lehovec’s patent 3,029,366. Nevertheless, Kilby’s claims were still inconsistent with monolithic-ICs. 9. Possible compromise of the laws of US Patent code 35 USC 112 and associated protocols: The fact that the claims of Kilby’s OA 791,602, patent 3,138,743, and patent 3,261,081 were not entirely supported by their specifications (which were almost the same in all three), would suggest a possible compromise of the laws of US Patent code 35 USC 112 and associated protocols. The proceedings in the award of patents 3,138,743 and 3,261,081 to Kilby, in particular allowing the filing date to be kept as Feb. 6, 1959 in view of the lawsuits and their outcomes (see Sections 5 and 7 above), appear rather unusual. Additional issues that further beg clarifications are that all the figures, which are exactly the same in the three documents of Kilby (OA 791,602, patent 3,138,743, and patent 3,261,081), show mesa structures for the devices and wire bonded interconnects which are never used in monolithic ICs. Also the figures in patent 3,138,744 show mesa structure, and its text specifies materials and technologies most of which are not used in monolithic ICs. The “shaping said wafer to obtain isolation between said components in said wafer” appears to include mesa etching, and selective formation of p–n junction formation. All the figures show the former but not the latter at all. See also Section 7 above regarding the decision by the Board of Patent Interference which ruled against Kilby in favor of Lehovec in this matter of p–n junction isolation. It is also interesting to note that the patents 3,138,743 and 3,138,744 differ in number by only 1, and they were awarded to Kilby on the same date June 23, 1964. Grouping more than one patent to be issued on the same day may not be unusual. But for two successive patents with different sets of claims for achieving the same invention, especially with their strange history, extra long review periods for over 5 years, patent interferences, and awarded on the same date, all of them raise some concern regarding the decisions of USPTO to award Kilby’s patents.

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10. Stewart’s patent6 no. 3,138,747: Also as discussed in Chapters 5 and 9, Stewart’s patent6 no. 3,138,747 was filed on Feb. 12, 1959, and it was awarded on the same date, viz., June 23, 1964, as were Kilby’s patents 3,138,743 and 3,138,744. Unlike Kilby’s, there was no controversy about the filing date of Stewart’s patent. Note its patent no. differs by 4 from Kilby’s patent 3,138,743, and by 3 from 3,138,744. All the patents of Kilby and Stewart were assigned to Texas Instruments (TI). Why was this patent of Stewart not referred to in any of Kilby’s papers and patents? It claims an integrated circuit with a plurality of transistors, resistors, isolation by P–N junction, and interconnections by conductive means (see Chapter 9). 11. Were any of Kilby’s patents ever used to manufacture ICs? The clear answer is “No”. Perhaps some aspects of the patents may be argued to have been usable, but it is extremely debatable. Did they affect the huge sums of royalties earned by TI from the others, and the patent agreement between TI and Fairchild? Yes. 12. Table 1.1 describes the key requirements for making the monolithicIC and whether or not they were met by Kilby and Noyce in their respective inventions. Re-stating them here, the four requirements are as follows: 12.1. All devices must be fabricated in the same single crystal semiconductor substrate (e.g., Ge, Si). 12.2. Planar technology must be used to fabricate the above devices. 12.3. All devices must be isolated from one another by an appropriate planar technology (e.g., p–n junction, LOCOS, trench). 12.4. All devices must be connected by planar interconnections adherent to oxide surface. Any other approach without meeting these four key criteria will not give monolithic-ICs. For a quantitative characterization of adhesion, which was a key issue in Kilby vs. Noyce patent interference, see Saxena.28

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The only exception in monolithic-ICs for the passive devices such as resistors and capacitors is that some of them may not need to be fabricated by planar technology; they could be fabricated by thin film technologies as well. However the criteria 12.1, 12.2, 12.3 and 12.4 above still must be met. In principle, monolithic-ICs could be made with mesa devices, grown (for Si devices) or deposited (for Ge or compound semiconductors) films of SiO2 and monolithic interconnects. However high leakage currents in such devices, and their unpredictable variations in the devices within a chip and from chip-to-chip in the wafers, would make such monolithic-ICs useless. It will be even worse at the higher integration levels of today. 13. Noyce’s invention covered all the criteria in 12.1, 12.2, 12.3 and 12.4. So his invention was for monolithic-ICs. 14. Kilby’s invention(s) met only the criterion 12.1 of fabricating the devices on the same single piece of a single crystal semiconductor. But Kilby did not specify planar technology in any of his patent(s). Kilby used Ge to demonstrate his reduction to practice, and 14.1. used MESA technology (see figs. in his patents), and 14.2. specified isolation by “shaping” with mesa etching, or p–n junctions (this was denied by the Board of Patent Interference in favor of Lehovec), and 14.3. interconnected by wire bonds dangling above the chip. Therefore, Kilby’s invention did not meet all the criteria in 12.2, 12.3 and 12.4. Therefore his invention was not for the monolithic-ICs; instead it was for hybrid-ICs. 15. Moss (Kilby’s co-op student in 1960 for testing Kilby’s “solid circuits”): A recent report by Moss49 who was a University of Florida college co-op student assigned to work with Kilby at TI in the summer of 1960, confirms

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the above facts as follows. The original copy of Moss’ article is given at the end of this chapter. Moss tested in 1960 Kilby’s “solid circuit” flip-flop (7 resistors, 2 capacitors, 2 transistors, “interconnected with very fine wires”). Kilby gave several thousand units to Moss for testing since “there was no automated testing of the solid circuits” available in 1960 at TI. He found that 1 out of 200 worked to specs (0.5% yield). Even though Moss49 confirms that “The components were interconnected with very fine wires”, but he doesn’t write about which technology was used to fabricate the devices. It is obvious that these “solid circuits” were built as hybrids with devices made from Ge-mesa technology available at TI at that time (planar technology was not available then at TI). That is why the yield was so poor. Again Moss does not give the failure analysis of the yield loss, but the most likely cause for this would have been the variable and uncontrolled leakage currents in the Ge mesa devices. Moss writes that “The first working units were available to outside companies who wanted to try them at US$250 each.” This price was in 1960. 16. The issues in the inventions of ICs are intricately entwined technically, chronologically, and legally patent wise. The analyses of the inventions of Kilby,1,23,34 Noyce,2 Hoerni8 and Lehovec,9 are complicated anyway. But they have been made more difficult by the mind boggling speed with which the rapid advancements and progress were made, and colossal sums of money were generated, in the IC business. Few had the time or the patience to stop and pay attention to the original key facts of the invention of ICs, and worry about who invented what? Many scientists and engineers have made outstanding contributions to bring the IC industry to its current level of multi-hundred billion dollars per year. Its snowballing effect, however, has not led to a destructive avalanche. Instead, it has revolutionized the entire mankind forever with businesses in many fields amounting to trillions of dollars per year. 17. The conclusion drawn from all the analyses of the documented facts is that Noyce invented the monolithic-IC. But its reduction to practice was done by the others who had worked under him. Kilby’s invention was at best that of a hybrid-UC-IC, whose basic ideas were similar to those described by several earlier contributors. The actions and the decisions of Kilby, USPTO,

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and the Nobel Committee are inexplicable. Similarly the inactions of almost all of the other key contributors, scientists, engineers and patent experts for about four decades to set the records of who invented the real IC straight, are also inexplicable indeed. I feel privileged to have been involved from the very inception of this magnificent phenomenon of the invention of ICs when the first few snowflakes were beginning to coalesce and form the initial tiny snowball, and thereafter. 18. Copy of the original article14 by Jeffrey Marque, “Getting History Right is an Important Matter”, F O R U M O N P H Y S I C S & S O C I E T Y of The American Physical Society, Vol. 36, No. 3, July 2007.

COMMENTARY Getting History Right is an Important Matter Jeffery Marque “Getting history right is an important matter.” Thus begins a paper by Dr. Arjun N. Saxena, entitled “Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce” and presented by him on May 24 at the Nano Science and Technology Institute Annual Conference in Santa Clara, California. Saxena himself was a primary participant in the development of integrated circuits (ICs), and his paper goes into great detail about matters about which many people (myself included) had not gotten the “history right”. I met Dr. Saxena at the 88th birthday celebration for Professor Wolfgang Panofsky at Stanford Linear Accelerator Center (SLAC) in April of this year. The conversation between us drifted toward the subject of historical accuracy, and he asked me who I thought had invented the integrated circuit. When I answered ”The usual understanding is that Jack Kilby invented the integrated circuit”, he told me about his upcoming talk about the subject and invited me to attend.

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Jack Kilby won the Nobel Prize in the year 2000 for his role in the invention of the integrated circuit, and many people assume that the ICs now in use are due to Kilby’s invention. At his presentation, however, Saxena presented extensive historical evidence pointing to major roles by other inventors. I would say that Saxena’s main point is that the monolithic IC was not invented by Kilby, but rather by Robert Noyce. Instead, Kilby invented a hybrid IC, a type that is not used commercially.Saxena emphasized the distinction between the monolithic and the hybrid IC, referring in his paper to the former as “. . . the only kind sold from the inception in the IC industry. . . ” Quotations from his paper give very clear voice to the points that he wished to emphasize: “The issues in the inventions of ICs by Kilby, Noyce and the others are intricately entwined technically, chronologically, and legally patent wise . . . the key concepts for the monolithic IC were first documented by Noyce, even though the reduction to practice of his invention was done by others, and it depended crucially on Hoerni’s and Lehovec’s inventions.” “Kilby missed the key concepts of monolithic interconnects and planar technology necessary to fabricate monolithic-IC. The reduction to practice was done by Kilby [himself] using Ge [germanium] mesa technology and wire bonded interconnects dangling above the chip which are not used in monolithic-ICs. Kilby was awarded the Nobel Prize in 2000, and he is generally regarded as the inventor of ICs, implying monolithic ICs, which is not pedantically accurate.” One of the more intriguing ideas presented by Saxena concerns the filing date of one of Kilby’s patents. Kilby claimed a filing date of February 6, 1959. However, when Saxena dealt with the patent officeapplication, he received two contradictory responses: One response indicated a filing date of May 6, 1959, and the other response said, “The product or service you requested cannot be fulfilled because the application . . . does not have an official filing date.” Saxena wrote in his paper, “The above seemingly contradictory responses from the USPTO cannot be explained . . . one fact is clear from the above responses: the official filing date of Kilby’s [application] . . . was not February 6, 1959, as claimed by Kilby . . . Either it was May 06, 1959 . . . or it did not have an official filing date at all. . . ”

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I found Dr. Saxena’s paper fascinating because it gives a detailed example, of great historical importance, of how ideas can be “intricately entwined”. In the case of important ideas, this can lead to distortions of history, both intentional and unintentional. The entire abstract of his paper can be viewed now at http://www.nsti.org/Nanotech2007/WCM2007/#Saxena Jeffrey Marque [email protected]

19. Copy of Marvin J. Moss,49 “Present for the Birth of the Integrated Circuit”, IEEE Life Member Newsletter, p. 4, April, 2007.

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Chapter 12

Award of the Nobel Prize I have already given a brief account of the Nobel Prize awarded to Jack Kilby in Section 6.8 of the Preface and in Section 3.3 of Chapter 1. I have done research using the original Nobel website (www.nobelprize.org) as my source for documents on the Nobel Awards in Physics throughout their entire history of existence. This website is available to anybody in public who wishes to obtain any information on this subject. For details, see Appendix 7. Based on my research, I can explain some of the actions of the Nobel Committee to award the Nobel Prize to Kilby in the way it did, but not several other issues. Consequently they remain still as an unexplained mystery. I must emphasize, however, that the explanations given here are strictly mine, not yet given by Nobel Committee. I shall give the relevant details in this chapter along with the excerpts from my communications recently in 2006 and 2007 with two members of the Nobel Committee who had participated in this momentous award in 2000. For the sake of discretion, respect and professional courtesy, I shall refer to them only as Dr. MNC-1 and Dr. MNC-2. I shall not divulge their names although I have hard copies of their e-mails in my possession. An unbiased, knowledgeable and serious reader, who has read this book up to this point, would have found that I have given facts with proper documents, not hearsay evidence of the IC inventions. My analyses of various contributors have been objective and thorough, and I have given the credits as well as criticism where they are due. In this chapter, the remarks are based primarily on published facts of both Kilby and the Nobel Committee. As I have stated in this book and my paper(s) published recently,12,13 Kilby did make a key contribution to the invention of ICs, but it was only a small part of the complete invention needed. With due 333

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respects for both Kilby and the Nobel Committee, in my opinion several of their actions and decisions are rather inexplicable. I will concede though that a casual reader of this book whose mind is made up and refuses to accept or understand the truth may still harbor an erroneous impression as if Kilby and the Nobel Committee are being assailed. But as I have written before, such is not the case at all in this book.

1. Excerpt from Nobel’s Will The quintessence of Nobel’s Will is that the Nobel Prizes shall be awarded to person(s) irrespective of nationality who, during the preceding year has (have) conferred the greatest benefit on mankind. The following is an excerpt copied from the original Will of Alfred Nobel. “The whole of my remaining realizable estate shall be dealt with in the following way: the capital, invested in safe securities by my executors, shall constitute a fund, the interest on which shall be annually distributed in the form of prizes to those who, during the preceding year, shall have conferred the greatest benefit on mankind. The said interest shall be divided into five equal parts, which shall be apportioned as follows: one part to the person who shall have made the most important discovery or invention within the field of physics; one part to the person who shall have made the most important chemical discovery or improvement; one part to the person who shall have made the most important discovery within the domain of physiology or medicine; one part to the person who shall have produced in the field of literature the most outstanding work in an ideal direction; and one part to the person who shall have done the most or the best work for fraternity between nations, for the abolition or reduction of standing armies and for the holding and promotion of peace congresses. The prizes for physics and chemistry shall be awarded by the Swedish Academy of Sciences; that for physiology or medical works by the Karolinska Institute in Stockholm; that for literature by the Academy in Stockholm, and that for champions of peace by a committee of five persons to be elected by the Norwegian Storting. It is my express wish that in awarding the prizes no consideration be given to the nationality of the candidates, but that the most worthy shall receive the prize, whether he be Scandinavian or not.”

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2. Highlights of the updated Nobel Awards The following are the highlights of the updated Nobel Awards copied from the Nobel website. The original list of the five subjects in which the Nobel Prizes were awarded was “physics, chemistry, physiology or medicine, literature and peace”. A sixth subject, Economics, was added to this list in 1968. “The prizes, as designated in the Will of Alfred Nobel, are in physics, chemistry, physiology or medicine, literature and peace. Only once during these years has a prize been added — a Memorial Prize — the Prize in Economic Sciences in Memory of Alfred Nobel, donated by the Bank of Sweden to celebrate its tercentenary in 1968. The Board of Directors later decided to keep the original five prizes intact and not to permit new additions.” 3. Award of the Nobel Prize for inventing ICs Nobel Prize is not awarded in the field of Engineering. The invention of ICs belongs more to the field of Engineering rather than any other basic field of science such as Physics, Chemistry, etc. Nevertheless the impact of the ICs on almost all the other basic sciences has been so huge in the last few decades that their invention definitely merited a Nobel Award. ICs are indispensable to do almost any kind of standard and advanced work in all the fields included in the original Nobel Award list. The Royal Swedish Academy of Sciences awarded the Nobel Prize7 for Physics in 2000 “for basic work on information and communication technology” to Zhores Alferov, Herbert Kroemer and Jack Kilby. Their names were listed in this order, not alphabetically. Kilby was listed last in this Nobel Prize,7 awarded 1/2 of the prize money, recognized solely for the invention of the ICs, and was cited as “for his part in the invention of the integrated circuit.” Kilby’s invention1,22,34 did not involve any contribution which was fundamental to physics. It had used the technology concepts which had been described earlier by the others (see Chapters 7 and 9). In the specifications of his invention, Kilby did not give the correct procedures for fabricating the devices and

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their electrical isolation. Moreover he missed completely giving the correct procedures to interconnect the devices (rectifying diodes, amplifying and switching transistors, resistors, and capacitors) in the chip, without which the IC is not complete and cannot work to process the electrical signals and information. These facts tell us that this is not a mystery; these were serious omissions by Kilby and not envisioned by Kilby at that time. But it is a mystery how all this important information was ignored and swept aside by the USPTO in granting the patents to Kilby, and by the key technical and patent personnel all over the world, and even by the Nobel Committee who simply accepted Kilby as the inventor of the IC. Also the Nobel citation did not state precisely what was Kilby’s part in the invention of which kind of integrated circuit? Why was it left vague and subject to interpretation and debate? Apparently, the Nobel Committee either construed Kilby’s invention to be a monolithic-IC, or credited him with the Nobel Prize award for his part in inventing only a hybrid-UCIC with mesa devices and wire-bonded interconnects (see Chapters 4 and 7). The other two co-recipients of this Nobel Prize, Alferov and Herbert Kroemer, were listed first in alphabetical order, each were awarded 1/4 of the prize money, and were cited jointly “for developing semiconductor heterostructures used in high-speed- and opto-electronics.” Unlike Kilby’s Nobel Award, the contributions of Alferov and Kroemer did involve contributions to fundamental physics. The winners in a 3-person Nobel Prize award are listed alphabetically most of the time, especially if the monetary part of the award is distributed equally. (For details, see Appendix 7.) However this procedure was not followed in listing Shockley, Bardeen and Brattain in 1956. Obviously, the award to Alferov, Kroemer and Kilby in 2000 was a 3-person Nobel Prize. The alphabetical order was also not followed in listing their names, and Kilby’s name was last in the sequence even though he was given twice the amount than given to each of the other two. Why was Kilby given twice the amount of financial award than to each of the other two co-recipients, unlike the equal amounts given in the Nobel Prize in Physics awarded to Shockley, Bardeen and Brattain for their invention of the transistor earlier in 1956? No explanation has been offered

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so far by the Nobel Committee for the vague and imprecise citation of such an important world renowned Prize, nor for the unequal and the double amount awarded to Kilby. It is generally known that the highly revered group of the Nobel Committee acts as a powerful closed institution which feels strongly that they do not owe any explanation to anyone regarding their choices and decisions. Without casting any aspersions on anybody, respectfully and punctiliously I only wish to state that the manner in which Kilby’s Nobel citation and award had been handled is quite inexplicable. Nevertheless one cannot obliterate the facts as published by the Nobel Committee itself and elsewhere in the literature. They are cast in concrete and therefore stated as such in this book. If Kilby’s invention was construed to be a monolithic-IC which is the only kind sold in the market from the beginning, then apparently the Nobel Committee accepted the monolithic-IC concept stated by Kilby in his patent1 at face value, rather than scrutinize the details of exactly what he had done to reduce it to practice, and what materials and technologies had he specified in the issued patent and the claims. As discussed in detail in Chapter 7, they would have produced only hybrid-UC-IC with mesa devices and wire-bonded interconnects which are not used in monolithicIC. The latter was invented by Bob Noyce.2 The integrated circuits (ICs) manufactured and sold in the market from the very beginning have been and are the monolithic-ICs, not hybrid-UC-ICs with mesa devices and wirebonded interconnects. The filing of the Original Application23 in 1959 and the award of the patents to Kilby1,22,34 in 1964 and 1966 were rife with controversy. Since the Nobel Award was given in 2000, where was the due diligence and scrutiny on the part of the Nobel Committee for all those 36 years before making their decision for this important award? If the Nobel Committee credited Kilby with the Nobel Prize award for his part in inventing only a hybrid-UC-IC with mesa devices and wirebonded interconnects, then an obvious question arises, “Why the other inventors of hybrid-UC-ICs earlier than Kilby were ignored?” Noyce had died in 1990; the Nobel Prizes are not awarded posthumously. So he was not included in the Nobel Prize awarded in 2000, although he was recognized as the co-inventor of the ICs by Kilby in his Nobel Lecture.7 That certainly was a gracious gesture by Kilby. Had Noyce

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not died, he would have been definitely included in this award in my opinion. Perhaps then the entire Nobel Prize award would have been worded and even awarded differently.

4. Excerpts from recent communications by Dr. MNC-1 with me I shall copy below excerpts of communications of one of the members of the Nobel Committee (referred by me here as Dr. MNC-1) with me. I shall quote only the relevant portions of our communications written by Dr. MNC-1 to me as follows: “I think that it is a wonderful idea to publish a paper on the history of ICs. . . . Once again, I strongly support your intention to publish a paper in which you define the monolithic concept unambiguously and give important facts of the invention. . . . Please consider my comments not as criticism but just as friendly remarks.” “You are right when you underline that Kilby did not invent the monolitihic-ICs. But why stressing this point so many times? As you correctly state, Kilby received the Nobel Prize ‘for his part in the invention of the integrated circuit’. We considered this phrasing very carefully. The prize was not given for the invention of monolithic-ICs! I always stress that in my lectures (see attachment). If Noyce would have been still alive in 2000, maybe the phrasing would have been different. Who knows? As a member of the Swedish Academy of Sciences, we are not allowed to give any information on such issues within 50 years.” “Once again, I strongly support your intention to publish a paper in which you define the monolithic concept unambiguously and give important facts of the invention. There are always colleagues who publish incorrect data. Personally, I never care and mention these mistakes preferable in subordinate clauses with references. I would also appreciate if you could mention in your paper the tremendous criticism of the so called experts at that time against the monolithic semiconductor approach. Not earlier than by the late 60s, most engineers had accepted the fact that integrated circuits were here to stay. I still remember several funny stories during

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my time at . . . . This has nothing to do with Kilby personally. Things like these always happen and are most unpleasant. I remind you of the early discussions on LEDs, plasma TV, Si/Ge etc.” It is nice to get agreement from Dr. MNC-1 when he writes “You are right when you underline that Kilby did not invent the monolitihic-ICs.” However, he still did not clarify what was Kilby’s part in the invention of which kind of IC. Since the Nobel Prize was awarded in 2000, and they cannot give out any information for 50 years, i.e., until 2050, I shall be long dead when the Nobel Committee may reveal the truth.

5. Excerpts from recent communications by MNC-2 with me I shall copy below excerpts of communications of another member of the Nobel Committee (referred by me here as Dr. MNC-2) with me. I shall quote only the relevant portions written by Dr. MNC-2. “I was intimately involved in the deliberations with the Nobel Committee in this case — but certainly will not divulge any details. Mark this: the IC has been recognized by the Prize as a tremendous invention — so much, not more. (I was at Stockholm for the bestowal). . . . I really liked Bob Noyce. . . . I tend to agree with your general statement that it was he, who has achieved the true invention of ICs.” So, quid pro quo, and there you are with the attest of one of my key conclusions on who really invented the monolithic-IC; Bob Noyce did.

6. Famous United States Patents The listing of “Famous United States Patents” donated by Professor Homer O. Blair,52 at Pierce Law Center, starts with the very 1st patent issued on July 30, 1790, to Samuel Hopkins on Improved Potash Process. Some of the other people whose patents are listed in this list of “Famous United States Patents”, include a few like Samuel Morse (in 1840), Louis Pasteur (in 1873), Thomas Edison (in 1892), Guglielmo Marconi (in 1897), Henry Ford (in 1901), Lee de Forest (in 1906), Philo Farnsworth (in 1930),

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Albert Einstein (in 1930), Vladimir Zworykin (in 1935), Enrico Fermi (in 1940), John Bardeen and Walter Brattain (in 1950), William Shockley (in 1951), Robert Noyce (in 1961), J. B. Gunn (in 1968), etc. Most of the inventions documented in this list revolutionized technology developments, and changed mankind forever. However, the list does not include Jack Kilby, whose patent was awarded in 1964. Apparently the criteria used by the Nobel Prize Award Committee and by Professor Blair at the Pierce Law Center do not jibe with each other. This is public knowledge and an interesting fact on record. Pierce Law Center is no Nobel Committee or vice versa depending on your viewpoint and basis; nevertheless it consists of distinguished and highly qualified patent law professors and experts in the USA which the Swedish Nobel Committee does not.

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Chapter 13

Moore’s Law In my opinion, no book on any aspect of ICs should be without at least a brief discussion of Moore’s Law.45,46 For a recent comprehensive account of Moore’s Law, see Brock41 and the articles by Moore and the others therein, and a brief discussion in Reference 20. The invention of ICs, which is the main topic of this book, of course provided the seed from which many trees of VLSICs grew eventually mushrooming into a giant forest bearing fruits of innumerable varieties of ULSICs. Even though hundreds of thousands of scientists and engineers all over the world contributed to the fantastic success of the IC industry, Gordon Moore’s insight into the technologies and business played a pivotal role to guide this. He enunciated his eponymous law which came to be known as the Moore’s Law. At the outset, it is important to realize that Moore’s Law applies only to the 2D-Si-ULSICs being sold still in the entire microelectronics industry, since the beginning about 50 years ago when the ICs were invented. This important fact has either been ignored or glossed over in the entire industry until my paper20 was published. As explained earlier briefly in Chapter 3, only electrical functions can be performed in these 2D-Si-ULSICs. They have all the devices laid out in the 2-dimensions of the Si wafer, and the 3rd-dimension is used primarily for the multilevel interconnects. Some thinfilm devices may be fabricated in levels above the main level of the Si wafer. As discussed by Moore in Chapters 4–7 of Reference 41, his eponymous law predicts the behavior of several parameters which are critical for the IC technologies and their evolution with time. It is not based on any fundamental laws of science; it is based primarily on the empirical behavior of a few parameters and the economics of IC manufacturing. Moore’s 341

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key insight and business acumen was to observe the behavior of these parameters of the then existing data of manufacturing various chips. Lo and behold, Moore found that a semi-log plot of these parameters versus time gave respective straight lines. To quote from Moore’s Chapter 741 that he wrote in the book by Brock,41 “Over time, the term (Moore’s Law) was used much more broadly, referring to almost any phenomenon related to the semiconductor industry that when plotted on semilog graph paper approximates a straight line.” This empirical correlation of the existing data provided the key guidance for the subsequent development of the technologies, materials and equipment of IC manufacturing and forecast their behavior in the future. This sums up essentially the birth, use, and the key role of Moore’s Law in the entire microelectronics industry. It sounds quite simple, but it has been a key beacon for almost all aspects of the current multi-hundred-billion dollar chip manufacturing industry, e.g., chips, processing and test equipment. Nevertheless to repeat a key fact which has been ignored in the entire industry, Moore’s Law applies only to these present 2D-ULSICs in which only the electrical signals are used and processed for circuit functions on a chip.20 Without going into the various intricacies of Moore’s Law, one of the simplest ways to express it is that the number of devices per chip doubles approximately every 18 months. For this to become a reality the minimum dimensions of the devices have to decrease and the chip sizes have to increase with time. A semi-log plot of these parameters versus time gives respective approximate straight lines. Thus their variation in future can almost be predicted due to an approximate linear behavior, which can easily be extrapolated as a function of time. Further to amortize the manufacturing cost of the chips per wafer in batch processing, the wafer sizes also have to become larger with time. All of this is borne to be true as evidenced by the successful progression and the fantastic growth of the microelectronics industry over the past 30 years. This is the essence of Moore’s Law. Figure 13.1 is a plot of Moore’s Law. It shows a semi-log plot of transistors per die (chip) versus time from the early data of 1965 onwards. The linear behavior according to Moore’s Law is followed in various segments whose slope is influenced by the associated technologies needed for the chips of various types.

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Fig. 13.1. A semi-log plot of transistors per die (chip) versus time for the early data of 1965 until the recent years and beyond. The linear behavior according to Moore’s Law is followed in various segments which were influenced by the associated technologies used for the chips.

To expand a little on this eponymous law, Moore was the first to observe the trend of the increase of number of devices per chip with time, which was also followed by the increase of die (i.e., chip) area, and the decrease of average minimum dimension of the device geometries. When these parameters were plotted by Moore45,58 as semi-log vs. time, they followed a linear behavior approximately. Since then, some minor corrections have been made due to the recent data. However, such linear behavior has been followed by the chip industry, and is known as the Moore’s Law. It has predicted remarkably well the evolution and the growth of the technologies and products in the entire multi-hundred-billion dollar monolithic Si IC industry for the past three decades. To give the readers a feel for how fast the industry has grown, I shall give the total dollar volume of all the Si products including the ICs in the world market (without discussing the details). The data is only for all

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Table 13.1. Total world market of all Si products including the ICs. Year

Dollar volume (Billions of $)

1970 1990 2000 2007

2.6 49.5 200 250

2D-Si-ULSICs. To re-emphasize, Moore’s Law is valid for only these types of ICs available currently. The above data do not include any numbers for the 3D-ICs and UPICs, because they have not yet been commercialized. I am quite hopeful that they will be available commercially in the next few years. Not only they will extend the validity20,48 of Moore’s Law, but the growth of the total market will be even higher than given above so far. This is because a new class of IC products will then be available, which will further enhance their applications in a variety of systems heretofore not possible by the present 2D-Si-ULSICs. Moore’s predictions of the growth and progress of the microelectronics industry have been met very well indeed. The technologies from various scientific and engineering disciplines have been harnessed to achieve the submicron features in ULSICs (Ultra Large Scale ICs) in ultra clean large volume manufacturing with good yields of complex chips. Also, to amortize the manufacturing cost per wafer for the huge investments needed for a modern fab (i.e., fabrication facility for manufacturing), the wafer sizes have grown now to 300 mm diameter, and larger size wafers such as 450 mm are being considered. The economics of constructing a fab with all the equipment needed for ULSIC manufacturing, as well as the fundamental limits of the materials and processes, appear to put a roadblock to the continued validity and success of Moore’s Law. Moore45 has reviewed several of these factors, and predicted that his law, which has guided the destiny of the entire industry so far, is now approaching the inevitable limits of its validity. Some observations on the current status and possible factors for the limitations of Moore’s Law are summarized as follows. A few key items

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which have been ignored in the literature have been repeated below to emphasize their importance. 1. All the ICs sold in the market are 2D-Si-ULSICs. This means that the various devices needed for the ICs are laid out in the 2-dimension on a bulk single crystal Si wafer. The 3rd dimension is used only for interconnecting these devices by using multilevel metallizations and inter-layer dielectrics (ILDs). Moore’s Law applies only to these 2D-Si-ULSICs. 2. These 2D-Si-ULSICs use only electrical signals to perform the desired functions in a chip. Thus, Moore’s Law applies only to 2D-Si-ULSICs performing electrical functions on a monolithic Si chip. 3. The key role of multilevel interconnects to enable the validity of Moore’s Law so far, has not been given its due recognition in the literature. Had it not been for the various materials, processes, and equipment technologies which were developed for the multilevel interconnects with high yields, Moore’s Law would have ceased to be valid several years ago. 4. One of the key features of Moore’s Law is that it predicts the rate of growth of the total number of devices per chip with time. This requires, and it also forecasts, the rate of decrease of minimum geometries, or critical dimensions (CDs), of the devices and interconnects. Consequently, increasing the number of electronic functions per chip requires device and interconnect scaling, and increasing the number of multilevel interconnects. In addition, photolithography, alignment of various masks, etching patterns, planarization and zero-defect manufacturing are all becoming more and more critical, and they are absolutely essential. These approaches are necessary if we continue along the current technology evolution path. However, they are becoming very expensive, and cause reliability problems, because of the limitations of the materials and the manufacturing technologies below certain minimum geometries. Thus, it is becoming harder to maintain the historical trends of the yields and profitability of the more advanced ULSICs. 5. It is well known that there is a limit of sizes and dimensions below which materials and technologies will cease to behave as they do in larger dimensions. As an example, thin films of SiO2 behave differently than bulk quartz. Now their film thicknesses are down to a few Angstroms, but it is

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unlikely that they will be suitable in the limit of atomic dimensions. While no definite limit has been established yet, it appears that the validity of Moore’s Law will cease at CDs smaller than about 0.018 µm (or 18 nm). This means that the rate of increase of the number of devices per chip in a 2DSi-ULSIC, will not follow Moore’s Law for CDs 8. (Continued)

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{cf: “Proceedings of the First International Symposium on BI/CMOS”, Vol. 89–8, pp. 1–133 Electrochemical Society, NJ. (1989)}; my contributions have been acknowledged in the video tape on Intel Corporation’s “Pentium” issued by Stanford University Video Communications. Taught the first device physics course on Ion Implantation; range-energy curves; VT control; Si3 N4 , SiO2 , SiC formation, GaN; obtained patent on etch-less patterning; MeV implantation use; RBS; invited papers in Brussels and Strasbourg. {cf: J. Matls. Sc. and Eng. B2, 1–13 (1989)}. Keynote addresses at the 1st and 3rd VMIC, and at the 1st International Workshop on W and other refractory metals; contact metallurgy; ρc ; electromigration; stress voiding; effect of passivation; jn ; planarization; dielectrics; silicides/polycides; salicides; refractory metals; Al and

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Then

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No.

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Appendix 1.

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SiO2

Year(s)

1977–

Now

Contributions

Status in 2008

More basic work needed on adhesion of films; important in ULSI and packaging.

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(Continued)

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alloys; Cu metallization technologies used currently; established and was the founding Director of SEMATECH Center of Excellence in Multilevel Metallizations; co-authored chapter in handbook of ICs. Gave the first measurement and characterization of the chemical state of Phosphorus in SiO2 {Proceedings of the International Topical Conference, Yorktown Heights, NY, pp. 195–199, March 22–24 (1978)}; kinetics of the change of its chemical state on annealing and processing {cf: J. Electrochem. Soc. 132, 932 (1985)}; effect on thermal reflow; thin-film thermal conductivity; applied it for quantitative characterization of adhesion of films in ULSI. {cf: First International Congress on Adhesion Science and Technology; Mittal Festschrifft, eds. W. J. van Ooij and H. R. Anderson, Jr., VSP International Science, Utrecht, The Netherlands, ISBN 90-6764-291-6, pp. 137–146 (1998)}.

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Field/Subject

Then

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No.

(Continued)

Appendix 1. Developments in Physics, Microelectronics

Appendix 1.

FA

Year(s)

15.

Medical Diagnostics

1973–74

16.

Optical Detectors

1979

17.

Measurement Science Lithography and Dry Etch

1979

18.

1969–

Status in 2008

Company president and CEO. Turned the Most important for fiber optic company around, and got it ready to go communications; now a reality in public. Won against The Teamsters telephone, satellite; medical, defense, Union. etc.; multi-billion dollar industry. Developed a new quantitative technique to Hundreds of millions of dollars have been characterize cytologic specimens; spent to have a quantitative technique demonstrated feasibility to diagnose and to screen and diagnose cancer routinely screen Pap smears for cancer in patients in Pap smears, but no such technique quantitatively (as compared to the has come to fruition so far. My subjective/qualitative evaluations by quantitative medical diagnostic conventional pathology); also used in-vitro technique appears quite promising and cells known to be normal and cancerous has applications to diagnose other type from the National Cancer Research of cancers also, but it needs further Institute, and showed unambiguous and development. quantitative characterization with my new technique; it has applications in various other applications in cytology and medical diagnostics. Chapter in handbook. Good progress; used routinely now in fiber optic communications. Keynote address. Essential for ULSIC manufacturing. Editor of fine line lithography issue of Solid State Technology, 1980; obtained patents; wrote chapter on dry etch.

Essential for ULSIC manufacturing.

(Continued)

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1972

Contributions

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Fiber Optics

Now

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No.

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Appendix 1.

FA

Field/Subject

Year(s)

Then

Now

Contributions

Status in 2008

1980–

“All you wanted to know about Al metallizations but were afraid to ask”; reliability studies.

20.

Silicides and Salicides Refractory Metals

1970–

Dielectrics in ULSI Recording: Audio and Video

1980–

Earliest review talk on silicides in I.C. technology; TiSi2 by RTA. Use of Hf in Schottky; W use in I.C. technology; my predictions of the use of W in manufacturing of ULSICs became a reality; keynote speaker of 1st International Conference. Inorganic and organic dielectrics.

21.

22. 23.

1971–

1981–

24.

Planarization

1983–

25.

GaAs/Si

1987–

26.

UPICs and 3D-ICs

1987–

Was awarded a key U.S. Patent # 4,280,148 on July 21, 1981, in the shortest time by the US Patent & Trademark Office. Review paper; gave key methods and development of technologies. Invited talk on process issues.

W technology met my predictions; used now in production.

Used in ULSI. This recording field has grown now to billions of dollars. Indispensable in ULSI production. Feasibility demonstrated; important for UPICs. Feasibility shown; huge potential of new multi-billion dollar business.

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391

Introduced Ultra Performance ICs (UPICs), which include 3D-ICs. UPICs are the ultimate in the monolithic ICs needed by mankind, and they allow integration levels beyond ULSICs, thus extending the validity of Moore’s Law. In addition, UPICs will allow both electronic and

Still a basic metallization technology in ULSICs, although Cu-based multilevel metallizations are used now in advanced ULSICs. Used in production.

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Aluminum Technology

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Appendix 1.

FA

28.

30.

1987–

1988–

1991–

1995–

Contributions

Status in 2008

optical functions monolithically on a chip, which has not been possible so far. Awarded a few key patents: #5,792,270 (Aug. 11, 1998); #6,103,019 (Aug. 15, 2000); #6,110,278 (Aug. 29, 2000); #6,392,253 (May 21, 2002). Invited talks in 1987 and 1990; key roles in SEMATECH; Member of Executive Committee; Director of SEMATECH Center of Excellence. Invited talk in 1988.

Promising new applications.

Important in today’s global economy.

Important impact on the reliability of the ICs and many other fields.

(Continued)

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Course development and teaching; Advanced Microelectronics Manufacturing; equipment technologies. Gave the first and only invited talk on the role of adhesion science and technology in microelectronics at the 1st International Congress on Adhesion Science and Technology in 1995; (see Section 13 above); proposed new quantitative diagnostic technique.

Crucial for microelectronics in the USA.

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29.

Cooperative Support Strategies in the USA High Tc Superconductors in ULSI Advanced Microelectronics Manufacturing Adhesion Science and Technology

Year(s)

Now

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Field/Subject

Then


No.

(Continued)

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392

Appendix 1.

FA

31.

Education, Research and Manufacturing

Year(s) 1987–

Status in 2008

Emeritus Professor (1996-for life.) Director of Center for Integrated Electronics (1987–89); established microelectronic fabrication facility for education and research; Professor (1987–) gave invited papers/lectures internationally (Belgium, Brazil, China, Czech Republic, England, France, Germany, India, Italy, Japan, Netherlands, Romania, and USA); Consulting Editor of a series of books on and consultant in Microelectronics Manufacturing; awarded four fundamental U.S. Patents recently on the next generation ICs beyond ULSI/GSI which will extend the validity of Moore’s Law. (see Section no. 26)

Important in today’s global economy. A graduate fellowship “Veera and Arjun Saxena Fellowship in Microelectronics” has been established at Rensselaer Polytechnic Institute because of his teaching and their substantial donation. This Fellowship is awarded every year to outstanding PhD students in advanced research in microelectronics. It is a real pleasure to receive letters from several students who have already benefited from this Fellowship. We will not be around sooner or later, but this Fellowship will live forever.

393

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Appendix 1.

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Appendix 2

Saxena Documents Regarding IC Invention, Discussions and Patents in Devices, ULSICs and Beyond

In the main text of this book, I have given all the relevant documents available for the invention of ICs by Kilby, Noyce and several others, and analyzed them thoroughly. Regarding the concepts of ICs given by me earlier than Kilby and Noyce that I shall write in this Appendix 2, I have followed the sage advice given to me by Gordon Moore,55 “On the part relating to your early insight you should do whatever you think is appropriate. . . . I think that your job is to distinguish your insight from what others saw as the potential.” My objective is to do just that when I give my concepts of ICs in this Appendix. I think that it is appropriate to at least document them for the sake of completeness of the historical record without trying to claim any credit. I have also given the relevant comparative information of Kilby and Noyce to distinguish my insight from theirs. Prior to giving the documents of my concepts of the IC invention, I shall first give a comparative summary of Kilby, Noyce and my contributions in Table App. 2.1. At the outset, it addresses the job assigned by Moore to distinguish my insight from what others saw as the potential. This table will also provide a background for the relevance and significance of my original documents to the invention of ICs. Their list is given in Section 2, and full copies of these original documents are given in the subsequent Sections 9–12 of this appendix. They are reviewed and discussed briefly in Sections 3–8 following essentially the sequence similar to that used for Kilby and Noyce in Chapters 7 and 8 respectively. 395

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Table App. 2.1.

Summary of comparisons of Kilby, Noyce and Saxena’s IC inventions

Important facts of IC invention

Kilby

Noyce

Saxena

1. When were the IC concepts given? 2. All devices must be fabricated in the same substrate (e.g., Ge, Si)? 3. Planar technology must be used to fabricate the above devices? 4. All devices must be electrically separated from one another by p–n junction isolations? 5. All devices must be connected by planar interconnections adherent to oxide surface? 6. What was invented?

1958/1959

1959

1954

Yes

Yes

Yes

No (mesa; Ge)

Yes (Hoerni’s8 planar; Si)

N/A (not known in 1954; Hoerni8 invented it in 1959)

No (mesa)

Yes (Lehovec’s9 p–n junction)

N/A (not known in 1954; Lehovec9 invented it in 1959 which became public knowledge in 1962)

No (wire bonds; Au)

Yes (Al)

Yes (ancient method of painted/stenciled metal lines)

Hybrid-IC

Monolithic-IC

7. Published a journal paper prior to disclosing the IC concepts? 8. How were the concepts disclosed?

No

No

Concepts given for both hybrid-IC and monolithic-IC Yes (1953; see Section 9)

Handwritten in notebook in 1958

Handwritten in notebook; 1959

9. Original documents available?

Yes

Yes

Handwritten on a piece of paper for transistors; described IC concepts in my 1954 lecture (see Section 10) Yes (see Section 11)

(Continued)

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Appendix 2. Saxena Documents Regarding IC Invention

Table App. 2.1. Important facts of IC invention

(Continued)

Kilby

Noyce

Saxena

10. Were they witnessed?

No

No

11. Test circuit defined? 12. Reduction to practice?

Yes

No

No (But my IC concepts were confirmed in writing by 5 attendees of my 1954 lecture in 2005; see Section 12) Yes (see Section 9)

Yes (Ge mesa; Au wire bonded; hybrid-IC)

No (Facilities and devices were not available in 1954)

13. Patent filed?

Yes (claimed to be filed on Feb. 6, 1959; USPTO records show May 6, 1959, or no filing date at all) Yes (June 23, 1964)

No (Not by Noyce, but by others using planar Si technology; monolithic-IC) Yes (Filing date July 30, 1959; note that it was about 6 mos. after Kilby)

Yes (April 25, 1961; note that it was about 3 years before Kilby) Yes (4 patents)

N/A

14. Patent issued?

15. Contributions to monolithic-IC technologies?

16. Contributions to advanced ULSICs, 3D-ICs, and UPICs?

No (Continued to regard the monolithic concept as controversial even in 1998; see Ref. 19) No

No (But co-founded Intel where advanced ULSIC technologies are developed and manufactured in large volume)

No (Not aware of procedures for patents in 1954)

Yes (16 patents; see Table App. 2.2)

Yes (3 patents; see Table App. 2.2)

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1. Cumulative summary of comparisons of Kilby, Noyce and Saxena’s IC inventions A combined summary of several facts relevant to the invention of ICs was given in Table 15.1 for Kilby, Noyce, Dummer and Saxena. However, a more detailed cumulative summary of the same is given in Table App. 2.1 for Kilby, Noyce and Saxena only. It compares the “Important Facts of IC Invention” between each on a one-to-one correspondence basis. As it is evident from the published records, neither Dummer nor Stewart or Johnson had pursued the development of ICs after disclosing their versions of the original concepts. Therefore, they have not been included in this table in which I have distinguished my insight from Kilby and Noyce. In their respective IC inventions as shown in Table App. 2.1 above, and in Table 1.1 in Chapter 1, Kilby met only 1 out of 4 criteria, whereas Noyce met all the 4 criteria. Therefore, Noyce’s invention was for the monolithicIC, but Kilby’s invention was not; it was only for hybrid-IC. Figure 1.1 in Chapter 1 shows Kilby’s reduction to practice of his invention of IC. Wire bonded interconnects can be seen clearly going from one device to another. Figure 1.2 in Chapter 1 shows the reduction to practice of Noyce’s invention of IC. Planar interconnects can be seen clearly between the devices of the monolithic-IC. Saxena met 2 and 2 were N/A, out of 4 criteria in 1954, which was 5 years earlier than both Kilby and Noyce. The 2 N/A criteria were planar and isolation technologies which were not known in 1954 even in the USA until 1959. As documented in the Table App. 2.1 above, my concepts for the ICs predate Kilby’s and Noyce’s. The credibility of my documents has some similarities with those of Kilby and Noyce. The reprint of my paper in a journal is no match for the US patents filed by Kilby and Noyce. However, the handwritten but un-witnessed notes are in the same category as those of Kilby and Noyce, because theirs were also handwritten and un-witnessed. The official announcement and the letters from 5 well qualified attendees of my 1954 lecture attest to what I had said. Unfortunately the details of my concepts for ICs were not documented when I had given them in 1954. I could not file for a patent in 1954 because I had no knowledge of doing so then.

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Appendix 2. Saxena Documents Regarding IC Invention Section 2. Saxena’s original documents of IC invention

399

It is known from publications that Dummer4 also did not file and obtain a patent for his disclosure even though he had lived in England and given his paper in USA where the procedures for patents were known. However, I did receive legally recognized US patents in devices, USLICs and beyond later as listed in Table 5.2 in Chapter 5, and also in Table App. 2.2 below. Therefore, because of the weakness in the documentation of the details of the concept for ICs that I had given in 1954, I have taken myself out from the list with the others given in Section 13 of Chapter 1. This makes it clear that I am not trying to claim any credit for inventing ICs earlier than the others. However I am giving all the available documents and what I had disclosed in my lecture in 1954 after publishing my paper in 1953, for the sake of historical record in this Appendix 2. 2. Saxena’s original documents of IC invention and patents in devices, ULSICs and beyond The list of my original documents of IC invention is as follows: 2.1. Reprint of my 1953 paper, “A Modification of the Model 50 Pulse Generator”. 2.2. Copy of the announcement notice of my lecture on “Transistors” on January 14, 1954. 2.3. Copy of my original handwritten notes. 2.4. Confirmation by five physicists of the IC concepts given by me in 1954. Full copies of these original documents are given in the Sections 9–12 of this appendix. Even though their list is given above, they are referred to and my patents in devices, ULSICs and beyond are listed in Table App. 2.2 below. The patents and earlier unpatented but documented work are listed chronologically with patent filing dates and public disclosures as publications. This procedure is similar to that I have followed for Kilby, Noyce and the other contributors (see Chapters 5 and 9). To emphasize, listing patent filing dates and public disclosures chronologically is important because it documents the origin and sequence of conception of an invention,

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Documents and patents of Saxena on and beyond the invention of ICs Patent#

•Saxena (ICs)

• • • • • • • • • • • •

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Table App. 2.2.

• • • •

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Saxena Saxena Saxena Saxena36 (Interconnect) Saxena Saxena Saxena Saxena Saxena Saxena Saxena Saxena Saxena Saxena Saxena37 (3D-ICs & UPICs) Saxena38 (3D-ICs & UPICs)

Filing date

Issue date

Notes

Gave concepts of ICs in 1953–54, but patent not filed. Reprint of 1953 paper; original handwritten notes and announcement of the lecture given on Jan. 14, 1954. (See Sections 9–11.) Documentation of Saxena’s comments in 1954 by several qualified personnel who had attended his lecture. (See section 12.) 3,450,957 Jan. 10, 1967 Jun. 17, 1969 1 co-inventor 3,450,958 Jan. 10, 1967 Jun. 17, 1969 ----------3,599,323 Nov. 25, 1968 Aug. 17, 1971 - - - - - - - - - - 3,687,722 Mar. 10, 1971 Aug. 29, 1972 - - - - - - - - - - 3,694,719 3,700,979 4,056,642 4,057,460 4,243,865 4,436,582 5,212,118 5,472,508 5,792,270 6,103,019 6,110,278

Nov. 27, 1970 Apr. 7, 1971 May 14, 1976 Nov. 22, 1976 May 14, 1976 Oct. 28, 1980 Aug. 9, 1991 Jan. 14, 1993 Oct. 21, 1993 Feb. 18, 1998 Aug. 10, 1998

Sept. 26, 1972 Oct. 24, 1972 Nov. 1, 1977 Nov. 8, 1977 Jan. 6, 1981 Mar. 13, 1984 May 18, 1993 Dec. 5, 1995 Aug. 11, 1998 Aug. 15, 2000 Aug. 29, 2000

6,392,253

Aug. 6, 1999

May 21, 2002

--------------------1 co-inventor 1 co-inventor ------------------------------------------------------------Next generation technologies Next generation ICs; extends Moore’s Law.

which is not reflected by the issue dates of the patents. The process in between the filing and the issue dates of the patent, as well as what each inventor did beyond his respective invention to advance its technology to what it is today, are also important to acknowledge and critique each contribution. 3. What were Saxena’s concepts of miniaturization in his 1954 lecture? What was invented? My lecture on January 14, 1954, was on “Transistors”. I had described the physics and technology of semiconductor (Ge; Si) transistors and diodes, as much as it was known until then. I had drawn the energy band

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Appendix 2. Saxena Documents Regarding IC Invention Section 3. What were Saxena’s concepts of miniaturization in his 1954 lecture?

401

diagrams and cross sectional structures of these devices, and explained their electrical performance during my lecture. No photographs were taken of these drawings. However, I did state that the semiconductor transistors and diodes would replace the vacuum tubes (as documented in my handwritten notes; see Section 11) in the future electronic circuits, and would enable their miniaturization. A few key reasons, some of them documented in the original notes of 1954, given by me for the miniaturization to occur were because the transistors had several advantages over the vacuum tubes: consumed less power, generated almost no heat, more reliable, longer life, smaller in size, enable miniaturization and cheaper to manufacture. Consequently, more complex electronic circuits with larger number of devices, and superior performance, could be fabricated in miniaturized packages which would also make them more portable. Further, I had specified that these devices could be fabricated singly or collectively on a single piece of semiconductor (Ge or Si). Such a single or more than one piece of the semiconductor with the devices could be mounted or cemented to an insulating substrate (e.g., glass, ceramic, high resistivity semiconductor, etc.), and the devices could be connected together by wire-bonding or painted metal lines or silk-screening through stencils to construct the circuit. I had shown to the audience the actual completed chassis containing the entire circuit built by me in 1953 with the vacuum tubes of the Model 50 Pulse Generator. Since I had improved its design, my colleague (late) T. N. Dave and I had co-authored and published it in 1953; reprint of the original paper is given in Section 9. I had used this circuit as an example for my miniaturization concept. The physical size of this chassis was about 12 inches × 10 inches. As illustrated in the circuit diagram of the paper, it had 4 vacuum tubes mounted in their sockets, and the various resistors and capacitors were wired according to the circuit design. When I had stated in my lecture that, the entire circuit could be miniaturized by using the solid state devices to a size which could be at least 100 to 1000 times smaller than the present chassis, the audience appeared shocked and reacted with skepticism. I had concluded my lecture by re-assuring them that such miniaturization was not fiction, but could become a reality in the not too distant future. My lecture was not recorded in 1954, so there is no official

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documentation to prove what I had said then. The only “documentation” I have now are the letters from 5 attendees of my 1954 lecture, who wrote them recently in 2005 based on their own respective individual recollections of what I had said 51 years earlier in the lecture. Unbeknownst to me at that time in 1954, the above description of my concepts to miniaturize electronic circuits was inclusive of the later inventions of Kilby’s in 1958 and of Noyce’s in 1959, both of whom had filed their respective patents in 1959. As discussed in Chapter 7, Kilby had used Ge mesa transistors, glued the Ge pieces to a glass slide, and had used wire-bonding to interconnect the transistors, resistors and capacitors. These procedures are not used for monolithic-ICs. Nevertheless, Kilby was credited as being the inventor of the IC (purported also to include monolithic-IC although this was not stated explicitly by the Nobel Committee), and he was awarded the Nobel Prize in Physics in 2000 along with Alferov and Kroemer (see Chapter 12). Noyce had written his concepts for monolithic-IC in his notebook, they were not witnessed by anyone else, and he also did not reduce his concepts to practice himself. The credibility of the evidence of one sheet of my original handwritten notes, though in a way similar to Noyce’s and Kilby’s handwritten and unwitnessed entries, is weaker than their documents given in Chapters 5, 7 and 8. The concepts to miniaturize electronic circuits were only described verbally by me; they were not recorded or documented by filing for patents. The procedures for filing patents and/or documenting otherwise were not even known to me in 1954. The answer to the question “What was invented?” is as follows. As explained in Chapter 7, Kilby’s invention1 was a hybrid-IC, not a monolithic-IC. To characterize it even more accurately, Kilby’s invention was a hybrid-UC-IC. My concept for the miniaturization of electronic circuits as described above was for a hybrid-UC-IC as well as a monolithicIC. Similar to the expression Integrated Circuit (IC), the concept and expression of monolithic-IC were also not known in 1954. However, I could envision that these devices could be fabricated singly or collectively on a single piece of semiconductor (Ge or Si), and that such a structure would be all in one block of semiconductor, i.e., monolithic. I had also anticipated that the devices connected together by wire-bonding could be done, which would have given as we know now a hybrid-UC-ICs. This would have

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Appendix 2. Saxena Documents Regarding IC Invention Section 4. The issue of reduction to practice

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been then similar to what Kilby1,23 had demonstrated unbeknownst to me 4 years after I had described my concepts. In addition, I had also suggested that painted metal lines or silk-screening through stencils could be used to connect the devices which would have given a monolithic-IC. This procedure had been in prevalent use for more than 100 years in China, India, Japan, and a few other countries in Asia when “Gold Ink adherent to paper” was used to write manuscripts and in paintings. Kilby1 had stated in his patent that “. . . various circuit elements including diodes, transistors, and resistors all be formed within a single block of semiconductor material, thereby eliminating the necessity for separate fabrication of the semiconductor devices and the interconnections as mentioned above”. This statement was similar and limited to the concepts given earlier by Dummer.4 As discussed earlier in Chapter 7, Kilby’s basic concept as stated was only partly consistent in a small way with monolithic-ICs. He missed several key items in his disclosure, the most important being that the devices had to be connected also by monolithic interconnects adherent to the insulator layers, and that the devices themselves must be fabricated by planar technology not by mesa technology. Kilby did not even suggest the correct procedures to accomplish what he had stated. The reduction to practice, and the materials and technologies specified by Kilby in his patent1 and in the original application23 to fabricate the devices and interconnects were not consistent with monolithic-ICs. They produced only hybrid-UC-ICs. The answer to the question “What was invented?” in 1954 is, that I had described both my concepts for the miniaturization of electronic circuit as a hybrid-UC-IC, which was similar to Kilby’s invention in 1958/59, and also as a monolithicIC which was similar to Noyce’s invention in 1959.

4. The issue of reduction to practice; similarities to Kilby’s and Noyce’s I had described my concepts in 1953–54 to miniaturize the circuit of Model 50 pulse generator by using the solid state devices in place of vacuum tubes. Using the packaged solid state transistors, diodes and passive devices, would have resulted in a miniaturized hybrid-PC-IC. Using the unpackaged active and passive solid state devices, all fabricated in one

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block of semiconductor and wire-bonded to interconnect them, would have resulted in a miniaturized hybrid-UC-IC a la Kilby. When “painted metal lines or silk-screening through stencils” type of interconnects were used, this would have resulted in monolithic-ICs a la Noyce. While the reduction to practice could not be done by me in 1954, it had some similarities to Kilby’s and Noyce’s accomplishments. I had suggested wire-bonding as one of the options to interconnect the devices, and Kilby 1 had used the same method in 1958 to demonstrate his concept as a hybridUC-IC. Kilby’s circuits were simpler than my pulse generator. Noyce did not reduce his concepts to practice. It was done by others using evaporation of Al, photolithography and etching in 1959. They can be defined as an advanced version of “painted metal lines or silk-screening through stencils” suggested by me 5 years earlier in 1954 as another option to interconnect the devices. However, the transistors, diodes, resistors and capacitors, all fabricated in one or more than one block of semiconductor to miniaturize the circuit, were not available to me then. Therefore I could not “reduce to practice” my concepts for the ICs. I could only describe them in 1954 in my talk to a large audience including several “witnesses” (professors and students). This was in a way similar also to Noyce who did not reduce his concepts to practice, and had only described them as handwritten notes which were also “not witnessed”.

5. Choice of semiconductor I had specified that Si and/or Ge could be used for the devices.

6. Fabrication of devices for the ICs I had specified that the devices could be fabricated singly or collectively within or on the same semiconductor substrate. The substrate could then be mounted on a suitable substrate like ceramic, glass or high resistivity semiconductor. The word “monolithic” was not known and consequently not used by me in 1953/54. However, its concept was anticipated by me when I had stated, “. . . . devices . . . . fabricated singly or collectively within or on the same semiconductor substrate” briefly in my talk in 1954. Even in the USA, the word “monolithic” was not known in 1954.

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7. Interconnects Like everybody else in the world, I was unaware of the planar technology in 1953–54. It was invented much later in 1959 by Hoerni8 at Fairchild Semiconductor; although Hoerni had combined the important work done by several others before him and claimed his planar invention in two patents. I had specified in my concepts of miniaturization that the devices could be interconnected by alloying leads or wire-bonding, which was earlier than but similar to what Kilby1 had done independently a few years later in 1958, and described in Kilby’s23 Application Serial No. 791,602. I had also suggested that techniques such as painted metal lines or silk-screening through stencils instead of wire-bonding could be used also to connect the devices. The former would have given a hybrid-UC-IC and the latter a monolithic-IC.

8. What did Saxena contribute toward the invention of ICs and beyond? In 1953–54 when I had given my concepts of miniaturization of electronic circuits leading to ICs, I was not aware, and had no knowledge then of documenting my key ideas in notebooks, having them witnessed, and filing for patents. Nobody in my university even knew about transistors, what to say about seeing and using them. I was only 21–22 years old then. Noyce and Kilby were about 32 and 36 yrs old respectively when they had invented the ICs in 1959. Of course they had lived in the USA, had access to transistors, and had experience in this field. I had no access to transistors, and had no experience in solid state devices and technology then. I had only my insight and extrapolation from my knowledge of electronics and physics. I feel quite fortunate to have given the concepts of miniaturization of electronic circuits in 1953–54, independent of Kilby and Noyce, which led to the ICs. Thereafter, I also obtained several patents in the conventional and the next generation ICs (see Table App. 2.2 above), as well as published and made contributions to several other fields of physics, technology and advanced education (see Appendix 1). Obviously if I had access in 1953–54 to the transistors, diodes and a suitable lab, I would have surely used them and attempted to build the Model 50 Pulse Generator at least as

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a hybrid-UC-IC, and demonstrated the feasibility of my concepts similar to what Kilby had done later in 1958–59. On a relative basis, fabricating it as a monolithic-IC at that time would have been far more difficult than the former. This is particularly true because a lab with the necessary facilities for such fabrication was not available to me at all in 1954. To summarize, I had described my concepts in 1953–54 to miniaturize electronic circuits which led independently to the monolithic-ICs, and beyond to ULSICs, 3D-ICs and UPICs.37,38 My description of the IC concepts in my talk to several “witnesses” (professors and students), was in a way similar to Noyce. He also did not reduce his concepts to practice, and described them only as handwritten notes which were “not witnessed”. Several attendees (“witnesses”) of my lecture in 1954 (two of whom later became Professors and Head of the Physics Department at the university), including one of my early professors, who had even taught me courses in electronics in 1950–52, have documented most of my comments of 1954 recently in 2005 based on their independent recollections (see Section 12). Finally to conclude writing this Appendix 2, I wish to emphasize that my aim has not been to equate my accomplishments in any manner with those of Kilby and Noyce, and a few others. As I have stated in the very beginning of Preface, “The main reason I am writing this book is to get history right and set the records straight of the invention of integrated circuits (ICs).” I believe that I have done that by giving credits and critical comments where they are due based on objective analyses of the documented facts. However, for the sake of completeness of the historical record following Gordon Moore’s sage advice,55 I have also given my contributions in this Appendix 2. Before giving the various documents related to my concepts of IC invention and conclude this Appendix 2, I would like to repeat a few statements I have made at the end of Chapter 15 as follows. I wish to acknowledge that I have been very lucky in many ways too. Having had the opportunities to be a part of the epoch of the birth and the growth of the ICs, and several other fields of physics and microelectronics and make my contributions (see Appendices 1 and 2), has been a rare privilege indeed. To quote from Frank Sinatra’s famous song, one important

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satisfaction I have is that “I did it my way!” to give the IC concepts, contribute to their advancement to the ULSICs, and invent the next generation ICs. The clap of the thunder of invention of ICs may be gone and belong only to a few. However, the thunder usually lasts momentarily or for a short duration only. But the resulting rains, akin to the invaluable contributions of many, bear the fruits and the crops for a long time to come, whether it is in the Silicon Valley and/or in the other global valleys. Certainly the invention of the ICs has borne, and continues to bear, the fruits and crops like the ULSICs to benefit all mankind. It is almost certain that the additional fruits like the 3D-ICs, UPICs, etc will also become realities in the future and benefit everybody. Whether it will be in my and readers’ lifetimes or not is of little or no consequence. What is satisfying to note is that the future generations will reap the harvest of the creativity and hard work of all the contributors so far who themselves have stood on the shoulders of the giants, recognized or not. 9. Reprint of the paper, “A Modification of the Model 50 Pulse Generator”, Current Science, Vol. 22, p. 199, July, 1953. This reprint is that of a research paper published in a bona fide journal, though obscure from the US point of view, its subject matter has been in print in the public domain for the past 53 years. So it should be considered as credible.

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10. The announcement of 1954 lecture This notice was issued in 1954 by Brig. SVS Chowdhry when he was a student and the Secretary of the Physical Society, Lucknow University, Lucknow, India, dated January 12, 1954, for the lecture on “Transistors”

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by A. N. Saxena on January 14, 1954. He had also attended this lecture on January 14, 1954. He is also the former President of the Computer Society of India.

11. Original handwritten notes I could find only one sheet so far of my original handwritten notes for the talk I had given on “Transistors” in 1954. Another file of my notes is still missing or lost. Since my talk was only on “Transistors”, this original sheet contains comments only on transistors. The very first sentence of the handwritten notes states, “Transistors will replace Vacuum Tubes”. These notes do not have any of the comments that I had given verbally on the

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miniaturization of electronic circuits in my talk. However, I refer in these notes to my 1953 paper on the circuit already improved, built and published by me and my (late) colleague. Towards the end of my lecture, I had used the circuit in the 1953 paper as an example for the miniaturization that could be achieved by replacing its vacuum tubes, diodes, resistors and capacitors with the solid state devices. The latter were not available to me then, either in packaged or in unpackaged forms. Therefore I could only describe my concepts of miniaturization of the electronic circuits, and could not demonstrate them by actual reduction to practice. This situation again is in a way similar to that of Bob Noyce who had only described his concepts in his notebook in 1959, which were not witnessed by anybody, and he also did not demonstrate the reduction to practice of his invention. It was done by a few others. However, Noyce did file for the US Patent for his concepts in 1959, so it was an official record of his invention. I did not know anything about patents, or about filing for a patent in 1954, so there is no such legal record of this invention. Copy of the original handwritten notes of Saxena; refers to his paper in 1953 also.

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12. Confirmation of Saxena’s description of his concepts of miniaturization leading to ICs by 5 qualified attendees of his lecture in 1954 A former professor of mine and 4 other qualified personnel, all of whom had attended my lecture in 1954, have written letters to confirm several of the key statements of my concepts of miniaturization of electronic circuits. They have confirmed most of my statements to the best of their individual recollections, which is very gratifying indeed to me. None of them were aware of the term integrated circuits in 1954, but they have used it in their respective letters as a hindsight based on what they have known in the recent years since then. Also not known to them, and perhaps to many still, were the differences between hybrid-PC-IC, hybrid-UC-IC and monolithicIC. As discussed earlier, Kilby had stated the concept of monolithic-IC only partly correctly, but also only as its small part in his patent.1 But Kilby did not give the materials and technologies correctly in his patent to fabricate it as such, and his reduction to practice was also for a hybrid-UC-IC, not monolithic-IC. Apparently, the Nobel Committee either construed Kilby’s invention to be a monolithic-IC, or credited him with the Nobel Prize award for his part in inventing only a hybrid-UC-IC with mesa devices and wirebonded interconnects (see Chapter 12). 12.1. Confirmation by Brig. S. V. S. Chowdhry of Saxena’s concepts of miniaturization leading to ICs given in the lecture on “Transistors” by A. N. Saxena on January 14, 1954. (Former President, Computer Society of India. He was the Secretary, Physical Society, Lucknow University, India, when he had issued the original announcement of Saxena’s talk on “Transistors” on January 14, 1954.)

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12.2. Confirmation by Dr. J. L. Dhar of Saxena’s concepts of miniaturization leading to ICs given in the lecture on “Transistors” by A. N. Saxena on January 14, 1954. (Former Advisor, Department of Science & Technology, Government of India.)

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12.3. Confirmation by Prof. Dr. T. P. Pandya of Saxena’s concepts of miniaturization leading to ICs given in the lecture on “Transistors” by A. N. Saxena on January 14, 1954. (Formerly Prof. & Head, Dept. of Physics, Lucknow University, India.)

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12.4. Confirmation by Prof. Dr. B. P. Pradhan of Saxena’s concepts of miniaturization leading to ICs given in the lecture on “Transistors” by A. N. Saxena on January 14, 1954. (Formerly Prof. & Head, Dept. of Physics, Lucknow University, India; Author of a book “Fundamentals of Solid State Electronics”, ISBN No: 81-85230-00-6.)

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12.5. Confirmation by Prof. Dr. M. C. Saxena of Saxena’s concepts of miniaturization leading to ICs given in the lecture on “Transistors” by A. N. Saxena on January 14, 1954. (Retired Professor of Physics, Lucknow University, India; taught A. N. Saxena courses on Electronics in M.Sc. classes 1950–52.)

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Appendix 6

Alphabetical List of Acronyms and Abbreviations Used in this Book ˚ A Al ALS AMD ASAP Au BiCMOS BPI C◦ CCPA CDs CMOS CNFET CS Cu 2D-ICs 3D-ICs DG-FET DOD DRAM ECS Fab GaAlAs GaAs GaN

= = = = = = = = = = = = = = = = = = = = = = = = =

Angstrom Aluminum Amyotrophic Lateral Sclerosis Advanced Micro Devices As soon as possible Gold Bipolar and CMOS on the same chip Board of Patent Interference Centigrade Court of Customs and Patent Appeals Critical dimensions Complementary MOS Carbon nanotube Field Effect Transistor Compound Semiconductor Copper 2-dimensional ICs 3-dimensional ICs Double-gate-field-effect-transistor Department of Defense Dynamic Random Access Memory The Electrochemical Society Fabrication facility Gallium Aluminum Arsenide Gallium Arsenide Gallium Nitride

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GaP Ge GPS HfO2 High-k

= = = = =

Hybrid-PC-ICs Hybrid-UC-ICs ibid IBM ICs ICTs IEDM IEEE IEEE-TED ILDs I/O LCD TV LED LOCOS Low-k

= = = = = = = = = = = = = = =

LPCVD MNC µm MOS

= = = =

MOSFET MOST mV N/A nm NPN transistor

= = = = = =

NSTI n+

= =

Gallium Phosphide Germanium Global Positioning System Hafnium-dioxide High dielectric constant (greater than that of silicon-dioxide) Hybrid-ICs fabricated with Packaged Chips Hybrid-ICs fabricated with Unpackaged Chips Same as referred to before International Business Machines Integrated Circuits Information and communication technologies International Electron Devices Meeting Institute of Electrical and Electronics Engineers IEEE-Transactions on Electron Devices Inter-layer dielectrics Input/Output Liquid Crystal Display Television Light Emitting Diodes LOCal-Oxidation-of-Si Low dielectric constant (lower than that of silicon-dioxide) Low pressure chemical vapor deposition. Member of Nobel Committee micrometer Metal-oxide-semiconductor; the semiconductor which is used predominantly for the MOS devices and technology is Si Metal-Oxide-Silicon-Field-Effect-Transistor Metal-Oxide-Silicon-Transistor millivolt Not applicable Nanometer(s) Transistor with n-type emitter, p-type base, and n-type collector Nano Science and Technology Institute Heavily doped n-type region

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O OA PCBs PECVD PhD PN junction

= = = = = =

P2 O5 Proc. Phys. Soc. QHL R&D RCA RIE RRE Sb Si SiGe SiO2 SOCs SOI Stacked FET Strained-Si FET TI ULSICs UPICs USA USC

= = = = = = = = = = = = = = = = = = = =

USPTO V. P. W

= = =

Oxygen Original Application Printed circuit boards Plasma enhanced chemical vapor deposition Doctorate in Philosophy In situ junction between p-type doped and n-type doped semiconductor Phosphorus-pent-oxide Proceedings of Physical Society Quality of human life Research and Development Radio Corporation of America Reactive ion etching Royal Radar Establishment Antimony Silicon Silicon-germanium alloy Silicon-di-oxide Systems-on-a-chip Silicon-on-insulator Stacked Field Effect Transistor Strained-Si Field Effect Transistor Texas Instruments Ultra Large Scale Integrated Circuits Ultra Performance ICs United States of America United States Code ; also University of Southern California United States Patent and Trademark Office Vice President Tungsten

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Appendix 7

History of Nobel Prize in Physics and its Award to Alferov, Kroemer and Kilby in 2000 1. Introduction The Nobel Prize is regarded as the most prestigious and highly visible award in the whole world. Winning it is like getting the stamp of approval to be the par excellence elite in one of the six fields in which it is awarded. The whole world stands in awe of and reveres the winner. All the information given by me in this Appendix 7 can be obtained in the original website, www.nobelprize.org. If all the information is public knowledge, a natural question that could be posed to me by a reader, “Why are you re-writing some of the information from this document if it is already available to the public?” I would regard this as an excellent question indeed. My answer to the above question can be summarized with a few facts as follows. 1. As you have read in this book, almost all the people in the world have known of Kilby and Noyce as the only two co-inventors of the integrated circuit (IC), an invention that has revolutionized mankind forever. The latter part of the statement, i.e., it has revolutionized mankind forever, is absolutely correct, but the former, i.e., Kilby and Noyce were the only two co-inventors, is not entirely correct. If this recognition accorded to Kilby and Noyce was entirely wrong or completely correct, then it would have been easy to prove it either way as completely false or as being the gospel truth respectively. Since it is neither, it is like half-truth in which it is not

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always easy to discern the fact from fiction. However, sorting this out and solving the mystery is important to get the history right and let the truth prevail for the sake of mankind, especially for the younger generation. This task gets even harder if the misinformation has been entrenched in the society for a very long time, which is now for about 50 years in the case of the invention of ICs. 2. While solving the mystery, the reader(s) should keep in mind that the only kind of ICs sold from the very beginning in the chip business of the microelectronics industry have been the Si-monolithic-ICs, commonly referred to as just ICs. Kilby did not invent the Si-monolithic-IC, but Noyce did. At best, Kilby’s invention1 was for a hybrid-IC. Also a less known fact is that Noyce’s invention2 used others’ (Hoerni8 and Lehovec9) inventions and did not acknowledge them in his patent. 3. Another not so well known fact is that a fundamental technology, called the planar technology, was mandatory to invent and manufacture the highly stable and reliable planar transistor, and the original Si-monolithicIC when it had only a few devices per chip. The planar technology has been and still is indispensable to manufacture in large volume all kinds of ICs in the microelectronics industry including the present super chips called Ultra Large Scale Integrated Circuits (ULSICs) having billions of devices per chip. Hoerni has been credited with the invention of the planar technology because he was awarded the basic patents for it. However, Hoerni’s invention was built upon a combination of important work done by several others earlier than him, and he also did not acknowledge them. 4. The Nobel Prize in physics7 was awarded jointly to Alferov, Kroemer and Kilby in 2000. Noyce had died in 1990, and the Nobel Prizes are not awarded posthumously. Otherwise he would have been definitely included in this award, and perhaps the entire Nobel Prize award would have been worded and even awarded differently. The inventions of Kilby and Noyce did not involve any basic contributions to physics. However, the work of Alferov and Kroemer did involve basic contribution to physics. 5. The citation for the above Nobel award to the co-winners Alferov, Kroemer and Kilby was published as “for basic work on information and communication technology”. The part of the citation specific to Alferov and

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Kroemer was written as, “for developing semiconductor heterostructures used in high-speed- and opto-electronics”, and the part of the citation specific to Kilby was written as, “for his part in the invention of the integrated circuit”. The Nobel Prize money was distributed as 1/4 each to Alferov and Kroemer, but 1/2 to Kilby. The citation of the Nobel Award to Kilby did not explain also what was his part to invent what kind of IC? I was the first to document this in my paper.12 6. The sequence of listing the names, i.e., the order in which the names were listed in the Nobel Award in 2000 was “Alferov, Kroemer and Kilby”. Before we worry about the sequence and the distribution of the Nobel Prize money to ALL the other 3-person awardees in Physics, we must recall the facts about the Nobel Prize in Physics awarded in 1956. The sequence of listing the names of the Nobel Prize in physics in 1956 was Shockley, Bardeen and Brattain in this order, and each had been given equal amounts of 1/3rd of the Nobel Prize money. Even though the prize money was distributed equally to all three, their names were not listed in alphabetical order. Shockley was listed as the senior recipient followed by Bardeen and Brattain in alphabetical order. There is a reason behind this non-alphabetical listing of their names in 1956 which is not generally known. The Nobel Committee never divulged this reason. (See Section 8.1) 7. I had written communications in 2006 with two members of the Nobel Committee which was responsible for the Nobel award in Physics in 2000. To the best of my knowledge, I was the first to raise the issues of the incomplete characterization in the citation and the double financial award to Kilby with them. They invoked Nobel’s original Will, and declined to answer my questions. For details, see Chapter 12, and Section 9 below. 8. As you have read in this book, and will read it again in section 6 below, a few facts about Kilby’s invention and the Nobel Prize are as follows. 8.1. The citation of the Nobel Award to Kilby was vague and inconsistent with the purported invention of the monolithic-IC by Kilby. 8.2. The enunciation of Kilby’s invention in one of his key patents filed in 1959 and issued in 1964 had striking similarities and limitations

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of prior art, but he did not acknowledge it. Another fact is that Kilby did not describe his invention as succinctly in his other patents as he had done in the patent referred to above. 8.3. There were irregularities in the award and processing of Kilby’s patents by the United States Patent and Trademark Office (USPTO). All the information regarding the Nobel award in 2000 to Alferov, Kroemer and Kilby given above has been available in the public documents of the Nobel website. But why nobody in the public domain ever looked into this information and raised a flag about the problems and the inconsistencies in the patents and the Nobel Prize awarded to Kilby? I wondered about the due diligence by the Nobel Committee before choosing Kilby to be a co-recipient of the Nobel Award in 2000, since he did not invent the monolithic-IC, and the Nobel citation purported that he did. There were a few other factors too in addition to the 8 points listed above which had raised an alarm in my mind. But without belaboring again the details anymore, which I have already discussed in my book, I shall stop now and respond to the question posed above. My answer to the above question is given in the 8 points listed above. The fact that nobody else in the entire literature had raised and clarified the issues for over 4 decades, prompted me to take action. I decided to do my own research into the award of the patents, all aspects of the technical issues, and dig into the Nobel website also. The latter resulted in writing this Appendix 7. My sole purpose is to correct the history of the invention of ICs. That is why I have documented and analyzed the relevant information in my paper12 and in this book.

2. Will of Alfred Nobel For the sake of thorough documentation, accuracy, as well as convenience of the readers, I shall copy several key passages verbatim from the original Nobel website and give them below within quotation marks. However, the underlining of some portions from the website has been done by me in this appendix. In my opinion they are more relevant to our discussions on the invention of ICs.

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“Since 1901, the Nobel Prize has been honoring men and women from all corners of the globe for outstanding achievements in physics, chemistry, medicine, literature, and for work in peace. The foundations for the prize were laid in 1895 when Alfred Nobel wrote his last will, leaving much of his wealth to the establishment of the Nobel Prize.” “On November 27, 1895, Alfred Nobel signed his last will in Paris. When it was opened and read after his death, the will caused a lot of controversy both in Sweden and internationally, as Nobel had left much of his wealth for the establishment of a prize! His family opposed the establishment of the Nobel Prize, and the prize awarders he named refused to do what he had requested in his will. It was five years before the first Nobel Prize could be awarded in 1901.” 2.1. Copy of the English translation of the original version of Nobel’s Will “I, the undersigned, Alfred Bernhard Nobel, do hereby, after mature deliberation, declare the following to be my last Will and Testament with respect to such property as may be left by me at the time of my death: To my nephews, Hjalmar and Ludvig Nobel, the sons of my brother Robert Nobel, I bequeath the sum of Two Hundred Thousand Crowns each; To my nephew Emanuel Nobel, the sum of Three Hundred Thousand, and to my niece Mina Nobel, One Hundred Thousand Crowns; To my brother Robert Nobel’s daughters, Ingeborg and Tyra, the sum of One Hundred Thousand Crowns each; Miss Olga Boettger, at present staying with Mrs. Brand, 10 Rue St Florentin, Paris, will receive One Hundred Thousand Francs; Mrs. Sofie Kapy von Kapivar, whose address is known to the AngloOesterreichische Bank in Vienna, is hereby entitled to an annuity of 6000 ¨ Florins O.W. which is paid to her by the said Bank, and to this end I have deposited in this Bank the amount of 150,000 Fl. in Hungarian State Bonds;

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Mr. Alarik Liedbeck, presently living at 26 Sturegatan, Stockholm, will receive One Hundred Thousand Crowns; Miss Elise Antun, presently living at 32 Rue de Lubeck, Paris, is entitled to an annuity of Two Thousand Five Hundred Francs. In addition, Forty Eight Thousand Francs owned by her are at present in my custody, and shall be refunded; Mr. Alfred Hammond, Waterford, Texas, U.S.A. will receive Ten Thousand Dollars; The Misses Emy and Marie Winkelmann, Potsdamerstrasse, 51, Berlin, will receive Fifty Thousand Marks each; Mrs. Gaucher, 2 bis Boulevard du Viaduc, Nimes, France will receive One Hundred Thousand Francs; My servants, Auguste Oswald and his wife Alphonse Tournand, employed in my laboratory at San Remo, will each receive an annuity of One Thousand Francs; My former servant, Joseph Girardot, 5, Place St. Laurent, Chˆ alons sur Saˆ one, is entitled to an annuity of Five Hundred Francs, and my former gardener, Jean Lecof, at present with Mrs. Desoutter, receveur Curaliste, Mesnil, Aubry pour Ecouen, S. & O., France, will receive an annuity of Three Hundred Francs; Mr. Georges Fehrenbach, 2, Rue Compiègne, Paris, is entitled to an annual pension of Five Thousand Francs from January 1, 1896 to January 1, 1899, when the said pension shall discontinue; A sum of Twenty Thousand Crowns each, which has been placed in my custody, is the property of my brother’s children, Hjalmar, Ludvig, Ingeborg and Tyra, and shall be repaid to them. The whole of my remaining realizable estate shall be dealt with in the following way: the capital, invested in safe securities by my executors, shall constitute a fund, the interest on which shall be annually distributed in the form of prizes to those who, during the preceding year, shall have conferred

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the greatest benefit on mankind. The said interest shall be divided into five equal parts, which shall be apportioned as follows: one part to the person who shall have made the most important discovery or invention within the field of physics; one part to the person who shall have made the most important chemical discovery or improvement; one part to the person who shall have made the most important discovery within the domain of physiology or medicine; one part to the person who shall have produced in the field of literature the most outstanding work in an ideal direction; and one part to the person who shall have done the most or the best work for fraternity between nations, for the abolition or reduction of standing armies and for the holding and promotion of peace congresses. The prizes for physics and chemistry shall be awarded by the Swedish Academy of Sciences; that for physiological or medical work by the Caroline Institute in Stockholm; that for literature by the Academy in Stockholm, and that for champions of peace by a committee of five persons to be elected by the Norwegian Storting. It is my express wish that in awarding the prizes no consideration whatever shall be given to the nationality of the candidates, but that the most worthy shall receive the prize, whether he be a Scandinavian or not. As Executors of my testamentary dispositions, I hereby appoint Mr. Ragnar Sohlman, resident at Bofors, Värmland, and Mr. Rudolf Lilljequist, 31 Malmskillnadsgatan, Stockholm, and at Bengtsfors near Uddevalla. To compensate for their pains and attention, I grant to Mr. Ragnar Sohlman, who will presumably have to devote most time to this matter, One Hundred Thousand Crowns, and to Mr. Rudolf Lilljequist, Fifty Thousand Crowns; At the present time, my property consists in part of real estate in Paris and San Remo, and in part of securities deposited as follows: with The Union Bank of Scotland Ltd in Glasgow and London, Le Crédit Lyonnais, Comptoir National d’Escompte, and with Alphen Messin & Co. in Paris; with the stockbroker M.V. Peter of Banque Transatlantique, also in Paris; with Direction der Disconto Gesellschaft and Joseph Goldschmidt & Cie, Berlin; with the Russian Central Bank, and with Mr. Emanuel Nobel in Petersburg; with Skandinaviska Kredit Aktiebolaget in Gothenburg and Stockholm, and in my strong-box at 59, Avenue Malakoff, Paris; further to this are accounts receivable, patents, patent fees or so-called royalties

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etc. in connection with which my Executors will find full information in my papers and books. This Will and Testament is up to now the only one valid, and revokes all my previous testamentary dispositions, should any such exist after my death. Finally, it is my express wish that following my death my veins shall be opened, and when this has been done and competent Doctors have confirmed clear signs of death, my remains shall be cremated in a so-called crematorium. Paris, 27 November, 1895 Alfred Bernhard Nobel That Mr. Alfred Bernhard Nobel, being of sound mind, has of his own free will declared the above to be his last Will and Testament, and that he has signed the same, we have, in his presence and the presence of each other, hereunto subscribed our names as witnesses: Sigurd Ehrenborg former Lieutenant Paris: 84 Boulevard Haussmann R. W. Strehlenert Civil Engineer 4, Passage Caroline Thos Nordenfelt Constructor 8, Rue Auber, Paris Leonard Hwass Civil Engineer 4, Passage Caroline” 2.2. Excerpt from Nobel’s Will “The whole of my remaining realizable estate shall be dealt with in the following way: the capital, invested in safe securities by my executors, shall constitute a fund, the interest on which shall be annually distributed in the

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Appendix 7. History of Nobel Prize in Physics Section 3. Updated summary of the Nobel Prize award

473

form of prizes to those who, during the preceding year, shall have conferred the greatest benefit on mankind. The said interest shall be divided into five equal parts, which shall be apportioned as follows: one part to the person who shall have made the most important discovery or invention within the field of physics; one part to the person who shall have made the most important chemical discovery or improvement; one part to the person who shall have made the most important discovery within the domain of physiology or medicine; one part to the person who shall have produced in the field of literature the most outstanding work in an ideal direction; and one part to the person who shall have done the most or the best work for fraternity between nations, for the abolition or reduction of standing armies and for the holding and promotion of peace congresses. The prizes for physics and chemistry shall be awarded by the Swedish Academy of Sciences; that for physiology or medical works by the Karolinska Institute in Stockholm; that for literature by the Academy in Stockholm, and that for champions of peace by a committee of five persons to be elected by the Norwegian Storting. It is my express wish that in awarding the prizes no consideration be given to the nationality of the candidates, but that the most worthy shall receive the prize, whether he be Scandinavian or not.” 2.3. A few highlights of the updated Nobel Awards “The prizes, as designated in the Will of Alfred Nobel, are in physics, chemistry, physiology or medicine, literature and peace. Only once during these years has a prize been added — a Memorial Prize — the Prize in Economic Sciences in Memory of Alfred Nobel, donated by the Bank of Sweden to celebrate its tercentenary in 1968. The Board of Directors later decided to keep the original five prizes intact and not to permit new additions.”

3. Updated summary of the Nobel Prize award The last sentence of 2.3 is somewhat confusing: “The Board of Directors later decided to keep the original five prizes intact and not to permit new additions.” The Board of Directors did allow the addition of Economics in 1968 to the original five prizes. Therefore six prizes are now being given since

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1969, but my understanding is that no further additions will be permitted. Thus the updated list including the original five fields in which the Nobel Prizes are awarded are as follows. 3.1. Physics. 3.2. Chemistry. 3.3. Medicine. 3.4. Literature. 3.5. Peace. 3.6. Economics. Thus, in accordance with Nobel’s Will, the Nobel Prizes shall be given annually in the above 6 fields to person(s) irrespective of nationality who, during the preceding year, shall have conferred the greatest benefit on mankind.

4. The field of Engineering missing from the Nobel Award list It must be noted that the field of Engineering is missing from the above list; consequently Nobel Prizes are not awarded in Engineering. However it is a well known fact that the innovations and contributions from the field of Engineering (over and beyond those from the six fields designated officially to receive the Nobel Prizes) have indubitably conferred the greatest benefit on mankind in many ways. Engineering has had this distinction even from an era well before 1901 when the Nobel Awards began. A few examples of Engineering which have conferred the greatest benefit to mankind are the invention of movable type by Gutenberg in 1450’s which led to the printing of books, the industrial revolution in the 1700’s which revolutionized travel, and the inventions of Alfred Nobel himself in 1863– 1868 (nitroglycerin, detonator, dynamite) which revolutionized, mining, warfare and construction.

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Appendix 7. History of Nobel Prize in Physics Section 5. Difficult job of Nobel Committees

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Nevertheless the Nobel Prizes, whose sole criterion to be selected for the award is to have “conferred the greatest benefit to mankind”, are not awarded in Engineering. Based on this sole criterion, the absence of Engineering from the above award list is conspicuous. This is just a statement of fact, not meant as any reflection on the priorities considered in the original Will by Alfred Nobel, and its update by the Nobel Committee in 1968 to limit the addition of only one field, viz., Economics, to the original five fields. The vision, wisdom and graciousness of Alfred Nobel are to be commended for having the foresight that the inventions in Engineering are rooted in the basic sciences like Physics and Chemistry. His magnanimity towards fellow human beings is also evident by his choice of Medicine, Literature and Peace, because without them the human race cannot live happily if not survive at all.

5. Difficult job of Nobel Committees; example of the Nobel Prize to Sir C.V. Raman The respective Nobel Committees have a very difficult job to select the Nobel Prize winner(s) in the chosen fields. According to the dictum of Nobel’s original Will, each Nobel Committee is charted with the responsibility to focus and select the recipient(s) based primarily on “the greatest benefit on mankind . . . conferred . . . during the preceding year” of the award. I shall not dwell on this difficult topic in my book, because it is a huge and debatable subject. However I shall give only one example of the Nobel Prize awarded in 1930 to Sir C.V. Raman. The citation for his Nobel award was, “for his work on the scattering of light and for the discovery of the effect named after him”. The phenomenon of the change in the frequency of light on scattering was named as Raman Effect. Naming the effect after Raman’s name certainly cannot be construed by itself as a great scientific achievement or having conferred “the greatest benefit on mankind”. But the experimental observation by Raman with the techniques available to him in 1920s must have been regarded, and it certainly was an outstanding contribution to Physics. However, I dare say that the Nobel Committee who had selected Raman to receive the Nobel Prize in 1930 could not have convinced anybody at that time that Raman’s experimental observation “during the

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preceding year” had indeed “conferred the greatest benefit on mankind”. Its important contribution then was restricted to a narrow field of Optics in Physics. So the Nobel Committee had a difficult job when they had selected Raman. It can also be surmised that the Committee probably had no inkling whatsoever to anticipate the even greater benefit to mankind that Raman’s discovery in 1920s would have well after the Nobel award into the future, especially now in the millennium of 2000. As it is well known, Raman Effect is crucial in many important applications in research and practical use including medicine nowadays. The advanced instrumentations based on Raman Effect are enabling benefit to various fields of science and technology, and consequently to mankind. Such developments are in the category of Engineering rather than any basic science. Thus Raman Effect is a rare example of how a Nobel Prize in a narrow field of Physics, has transmuted to Engineering and conferred “the greatest benefit on mankind”, and it is expected to carry on benefiting mankind well into the future. Such a rare example can be given only for a small percentage of the Nobel Prizes awarded in their entire history. So it is fair to say that the Nobel Committees, while having a difficult job to select the Nobel Awardees, are lucky sometimes in their decisions when they hit a jackpot. For whatever it is worth, humbly I wish to state that I have had the distinguished privilege and the great honor to have met personally many of the Nobel Laureates in my career. The first whom I had met in 1950 was Sir C.V. Raman who had won the Nobel Prize in Physics in 1930. My meetings with him and several others were very interesting indeed. Since they are not the subject of this book, I shall not discuss them.

6. History of all the Nobel Awards in Physics from the very beginning in 1901 to 2007 I shall copy from the Nobel website ALL the Nobel Awards in Physics given from the very beginning in 1901 to 2007 in Table App. 7.1. As the readers will note, the number of awardees in each year of the Nobel award have ranged from one to at most three persons. The sequence of the names of

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the awardees in two- or three-person categories is from the original Nobel list. While most sequences follow the alphabetical order, it is not so in several cases. The Nobel Committee does not offer any explanation for these deviations from the alphabetical order when they announce the Nobel Awards. Similarly it does not give any explanation for the unequal financial awards given to some of the awardees in a multi-recipient Nobel Prize (see Section 7). Table App. 7.1 — The entire list of the Nobel Awards in Physics from the very beginning in 1901 to 2007 The following entire list of the Nobel Awards in Physics from the very beginning in 1901 to 2007 has been copied verbatim from the original Nobel website. “The Nobel Prize in Physics has been awarded to 180 individuals since 1901. (John Bardeen was awarded the prize in both 1956 and 1972.) • • • • • • • • • • • • • • • • • • • •

2007 2006 2005 2004 2003 2002 2001 2000 1999 1998 1997 1996 1995 1994 1993 1992 1991 1990 1989 1988

— — — — — — — — — — — — — — — — — — — —

Albert Fert, Peter Gr¨ unberg John C. Mather, George F. Smoot Roy J. Glauber, John L. Hall, Theodor W. H¨ ansch David J. Gross, H. David Politzer, Frank Wilczek Alexei A. Abrikosov, Vitaly L. Ginzburg, Anthony J. Leggett Raymond Davis Jr., Masatoshi Koshiba, Riccardo Giacconi Eric A. Cornell, Wolfgang Ketterle, Carl E. Wieman Zhores I. Alferov, Herbert Kroemer, Jack S. Kilby Gerardus’t Hooft, Martinus J.G. Veltman Robert B. Laughlin, Horst L. St¨ ormer, Daniel C. Tsui Steven Chu, Claude Cohen-Tannoudji, William D. Phillips David M. Lee, Douglas D. Osheroff, Robert C. Richardson Martin L. Perl, Frederick Reines Bertram N. Brockhouse, Clifford G. Shull Russell A. Hulse, Joseph H. Taylor Jr. Georges Charpak Pierre-Gilles de Gennes Jerome I. Friedman, Henry W. Kendall, Richard E. Taylor Norman F. Ramsey, Hans G. Dehmelt, Wolfgang Paul Leon M. Lederman, Melvin Schwartz, Jack Steinberger

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• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

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1987 — J. Georg Bednorz, K. Alex M¨ uller 1986 — Ernst Ruska, Gerd Binnig, Heinrich Rohrer 1985 — Klaus von Klitzing 1984 — Carlo Rubbia, Simon van der Meer 1983 — Subramanyan Chandrasekhar, William A. Fowler 1982 — Kenneth G. Wilson 1981 — Nicolaas Bloembergen, Arthur L. Schawlow, Kai M. Siegbahn 1980 — James Cronin, Val Fitch 1979 — Sheldon Glashow, Abdus Salam, Steven Weinberg 1978 — Pyotr Kapitsa, Arno Penzias, Robert Woodrow Wilson 1977 — Philip W. Anderson, Sir Nevill F. Mott, John H. van Vleck 1976 — Burton Richter, Samuel C.C. Ting 1975 — Aage N. Bohr, Ben R. Mottelson, James Rainwater 1974 — Martin Ryle, Antony Hewish 1973 — Leo Esaki, Ivar Giaever, Brian D. Josephson 1972 — John Bardeen, Leon N. Cooper, Robert Schrieffer 1971 — Dennis Gabor 1970 — Hannes Alfvén, Louis Néel 1969 — Murray Gell-Mann 1968 — Luis Alvarez 1967 — Hans Bethe 1966 — Alfred Kastler 1965 — Sin-Itiro Tomonaga, Julian Schwinger, Richard P. Feynman 1964 — Charles H. Townes, Nicolay G. Basov, Aleksandr M. Prokhorov 1963 — Eugene Wigner, Maria Goeppert-Mayer, J. Hans D. Jensen 1962 — Lev Landau 1961 — Robert Hofstadter, Rudolf M¨ ossbauer 1960 — Donald A. Glaser 1959 — Emilio Segrè, Owen Chamberlain 1958 — Pavel A. Cherenkov, Il’ja M. Frank, Igor Y. Tamm 1957 — Chen Ning Yang, Tsung-Dao Lee 1956 — William B. Shockley, John Bardeen, Walter H. Brattain 1955 — Willis E. Lamb, Polykarp Kusch 1954 — Max Born, Walther Bothe 1953 — Frits Zernike 1952 — Felix Bloch, E.M. Purcell 1951 — John Cockcroft, Ernest T.S. Walton 1950 — Cecil Powell

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Appendix 7. History of Nobel Prize in Physics Section 6. History of all the Nobel Awards in Physics

• • • • • • • •

1949 1948 1947 1946 1945 1944 1943 1942

•

1941

•

1940

• • • • • •

1939 1938 1937 1936 1935 1934

• • •

1933 1932 1931

• • • • • • • • • • • • • •

1930 1929 1928 1927 1926 1925 1924 1923 1922 1921 1920 1919 1918 1917

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— Hideki Yukawa — Patrick M.S. Blackett — Edward V. Appleton — Percy W. Bridgman — Wolfgang Pauli — Isidor Isaac Rabi — Otto Stern — The prize money was with 1/3 allocated to the Main Fund and with 2/3 to the Special Fund of this prize section — The prize money was with 1/3 allocated to the Main Fund and with 2/3 to the Special Fund of this prize section — The prize money was with 1/3 allocated to the Main Fund and with 2/3 to the Special Fund of this prize section — Ernest Lawrence — Enrico Fermi — Clinton Davisson, George Paget Thomson — Victor F. Hess, Carl D. Anderson — James Chadwick — The prize money was with 1/3 allocated to the Main Fund and with 2/3 to the Special Fund of this prize section — Erwin Schr¨ odinger, Paul A.M. Dirac — Werner Heisenberg — The prize money was allocated to the Special Fund of this prize section — Sir Venkata Raman — Louis de Broglie — Owen Willans Richardson — Arthur H. Compton, C.T.R. Wilson — Jean Baptiste Perrin — James Franck, Gustav Hertz — Manne Siegbahn — Robert A. Millikan — Niels Bohr — Albert Einstein — Charles Edouard Guillaume — Johannes Stark — Max Planck — Charles Glover Barkla

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• • • • • • • • • • • • •

•

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1916 — The prize money was allocated to the Special Fund of this prize section 1915 — William Bragg, Lawrence Bragg 1914 — Max von Laue 1913 — Heike Kamerlingh Onnes 1912 — Gustaf Dalén 1911 — Wilhelm Wien 1910 — Johannes Diderik van der Waals 1909 — Guglielmo Marconi, Ferdinand Braun 1908 — Gabriel Lippmann 1907 — Albert A. Michelson 1906 — J.J. Thomson 1905 — Philipp Lenard 1904 — Lord Rayleigh 1903 — Henri Becquerel, Pierre Curie, Marie Curie 1902 — Hendrik A. Lorentz, Pieter Zeeman 1901 — Wilhelm Conrad R¨ ontgen

7. The entire list of all Nobel Prize in Physics winners to 3-person awardees from the very beginning with their citations and distribution of the award money As explained in Section 6, since my main focus in this book is to give the facts and possible explanations for the invention of the ICs, and that its Nobel Award was given to three persons (Alferov, Kroemer, Kilby), I shall give the entire listing of only the three-person Nobel Prize recipients throughout the history of the Nobel Awards in Physics in Table App. 7.2. Of course the entire list (single; two-persons; three-persons) of the Nobel Awards in Physics from the very beginning in 1901 to 2007 has already been given in Table App. 7.1 above. However, in Table App. 7.2 below, I shall also give additional information on the respective specific Nobel citations and the distribution of the Prize money for the awards which was not given in Table App. 7.1. My comments and explanations shall be restricted to the 3-person awardees only, the maximum number of the recipients in a multi-person-Nobel Prize in Physics throughout their existence so far. The style of presentation in Table App. 7.2 is mine, but all the data are copied unchanged from the original Nobel website.

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Appendix 7. History of Nobel Prize in Physics Section 7. The entire list of all Nobel Prize in Physics winners

Table App. 7.2. The entire list of all Nobel Prize in Physics winners to 3-person awardees from the very beginning with their citations and distribution of award money. Year awarded 1903

1956

1958

1963

Distribution of award money

Citation of award

1. Antoine Henri Becquerel

1/2

2. Pierre Curie

1/4

3. Marie Curie, née Sklodowska 1. William Bradford Shockley

1/4

“in recognition of the extraordinary services he has rendered by his discovery of spontaneous radioactivity” “in recognition of the extraordinary services they have rendered by their joint researches on the radiation phenomena discovered by Professor Henri Becquerel” (same as above)

2. John Bardeen 3. Walter Houser Brattain 1. Pavel Alekseyevich Cherenkov

1/3 1/3

2. Il’ja Mikhailovich Frank 3. Igor Yevgenyevich Tamm 1. Eugene Paul Wigner

1/3

“for the discovery and the interpretation of the Cherenkov effect” (same as above)

1/3

(same as above)

1/2

2. Maria Goeppert-Mayer

1/4

3. J. Hans D. Jensen

1/4

“for his contributions to the theory of the atomic nucleus and the elementary particles, particularly through the discovery and application of fundamental symmetry principles” “for their discoveries concerning nuclear shell structure” (same as above)

Names

1/3

1/3

“for their researches on semiconductors and their discovery of the transistor effect” (same as above) (same as above)

(Continued)

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Table App. 7.2. Year awarded

(Continued)

Names


Citation of award

1964

1. Charles Hard Townes

1/2

1/4 1/4

(same as above)

1965

2. Nicolay Gennadiyevich Basov 3. Aleksandr Mikhailovich Prokhorov 1. Sin-Itiro Tomonaga

“for fundamental work in the field of quantum electronics, which has led to the construction of oscillators and amplifiers based on the maser-laser principle” (same as above)

1/3

1972

2. Julian Schwinger 3. Richard P. Feynman 1. John Bardeen

1/3 1/3 1/3

1973

2. Leon Neil Cooper 3. John Robert Schrieffer 1. Leo Esaki

1/3 1/3 1/4

2. Ivar Giaever 3. Brian David Josephson

1/4 1/2

“for their fundamental work in quantum electrodynamics, with deep-ploughing consequences for the physics of elementary particles” (same as above) (same as above) “for their jointly developed theory of superconductivity, usually called the BCS-theory” (same as above) (same as above) “for their experimental discoveries regarding tunneling phenomena in semiconductors and superconductors, respectively” (same as above) “for his theoretical predictions of the properties of a supercurrent through a tunnel barrier, in particular those phenomena which are generally known as the Josephson effects” (Continued)

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(Continued)


Citation of award

1. Aage Niels Bohr

1/3

2. Ben Roy Mottelson 3. Leo James Rainwater 1. Philip Warren Anderson

1/3 1/3 1/3

2. Sir Nevill Francis Mott 3. John Hasbrouck van Vleck 1. Pyotr Leonidovich Kapitsa

1/3 1/3

“for the discovery of the connection between collective motion and particle motion in atomic nuclei and the development of the theory of the structure of the atomic nucleus based on this connection” (same as above) (same as above) “for their fundamental theoretical investigations of the electronic structure of magnetic and disordered systems” (same as above) (same as above)

2. Arno Allan Penzias

1/4

1/4

1979

3. Robert Woodrow Wilson 1. Sheldon Lee Glashow

1/3

1981

2. Abdus Salam 3. Steven Weinberg 1. Nicolaas Bloembergen

1/3 1/3 1/4

2. Arthur Leonard Schawlow 3. Kai M. Siegbahn

1/4

1975

1977

1978

Names

1/2

1/2

“for his basic inventions and discoveries in the area of low-temperature physics” “for their discovery of cosmic microwave background radiation” (same as above) “for their contributions to the theory of the unified weak and electromagnetic interaction between elementary particles, including, inter alia, the prediction of the weak neutral current” (same as above) (same as above) “for their contribution to the development of laser spectroscopy” (same as above) “for his contribution to the development of high-resolution electron spectroscopy” (Continued)

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Table App. 7.2. Year awarded 1986

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Names

(Continued)


1. Ernst Ruska

1/2

2. Gerd Binnig

1/4

1988

3. Heinrich Rohrer 1. Leon M. Lederman

1/4 1/3

1989

2. Melvin Schwartz 3. Jack Steinberger 1. Norman F. Ramsey

1/3 1/3 1/2

2. Hans G. Dehmelt

1/4

1990

3. Wolfgang Paul 1. Jerome I. Friedman

1/4 1/3

1996

2. Henry W. Kendall 3. Richard E. Taylor 1. David M. Lee

1/3 1/3 1/3

1997

2. Douglas D. Osheroff 3. Robert C. Richardson 1. Steven Chu

1/3 1/3 1/3

Citation of award “for his fundamental work in electron optics, and for the design of the first electron microscope” “for their design of the scanning tunneling microscope” (same as above) “for the neutrino beam method and the demonstration of the doublet structure of the leptons through the discovery of the muon neutrino” (same as above) (same as above) “for the invention of the separated oscillatory fields method and its use in the hydrogen maser and other atomic clocks” “for the development of the ion trap technique” (same as above) “for their pioneering investigations concerning deep inelastic scattering of electrons on protons and bound neutrons, which have been of essential importance for the development of the quark model in particle physics” (same as above) (same as above) “for their discovery of superfluidity in helium-3” (same as above) (same as above) “for development of methods to cool and trap atoms with laser light” (Continued)

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Names

(Continued)


Citation of award

1/3

(same as above)

1998

2. Claude Cohen-Tannoudji 3. William D. Phillips 1. Robert B. Laughlin

1/3 1/3

2000

2. Horst L. St¨ ormer 3. Daniel C. Tsui 1. Zhores I. Alferov

1/3 1/3 1/4

2. Herbert Kroemer 3. Jack S. Kilby

1/4 1/2

2001

1. Eric A. Cornell

1/3

2002

2. Wolfgang Ketterle 3. Carl E. Wieman 1. Raymond Davis Jr.

1/3 1/3 1/4

2. Masatoshi Koshiba 3. Riccardo Giacconi

1/4 1/2

1. Alexei A. Abrikosov

1/3

(same as above) “for their discovery of a new form of quantum fluid with fractionally charged excitations” (same as above) (same as above) “for basic work on information and communication technology” “for developing semiconductor heterostructures used in high-speed- and opto-electronics” (same as above) “for his part in the invention of the integrated circuit” “for the achievement of Bose-Einstein condensation in dilute gases of alkali atoms, and for early fundamental studies of the properties of the condensates” (same as above) (same as above) “for pioneering contributions to astrophysics, in particular for the detection of cosmic neutrinos” (same as above) “for pioneering contributions to astrophysics, which have led to the discovery of cosmic X-ray sources” “for pioneering contributions to the theory of superconductors and superfluids”

2003

(Continued)

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Names

(Continued)


2004

2. Vitaly L. Ginzburg 3. Anthony J. Leggett 1. David J. Gross

1/3 1/3 1/3

2005

2. H. David Politzer 3. Frank Wilczek 1. Roy J. Glauber

1/3 1/3 1/2

2. John L. Hall

1/4

3. Theodor W. H¨ ansch

1/4

Citation of award (same as above) (same as above) “for the discovery of asymptotic freedom in the theory of the strong interaction” (same as above) (same as above) “for his contribution to the quantum theory of optical coherence” “for their contributions to the development of laser-based precision spectroscopy, including the optical frequency comb technique” (same as above)

It is interesting to note that since the inception of the Nobel Awards in 1901, the first three-person awardees were in 1903 (Becquerel; Curie; Curie née Sklodowska). Most of the other winners in the early years were singleperson, and a few were two-person awardees. It took 53 years before the next three-person Nobel Prize was awarded in 1956 to Shockley, Bardeen, and Brattain. Although there were several three-person awardees in Physics after that, but it took another 44 years until the next Nobel Prize after 1956 in semiconductor devices was awarded in 2000 to Alferov, Kroemer and Kilby.

8. Overall comments on the sequence of listing and the distribution of the financial amounts of 3-person awardees throughout the entire history of Nobel Awards I have summarized the 3-person Nobel awardees throughout the entire history in Table App. 7.2 above. I have given the year of the award, the sequence of listing their names, distribution of the award money, and the citations of their awards. Without discussing the specific details of each

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Nobel Prize, the list will be obvious to most of the readers to understand what the awards were for in each year. Therefore for brevity, I shall give only overall comments on the 3-person awardees below. However, I shall discuss the details of only the Nobel Prize awarded in Physics in 2000 to Alferov, Kroemer and Kilby in the next Section no. 9, since it is the subject of my book. First, my overall comments on 3-person awardees of Nobel Prizes are as follows. 8.1. The sequence of listing of the names of the winners in 3-person awardees in a single-subject citation is usually alphabetical. However, the order in which the names are listed can be changed by the Nobel Committee based on its judgment of the importance and the seniority of the contributor(s). It is generally known but not publicized blatantly that the influence peddling also works to alter the sequence of listing. The seniormost voted by the Committee eventually gets his/her name listed first in the sequence, which is sometimes subjective rather than objective. 8.2. The prize distribution among the 3-person awardees with a single subject citation is usually equal, i.e., 1/3, 1/3, 1/3 of the total amount. But here again, evaluations of the importance and seniority adjudged by the Nobel Committee including influence peddling as described in Section 8.1 above, the prize money distribution can be unequal, i.e., 1/2, 1/4, 1/4, and its order can be reversed.

9. Discussion of the Sequence of Listing and the Distribution of the Financial Amounts in the Nobel Prize Awarded in Physics in 2000 to Alferov, Kroemer and Kilby As stated in the previous Section 8, I shall discuss now the details of only the Nobel Prize awarded in Physics in 2000 to Alferov, Kroemer and Kilby in this section. For the sake of continuity, I shall repeat that the Nobel Prize in Physics was awarded in 2000 to Alferov, Kroemer and Kilby, listed in this order. The citations for their Nobel award read as “for basic work on information and communication technology”; the part of the citation listed

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first specific to Alferov and Kroemer read as, “for developing semiconductor heterostructures used in high-speed- and opto-electronics”; the part of the citation listed next which was specific to Kilby read as, “for his part in the invention of the integrated circuit”. The Nobel Prize money was distributed as 1/4 each to Alferov and Kroemer, and 1/2 to Kilby. For additional discussions, see Chapters 1 and 12. The Nobel Committee members were either not aware or had ignored the key facts given in Section 3.2 of Chapter 1 when they had included Kilby as a co-winner of the Nobel Prize7 in Physics in 2000. There was hardly any physics involved in Kilby’s invention of the IC. If any field to which Kilby’s invention could have been ascribed to, would have been Engineering. But as discussed above in section 4, Engineering is not one of the designated fields in Nobel’s Will in which the award could have been given. The citation specific to Kilby’s award in the Prize, “for his part in the invention of the integrated circuit”, did not state precisely what was Kilby’s part in the invention of which kind of integrated circuit? It was incomplete and inconsistent with his contribution to the purported invention of monolithic-ICs for which he was given the Nobel award. I was the first to document in my paper12 that Kilby’s invention was not for the monolithic-IC (see also Chapter 7). This key fact had been neglected in the entire literature until my paper12 was published. A member of the Nobel Committee (Dr. MNC-1) in his written communications with me confirmed recently that I was correct, i.e., Kilby indeed did not invent the monolithicIC. Despite acknowledging this crucial fact, Dr. MNC-1 refused to clarify why then Kilby was chosen to receive the Nobel Award in 2000 if he did not invent the monolithic-IC, and why the language of the citation for his award was incomplete and inconsistent with the award? Another fact that Kilby was given twice the amount of financial award than to each of the other two co-recipients (Alferov and Kroemer) whose fundamental contributions did involve physics, struck me as unusual. This unequal financial award to Kilby enhanced the odd feeling, in particular when I had remembered that equal financial amounts had been given to Shockley, Bardeen and Brattain for their invention of the transistor when they were awarded the Nobel Prize in Physics in 1956. The refusal of Dr. MNC-1 to clarify this also added to the mystery of the Nobel Award during my written communications with him. Referring to the original Will

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of Alfred Nobel that no explanations can be given until after 50 years of the Award, Dr. MNC-1 gave it as the reason for his inability to explain all this now. This reply did not satisfy me, because I did not find this restrictive clause of 50 years in Nobel’s Will. Similar and additional comments were also made by another member of the Nobel Committee, Dr. MNC-2 in his written communications with me. Therefore I did personal research into this matter using the Nobel website itself as the key source of my documented information, which resulted finally in this Appendix 7. I came to the conclusion that the imprecise citation of the Award to Kilby cannot still be explained, but perhaps I can offer explanations for the sequence of non-alphabetical listing of the names and the unequal financial Award as follows. As stated above and to repeat, the citation of the Nobel Prize in Physics in 2000 common to all three, viz, Alferov, Kroemer and Kilby was, “for basic work on information and communication technology”. The part of the sub-citation specific to Alferov and Kroemer read as “for developing semiconductor heterostructures used in high-speed- and opto-electronics”. The part of the sub-citation specific to Kilby read as “for his part in the invention of the integrated circuit”. What was Kilby’s part to invent what kind of the integrated circuit was never spelled out? Kilby had invented at best only a hybrid-IC whose use is very small as compared to the use of Si monolithic-ICs invented a la Noyce. I assume that all the members of the Nobel Committee from the early years, even before Dr. MNC-1 and Dr. MNC-2 had come on board, would have known the above facts. Even though the Nobel Committee has not, and will not divulge the reasons at this time for giving the award the way they did in 2000, my interpretation is that the whole world had come to the realization that a Nobel Prize was long overdue for recognizing the invention of the IC. The Nobel Committee apparently could not focus on a clear winner for this invention for a very long time, and unfortunately Bob Noyce had died in 1990. Most probably the Committee was also aware of the key contributions from some of the others to Noyce’s invention. But the Committee was just unable to come to a clear cut decision in 1980s–1990s. In the meantime, the exponential growth of the information and communication technology (ICT) was glaring at the Nobel Committee

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to do something to recognize the key inventions which had made ICT possible. The work of Alferov and Kroemer, which had gone somewhat unnoticed before, gained in importance also because of their applications in the ICTs. Alferov and Kroemer’s work did make basic contributions to physics. But Noyce’s and Kilby’s work made no basic contributions to Physics; instead their work was in Engineering. From the criterion of “the greatest benefit on mankind” in Nobel’s Will, there is no question in my mind, and probably in all the readers’ mind too after reading my book, that the IC invention fulfilled if not exceeded this criterion. Therefore it deserved to be recognized ASAP. Since Noyce had died in 1990, he could not have been chosen for the award in 2000. But why Kilby was chosen and recognized by a Nobel Prize for the IC invention, especially knowing the details of his invention which was not what it was touted to be, cannot be explained. My interpretation and rationale of the decisions made by the Nobel Committee for the Nobel Prize in Physics in 2000 are given below. Considering the time period prior to the announcement of the Nobel Award in 2000, the decisions made by the Nobel Committee can be construed to have occurred most likely as follows. 9.1. The subject chosen for the Nobel Prize in physics in 2000 shall be “the information and communication technology” which has “conferred the greatest benefit on mankind” at least from and “during the preceding year”, the criteria specified in Nobel’s Will. The name of the subject chosen, viz., information and communication technology (ICT) for the Nobel Prize clearly identifies it to be in Engineering rather than in Physics. But the Committee made an ad hoc decision for awarding the Nobel Prize in 2000 to assign ICT to Physics. 9.2. The Si ICs and semiconductor heterostructure devices are both essential for ICT. So the decision was made that both the subjects will be recognized jointly in the Nobel Prize in Physics. Kilby did not invent the Si IC, but he gave the concept of fabricating multiple devices in a single piece of semiconductor like Si and Ge (similar to Dummer’s concept given earlier, but we shall overlook it). Therefore Kilby shall be chosen as the recipient for it but cited as “for his part in the invention of the integrated circuit”. What was his part in the invention of which kind of

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integrated circuit shall not be given? Alferov and Kroemer contributed independently to develop semiconductors heterostructures. Therefore they shall be chosen as co-recipients and cited jointly as “for developing semiconductor heterostructures used in high-speed- and opto-electronics”. 9.3. The work of Alferov and Kroemer had made basic contributions to physics. Hence it will be considered more important than the IC invention by Kilby which did not make basic contribution to physics. Therefore they shall be listed first in the sequence of the names jointly. Alferov and Kroemer will be cited jointly and listed alphabetically, i.e., Alferov first and Kroemer second. Kilby’s citation and name will be listed after Alferov and Kroemer (as explained above in 9.2). 9.4. From the financial aspect of the Nobel Award, even though the impact of the invention of IC is orders of magnitude larger than the semiconductor heterostructures, and has “conferred the greatest benefit on mankind” at least from and “during the preceding year”, the award money shall be divided equally between the two fields being recognized in the Nobel Prize in Physics in 2000. This will reflect the unbiased and egalitarian principles of the Nobel Committee by giving 1/2 the prize money to each field. This meant that since there were two winners in the semiconductor heterostructures field, they shall divide equally and Alferov and Kroemer shall each receive 1/4 of the prize money. Since Kilby is the only person being recognized in the IC invention, he will receive the 1/2 of the prize money. Thus, the items 9.1 to 9.4 above explain the most likely scenario that may have occurred during the difficult deliberations of the Nobel Committee to arrive at a consensus decision for the Nobel Prize in Physics in 2000. Why the citation specific to Kilby’s award was worded as given above, because it was inconsistent and incomplete to clearly characterize Kilby’s IC invention purported to be of monolithic-IC, is inexplicable indeed. The “50 year” clause invoked by the Nobel Committee for not divulging its deliberations for 50 years for an award does not seem to exist in Nobel’s original Will. Since it has been invoked by Dr. MNC-1, it is fair to say that neither the Committee members, nor most of the readers, and for sure I shall be long gone to receive a satisfactory answer for Kilby’s inclusion and the wording of citation in his award. Hopefully the younger generations of that era in

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the future will be able to compare notes with this book, if it survives its existence until then. 10. Conclusion Based on my understanding of how the Nobel Committee works, my concluding comments and observations are as follows. 10.1. The Nobel Committee is a closed society which does not feel obligated to offer any explanation to anybody else for their decisions and actions. 10.2. The details of the nomination process can be obtained from the Nobel website. Even though the awardees may be eminently qualified to receive the Nobel Prize, the overriding influence in the selection process comes also from the campaigning and the votes of the previous Nobel Laureates and other senior people in the field(s). 10.3. Because of item 10.2, many a worthy winner is delayed to receive or even denied the Nobel Prize. Examples of some of the delayed recipients are documented in Table 7.1 copied from the original Nobel website, but they shall not be discussed here. 10.4. The quintessence of Nobel’s Will is that the Award should be given to person(s) irrespective of nationality who, during the preceding year, shall have conferred the greatest benefit on mankind. My comments on the decisions of the Nobel Committee in this appendix are restricted to the Nobel Prizes in Physics only. The Committee has a very difficult job to choose from the work of the physicists done during the period up to the preceding year of the award, and decide whether it has “conferred the greatest benefit on mankind” until then. From a pedantic point of view, the Committee does not need to consider how would it benefit mankind in the future also? Whether or not this factor is also taken into account can be debated, not knowing the workings of the inner sanctum of the Committee. However, I imagine that the Committee would take into account the impact of the work of a nominee on the future also in their deliberations to choose the Nobel Prize winner. This onus appears to be implicit in the responsibility of the Committee expected in Nobel’s Will.

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10.5. I shall not offer the critique in detail on whether the majority of the awardees did or did not meet the original criterion for the Nobel award. Nevertheless I shall offer my humble opinion as follows. In majority of the cases, the selection of the awardees and their respective Nobel citations have not met the original criterion explicitly stated in Nobel’s Will. What to say about the work of Nobel Prize winners to have “conferred the greatest benefit on mankind”, most of the work is so restrictive and esoteric that it is hard to judge that each awardees’ work has “conferred the greatest benefit even to the field of physics”. The excitement generated by a new discovery is quite short lived especially in the recent years, sometimes akin as an example to the half-life of the new elementary particles being discovered by the ever more powerful accelerators. What is their utility to have “conferred the greatest benefit on mankind”? Even their benefit to physics is not accepted universally. Nevertheless it is fair to say that the Nobel Committee has done a reasonably good job to select the awardees some of the time, if we keep the quintessential criterion of Nobel’s Will in the forefront. It is well known from the entire history of mankind that “Power corrupts; absolute power corrupts absolutely.” This cliché unfortunately applies to scientific research also, even though the absolute value of a scientific research comes from the unwritten but well accepted norm that it must be verifiable independently by other researchers. It is an established fact that the members of the august group comprising the Nobel Committee conduct their business with absolute power behind closed doors. They do not believe that they owe any explanation to anybody for their actions and decisions. If they are pressed to clarify some Nobel awards, they invoke Nobel’s Will which gives them the power to refuse to divulge any information for 50 years after the award of a Nobel Prize. Nowhere did I find this clause of 50 years in Nobel’s Will. Perhaps it may have been instituted by the Board of Directors after Nobel had died, as they did to add the 6th field, Economics, to the original fixed list of five fields, viz., Physics, Chemistry, Medicine, Literature and Peace. It is also “known” that the Committee does solicit recommendations from the ex-Nobel Laureates and other experts. Campaigning and votes from the latter groups do have a considerable influence on the selection of a Nobel Prize winner. Undoubtedly, even some of the Committee members have differences of opinion among themselves. The most proficient and authoritative speaker in the Committee usually prevails based more on forceful compaigning rather

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than facts. Sometimes irreversible errors of judgment are made, and the Nobel Prize is awarded to a less worthy person, and/or not awarded to an eminently qualified person. I shall repeat my statements from the Preface. The Nobel Committee consists of highly qualified people belonging to a highly respected institution with an impeccable record. But as one of my late very distinguished physicist professor, who had produced both PhDs and Nobel Laureates, had told me recently in a tongue-in-cheek manner, “You must not forget that they are also human beings who can be fallible sometimes!” Any organization built upon the guidelines of the original founders must of course follow them to grow and continue to “confer the greatest benefit to its business and on mankind”. However, without the checks and balances on the actions of the organizations, more often than not, they can deteriorate and perhaps decay eventually. Keeping the core values intact but having the prudence to continue to adjust them according to the needs of the present and the evolving requirements of the future, requires finesse as yet unachievable globally in the various fields of science, politics, religion, and human behavior. Returning to the Nobel Committee which is the subject of this Appendix, I have critiqued constructively and respectfully its decisions on the invention of ICs which has revolutionized the entire mankind forever. My analyses of the decisions by the Nobel Committee for the Nobel Award in Physics in 2000 have been punctilious and courteous to state the facts derived from their own public records. I am grateful to both Dr. MNC-1 and Dr. MNC-2 for their candor, help and professionalism in their written communications with me.

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References 1. Jack S. Kilby, “Miniaturized Self-Contained Circuit Modules and Method of Fabrication”, U. S. Patent No. 3,138,744, filed on May 6, 1959; Ser. No. 811,486; issued June 23, 1964. 2. R. N. Noyce, “Semiconductor Device-and Lead Structure”, U. S. Patent No. 2,981,877, filed on July 30, 1959, Ser. No. 830,507; issued on April 25, 1961. 3. Michael F. Wolff, “The genesis of the integrated circuit”, IEEE Spectrum, p. 45–53 (1976); see Jack Kilby, Fig. 1 in this paper. 4. G. W. A. Dummer: 4.1 “Electronic Components in Great Britain”, Proc. Components Symp., Washington, DC, p. 15 - 20, May 6, 1952. 4.2 “Integrated Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, P. 1412–1425, December, 1964. 5. Harwick Johnson, “Semiconductor Phase Shift Oscillator and Device”, U. S. Patent no. 2,816,228, filed on May 21, 1953; Ser. No. 356,407; issued on December 10, 1957.

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6. Richard Stewart, “Integrated Semiconductor Circuit Device”, U. S. Patent no. 3,138,747; Ser. No. 792,840; filed on February 12, 1959, issued on June 23, 1964. 7. Jack S. Kilby, “Turning Potential into Realities: The Invention of the Integrated Circuit”, Nobel Lecture, p. 474–485, Dec. 8 (2000); www.Nobelprize.org; The Nobel Prize in Physics, (co awarded with Zhores I. Alferov and Herbert Kroemer). See also Jack S. Kilby, “Autobiography”, (2000); www.Nobelprize.org. 8. J. A. Hoerni, “Method of Manufacturing Semiconductor Devices”, U. S. Patent No. 3,025,589, filed on May 1, 1959; Ser. No. 810,388; issued on March 20, 1962. J. A. Hoerni, “Semiconductor Device”, U. S. Patent No. 3,064,167, filed on May 1, 1959; Ser. No. 810,388; Divided and this application May 19, 1960, Ser. No. 30,256; issued on Nov. 13, 1962. 9. K. Lehovec, “Multiple Semiconductor Assembly”, U. S. Patent No. 3,029,366, filed on April 22, 1959; Ser. No. 805,249; issued on April 10, 1962. 10. Chih-Tang Sah, “Diffusion of Phosphorus in Silicon Oxide Film”, Shockley Semiconductor Laboratory Technical Memoranda 61, 27 pages, 8 references cited, and 14 figures, 2 March 1959. Chih-Tang Sah, Harry Sello and Douglas A. Tremere (identical to TM61 with no revisions) received on 17 June 1959 and published in the SeptemberOctober 1959 bimonthly issue of J. Phys. Chem. Solids, Vol. 11, No. 3-4, 288-298, September-October, 1959. 11. C. J. Frosch and L. Derrick, “Surface Protection and Selective Masking during Diffusion in Silicon”, J. Electrochem. Soc., Vol. 104, 547–552 (1957); Lincoln Derrick and Carl J. Frosch, “Manufacture of Silicon Devices”, U. S. Patent No. 2,804,405, filed on Dec. 24, 1954, issued on Aug. 27, 1957.

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12. Arjun N. Saxena, “Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce”, Invited Paper no. TH28.51, p.63, Program Guide,, Nano Science and Technology Institute Annual Conference, Santa Clara Convention Center, California, USA, May 2024, 2007. http://www.nsti.org/Nanotech2007/WCM2007/Saxena.pdf 13. Arjun N. Saxena, “Fundamentals of the Invention and Impact on Future Developments of Integrated Circuits and Nano-optoelectronic Devices” — Proceedings of IEEE EDS Mini-Colloquium NADENanoelectronic Devices-Present and Perspectives- Sinaia, Romania, 14th of October 2007. 14. Jeffrey Marque, “Getting History Right is an Important Matter”, Forum on Physics & Society of The American Physical Society, Vol. 36, No. 3, July 2007. 15. George Rostky, “The 30th Anniversary of the Integrated Circuit”, VLSI Systems Design, CMP Publications Inc., Vol. IX, No. 9A, September, 1988. 16. Michael Riordan and Lillian Hoddeson, “Crystal Fire”, W. W. Norton & Company, NY, ISBN: 0-393-31851-6, 1998; Michael Riordan, “The Road to Silicon was Paved with Germanium”, p. 134–142, Proceedings of the Eighth International Symposium on Silicon Materials Science and Technology, Vol. 98-1, Editors: H. R. Huff, H. Tsuya and U. G¨ osele. The Electrochemical Society, Pennington, NJ 08534-2896; ISBN: 1-56677195-1, 1998. 17. Leslie Berlin, “The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley”, p. 97–127; p. 141; Oxford University Press, ISBN–13: 978-0-19-516343-8, 2005. 18. Alex Braun, Senior Editor, Semiconductor International, August 1, 2005. 19. Jack S. Kilby, “Origins of the Integrated Circuit”, p. 342–349, Proceedings of the Eighth International Symposium on Silicon

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Materials Science and Technology, Vol. 98-1, Editors: H. R. Huff, H. Tsuya and U. Gösele. The Electrochemical Society, Pennington, NJ 08534-2896, ISBN: 1-56677-195-1, 1998. 20. Arjun N. Saxena, “Transistors to ICs to ULSICs and Beyond: Impact on Various Applications to Improve the Quality of Human Life”, IETEGolden Jubilee Compendium, p.23-31, ISBN 81-901477-2-2, 2003. 21. Jack S. Kilby, “Invention of the Integrated Circuit”, p. 648-654, IEEE Transactions on Electron Devices, Vol. ED-23, No. 7, July, 1976. 22. Jack S. Kilby, “Miniaturized Electronic Circuits”, US Patent No. 3,138,743, serial no. 791,602; issued June 23, 1964. This filing date is controversial because this patent was based on the OA whose filing date was not recorded to be on February 6, 1959. 23. Jack S. Kilby, “Miniaturized Electronic Circuits and Method of Making”, Application: No. 03/791,602 claimed to have been filed officially with the US Patent Office on Feb. 6, 1959; referred to in Kilby’s patent no. 3,138,744. On this application No. 791,602, the patent no. 3,138,743 was issued on the same date as 3,138,744 (See Table 6.2; note the difference in no. by only 1 between these two patents). 24. Hans J. Queisser: 24.1. “Materials Research in Early Silicon Valley–and Earlier Yet”, p. 4 – 25, Proceedings of the Eighth International Symposium on Silicon Materials Science and Technology, Vol. 98-1, Editors: H. R. Huff, H. Tsuya and U. G¨ osele. The Electrochemical Society, Pennington, NJ 08534-2896; ISBN: 1-56677-195-1, 1998. 24.2. Private communication at 4217 Pomona Avenue, Palo Alto, CA 94306; November 17, 2001. 24.3. Seminar at Stanford University, Stanford, CA 94305; December 11, 2001 24.4. “Slow Solar Ascent”, March meeting of German Physical Society (2004).

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25. E. Kooi, U. S. Patent No. 3,970,486, filed on Oct. 3, 1966, issued on July 20, 1976. E. Kooi, U. S. Patent No. 3,752,711, filed on June 4, 1970, issued on Aug. 14, 1973. 26. K. Lehovec 26.1. Private communication; Los Angeles, September 10, 2006. 26.2. K. Lehovec, “Invention of p-n Junction Isolation in Integrated Circuits”, p. 495-496, IEEE Transactions on Electron Devices, Vol. ED-25, No. 4, April, 1978. [Ref. no. 6 in Lehovec’s paper: “J. S. Kilby, US Application 811476 filed on May 6, 1959. This is the key patent no. 3,138,744 of Kilby; refiled as US Application 218-206 on Aug. 16, 1962.” Nothing happened on this refiling.] [Ref. no. 7 in Lehovec’s paper: — (Kilby), “Miniaturized electronic circuits,” US Patent 3,183,743, issued June 23, 1964, filed Feb. 6, 1959. This is incorrect; it is NOT Kilby’s patent. This US patent no.3,183,743, “Sheet Cutting Machine”, was filed by Francis O’Donnell, Francis Hallatt, Arthur Hallatt, and Fritz Doerscheln on July 17, 1962, Ser. No. 210,421, and it was issued on May 18, 1965. This has nothing to do with ICs. The correct patent no. should have been 3,138,743.] 27. A. N. Saxena, “Roadmap of Future Monolithic ICs”, VMIC State-ofthe-Art Seminar, p. 8 (1989); A. N. Saxena, K. Ramkumar, S. K. Ghosh & M. A. Bourgeois, “Technology and Reliability Issues of Multilevel Interconnects in Bipolar, BiCMOS and CMOS VLSIC/ULSIC”, Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), p. 12-19 (1993). 28. Arjun N. Saxena, “Current status and future directions of ultra large scale integrated circuits and the crucial role of adhesion science and technology”, First International Congress on Adhesion Science and Technology, Mittal Festschrift , p.137-146, W. J. Van Ooij and H. R. Anderson, Jr. (Eds.), VSP, ISBN 90-6764-291-6, 1998.

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29. E. Bornett, Certifying Officer, USPTO, to Dr. Arjun N. Saxena, “This is to certify that annexed hereto is a true copy from the records of the United States Patent and Trademark Office of those papers of the below identified patent application that met the requirements to be granted a filing date under 35USC111. Application: No. 03/791,602; Filing date: May 06, 1959.” Sent by USPTO to Dr. Saxena on September 26, 2005; given as Fig. 5 in this paper. 30. Customer Service Department, USPTO, to Dr. Arjun N. Saxena, “The product or service you requested cannot be fulfilled because the application #03/791,602 does not have an official filing date.” Sent by USPTO to Dr. Saxena on November 02, 2005; given as Fig. 6 in this paper. 31. J. S. Kilby, “Semiconductor Structure Fabrication”, US Patent No. 3,072,832, filed May 6, 1959; issued Jan. 8, 1963. 32. J. S. Kilby, “Miniature Semiconductor Integrated Circuit”, US Patent No. 3,115,581, filed May 6, 1959; issued Dec. 24, 1963. 33. J. T. Last, “Solid State Circuitry Having Discrete Regions of Semiconductor Material Isolated by an Insulating Material”, US Patent No. 3,158,788, filed Aug. 15, 1960, Ser. No. 49,717; issued Nov. 24, 1964. 34. J. S. Kilby, “Method of Making Miniaturized Electronic Circuits”, US Patent No. 3,261,081, original filed on Feb. 6, 1959; divided and this application filed on March 16, 1964, issued on July 19, 1966 35. J. T. Last, “Method of Making Solid State Circuitry”, US Patent no. 3,313,013; Original filed Aug. 15, 1960; Divided and this application Oct. 5, 1964; issued April 11, 1967. 36. A. N. Saxena, “Method of Coating Selective Areas of the Surface of a Body”, U. S. Patent No. 3,687,722, filed on March 10, 1971, issued on Aug. 29, 1972. 37. Arjun N. Saxena, “Methods for and Products of Growth of SingleCrystal on Arrayed Nucleation Sites (SCANS) Defined in Nucleation

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Unfriendly Substrates”, U. S. Patent No. 6,110,278, filed on Aug. 10, 1998, issued on Aug. 29, 2000. 38. Arjun N. Saxena, “Semiconductor Device with Single Crystal Films Grown on Arrayed Nucleation Sites on Amorphous and/or Non-Single Crystal Surfaces”, U. S. Patent No. 6,392,253, filed on Aug. 6, 1999, issued on May 21, 2002. 39. T. R. Reid, “The Chip–How Two Americans Invented the Microchip and Launched a Revolution”, Random House, New York; ISBN 0-3757528-3; TK7874.R43 (2001). 40. Thomas H. Lee, “The (Pre-) History of the Integrated Circuit: A Random Walk”, IEEE SSCS News, Vol. 12, No. 2, Spring 2007. 41. David C. Brock, “Understanding Moore’s Law: Four Decades of Innovation”, Chemical Heritage Press, Philadelphia, PA, p. 3–108, ISBN 0-941901-41-6, 2006. 42. Bo Lojek, “History of Semiconductor Engineering”, ISBN-10-3-54034257-5, Springer (2007). 43. Robert N. Noyce, “Microelectronics”, Scientific American, Vol. 237, p. 63 (1977). 44. Jack S. Kilby, “The Integrated Circuit’s Early History”, p. 109–111, Proceedings of the IEEE, Vol. 88, No. 1, January, 2000. 45. G. E. Moore, “Progress in Digital Integrated Electronics”, IEDM Technical Digest, 21, p. 11 - 13 (1975); G. E. Moore, “Lithography and the Future of Moore’s Law”, Optical/Laser Microlithography VIII: Proc. SPIE, 2440, p. 2 - 17, Feb. 20 (1995); G. E. Moore, “No exponential is forever - some approaching limits to VLSI technology”, Keynote address, VLSI Multilevel Interconnection Conference (VMIC), unpublished (1993). 46. G. E. Moore, “Moore’s Law at 40”, Chapter 7, p. 67–84, “Understanding Moore’s Law: Four Decades of Innovation”, Edited by

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David C. Brock, Chemical Heritage Press, Philadelphia, PA, ISBN 0941901-41-6, 2006. 47. G. E. Moore, “The Role of Fairchild in Silicon Technology in the Early Days of Silicon Valley”, Proc. IEEE, Vol. 86, p. 53 (1998). 48. Arjun N. Saxena, “Technologies to Extend the Validity of Moore’s Law: New Business Opportunities in Microelectronics”, p. 1 -2, & p. 1–7, June 2 (1998); private communication to Gordon Moore, Intel, June 4 (1998). 49. Marvin J. Moss, “Present for the Birth of the Integrated Circuit”, IEEE Life Member Newsletter, p. 4, April, 2007. 50. R. Norman, J. Last and I. Haas, “Solid-State Micrologic Elements”, IRE Solid State Conference, Feb. 12, 1960; cf. Lojek,42 p. 137, Fig. 4.33. 51. Michael Riordan, “The Silicon Dioxide Solution”, IEEE Spectrum, p. 50 – 56, December, 2007. 52. Homer O. Blair, “Famous United States Patents”, Pierce Law Center, 2 White Street, Concord, NH 03.01; www.PierceLaw.edu; also personal communication (2006). 53. Robert Norman (personal communication). 54. Kurt Lehovec (personal communication; 1962; August 9, 2007). 55. Gordon Moore (personal communication; May 30, 2006). 56. Chih-Tang Sah, “Evolution of the MOS Transistor–From Conception to VLSI”, Proceedings of the IEEE, Vol. 76, p. 1280–1326 (1988). 57. A. N. Saxena and K. L. Mittal, “Optical and Dielectric Constants of Hafnium and Its Anodic Oxide Films”, Appl. Phys. Letters, 46, 2788 (1975).

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58. Gordon E. Moore, “Cramming More Components Onto Integrated Circuits”, Electronics, 38:8, 114–117 (1965). 59. Tekla S. Perry, “Gordon Moore’s Next Act”, IEEE Spectrum, 45, 40–43 (2008). 60. Sally Adee, “Thirty-seven Years of Moore’s Law”, IEEE Spectrum, 45, 56 (2008). 61. Federico Faggin, “Guest Editor’s Introduction: The Microprocessor”, IEEE Micro, 7–9, December, 1996; Federico Faggin, Marcial E. Hoff Jr., Stanley Mazor and Masatoshi Shima, “The History of the 4004”, IEEE Micro. 10–20, December, 1996. 62. Arjun Saxena: ”Law of the Famous” - The famous are given most if not all the credit, and a large number of others who also made key contributions to the success are often ignored. 63. Chih-Tang Sah and Bin B. Jie, monthly articles on the bipolar theory of the nanometer field-effect transistor, with the double-gate thin-base MOSFET or FinFET; complete theoretical analyses reported in the monthly issues of the Chinese Journal of Semiconductors, from October 2007 to December 2008; further articles to continue to be published. 64. M. M. Atalla, M. Tannenbaum, and E. J. Scheibner, ”Stabilization of Silicon Surface by Thermally Grown Oxides,” Bell Syst. Tech. I., vol. 38, no. 3, p. 123, May 1959. For a recent review and analysis of the interface state properties of oxidized silicon surfaces, see [65 below]. 65. C. T. Sah, ”Interface traps on Si surface,” in Properties of SILICON. London, England: INSPEC, The Institution of Electrical Engineers, section 17.1, pp. 499-507, May 1988. Available from I NSPEC Dept., IEEE Service Center, 455 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331. 66. V. Gopal K. Reddi (personal communication; 1967; September 24, 2006).

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67. J. A. Hoerni, ”Planar silicon transistors and diodes,” presented at the 1960 IRE International Electron Device Meeting, Oct. 27-29, 1960. Technical Article and Paper Series, No. TP-14, 9 pp., 1961. Fairchild Semiconductor Corporation, 645 Whisman Road, Mountain View, CA. 68. G. C. Dacey and I. M. Ross, ”Unipolar field-effect transistor,” Proc. IRE, vol. 41, no. 8, pp. 970-979, Aug. 1953. 69. C. T. Sah (personal communication; many e-mails in 2007 and 2008). 70. Chih-Tang Sah, Fundamentals of Solid-State Electronics, World Scientific Publishing Company, 2001, 1001pp. On metal/semiconductor barrier current-voltage theory and the Mott and Bethe Barrier theories, see Sections 560 to 564 on pages 474 to 497. For the Bethe and Mott theories, see respectively Section 562 on pages 483 to 489 and Section 564 on pages 493 to 497. 71. Joel N. Shurkin, “Broken Genius: The rise and fall of William Shockley, creator of the electronic age,” Macmillan, N. Y. (2008).

List of Tables 1.

Table 1.1: Key requirements for making the monolithic-IC and whether or not they were met by Kilby and Noyce in their respective inventions

5

2.

Table 5.1: Summary of IC inventions by Kilby and Noyce.

72

3.

Table 5.2: Filing and issue dates of patents and publications relevant to IC inventions (Updated version for this book)

78

4.

Table 5.3: Filing and issue dates of patents and publications relevant to IC inventions (Copied from the earlier NSTI paper12 for the sake of comparison with the above Table 5.2. The references in the following table correspond to those in the NSTI paper.12 )

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505

5.

Table 7.1: Important items of Kilby’s Original Application No. 791,602, analyses and comments on related patents based on it.

141

6.

Table 7.2: Summary of comparisons between Kilby’s two IC patent nos. 3,138,743 and 3,138,744, and a few additional comments.

166

7.

Table 9.1: Similarity between and limitations in both Dummer’s and Kilby’s concepts.

263

8.

Table 10.1: List of patents of Jack Kilby on and beyond the invention of ICs.

314

9.

Table 10.2: List of patents of Bob Noyce on and beyond the invention of ICs.

318

10.

Table 13.1: Total world market of all Si products including the ICs.

344

11.

Table 15.1: Combined summary of several facts relevant to the invention of the ICs.

360

12.

Table App. 2.1: Summary of comparisons of Kilby, Noyce and Saxena’s IC inventions.

396

13.

Table App. 2.2: Documents and patents of Saxena on and beyond the invention of ICs.

400

14.

Table App. 7.1: The entire list of the Nobel Awards in Physics from the very beginning in 1901 to 2007.

477

15.

Table App. 7.2: The entire list of all Nobel Prize in Physics winners to 3-person awardees from the very beginning with their citations and distribution of award money.

481

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List of Figures 1.

Fig. 1.1: Kilby’s reduction to practice of his invention of IC.

6

2.

Fig. 1.2: Reduction to practice of Noyce’s invention of IC.

7

3.

Fig. 3.1: A typical cross section of twin-tub CMOS structure (not drawn to scale).

42

4.

Fig. 3.2: Roadmap of ICs.20,27

48

5.

Fig. 3.3: Roadmap of ICs.20,27 Same as Fig. 3.2, but it also gives additional comments on the role of scaling, multilevel interconnections, and the device integration regimes. The largest segment of the present ULSIC business of multi-hundred dollar volume is Si CMOS.

49

6.

Fig. 3.4: Cross section of an UPIC chip38 using both Si and compound semiconductors. It shows four layers of devices fabricated on single crystal films of Si and compound semiconductors, and connected to each other with multilevel interconnects.

56

7.

Fig. 5.1: Figs. 1-4 copied from Kilby’s1 patent no. 3,138,744. Note the mesa structures in Kilby’s Figs. 3 & 4 (instead of the planar structures which are necessary in monolithic-ICs).

86

8.

Fig. 5.2: shows Figs. 1-5 copied from Kilby’s23 patent application no. 03/791,602. Note the mesa structures in Kilby’s Figs. 4 & 5 (instead of the planar structures which are necessary in monolithic-ICs).

87

9.

Fig. 5.3: Figs. 6 & 8 copied from Kilby’s23 patent application no. 03/791,602. Note the wire-bonding in Kilby’s Figs. 6 & 8 (instead of the monolithic interconnects which are necessary in monolithic-ICs).

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507

10.

Fig. 5.4: Figs. 3, 4 & 5 copied from Noyce’s2 patent no. 2,981,877. Note the planar structures and monolithic interconnects in Noyce’s Figs. 3 and 4 (instead of the mesa structures and wire-bonding). Fig. 5 shows the circuit diagram of Noyce’s invention.

89

11.

Fig. 5.5: Response from E. Bornett,29 Certifying Officer, USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on September 26, 2005, regarding its filing date to be May 6, 1959 (NOT Feb. 06, 1959 claimed by Kilby.1,19,23

90

12.

Fig. 5.6: Response from Customer Service Department,30 USPTO, sent to Saxena on Kilby’s Application No. 03/791,602 on November 02, 2005, stating that it “does not have an official filing date”.

91

13.

Fig. 13.1: A semi-log plot of transistors per die (chip) versus time for the early data of 1965 until the recent years and beyond. The linear behavior according to Moore’s Law is followed in various segments which were influenced by the associated technologies used for the chips.

343

14.

Fig. 15.1: Communication from USPTO to Arjun N. Saxena, dated July 03, 2008, received by Saxena on July 10, 2008, regarding Saxena’s attempts to get the “Certified Copy each of the File History of patent numbers 3,138,743 and 3,138,744, both being based on the original application number 03,791,603” from the USPTO. The response from the USPTO states, “We are unable to fill your order because the files for the above patent numbers above are unavailable due to being in the lost category. . . . ”

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List of Original Patents, Applications and Papers 1.

Jack Kilby23 : Original Application no. 791,602, “Miniaturized Electronic Circuits and Method of Making”; claimed to have been filed on February 6, 1959, but the recorded filing date by USPTO was May 6, 1959. No patent action was taken and no patent was issued on this application per se. (See Saxena.29,30 ) [Given at the end of Chapter 7]

189

2.

Jack Kilby23 : US patent no. 3,138,743, “Miniaturized Electronic Circuits”; filed February 6, 1959; serial no. 791,602; issued June 23, 1964. This filing date is controversial because this patent was based on the OA whose filing date was not recorded to be on February 6, 1959. [Given at the end of Chapter 7]

211

3.

Jack Kilby1 : US patent no. 3,138,744, “Miniaturized Self-contained Circuit Modules and Method of Fabrication”; filed May 6, 1959; serial no. 811,486; issued June 23, 1964. [Given at the end of Chapter 7]

220

4.

Jack Kilby34 : US patent no. 3,261,081, “Method of Making Miniaturized Electronic Circuits”; USPTO wrote on the front page of the patent, “Original Filed Feb. 6, 1959”, and “July 19, 1966” as the patented date. On inside above column 1, the USPTO wrote “Original application February 6, 1959, Ser. No, 791,602, now Patent No. 3,138,743, dated June 23, 1964. Divided and this application Mar. 16, 1964, Ser. No. 352,380”, for which this patent no. 3,261,081 was issued on July 19, 1966. As stated in section 1.1, the filing date of the OA was not recorded by the USPTO to be Feb. 6, 1959. [Given at the end of Chapter 7]

226

5.

Robert Noyce2 : US Patent no. 2,981,877, “SEMICONDUCTOR DEVICE-AND-LEAD STRUCTURE”, filed July 30, 1959; serial no. 830,507;issued April 25, 1961. [Given at the end of Chapter 8]

252

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509

6.

Jean Hoerni8 : US Patent no. 3,025,589, “Method of Manufacturing Semiconductor Devices, filed May 1, 1959; Ser. No. 810,388; issued March 20, 1962. [Given at the end of Chapter 6.]

107

7.

Jean Hoerni8 : US Patent no. 3,064,167, “Semiconductor Device”; filed May 1, 1959; Ser. No. 810,388. Divided and this application May 19, 1960, Ser. No. 30,256; issued Nov. 13, 1962. [Given at the end of Chapter 6.]

113

8.

Kurt Lehovec9 : US Patent no. 3,029,366, “Multiple Semiconductor Assembly”; filed April 22, 1959; Ser. No. 805,249; issued April 10, 1962. [Given at the end of Chapter 6.]

119

9.

Kurt Lehovec,26 “Invention of p-n Junction Isolation in Integrated Circuits”, p. 495-496, IEEE Transactions on Electron Devices, Vol. ED-25, No. 4, April, 1978. [Given at the end of Chapter 6.]

123

10.

Copy of the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec. See reference 8 of Lehovec’s paper,26 given as “Decision of the Board of Interferences in the patent interference Kilby vs. Lehovec,” No. 93612, April 5, 1966. [Given at the end of Chapter 6.]

124

11.

Geoffrey Dummer4.1 : Reprint of the paper, “Electronic Components in Great Britain”, Proc. Components Symp., Washington, DC, p. 15–20, May 6, 1952. [Given at the end of Chapter 9.]

278

12.

Geoffrey Dummer4.2 : Reprint of the paper “Integrated Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, p. 1412 – 1425, December, 1964. [Given at the end of Chapter 9.]

284

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13.

Harwick Johnson5 : US Patent no. 2,816,228, “Semiconductor Phase Shift Oscillator and Device”, filed on may 21, 1953, Serial No. 356,407; issued on December 10, 1957. [Given at the end of Chapter 9.]

298

14.

Richard Stewart,6 “Integrated Semiconductor Circuit Device”, US Patent no. 3,138,747; filed on February 12, 1959; Ser. No. 792,840; issued on June 23, 1964. [Given at the end of Chapter 9.]

301

15.

Jay Last,33 “Solid State Circuitry Having Discrete Regions of Semi-Conductor Material Isolated by an Insulating Material”, US Patent no. 3,158,788, filed Aug. 15, 1960, Ser. No. 49,717, issued Nov. 24, 1964. [Given at the end of Chapter 9.]

305

16.

Jeffrey Marque,14 “Getting History Right is an Important Matter”, F O R U M O N P H Y S I C S & S O C I E T Y of The American Physical Society, Vol. 36, No. 3, July 2007. [Given at the end of Chapter 11.]

330

17.

Marvin J. Moss,49 “Present for the Birth of the Integrated Circuit”, IEEE Life Member Newsletter, p. 4, April, 2007. [Given at the end of Chapter 11.]

332

18.

Arjun Saxena, “Developments in Physics, Microelectronics and a Few Other Technologies in The Past 55 Years - Dr. Arjun Saxena’s Contributions (Listed in chronological order; only a few publications given.”

379

19.

T. N. Dave and A. N. Saxena, “A Modification of the Model 50 Pulse Generator”, Current Science, Vol. 22, p. 199, July, 1953. [Given in Appendix 2, section 9]

407

20.

The announcement of 1954 lecture. [Given in Appendix 2; Section 10]

409

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511

21.

Copy of the original handwritten notes of Saxena; refers to his paper in 1953 also. [Given in Appendix 2; Section 11]

410

22.

Confirmation of Saxena’s description of his concepts of miniaturization leading to ICs by 5 qualified attendees of his lecture in 1954. [Given in Appendix 2; Section 12]

413

23.

Arjun N. Saxena,12 “Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce”, NSTI. [Given in Appendix 3]

420

24.

Arjun N. Saxena,13 “Fundamentals of the Invention and Impact on Future Developments of Integrated Circuits and Nano-optoelectronic Devices”, Proc. IEEE EDS Mini-Colloquium NADE. [Given in Appendix 4]

436

25.

Arjun N. Saxena,20 “Transistors to ICs to ULSICs and Beyond: Impact on Various Applications to Improve the Quality of Human Life”, IETE — Golden Jubilee Compendium. [Given in Appendix 5]

452

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Index

Acknowledgement — After the fact, xi Peers, xxv Publishers, 519 Adcock, W. A., 265 Adee, Sally, 503 Advanced Micro Devices (AMD), xxi Alferov, Zhores, xiv, 465, 466, 487 Aluminum (Al), xvii Apollo, 364 Atalla, M. M. (John), 97

Braun, Alex, 135 Brock, David, 20, 341 Chip, 47, 378 Chowdhry, S. V. S., 410, 414 CMOS IC Evolution (Sah), 48 Largest segment, 48 Nano-scale, 51 Twin-Tub, 42 Combined summary, 355, 358. Kilby/Noyce/Dummer/Saxena, 360 Kilby/Noyce/Saxena, 396 Conclusions from analyses of all facts, 355 Court of Customs and Patent Appeals (CCPA), 369, 128 2D-Si-ULSICs, 50, 80 3D-IC, 18, 337

Bardeen, John, xv, 340 Citation of Nobel Prize, 367 Basic concept of inventions Kilby, Jack, 23 Dummer, Geoffrey, 24 Johnson, Harwick, 24 Saxena, Arjun, 27 Stewart, Richard, 25 Beckman, Arnold, xxiv Beckman Instruments Corporation, xxiv Bell Labs, 44, 262 Berlin, Leslie, 20, 136 Bipolar transistors, 100 Blair, Homer O., 339 Blank, Julius, xxvi Board of Interference Decision, 107, 125, 128 Borovoy, Roger, xxvi Brattain, Walter, xv, 340 Citation of Nobel Prize, 367

Department of Defense (DOD), 363 Derrick, Lincoln, 12, 97, 496 Dhar, J. L., 415 Discovery, 32 Discussion, 321 Harwick’s patent, 237 Kilby’s OA and patents, 322 Kilby’s filing date, 324 Marque’s paper, 330 Moss’ report, 328, 332 Noyce’s patent, 321 Stewart’s patent, 327

513

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Documented facts, 16 Dr. MNC-1, 333, 338 Dr. MNC-2, 333, 339 Dummer, Geoffrey, xi, 262 Concepts of, 264 Comparison with Kilby, 263 Early British work, 265 Reprint of papers, 278, 284 Edison, Thomas, 339 Einstein, Albert, 14, 340 Epilogue, 374 Evolution of miniaturization, 41, 47 Faggin, Federico, xxvi, 49 Fairchild, xvii Famous US patents, 339 Farnsworth, Philo, 339 Fermi, Enrico, 339 Ford, Henry, 339 Forest, Lee de, 339 Franklin, P. J., 265 Frosch, Carl. J, 12, 97 Funding to write book, xxv Germanium (Ge), xiii Ghoshal, S. N., xxvi Gimlan, Gideon, xxvi Gold (Au), xiii Grinich, Vic, xxiii, 98 Gunn, J. B., 340 Historical facts, 355, 362 History, Getting Right, xi, 13 Why important?, 15 File History lost by USPTO, 369 Hitler, Adolf, 14 Hoddeson, Lillian, 20 Hoerni, Jean, xvii, 12, 95, 107, 113, 262 Credited for Si planar technology, 356 Four sets of experiments, 99 IEDM, 101 Key points of patents, 104, 105

Patent no. 3,025,589, 107 Patent no. 3,064,167, 113 Planar technology, ix, 5, 12, 66, 95 Work of others, 97, 98 Hoff Jr., Ted, 49 Hopkins, Samuel, 339 Horsey, E. F., 265 Hybrid-IC, 43, 46, 59, 60 With packaged chips, 61 With unpackaged chips, 61 Onset of ICs, 62 IBM360, 63 IBM370, 67 IBM Solid Modules, 62, 69 IC Technology, Summary of, 69, 70, 72 IEDM, 101 ILDs, 43 Improvement, 36 Inexplicable decisions, 356 Kilby, 356 Nobel Committee, 357 Noyce, 358 Other contributors etc, 358 USPTO, 356 Integrated Circuits (IC), vii, 44 Evolution to VLSICs to ULSICs, 47 Key Requirements, 4 Roadmap of, 48 Summary of fabrication, 69 Summary of inventions, 72 What is it?, xi, 3 When?, 45 World market, 344 Intel, xxi, 19 Interconnections — Monolithic ICs, 5, 66 Hybrid ICs, 61 Invention, Importance of IC, viii, 32 Isolation p-n junction, 95 LOCOS, 5 Trench, 5

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Index

Jie, Bin B., 503 Johnson, Harwick, xiii, 261, 267 Patent no. 2,816,228, 298 Kilby, Jack, x Choice of semiconductor, 137 Comparison with Dummer, 263 Contribution beyond invention, 313, 314 Controversy over filing dates, 83 Dialectic approach to explain, 315 Discussion: OA and patents, 322 Importance of filing date, 325 Monolithic concept: controversial, 324 Monolithic interconnects, 325 P-N Junction isolation, 325 Stewart’s patent, 327 35 USC 112, 326 Fabrication method, 138 File History of Patents (Lost by USPTO), 129, 369 Important facts and comments, 130 Insulating layers, 138 Interconnects, 139 Key claims, 135 Key figures, 134 Key Points, xii Monolithic concept: controversial, 324 Nobel Award, 132, 333, 465, 466, 487 Original application (OA), 141 Original patents, 134, 211, 220, 226 Original photograph of invention, 132 Overall comments, 140 Patent no. 3,138,743, 211 Patent no. 3,138,744, 220 Patent no. 3,261,081, 226 Patents: Invention and Beyond, 314 Reduction to practice, 6, 135

2nd reading

Similarity to Dummer, 131 Similarity to Johnson, 267 Similarity to Stewart, 130 Sole credit, 6 Strong and weak points, 75. Summary of invention, 72, 134 Violation of 35USC112, 132, 139 Kleiner, Gene, xxiii, 13 Kooi, Else, 5, 78 Kroemer, Herbert, xiv, 465, 466, 487 Last, Jay, xvii, 261, 276 Patent no. 3,158,788, 305 Laue, Max von, 14 Law of the Famous, 97, 503 Lee, Tom, 20 Lehovec, Kurt, xiii, 95, 119 Key points of patents, 105 Final hearing Kilby vs. Lehovec, 124 Invented p-n isolation, 356 Isolation, p-n, 95 Patent no. 3,029,366, 119 Reprint of paper, 123 Linvill, John, xxiv LOCOS, 5 Lojek, Bo, 20 Marconi, Guglielmo, 339 Marque, Jeffrey, 13, 321 Original paper, 330 Masuhara, Toshiaki (Toshi), xxvi Maydan, Dan, xxvi Mazor, Stanley, 49 Members of Nobel Committee Dr. MNC-1, 8 Dr. MNC-2, 10 Mesa Technology, 70, 127, 262 Methodology of analyses, 92 Microprocessors, 49 Miniaturization present status, 42 need and evolution, 43 Minimum geometries, 4 Minuteman missile, 364

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Mittal, K. L., 502 Monolithic-IC, 43, 59, 65 Definition, 4 Key Requirements for making, 5 Moore, Gordon, xii, 341 Contributions beyond invention, 346 Moore’s Law, 4, 341, 343 Extension of validity, 344 Figure, 343 Key observations, 344 Limitations, 344 Valid for 2D-ICs only, 81, 344 Morton, Jack, 38 Moss, Marvin, 136, 328, 332 Mystery of invention of ICs, 8 Nobel Committee, xii, 333 Communications with, xvi, 333, 338, 339 Concluding comments on, 492 Nobel Prize in Physics, 333 Awarded throughout history (1901 to 2007), 475, 477 3-person awards, 11, 336, 480 All distributions and citations, 336, 481 Entire list of, 481 Sequence of listing names, 486 Citation for Alferov, Kroemer and Kilby, 9, 336, 465, 466, 487 Citation for Alferov and Kroemer, 10, 465, 466, 487 Citation for Kilby, 10, 335, 336, 465, 466, 487 Citation for Shockley, Bardeen and Brattain, 367 Concluding comments on Nobel’s Will and Awards, 492 Detailed discussion of award to Alferov, Kroemer and Kilby, 487 Division of Prize Money, xiv, 336, 481

Engineering missing from Nobel Awards, 474 For inventing ICs, 335 Highlights of Awards, 335, 473 History of, 465 Members of Nobel Committee (MNC), 333 Overall comments on 3-person awards, 486 Raman, C. V., 475 Royal Swedish Academy of Sciences, 335 Updated summary of Awards, 473 Nobel’s Will, xiv, 9, 334, 468 Engineering missing, 474 Excerpts from, 472 Original Will, 469 Norman, Robert (Bob), xxvi Noyce, Bob, x, 237, 340, 367 Choice of semiconductor, 241 Contribution beyond invention, 331, 318 Dialectic approach for explanation, 318 Detailed analyses of claims, 246 Fabrication of devices, 242 Impact of 35 USC 112, 245 Insulating layers, 242 Interconnects, 244 Invented monolithic-IC, 355 Isolation of devices, 243 Key claims, 239 Key figures, 239 Key patent, 252 Key Points, xvii Original patent, 237 Overall comments, 245 Patent no. 2,981,877, 252 Patents: Invention and Beyond, 318 Reduction to practice, 7, 241 Sole credit, 6

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Index

Strong and weak points, 76 Summary of invention, 72, 238 Onset of miniaturized ICs, 62 Original Application (OA) of Kilby, xiv, 127, 140, 189 Detailed analysis of claims, 140 Other contributors/efforts, xviii, 261 Also gave IC concepts, 356 Other semiconductors, 81 Pandya, T. P., 416 Panofsky, W. K. H. (Pief), xxvi Patent filings, 78, 82 Patents, 37 Additional important facts, 84 Famous US Patents, 339 Filing and issue dates, 78 Hoerni — Patent no. 3,025,589, 107 Johnson — Patent no. 2,816,228, 298 Patent no. 3,064,167, 113 Kilby, 128, 152, 159, 179, 189, 211, 220, 226 Comparison between two patents, 166 Controversy over filing dates, 83, 80, 91 Original Application (OA), 189 Patent no. 3,138,743, 211 Patent no. 3,138,744, 220 Patent no. 3,261,081, 226 Last — Patent no. 3,158,788, 305 Lehovec — Patent no. 3,029,366, 119 Noyce — Patent no. 2,981,877, 252 Saxena, 82, 400 Stewart — Patent no. 3,138,747, 301 Perry, Tekla, 503 Physical Review, xxiv Physical Review Letters, xxiv

2nd reading

Pierce Law Center, 327 Planar Technology, ix “dish” junctions, 99 Hoerni, 5, 12, 66, 95, 262 IEDM, 101 Key input, 99 Sah’s key work, 100 Sequence and serendipity, 97, 99 Plessey Company, 266 Pradhan, B. P., 417 Printed circuit boards (PCBs), 44 Proceedings of Physical Society (London), xxiv Publications, 38 Quality of Human Life (QHL), 32, 349 Banking, 352 Communications/Internet/GPS, 352 Education/Careers, 351 Effect of invention of ICs, 349 Electricity/Oil/Nuclear Power, 351 Entertainment/TV/News, 352 Family/Progeny-Pleasure, 351 Food and Water, 351 Global Business, 353 Good Government, 352 Healthcare, 350 Job/Business, 351 Law & Order, 352 Predictable Future, 353 Religion/Philosophy/Ethics/ Morality, 353 Safe Environment, 352 Secure housing/Neighborhoods, 351 Strong Defense, 353 Travel, 351 Queisser, Hans J., 498 Ralls, John, xvii, 102 RCA, xi Reddi, V. Gopal K., xxvi, 503

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Reid, T. R., 20 Riordan, Michael, 12 Roberts, C. Sheldon, xxvi Ross, Ian, 262 Rostky, George, 20 Royal Radar Establishment (RRE), 262 Russians, 363 Sah, C-T (Tom), xxvi, 12, 48, 97, 100 Saxena, Arjun N., xxvi, 269 Comparisons: Kilby, Noyce, Saxena, 396, 398 Documents, 395, 399 Patents beyond invention of ICs, 400 Strong and weak points, 359, 362 Saxena, Karen, xxvi Saxena, M. C., 418 Saxena, Veera, v, xxvi Scheibner, E. J., 503 Section 35 USC 112, 132 Impact on Kilby’s invention, 132, 139 Sello, Harry, 496 Shima, Masatoshi, 49 Shockley, William, xv, 96, 340 Citation of Nobel Prize, 367 Shockley Semiconductor Laboratory, xxiv Shockley Transistor Corporation, xxiv Shurkin, Joel, xxiv, 504 Silicon (Si), xiii Importance over Ge etc, 96 Silicon gate technology, 49 Silicon Valley, xxi Sinatra, Frank, 378 Solar cells, 46

Sole credit, x Sprague Electric Company, xx Sputnik, 363 Stanford University, xxiv Stewart, Richard, xiii, 261, 269 Analyses of claims, 271 Overall comments, 271 Patent no. 3,138,747, 301 Summary of invention, 271 Sze, Simon, xxvi Tanenbaum, M., 503 Texas Instruments (TI), xi Trade secrets, 39 Tremere, Doug, 496 ULSIC, ix, 41 Unanswered questions of IC invention, 355, 368 University of Southern California (USC), xxi UPIC, 18, 55, 81 Advantages over 2D-ICs, 56 USPTO, x, 90, 91 Bornett, E., 90 Certified copy of File History lost, 129, 369 Customer Service Department, 91 VLSIC, 41 Wafer sizes, 344 Walker, Rob, xxvi Wanlass, Frank, 102 Wolff, Michael, 8 World Market for ICs, 344 Zworykin, Vladimir, 340

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1. Chapter 6: Hoerni and Lehovec Inventions Reprint of the paper by Kurt Lehovec26 , “Invention of p-n Junction Isolation in Integrated Circuits”, p. 495–496, IEEE Transactions on Electron Devices, Vol. ED-25, No. 4, April, 1978. c 2007 IEEE. Reprinted, with permission, Kurt Lehovec, “Invention of p-n Junction Isolation in Integrated Circuits”, p. 495–496, IEEE Transactions on Electron Devices, Vol. ED-25, No. 4, April, 1978. Additional approval to publish by Dr. Kurt Lehovec was obtained from him on October 28, 2006.

2. Chapter 6: Hoerni and Lehovec Inventions Copy of the first page of the final hearing on March 16, 1966, of Kilby vs. Lehovec. See reference 8 of Lehovec’s paper26 , given as “Decision of the Board of Interferences in the patent interference Kilby vs. Lehovec,” No. 93612, April 5, 1966. Reprinted, with permission, to publish from Dr. Kurt Lehovec obtained from him on October 28, 2006.

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3. Chapter 9: Other efforts to invent and/or contribute to the invention of ICs. Reprint of the paper by G. W. A. Dummer4.2 , “Integrated Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, p. 1412–1425, December, 1964. c 2007 IEEE. Reprinted, with permission, G. W. A. Dummer, “Integrated “ Electronics Development in the United Kingdom and Western Europe”, Proc. IEEE, P. 1412–1425, December, 1964. Additional approval to publish by Dr. Geoffrey Dummer could not be obtained; according to IEEE records, he would be more than 100 years old if he was alive.

4. Chapter 11: Discussion 2.1 Copy of the original article14 by Jeffrey Marque, “Getting History Right is an Important Matter”, F O R U M O N P H Y S I C S & S O C I E T Y of The American Physical Society, Vol. 36, No. 3, July 2007. Reprinted the entire original publication verbatim with permission, from Dr. Jeffrey Marque, Editor, Forum on Physics & Society of The American Physical Society. 2.2 Copy of Marvin J. Moss49 , “Present for the Birth of the Integrated Circuit”, IEEE Life Member Newsletter, p. 4, April, 2007. c 2007 IEEE. Reprinted, with permission, Marvin J. Moss, “Present for “ the Birth of the Integrated Circuit”, IEEE Life Member Newsletter, p. 4, April, 2007. Additional approval to publish was given by Dr. Marvin J. Moss (Retired).

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5. Appendix 4: Fundamentals of the Invention and Impact on Future Developments of Integrated Circuits and Nanooptoelectronic Devices c 2007 IEEE. Reprinted, with permission, Arjun N. Saxena, “Fundamentals of the Invention and Impact on Future Developments of Integrated Circuits and Nano-optoelectronic Devices” — Proceedings of IEEE EDS Mini-Colloquium NADE-Nanoelectronic Devices-Present and PerspectivesSinaia, Romania, 14th of October 2007. According to IEEE policies, the above permission is not required since I am its author. Nevertheless, it was obtained for the sake of formality. Additional approval to publish was given by Marcel D. Profirescu, Professor Faculty of Electronics, Telecommunications and Information Technology University Politehnica of Bucharest, Romania; IEEE Electron Device Society Vice-Chair, EDS Europe, Africa and Middle East SRC Chair, ED Romania Chapter.

6. Appendix 5: Transistors to ICs and Beyond: Impact on Various Applications to Improve the Quality of Human Life c 2003, with the permission from the IETE ‘Golden Jubilee Compendium: “ Evolution and Perspective — Electronics, Telecommunications, IT and Broadcasting’ by The Institution of Electronics and Telecommunications Engineers (IETE) bearing ISBN 81-901477-2-2; p. 23–31 (2003).”

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About the Author

Dr. Arjun N. Saxena is an Emeritus Professor of the Rensselaer Polytechnic Institute. He has both state of the art industrial experience and advanced academic background. He has been a Director and Professor, and established major R & D programs at Rensselaer, and at several industrial corporations. He is an inventor or co-inventor of major semiconductor technologies which are used currently in manufacturing. He has had over 40 years of experience in the multibillion dollar Si VLSI/ULSIC field, microelectronics technologies and other high-tech areas. He has served as the Consulting Editor of a book series on Microelectronics Manufacturing. He is a Life Senior Member of IEEE. A graduate fellowship has been established at Rensselaer Polytechnic Institute in his and his wife’s name for advanced research in microelectronics, because of his teaching and their substantial donation. Prior to 1960, Dr. Saxena has published in and contributed to the fields of Nuclear Shell Structure and High Energy Physics at the Institute of Nuclear Physics, India, and at Stanford University. He earned the PhD degree in Physics from Stanford and is listed in the Who’s Who in the World and Who’s Who in America. 523

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