IC Mask Design Essential Layout Techniques
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IC Mask Design Essential Layout Techniques
Christopher Saint Judy Saint
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Copyright © 2002 by Christopher Saint and Judy Saint. All rights reserved. Manufactured in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. 0-07-150093-6 The material in this eBook also appears in the print version of this title: 0-07-138996-2. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps. McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. For more information, please contact George Hoare, Special Sales, at
[email protected] or (212) 904-4069. TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc. (“McGraw-Hill”) and its licensors reserve all rights in and to the work. Use of this work is subject to these terms. Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent. You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited. Your right to use the work may be terminated if you fail to comply with these terms. THE WORK IS PROVIDED “AS IS.” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. McGraw-Hill and its licensors do not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free. Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom. McGraw-Hill has no responsibility for the content of any information accessed through the work. Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages. This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise. DOI: 10.1036/0071389962
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Contents Introduction Acknowledgments Open Letter to Circuit Designers
Chapter 1
Digital Layout
Chapter Preview Opening Thoughts on Digital Layout Design Process Verifying the Circuitry Logic Compiling a Netlist Drive Strength Clock Tree Synthesis Layout Process Floorplanning Block Placement Gate Grouping Block Level Connectivity Using Flylines Timing Checks Placement I/O Drivers Routing Power Nets Strapping Clock Net Wiring Other Critical Nets Remaining Nets Finishing the Wiring by Hand Prefabricated Gate Array Chips Verification Design Verification Physical Verification
xiii xv xvii
1
1 1 2 2 3 4 5 7 7 7 8 8 9 10 11 12 13 13 14 15 16 16 17 18 19 19 20 v
vi | CONTENTS
Chapter 2
Chapter 3
GDSII File DRC and LVS Checks Library Management Summary and Flowchart Closure on Digital Layout Here’s What We’ve Learned
20 20 21 22 23 24
Standard Cell Techniques
25
Chapter Preview Opening Thoughts on Standard Cell Techniques Standardized Grids Grid-Based Systems Determining Grid Size Rule-Based Routers Directional Layer Technique Library Rules for Grid-Based Systems Input and Output Alignment Fixed Height, Variable Width Determining Wire Gauge Common N Well Half-Grid Cell Sizing Half Design Rule Routing Channels Channel Routers Antenna Rules Standardized Input and Output Cells Using Standardization in Analog Mask Design Closure on Standard Cell Techniques Here’s What We’ve Learned
25 25 26 26 26 28 29 32 32 34 35 35 37 38 39 43 45 45 46 47 48
Analog Layout
49
Chapter Preview Opening Thoughts on Analog Layout Digital Skills vs. Analog Skills Difference of Scale Difference of Primary Objective Difference of Teamwork Difference of Completion Schedule Difference of Innovation Difference of Constraints Difference of Understanding Circuit Techniques Three Key Questions
49 49 50 50 51 51 52 52 52 53 53
Contents
Chapter 4
Chapter 5
| vii
QUESTION 1: What does this circuit do? QUESTION 2: How much current does it take? Calculating Current Densities QUESTION 2a: Where are the high and low current paths? Device Orientation QUESTION 3: What matching requirements are there? Additional Questions Bipolar Analog Expectations of an Analog Mask Designer Closure on Analog Layout Here’s What We’ve Learned Appendix: Key Questions Discussion
55 56 57
Parasitics
79
Chapter Preview Opening Thoughts on Parasitics Parasitic Capacitance Wire Length Metal Selection Metal over Metal Parasitic Resistance Calculating IR Drops Wiring Options Parasitic Inductance Device Parasitics CMOS Transistor Example Bipolar Transistor Example Full Custom Options Closure on Parasitics Here’s What We’ve Learned
79 79 80 81 82 84 86 86 88 91 92 92 93 94 94 95
Matching
97
Chapter Preview Opening Thoughts on Matching Importance of Layout Importance of Communication Simple Matching Root Device Method Interdigitating Devices Dummy Devices Common Centroid
58 59 64 64 65 66 70 70 71
97 97 98 100 100 103 105 108 109
viii | CONTENTS
Chapter 6
Chapter 7
Cross-Quading Symmetry Matching Signal Paths Device Size Choices Closure on Matching Here’s What We’ve Learned Rules of Matching
110 113 114 117 119 120 120
Noise Issues
121
Chapter Preview Opening Thoughts on Noise Issues Noisy Neighbors Common Sense Noise Solutions Turn Down the Volume Rock Band Moves Inside Their House Go Inside Your Own House Close All Windows Call the Sheriff Move to a New Neighborhood Wire Solutions Coaxial Shielding Differential Signals Decoupled Power Rails Stacked Power Rails Harmonic Interference Closure on Noise Issues Here’s What We’ve Learned
121 121 122 124 124 125 128 128 128 129 130 130 132 134 135 136 139 139
Floorplanning
141
Chapter Preview Opening Thoughts on Floorplanning Primary Drivers of Floorplanning Pin-Driven Planning Effect of Pin Placement ESD Supply Strategies Block-Driven Planning Signal-Driven Planning Reshaping Blocks Sizing Estimates Leaving Enough Room Estimating with Existing Circuitry Closure on Floorplanning Here’s What We’ve Learned
141 141 142 143 143 145 149 152 153 155 155 158 159 160
Contents
Chapter 8
Chapter 9
| ix
General Techniques
161
Chapter Preview General Techniques #1 Pick Five or Six Non-minimum Design Rules #2 Get Thee to the Lowest Parasitic Metal #3 Plenty of Wide Wiring and Vias #4 Don’t Believe Your Circuit Designer #5 Use a Consistent Orientation #6 Don’t Go Overboard #7 Keep Off the Blocks #8 Care for Your Sensitive and Noisy Signals Early #9 If It Looks Nice, It Will Work #10 Learn Your Process #11 Don’t Let Noise Find the Substrate #12 Spread Your Spinach around Your Dinner Plate #13 Copy and Rename Cells before Making Changes #14 Remember Your Hierarchy Level #15 Build-in Easy Metal Revisions #16 Draw Big Power Buses #17 Break Up Large Circuits Closure on General Techniques Ancient Secrets of Mask Design
161 161 162 165 165 167 168 169 169 170 170 171 172 172 175 176 177 182 184 184 185
Packaging
187
Chapter Preview Opening Thoughts on Packaging Bonding Methods Ultrasonic Wedge Bonding Ultrasonic Ball Bonding Flip Chip Technology Multi-Tier Packaging Issues in Packaging Overall Appearance 45-Degree Rule Minimal Silicon Overlap Wire Length Pad Distribution Sizing Estimates Pad-Limited Design Core-Limited Design Package Maximum Check Final Die Size Calculations Filling Pad Gaps Closure on Packaging Here’s What We’ve Learned
187 187 188 189 190 191 192 193 193 194 195 195 196 197 197 199 200 200 206 207 208
x | CONTENTS Chapter 10
Chapter 11
Verification
209
Chapter Preview Opening Thoughts on Verification Checking Software Design Rule Check (DRC) Boolean Command Lines AND Function OR Function NOT Function Rule Checking Command Lines Layout Versus Schematic (LVS) Netlists Problem Solving 1. Check Number of Devices 2. Check Types of Devices 3. Check Number of Nets 4. Solving Complex Net Problems a. Power Supplies b. Named Nets 5. Don’t Trust Your Circuit Designer 6. Check for Possible Swapping Over 7. Check for a Top Level Short 8. Check for Ninja Invisibility 9. Know Your Circuits 10. Let Others Help Closure on Verification Here’s What We’ve Learned
209 209 210 211 211 212 214 215 218 220 221 222 222 223 224 226 226 228 229 230 232 232 233 234 234 235
Data Formats
237
Chapter Preview Opening Thoughts on Data Formats Industry Standard Database Formats Header Information Coordinating Resolutions Pattern Generation Know Your Grids Closure on Data Formats Here’s What We’ve Learned
237 237 238 238 238 241 242 243 243
Case Study #1 CMOS Amplifier
The New Job Assignment Bill Reasons His Floorplan Bill Thinks Through His Layout
247
247 255 259
Contents
Ted Returns Bill Rethinks The Chip Is Assembled Packaging Appendix Case Study #2 Bipolar Mixer
Introduction to Case Study 2 The Assignment “What Does the Circuit Do?” “What Are the Circuit Requirements?” Bipolar Transistor Review First Layout Initial Overview Current Source Transistors Resistors Lower Pair Emitters Bases Collectors Upper Quad Emitters Bases Collectors Loads Output Resistors Analysis of First Layout Bipolar Transistor Layout—Wrap-Around Technique Second Layout Current Source Emitters Bases Collectors Resistors Lower Pair Interdigitation Plan Emitters Collectors Bases Inputs Upper Quad Interdigitation Plan
| xi
272 280 304 325 326 341
341 342 342 345 345 346 346 349 349 349 351 352 353 354 355 355 357 358 358 358 361 362 362 365 365 367 368 368 368 370 370 371 371 373 373 375 375
xii | CONTENTS
Emitters Collectors Bases Inputs Loads Interdigitation Plan Resistors Outputs Analysis of Second Layout Third Layout Lower Pair Cross-Quading Plan Emitters Collectors Bases Inputs Final Analysis Comparison of Case Study 1 and Case Study 2 Beginnings The Four Engineers Outtakes Contact Us Suggested Readings and Resources Educational Programs Glossary Index
376 377 377 380 380 380 382 383 384 385 386 387 387 388 388 390 393 393 395 409 411 415 417 419 421 445
Introduction
Mask design techniques have developed at an enormous rate. As circuit speeds increase, the mask designer is expected to quickly, efficiently, and accurately translate a schematic into layout, make informed choices based on knowledge of increasingly complex tools, and understand how circuit function can affect layout decisions. Mask design has evolved into a highly valued profession. Are your skills as sharp as they could be? Are you highly valued? IC Mask Design: Essential Layout Techniques provides step-by-step detailed guidance on every aspect of the mask design process, including techniques you will use on a daily basis. This book is written for mask designers and circuit designers alike. A circuit designer who understands layout techniques can help improve circuit function and reduce design times. The mask designer who understands the roles of communication, teamwork, and knowledge of circuit function as they apply to integrated circuit layout can help produce an integrated circuit with superior performance. A good mask designer is crucial to the development of superior integrated circuits. IC Mask Design covers matching, noise issues, high frequency layout concerns, analog and digital layout, Bipolar RFIC layout techniques, and much more. Two Case Studies included with this book provide insight into the mask design process, demonstrating essential techniques in action. All material is presented in an enjoyable light style, easily readable, with emphasis on practical application. We hope this book is horizon-expanding for you. We hope you learn to question, to be creative, to think, to innovate, and to become a critical team player
xiii Copyright © 2002 by Christopher Saint and Judy Saint. Click here for terms of use.
xiv | INTRODUCTION
in designing successful products at your site. Above all, we hope you love your job. Keep your sense of humor. Enjoy the book. Christopher Saint Judy Saint
Acknowledgments
We would like to thank the following people for their contributions to the two books IC Layout Basics and IC Mask Design. Professional support: Jim Comfort, Hassan Zamat, IBM Management Noise reduction discussions: Jerry Twomey Format assistance: Tamara Dever, Jack Pryor McGraw-Hill acquisition and vision: Steve Chapman Experience and training: All the design team members with whom Chris has worked over the years, who helped him learn all these techniques. Moral support: Michelle Saint, Jack Pryor, Jack Kennedy, Linda Kennedy, The Pryor Family
xv Copyright © 2002 by Christopher Saint and Judy Saint. Click here for terms of use.
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Open Letter to Circuit Designers
As a designer, every choice and decision you make within your circuit directly impacts the final piece of silicon that gets built. Circuit design goes beyond the simulator. The physical attributes of your designs can determine whether the circuit thrives or fails. Mask design issues are now, more than ever, part of the circuit design process. Your design is not complete until the circuit is in silicon. The responsibility of getting your design onto silicon is yours. The responsibility of understanding how your design impacts layout options is yours. The responsibility of communicating circuit requirements to a mask designer is yours. To do all this you must know your mask designers' job as well as they do, if not better. How can you effectively achieve this difficult part of your job? First, you need to completely understand your circuit, both electrically and physically. Understanding what your circuit needs to achieve electrically will enable you to make informed decisions about what device sizes to use and what layout techniques to employ. Every time you place a device or an interconnect in your schematic you should be thinking, "What will this look like physically?" You should live, breathe, and think mask design. Every waking thought should be how your circuit will be physically implemented. Second, you need to understand your manufacturing process intimately—how every component in the process is built and used. If you understand your process, you can make intelligent choices that are based upon documented behaviors instead of wild guesses. Know your manuals. Check your equations. Bother to look them up. Above all, make sure that your mask designers get all the information they need to do their job effectively. A trap many circuit designers fall into is that they seem to consider a schematic capture tool as merely an electronic front xvii Copyright © 2002 by Christopher Saint and Judy Saint. Click here for terms of use.
xviii | OPEN LETTER TO CIRCUIT DESIGNERS
end to their simulation software. Instead, the schematic database should be considered as the primary source of documentation for a chip design. The following schematic practices can greatly improve any project and reduce rework: ■ Annotate current values and paths ■ Add layout notes to your schematic ■ Place the circuit name onto the schematic ■ Keep an effective revision history on the schematic (particularly dates
and times) ■ Make schematics readable when printed out
This list of practices will not only make your schematics more usable for a mask designer, but also for any subsequent circuit designers who may wish to reuse your innovative, world-shattering concepts. A small warning: Be careful to choose your mask design techniques wisely. It is easy to overburden your mask designer unnecessarily. For example, if your circuit requires that two resistors match each other to within 5%, then why bother specifying the use of a complex layout technique to produce a match of better than 1%? The increased matching you achieve does not make your circuit any better, but does require extra effort during the mask design phase. Circuit designers who blindly require a mask designer to apply every layout technique in the book (e.g., this one) on their components are potentially costing their company money due to the increased design cycle times. Know what needs to be communicated to your mask designer. Know how your mask designer can help you. A mask designer is a valuable resource and has probably had extensive exposure to many different circuit design and layout techniques during his or her career. Use that resource. Work as a team. Communicate. Listen. Suggest. Explain. Annotate. Calculate. Learn. Did I say communicate? Especially communicate. Good layout means successful circuits. If you follow these simple concepts and ideals you will become a cut above the rest. Use this book to build your skills and learn the language of mask design. Today's competetive marketplace demands it.
IC Mask Design Essential Layout Techniques
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CHAPTER
1
Digital Layout
Chapter Preview Here’s what you’re going to see in this chapter: ■ Close look at automated layout software ■ Why automated layout only works with certain cells ■ Knowing the circuit really does what it should ■ How to know in advance if your floorplan choice is good ■ Automated programs getting stuck ■ Troubleshooting tips ■ Which nets to wire first ■ Which nets to wire by hand ■ Techniques to guarantee rule-perfect layout ■ Flowchart of digital layout procedures ■ Lots of feedback loops ■ How to keep the power moving through big cells ■ Chicken or egg wiring and timing circle ■ Did you really build what you designed? ■ How to build quickie chips for testing
Opening Thoughts on Digital Layout The majority of integrated circuits built today are large. I mean really huge CMOS digital chips. One chip might have literally millions of transistors in it. It’s beyond any single mask designer’s capabilities to lay out a chip like that by hand—in any reasonable time frame, at least. Consequently, the majority of large digital chips are laid out with the assistance of computer-aided tools. 1 Copyright © 2002 by Christopher Saint and Judy Saint. Click here for terms of use.
2 | CHAPTER 1
Understanding how these automated digital layout tools operate allows you to develop skillful daily habits in your work—even in your analog work. If you understand how the software operates, you can lay out better circuits faster, compensate for software inadequacies, and steer clear of roadblocks before they happen.
Design Process Let’s build a digital chip. In this chapter, we will follow a design team as they progress from concept, through circuit testing, and finally to the actual gate placement and wiring of a digital chip, using a suite of software tools. Let’s start. It’s the circuit designer’s move first. Verifying the Circuitry Logic Circuit designers typically use languages called VHDL or Verilog to design their enormous digital circuits. VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language, an IEEE standard since 1987. Verilog is another proprietary logic description language. We will use VHDL in our examples. Circuit designers use the VHDL language to create a chip that exists first as only a database of numbers. The circuit designer’s VHDL files are very Clike.1 The files essentially say, for example, “I want a circuit function that adds two 16-bit numbers together.” In this way, the VHDL files describe our microprocessor, our digital functions, or whatever functions we need. These VHDL data files are then submitted to a computer simulator, which tests the chip circuitry while it is still in software form. The logic functions of the VHDL code run very quickly, much faster than a traditional transistor level SPICE simulation (but not as fast as the real silicon.) The VHDL simulator needs to have process-specific software descriptions of each logic function it wants to use, such as rise time, fall time, gate propagation delays. This information, as well as other device parameters, is stored as a series of files that the VHDL simulator can access. Along with these electrical descriptions, there are also physical representations of each of the gates that the simulator and logic synthesizer can use. All of these files are collectively known as a standard cell library or logic library.
1
The computer language, C.
Digital Layout
| 3
VHDL Code Segment
architecture STRUCTURE of TEST is component and2x port(A,B,C,D: in std_ulogic := ‘1’; Y: out std_ulogic); end component; constant VCC: std_ulogic := ‘1’; signal T,Q: std_ulogic_vector(4 downto 0); begin T(0) Q(0), B=>Q(1), Y=>T(2)); A2: and2x port map(A=>Q(0), B=>Q(1), C=>Q(2), D=>Q(3), Y=>T(4)); Count
