Error Control for Network-on-Chip Links

Error Control for Network-on-Chip Links

Bo Fu

l

Paul Ampadu

Error Control for Network-on-Chip Links

Bo Fu Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA [email protected]

Paul Ampadu Department of Electrical and Computer Engineering University of Rochester Rochester, NY 14627, USA [email protected]

ISBN 978-1-4419-9312-0 e-ISBN 978-1-4419-9313-7 DOI 10.1007/978-1-4419-9313-7 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011936003 # Springer Science+Business Media, LLC 2012 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.

Printed on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com)

To Luzviminda, Luzann, Majelia and Paul Jr for Love, Patience, Courage and Dedication

Preface

Traditional bus-based infrastructures can no longer handle the intensive communication among various modules, as hundreds and even thousands of intellectual property (IP) cores are integrated on a single chip. Network-on-Chip (NoC) is emerging as an efficient solution to solve the aggravating scalability and contention issues of on-chip communication. With technology scaled into the nanometer regime, the physical links in NoCs are facing important design challenges of delay, power and reliability. The purpose of this book is to present current solutions addressing reliability issues in on-chip communications. Reliability is an important issue in NoC design. For example, errors in the header of a packet may lead to loss of packet. The reliability issue of on-chip communication can be addressed at different NoC layers, such as physical layer, data link layer and network layer. This book focuses on techniques applied to the data link layer. Error control coding is a common technique used in the data link layer to provide reliable on-chip communication. With the shrinking link feature size, on-chip interconnects are becoming susceptible to multiple random and burst errors, requiring more powerful error control codes (ECCs) than those previously used. At the same time, the energy consumption of on-chip interconnect is becoming an increasingly large portion of on-chip power dissipation, motivating the need for more energy efficient communication solutions. In this book, we present energy-efficient error control approaches for on-chip interconnects. We introduce a method of combining extended Hamming product codes with type-II hybrid automatic repeat request (HARQ). This method provides a strong error correction capability against multiple random and burst errors; while keeping the hardware overhead reasonable. The combination of extended Hamming product codes with type-II HARQ has been shown to meet the same reliability requirements as previous solutions while using a lower link swing voltage to reduce energy consumption. The extended Hamming product codes can also be integrated into a configurable error control scheme by combining it with a traditional Hamming code. The different coding strengths provided by this realization can achieve better energy performance in the presence of varying noise conditions.

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Capacitive crosstalk coupling greatly increases with increased interconnect aspect ratio with each scaled technology node. Capacitive crosstalk coupling can cause delay uncertainty, which greatly decreases the system performance resulting in timing errors. ECCs have been successfully applied to improve the reliability of on-chip interconnect by correcting logic errors. Unfortunately, conventional ECCs are not as efficient in addressing delay uncertainty caused by capacitive crosstalk coupling. In this book, we also present methods that simultaneously address logic errors and crosstalk-induced delay uncertainty. We introduce a method of combining ECCs with conventional skewed transitions. Here, the inherent skew resulting from the ECC parity generation is exploited to ensure that no two adjacent wires switch in opposite directions simultaneously, thereby reducing worst-case on-chip capacitive coupling. This method can reduce the overhead of conventional skewed transitions by hiding the delay insertion overhead in parity calculations. Compared with other solutions that simultaneously handle logic errors and delay uncertainty, this method requires fewer wires, resulting in smaller link area and energy consumption. This book is based on the first author’s Ph.D. dissertation completed at the University of Rochester. The research work was supported in part by the U.S. National Science Foundation under grant NSF-ECCS-0733450. The authors would like to thank friends and colleagues Prof. Eby Friedman, Prof. Chen Ding, and Prof. Thomas Tucker for their invaluable suggestions during the writing of the dissertation that led to this version of the book. Dr. Bo Fu expresses gratitude to his exceptional colleagues, Dr. David Wolpert (now at IBM) and Dr. Qiaoyan Yu (now at UNH), for their productive, supportive and enjoyable collaborations during his studies in the Embedded Integrated System-on-Chip (EdISon) research group at the University of Rochester. Dr. Fu also thanks friends, Lin Zhang, Chao Yu, Qiang Sun, Xin Li, Gaojie Lu, Xiaohua Zhang and Fan Yang for their help and friendship. His deepest gratitude and immense appreciation goes to his parents and his wife for their constant encouragement and unwavering support. Many thanks also to graduate student Meilin Zhang for his assistance in formatting the book and to Charles B. Glaser from Springer for his support and assistance throughout. Santa Clara, CA, USA Rochester, NY, USA

Bo Fu Paul Ampadu

Contents

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Impact of Scaling on Interconnect Parameters . . . . . . . . . . . . . . . . . . . . . . . 1.2 Reliability Issues for On-Chip Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Types of Errors and Error Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Types of Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Error Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Book Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 4 8 8 9 12 13

2

Solutions to Improve the Reliability of On-Chip Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Wire Sizing and Spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Repeater Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Crosstalk Avoidance Codes (CACs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Skewed Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Error Control Coding Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Automatic Repeat Request (ARQ). . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Forward-Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Hybrid ARQ (HARQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Spare Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 17 18 19 21 22 24 24 26 27 28 28

Networks-on-Chip (NoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Bus Based On-Chip Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 NoC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 NoC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Routing and Switching Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Router Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Reliability in NoC Links. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33 33 34 35 38 41 42 45

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Error Control Coding for On-Chip Interconnects. . . . . . . . . . . . . . . . . . . . . 4.1 Error Control Coding Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Linear Block Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Systematic Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 Hamming Distance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 Code Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Error Control Codes for On-Chip Interconnect . . . . . . . . . . . . . . . . . . . . . 4.2.1 Single Parity Check (SPC) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Duplicate-Add-Parity (DAP) Code . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Hamming Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Hsiao Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 SEC Codes with Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Cyclic Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Bose-Chaudhuri-Hocquenghem (BCH) Codes . . . . . . . . . . . . . . 4.2.8 Reed-Solomon (RS) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.9 Hamming Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49 49 49 51 52 54 56 57 57 58 59 61 63 64 66 73 73 78

5

Energy Efficient Error Control Implementation . . . . . . . . . . . . . . . . . . . . . . 5.1 Error Control Coding with Low Link Swing Voltage System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Error Control Coding with Dynamic Voltage Swing Scaling System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Product Codes with Type-II ARQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 The Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Extended Hamming Product Codes with Type-II HARQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Configurable Error Control System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Configurable Encoder Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Configurable Decoder Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Combining Error Control Codes with Crosstalk Reduction . . . . . . . . . 6.1 Duplicate-Add-Parity (DAP) Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Boundary Shift Code (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Crosstalk Avoidance and Multiple Error Correction Code (CAMEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Unified Coding Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Forbidden Overlap Condition (FOC) Codes. . . . . . . . . . . . . . . . 6.4.2 Forbidden Transition Condition (FTC) Codes. . . . . . . . . . . . . .

79 81 87 87 92 95 104 104 105 108 109 114 115 117 117 119 120 123 124 125

Contents

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6.4.3 Forbidden Pattern Condition (FPC) Codes . . . . . . . . . . . . . . . . . 6.4.4 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Error Control Codes with Skewed Transitions . . . . . . . . . . . . . . . . . . . . . 6.5.1 The Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Data Mapping Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

126 127 130 130 133 136 141 143

List of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 1

Introduction

On-chip interconnects play an important role for the performance of current VLSI system. As technology scales into nanoscale regime, interconnect is facing several design challenges in terms of delay, power and reliability [1–3].

1.1

Impact of Scaling on Interconnect Parameters

An interconnect can be characterized by three electrical properties – resistance R, capacitance C and inductance L. The resistance R is calculated using (1.1), R¼

r  Lint Tint  Wint

(1.1)

where r is the resistivity of metal. Lint, Tint, and Wint are the interconnect length, thickness, and width, respectively, as shown in Fig. 1.1 H is the distance between interconnect and ground plane. From (1.1), the resistance R of a wire increases with the reduced value of Tint and Wint. As technology scales, the resistivity r of a metal interconnect can increase [4]. This phenomenon is caused by carrier collisions when the thickness of a wire is approaching the mean free path of electrons. Also, the increased clock frequency aggravates the skin effects [5], in which the current starts to flow through the skin of the wire. Skin effects reduce the effective cross-area that carries the current through a wire further increasing the wire resistance. Figure 1.2 shows that the resistance greatly increases with technology scaling. A large value of wire’s resistance greatly increases the interconnect delay; also causes a large signal attenuation. The interconnect capacitance C of a wire consist of parallel plate capacitance Cg1, fringing capacitance Cg2 and sidewall capacitance CC, as shown in Fig. 1.3. The parallel plate capacitance Cg1 refers to the capacitance between metal wire and substrate or ground, which is proportion to (Wint·Lint)/H. The sidewall capacitance B. Fu and P. Ampadu, Error Control for Network-on-Chip Links, DOI 10.1007/978-1-4419-9313-7_1, # Springer Science+Business Media, LLC 2012

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1 Introduction

Fig. 1.1 Dimensional parameters of single interconnect

Fig. 1.2 Resistance value with technology scaling [6]

Fig. 1.3 Parallel plate, fringing and coupling interconnect capacitances

CC refers to the coupling capacitance between two adjacent wires on the same metal layer, which is proportion to (Tint·Lint)/Sint. As technology scales, the interconnect thickness Tint decreases at a slower rate than the interconnect width Wint and spacing Sint [7]. Thus, the interconnect aspect ratio, defined as the ratio of Tint to Wint, increases with each technology node. The increased interconnect aspect ratio has caused an increase in capacitive coupling effects, which can greatly affect the reliability of on-chip interconnects. The inductance L of an interconnect is caused by the current loop formed by the signal wire and its return. As multi-GHz clock frequencies are widely applied in current VLSI system, the inductive effects become significant, especially for long

1.1 Impact of Scaling on Interconnect Parameters

3

Fig. 1.4 Interconnect delay as technology scaling [11]

and wide global wires [8, 9]. Inductance effects increase the design complexity, as it is difficult to accurately extract inductance. Further, the inductance effects can exist over a long distance, which exacerbates the crosstalk coupling [10]. The technology scaling has a significant impact on the performances of on-chip interconnects [11, 12]. The rise in wire resistance increases the RC time constant resulting in a delay increase for a fixed length of inter connect. Moreover, the length of global interconnect grows as the chip size increases to integrate more components. By considering the chip scaling factor, the delay of global interconnects increases by S2Sc2, where S is the technology scaling factor and Sc is chip size scaling factor [7]. Figure 1.4 shows the scaling trend of the gate delay, local wire delay, and global wire delay with or without repeater insertion. The global interconnect has a considerable increase in delay compared to logic gates and becomes the performance bottleneck with technology scaling. The power consumption is another critical factor faced with on-chip interconnects in nanoscale system [13, 14]. A great portion of the total chip power is consumed by on-chip interconnects because a large interconnect capacitance is charged and discharged every time a transition occurring. The use of large-sized repeaters to reduce the delay of the global interconnect further aggravates the power consumption of on-chip interconnects. Figure 1.5 shows that the dynamic power breakdown of UltraSPARC T3 SoC processor with 16 SPARC cores using 40 nm technology [15]. The power consumption of interconnect is the same as the power consumption of logic gates. Figure 1.6 shows the total interconnect length integrated into a chip with technology scaling. Because the wire capacitance is linearly related to the wire’s length, the increased interconnect capacitance will greatly increases the power consumed by on-chip interconnects.

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1 Introduction

Fig. 1.5 UltraSPARC T3 and its dynamic power breakdown [15]

Fig. 1.6 Total interconnect length on a chip as technology scales [11]

1.2

Reliability Issues for On-Chip Interconnect

Interconnect reliability issues are caused by manufacturing defects [16, 17] or a variety of noise sources, such as external radiation [18, 19], crosstalk coupling [8, 9, 20–22], supply voltage fluctuations [23, 24], process variations [25–31], temperature variations [4, 32], electromagnetic interference (EMI) [33] and combinations of these sources.

1.2 Reliability Issues for On-Chip Interconnect

5

Fig. 1.7 manufacturing defects in interconnects

Imperfect manufacturing process can cause on-chip interconnects. Figure 1.7 shows metal sliver and crack in on-chip interconnects caused by manufacturing defects. Metal sliver is a small piece of extra metal left between two metal wires during manufacturing process. When the metal temperature increases, the metal sliver will expand and touch both of these two wires. A short connection can be caused by metal sliver. Crack is another common manufacturing defect caused by material stresses. Crack can cause an open connection. The rise of the occurrence probability of manufacturing defects in nanoscale technology results in a decrease in the manufacturing yield of large-area chips. Techniques to improve the yield must be considered. Noise sources affect the reliability of on-chip interconnect in two ways – signal integrity [2] and delay uncertainty [34]. Noise sources reduce the signal integrity of on-chip interconnect by inducing voltage glitches. If a voltage glitch is greater than the tolerable noise margin of the circuit and has a sufficient duration, it can cause logic errors. Delay uncertainty refers to an unknown fluctuation in the timing of a signal transition. Delay uncertainty decreases the system operating frequency because a large design margin is required to guarantee correct operation. In nanoscale technology, crosstalk-induced delay uncertainty can be a critical bottleneck for the operation of high speed synchronous systems. Crosstalk coupling is one of the most important factors affecting reliability of on-chip interconnects. Crosstalk coupling is caused by the mutual capacitance or mutual inductance between wires [10]. As technology scales, the increased interconnect aspect ratio has caused an increase in capacitive coupling effects. Inductive coupling occurs when signal switching causes a change in magnetic field. The gigahertz clock frequencies in nanoscale technology result in a nonnegligible inductive effect in on-chip interconnects [8, 9]. Unlike capacitive coupling, inductive coupling can be a long range phenomenon and is more important in the presence of wide busses [10]. Crosstalk coupling effects can induce significant voltage glitches on a victim line. Figure 1.8 shows noise waveforms resulting from capacitive and inductive coupling between two fully coupled lines [9]. The peak noise voltage can exceed 20% of the supply voltage, potentially inducing logic errors. Crosstalk-induced delay uncertainty is mainly caused by the dependence of coupling capacitance on signal switching patterns. Depending on the switching behavior of a wire and its

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1 Introduction

Fig. 1.8 Noise waveforms of crosstalk coupling between two coupled lines [9]

Fig. 1.9 Soft errors caused by particle strikes

neighbors, the effective capacitance Ceff of a wire can change from Cg to Cg + 4Cc [35] (where Cg ¼ Cg1 + Cg2). The best case Ceff exists when all three adjacent wires switch in the same direction. The worst case Ceff occurs when there is a transition 010!101 (101!010) on three adjacent wires. The dependence of Ceff on signal switching patterns can result in up to 50% delay change in on-chip interconnect [36]. Figure 1.9 shows an example of soft error caused by particle strikes. As technology scales, integrated circuits become more vulnerable to soft errors caused by particle strikes [18], such as alpha particles and neutron. As the node capacitance decreases in

1.2 Reliability Issues for On-Chip Interconnect

7

Fig. 1.10 A single event transient (SET) jumping from one interconnect to another in the presence of crosstalk [37]

nanoscale technology, a smaller injection of charge can induce errors (the amount of charge required to induce in error is referring to as the critical charge Qcrit). This is exacerbated by the scaling of supply voltage, which decreases circuit noise margins and makes them more susceptible to particle strikes. Higher clock frequency and deep pipelined design also increase the probability that any faults resulting from a strike will be latched by flip-flops, creating errors. When crosstalk coupling is considered, particle strikes become even more problematic [37, 38]. In the presence of a transient error caused by alpha particles or neutron strikes, crosstalk coupling may propagate this error to other parts of the circuit by inducing large voltage glitches on neighboring wires, as shown in Fig. 1.10. The coupling effect increases the probability that multiple adjacent errors (also referred to as a burst error) are caused by a single particle strike. The probability of errors caused by electromigration also increases in nanoscale technology [3, 39, 40]. Electromigration is the alteration of an atomic structure caused by electromagnetic forces, i.e., the dense flow of electrons in interconnects. Over time, the atomic displacement can result in opens or shorts. With the aggressive scaling of interconnect dimensions, the current density within these interconnects significantly increases. This rise in current density, combined with the use of low-k dielectrics, (which have lower thermal conductivities [4]), results in a significant increase in the metal temperature. The large rise in metal temperature exacerbates electromigration, degrading system lifetime [4]. The impact of process variations on interconnect is also expected to increase as technology scales [25–27]. Process variation in interconnects are caused by the imperfect processes of photolithography, planarization and metal etching. Variations in the geometric parameters of interconnects lead to a change in interconnect resistance and capacitance, which causes a variation in the delay of on-chip interconnects. The variations in interconnect delay may lead to timing closure problems. The variations in interconnect dimensions also increase the probability of opens caused by electromigration in narrower sections of a wire. Moreover, device parameter variations introduce delay variations in the drivers and repeaters, which can also result in link delay errors.

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Supply voltage fluctuations are another factor affecting signal integrity of on-chip interconnects [23, 24, 41]. Supply voltage fluctuations can affect the driver and repeaters performance and noise margins, increasing the susceptibility to both logic and timing errors. There are two components of power supply noise – low frequency and high frequency. The low frequency component is known as IR drop, which is the reduction in voltage caused by passing current through a resistive line. The high frequency component is known as L@i=@t noise, which is caused by the inductive properties of currents flowing through the chip power grid. A sudden current demand caused by simultaneous switching of a large number of logic gates results in a large L@i=@t noise. On-chip inter connect reliability issues can also be caused by temperature variations [32]. Interconnect resistance is linearly dependent on temperature. On-chip temperature variations result in different wire resistances, which cause delay uncertainty. It has been reported that thermal gradients can be as large as 50 C across high performance microprocessor substrate [32]. Thus, it is very important to take into account the impact of temperature variations on interconnect performance. All of these factors decrease the reliability of on-chip interconnects in nanoscale technology. Design techniques, which can improve the reliability of on-chip interconnects, should be considered.

1.3 1.3.1

Types of Errors and Error Models Types of Errors

Depending on their duration, errors can be divided into three classes – transient, permanent and intermittent. Transient errors, which are also called soft errors, are short-term malfunctions temporarily induced by external radiation or electrical noises rather than manufacturing defects [3, 42, 43]. Transient errors can be caused by neutron or alpha particle strikes. As the node capacitance decreases with technology scaling, a smaller injection of charge can induce errors. It has been shown that transient errors caused by particle strike increase by two orders of magnitude from a 180 nm technology to a 45 nm technology [44]. Also, the probability of multiple errors caused by a single particle strike increases in nanoscale technology [45]. Crosstalk coupling is another factor that causes transient errors. In nanoscale technology, capacitive coupling effects increase with rising of interconnect aspect ratios. A high clock frequency results in a non-negligible inductive coupling. Instead of inducing single errors, crosstalk coupling can cause spatial burst errors, which occur in multiple adjacent wires. Crosstalk coupling can also propagate transient errors caused by particle strikes from a victim wire to its neighbors, further increasing the probability of multiple errors in on-chip interconnects.

1.3 Types of Errors and Error Models

9

Transient errors can also be caused by other noise sources such as process variations, supply voltage fluctuation, electromagnetic interference (EMI), and electrostatic discharge [42]. As technology scales, impacts of these noise sources are expected to increase because of smaller feature sizes, lower supply voltage and higher clock frequency. Permanent errors are irreversible malfunctions caused by physical changes; once permanent errors occur, they will not disappear. Permanent errors are usually a result of manufacturing defects, which can be detected during manufacture testing. However, permanent errors can also occur at run-time (e.g., caused by electromigration or aging) [3]. An efficient approach to fix permanent errors is to use spare wires [17, 46]. Intermittent errors are long-duration errors (but not permanent [3]) occurring in the same position. Intermittent errors are usually activated by voltage or environmental (e.g., temperature) changes or specific input patterns. Intermittent errors can lead to the occurrence of permanent errors. For example, electro migration usually causes timing errors resulting from increased resistance, before it finally breaks down the link and creates an open. The occurrence of permanent and intermittent errors decreases the efficiency of error control schemes. For example, error detection and retransmission (EDR) can be used to address transient errors; but it can be ineffective against intermittent errors (a system may stall while sending many retransmissions of a single piece of data) and EDR fails to work in the presence of permanent errors. Intermittent and permanent errors also reduce the capability of error control codes to tolerate transient errors and require more powerful error control codes, which lead to large power and area overheads.

1.3.2

Error Models

Modeling error rates of on-chip interconnects can be difficult, because it requires the knowledge of various noise sources and their dependence upon the supply voltage. In [47, 48], a simplified model is applied by assuming that all the noise effects on a wire can be modeled as a normal distribution noise VN with standard deviation sN. The probability of an error occurring in this model (shown by the shaded area in Fig. 1.11) is the sum of two components – the probability of noise causing a logic low to exceed the gate switching threshold voltage (Vdd/2), and the probability of noise causing a logic high to fall below the gate switching threshold voltage. The probability of a single wire being erroneous e during a transition can be expressed by a Gaussian pulse function [47],
 Z 1 Vswing 1 2 ¼ V pffiffiffiffiffiffi ey =2 dy e¼Q swing 2sN 2p 2s N

(1.2)

10

1 Introduction

Fig. 1.11 Error probability of independent error model

Fig. 1.12 multiple adjacent errors caused by a noise source

where Vswing is the link swing voltage and sN is the standard deviation of the noise voltage. In this model, the error probability in each wire is assumed to be independent. As technology scales, the probability that a single noise source causes errors in multiple neighboring wires increases [49–54]. As shown in Fig. 1.10, a single particle strike can cause multiple errors because of crosstalk coupling effects [37, 38]. Thus, a more realistic error model should include spatial burst errors, where multiple adjacent wires are erroneous. Equation 1.2 can be extended to include burst errors. Instead of only affecting one wire, the noise source is modeled to affect its neighbors. The effect on neighboring wires can be described by a coupling probability Pn [54], as shown in Fig. 1.12. The higher Pn, the more likely the noise source causes errors in multiple neighboring wires. The probability of the noise source causing an error in ln can be expressed as (1.3) below, Pðb ¼ 1Þ ¼ ð1  Pn Þ2  e

(1.3)

where e is the probability of a single wire being erroneous if no coupling effects are considered.

1.3 Types of Errors and Error Models

11

Fig. 1.13 Residual flit error rate of Hamming code for different error models, the coupling probability Pn ¼ 102 in dependent error model

The probability of two- and three-wire errors caused by the same noise source P(b ¼ 2) and P(b ¼ 3) can be expressed as (1.4) and (1.5), respectively, Pðb ¼ 2Þ ¼ 2  Pn ð1  Pn Þ  e

(1.4)

Pðb ¼ 3Þ ¼ Pn 2  e

(1.5)

The probability of the same noise source at ln also affecting ln + 2 and ln2 is usually much smaller than Pn. So we ignore the probability of a noise source causing burst errors of four bits or more P(b  4 | ln) ¼ 0. Equation 1.2 above can be considered a specific case of the extended model when Pn is 0. The value of Pn depends on coupling effects and the amplitude of the noise voltage. For simplicity, we use different Pn values to describe the coupling effects in the following analysis and simulation. Figure 1.13 shows the residual flit error of Hamming codes using independent and dependent error models. In the dependent error model, coupling probability Pn is 102. The results show that the residual flit error rate using the dependent error model increases greatly compared to using the independent error model. A more complex error model is proposed in [49]. In this error model, effects of a single noise source are described by a normalized matrix P with the following format (1.6),

12

1 Introduction

2

pð1; 1Þ

...

pð1; tmax Þ

3

7 6 . . . pð2; tmax Þ 7 6 pð2; 1Þ 7 6 P¼6 . 7 .. .. 7 6 .. . . 5 4 pðwmax ; 1Þ . . . pðwmax ; tmax Þ

(1.6)

The element p(o, t) in the matrix P represents the probability of a single noise source affecting o wires for t cycles. omax and tmax are the maximum number of wires and cycles affected by this noise source. Compared to previous models, the error model in [49] can be used to express the probability of multiple-wire and multiple-cycle errors.

1.4

Book Overview

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book mainly focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. In Chap. 2, we examine various techniques used to improve the reliability of on-chip interconnects. These techniques can be separated into noise reduction techniques and error control methods. Noise reduction techniques can reduce the noise effects and lower the probability of error occurring, such as a wider metal wire and a larger interconnect spacing, shielding, skewed transition, repeater insertion, and crosstalk avoidance codes (CACs). Error control methods are used to detect or correct errors after error occurs. The use of spatial redundancy, temporal redundancy and information redundancy are the common techniques exploited in error control methods. An important application of error control coding for on-chip interconnects is to improve the communication reliability in network-on-chip (NoC) architecture. As technology scales, billions of transistors can are integrated into a single chip, and traditional bus-based infrastructures are no longer sufficient to handle intensive on-chip communication. NoC is emerging as an efficient solution to solve the aggravating scalability and contention issues of on-chip communication. In Chap. 3, we introduce different architectures and design components of a NoC. The techniques used to improve the communication reliability in NoC are also discussed in this chapter. Error control codes (ECCs) have been widely applied in conventional communication systems. As area and energy costs of ECCS are relatively small in nanoscale technology, ECCs become a promising solution to address the reliability issue in on-chip interconnects. Simple ECCs such as single parity

References

13

check (SPC) codes, Hamming codes, and duplicate-add-parity (DAP) codes are widely used in previous work. As the probability of multiple errors increases in nanoscale technology, more complex error control codes, such as BoseChaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes and product codes are applied to improve the reliability of on-chip interconnects. In Chap. 4, we will discuss these ECCs and their hardware implementation. On-chip interconnects have tight speed, area, and energy constraints. Thus, the implementation of error control codes for on-chip interconnects needs to balance reliability and performance. In Chap. 5, we introduce various design techniques to tradeoff the reliability and energy consumption of on-chip interconnects. These techniques include the implementation of low link swing voltage and dynamic voltage scaling with error control codes, the combination of Hamming product codes with type-II hybrid ARQ, and the configurable error control codes implementation. Conventional error control codes, such as Hamming and BCH codes, have been successfully applied to improve the reliability of on-chip interconnect by correcting logic errors. Unfortunately, these codes are inefficient to address crosstalk-induced delay uncertainty. As the effects of coupling capacitance increase with technology scaling, the delay uncertainty caused by capacitive coupling greatly reduces the system performance because a large additional design margin is required. In Chap. 6, we will discuss the solutions, which can efficiently address both logic errors and capacitive crosstalk induced delay uncertainty simultaneously.

References 1. Davis AJ et al (2001) Interconnect limits on gigascale integration (GSI) in the 21st Century. Proc IEEE 89:305–324 2. Caignet F, Bendhia DS, Sicard E (2001) The challenge of signal integrity in deepsubmicrometer CMOS technology. Proc IEEE 89:556–573 3. Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 23:14–19 4. Im S, Srivastava N, Banerjee K, Goodson EK (2005) Scaling analysis of multilevel interconnect temperatures for high performance ICs. IEEE Trans Electron Devices 52:2710–2719 5. Kleveland B, Qi X, Madden L et al (2002) High-frequency characterization of on-chip digital interconnects. IEEE J Solid-State Circuits 37:716–725 6. Ho R, Mai WK, Horowitz AM (2001) The future of wires. Proc IEEE 89:490–504 7. Bakoglu BH, Meindl DJ (1985) Optimal interconnect circuits for VLSI. IEEE Trans Electron Devices 32:903–909 8. Ismail IY, Friedman GE, Neves LJ (1999) Figures of merit to characterize the importance of on-chip inductance. IEEE Trans Very Large Scale Integr (VLSI) Syst 7:442–449 9. Agarwal K, Sylvester D, Blaauw D (2006) Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 25:892–901 10. Ismail IY (2002) On-chip inductance cons and pros. IEEE Trans Very Large Scale Integr (VLSI) Syst 10:685–694 11. International Technology Roadmap for Semiconductors (2005) http://public.itrs.net 12. Horowitz M, Dally B (2004) How scaling will change processor architecture. In: Proceedings of the international solid state circuits conference (ISSCC), pp 132–133

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13. Magen N, Kolodny A, Weiser U, Shamir N (2004) Interconnect-power dissipation in a microprocessor. In: Proceedings of the international workshop on system-level interconnect prediction (SLIP), pp 7–13 14. Soteriou V, Peh SL (2004) Design-space exploration of power-aware on/off interconnection networks. In: Proceedings of the International conference on computer design (ICCD), pp 510–517 15. Shin LJ et al (2011) A 40 nm 16-core 128-thread SPARC SoC processor. IEEE J Solid-State Circuits 46:131–144 16. Zorian Y, Gizopoulos D, Vandenberg C, Magarshack P (2004) Guest editors’ introduction: design for yield and reliability. IEEE Des Test Comput 21:177–182 17. Grecu C, Ivanov A, Saleh R, Pande PP (2006) NoC interconnect yield improvement using crosspoint redundancy. In: Proceedings of the IEEE international symposium on defect and fault tolerance in VLSI system (DFT), pp 457–465 18. Karnick T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput 1:128–143 19. Munteanu D, Autran LJ (2008) Modeling and simulation of single-event effects in digital devices and ICs. IEEE Trans Nucl Sci 55:1854–1878 20. Tang TK, Friedman GE (2000) Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. Integr VLSI J 29:131–165 21. Vittal A, Chen HL, Marek MS et al (1999) Crosstalk in VLSI interconnections. IEEE Trans Comput Aided Des Integr Circuits Syst 18:1817–1824 22. Sylvester D, Hu C (2001) Analytical modeling and characterization of deep submicron interconnect. Proc IEEE 89:634–664 23. Larsson P (1999) Power supply noise in future IC’s: a crystal ball reading. In: Proceedings of the IEEE custom integrated circuits conference, pp 467–474 24. Mezhiba VA, Friedman GE (2004) Scaling trends of on-chip power distribution noise. IEEE Trans Very Large Scale Integr (VLSI) Syst 12:386–394 25. Scheffer L (2006) An overview of on-chip interconnect variation. In: Proceedings of the 2006 international workshop on system-level interconnect prediction, pp 27–28 26. Lin Z et al (1998) Circuit sensitivity to interconnect variations. IEEE Trans Semiconductor Manuf 11:557–568 27. Lopez G et al (2007) The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors. In: Proceedings of the international interconnect technology conference, pp 40–42 28. Demircan E (2006) Effects of interconnect process variations on signal integrity. In: Proceedings of the IEEE international SOC conference, pp 281–284 29. Mehrotra V, Nassif S, Boning D, Chung J (1998) Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance. In: Proceedings of the IEEE electron devices meetings (IEDM), pp 767–770 30. Mehrotra V, Sam LS, Boning D et al (2000) A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. In: Proceedings of the ACM/IEEE design automation conference (DAC), pp 172–175 31. Qi X, Lo S, Luo Y et al (2005) Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations. In: IEEE custom integrated circuit conference, pp 309–312 32. Ajami HA, Banerjee K, Pedram M (2005) Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 24:849–861 33. Khazaka R, Nakhla M (1998) Analysis of high-speed interconnects in the presence of electromagnetic interference. IEEE Trans Microw Theory Tech 46:940–947 34. Nassif S (2000) Delay variability: sources, impacts and trends. In: Proceedings of the IEEE international solid-state circuits conference digest of technical papers, pp 7–9

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35. Sotiriadis P (2002) Interconnect modeling and optimization in deep submicron technologies. Dissertation, Massachusetts Institute of Technology 36. Tamhankar R, Murali S, Stergiou S et al (2007) Timing-error-tolerant network-on-chip design methodology. IEEE Trans Comput Aided Des Integr Circuits Syst 26:1297–1310 37. Balasubramanian A, Sternberg LA, Bhuva LB, Massengill WL (2006) Crosstalk effects caused by single event hits in deep sub-micron CMOS technologies. IEEE Trans Nucl Sci 53:3306–3311 38. Balasubramanian A et al (2008) Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Trans Nucl Sci 55:2079–2084 39. Srinivasan J, Adve V S, Bose P, Rivers AJ (2004) The case for lifetime reliabilityaware microprocessors. In: Proceedings of the 31st international symposium on computer architecture (ISCA), pp 276–287 40. Xuan X, Singh A, Chatterjee A (2003) Reliability evaluation for integrated circuit with defective interconnect under electromigration. In: Proceedings of the international symposium on quality electronic design, pp 29–34 41. Heydari P, Pedram M (2003) Ground bounce in digital VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 11:180–193 42. Zhao C, Bai X, Dey S (2007) Evaluating transient error effects in digital nanometer circuits. IEEE Trans Reliab 56:381–391 43. Maheshwari A, Burleson W, Tessier R (2004) Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 12:299–311 44. Heidel FD et al (2008) Alpha-particle-induced upsets in advanced CMOS circuits and technology. IBM J Res Dev 52:225–232 45. Tipton DA et al (2006) Multiple-bit upset in 130 nm CMOS technology. IEEE Trans Nucl Sci 53:3259–3264 46. Lehtonen T, Wolpert D, Liljeberg P, Plosila J, Ampadu P (2010) Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans Very Large Scale Integr (VLSI) Syst 18:527–540 47. Hegde R, Shanbhag RN (2000) Toward achieving energy-efficiency in presence of deep submicron noise. IEEE Trans Very Large Scale Integr (VLSI) Syst 8:379–391 48. Bertozzi D, Benini L, De Micheli G (2005) Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans Comput Aided Des Integr Circuits Syst 24:818–831 49. Zimmer H, Jantsch A (2003) A fault model notation and error-control scheme for switch-toswitch buses in a network-on-chip. In: Proceedings of the international conference on hardware/software codesign and system synthesis (CODES-ISSS), pp 188–193 50. De Micheli G, Benini L (2006) Networks on chips: technology and tools. Elsevier, Amsterdam 51. Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC. VLSI Des. Article ID 94676:13 52. Fu B, Ampadu P (2008) A multi-wire error correction scheme for reliable and energy efficient SoC links using Hamming product codes. In: Proceedings of the IEEE international SoC conference (SoCC), pp 59–62 53. Fu B, Ampadu P (2008) An energy-efficient multi-wire error control scheme for reliable onchip interconnects using Hamming product codes. VLSI Des Article ID: 109490, 1–14, doi:101155/2008/109490 54. Fu B, Ampadu P (2009) On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans Circuits Syst I Reg Papers 56:2042–2054

Chapter 2

Solutions to Improve the Reliability of On-Chip Interconnects

Various noise reduction and error control techniques have been applied to improve the reliability of on-chip interconnects. Noise reduction techniques include increasing wire width and spacing [1, 2], shielding [3–7], repeater insertion [8–13], crosstalk avoidance codes [14–18], skewed transition [19–25] and decoupling capacitors [26–28]. Error control techniques improve the reliability of on-chip interconnect by correcting errors using retransmission, error control codes and spare wires. The use of these techniques relaxes the reliability requirements of circuit components reducing the cost of manufacturing, verification, and testing. In this chapter, we will review both noise reduction and error control techniques and their pros and cons.

2.1

Wire Sizing and Spacing

Increasing interconnect width has different effects on capacitive coupling and inductive coupling. When the interconnect width is increased, inter-wire capacitive coupling effects decreases because a wider wire has a larger ground capacitance. Inductive coupling increases with the interconnect width. Thus, the total impact of crosstalk coupling is only weakly dependent on interconnect width when both capacitive and inductive effects are considered [1]. Capacitive coupling is linearly related to the spacing between two interconnect lines. Increasing the interconnect spacing can effectively reduce the capacitive coupling. Inductive coupling is logarithmically related to the spacing between two wires [1, 2]. As the spacing between two interconnect wires increases, the inductive coupling decreases at a much slow rate than that of capacitive coupling. Above a certain threshold value of the spacing between two interconnect lines, inductive coupling will dominate the total coupling effects, as shown in Fig. 2.1. The dominancy of inductive coupling reduces the efficiency of using wider spacing to reduce crosstalk coupling. The drawback of using wire sizing and spacing is the increase of the link routing area. B. Fu and P. Ampadu, Error Control for Network-on-Chip Links, DOI 10.1007/978-1-4419-9313-7_2, # Springer Science+Business Media, LLC 2012

17

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2 Solutions to Improve the Reliability of On-Chip Interconnects

Fig. 2.1 Effects of wire spacing on the capacitive and inductive coupling noises [1]

2.2

Shielding

Shielding is the most common design technique to prevent crosstalk coupling. There are two kinds of shielding methods – passive shielding [3, 4] and active shielding [6, 7]. In passive shielding, the shield wires, which are statically connected to power or ground, are placed on either side of the signal wire. The effects of capacitive coupling is reduced by isolating the signal wire from its neighboring signal wires. Passive shielding also reduces inductive coupling by providing a closer return path for the operating currents. In [6, 7], an active shielding approach is proposed that connects the shield wires to the signal wire, as shown in Fig. 2.2. In the active shielding method, the shield wires have the same switching behavior as the signal wire. Active shielding can achieve a larger delay reduction than passive shielding by taking advantage of the Miller effect (The Miller effect states that when two parallel wires switch in the same direction, the effective coupling capacitance is zero, while when they switch in opposite directions, the effective coupling capacitance is doubled). Active shielding reduces the link power consumed by coupling capacitance; however, the self-switching power consumption is increased in active shielding because of the additional switching of the shield wires. Both active and passive shielding requires additional wires, greatly increasing link routing area. Instead of adding the shield wire for each signal line, shield wires can be inserted between every two to four signal wires to reduce the area cost while giving up some of the coupling improvement [3].

2.3 Repeater Insertion

19

Fig. 2.2 An example of active shielding

2.3

Repeater Insertion

In repeater insertion, a long interconnect line is separated into several segments, each driven by an inverting or non-inverting buffer. Repeater insertion has been successfully used to reduce the global interconnect delay. Without repeater insertion, the delay of global interconnect increases quadratically with the interconnect length. By properly sizing and placing repeaters, the global interconnect delay is reduced to a linear dependence on length. Repeater insertion can also be used to reduce the capacitive coupling noise between two adjacent interconnect lines. The coupling capacitance between two neighboring wires is proportional to the interconnect length. By inserting repeaters, a long interconnect wire is divided into several small pieces. The coupling capacitance of each segment is smaller than that of the overall link without repeater insertion resulting in a reduction in coupling noise. In traditional repeater insertion, each segment has the same length and each repeater has the same size, as shown in Fig. 2.3a. Traditional repeater insertion cannot effectively handle delay uncertainty caused by capacitive coupling between adjacent interconnect lines. In order to reduce the delay uncertainty caused by capacitive coupling, several new repeater insertion methods have been proposed [10–13]. In [10], a staggered repeater insertion scheme is presented to reduce the capacitive coupling effect by shifting the inverters locations on adjacent lines, as shown in Fig. 2.3b. In the staggered repeater method, the worst case delay is reduced because the transition with the worst case capacitive coupling is limited to only half of each segment. For example, the transition 010!101 with the worst case capacitive coupling in the first half of each segment becomes the transition 000!111 with the best case capacitive coupling in the second half of each segment. The performance of staggered repeater is sensitive to the repeater insertion position. Thus, the selection of the repeater position of staggered repeater insertion is more complex than that of traditional repeater insertion. An optimum position for staggered repeater insertion is presented in [11]. A hybrid polarity repeater insertion method is presented in [12], shown in Fig. 2.3c. In this method, inverting repeaters (single inverter) and non-inverting (two inverters) repeaters are alternately used at the midpoint of the bus. Similar to

20

2 Solutions to Improve the Reliability of On-Chip Interconnects

Fig. 2.3 Repeater insertion: (a) Traditional repeater insertion, (b) staggered repeater insertion, (c) hybrid polarity repeater insertion, (d) Alternate repeater insertion

the staggered repeater method, a worst case delay transition in the first half of a line becomes a best case delay transition in the second half. Thus the worst case delay is reduced by averaging the coupling effects during the transition across the whole bus

2.4 Crosstalk Avoidance Codes (CACs)

21

line. Compared to staggered repeater method, the hybrid polarity repeater method does not need a shift in repeater positions and the transition patterns are inverted only once at the middle point of the whole interconnect length. Instead of only using non-inverting repeaters at the midpoint of the bus line, an alternate repeater insertion method [13] is proposed by using inverting and noninverting repeaters alternately along the bus line, as shown in Fig. 2.3d. In alternate repeater insertion, the placement of the non-inverting repeaters is shifted for two adjacent interconnect lines. Alternate repeater insertion is suitable for a shared bus line with multiple drivers and receivers. As long as the driver and receiver are separated by more than one segment, the worst case delay caused by crosstalk coupling can be reduced.

2.4

Crosstalk Avoidance Codes (CACs)

The delay of a wire l in a k-bit bus can be modeled as [29], 8 2 l¼1 >