13.Computer-Aided Design of Integrated Circuits

13• Computer-Aided Design of Integrated Circuits

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Wiley Encyclopedia of Electrical and Electronics Engineering Automatic Testing Standard Article Lee A. Belfore II1 1Old Dominion University, Norfolk, VA Copyright © 1999 by John Wiley & Sons, Inc. All rights reserved. : 10.1002/047134608X.W1804 Article Online Posting Date: December 27, 1999 Abstract | Full Text: HTML PDF (207K)

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Abstract The sections in this article are Testing Principles Design for Testability Test Pattern Generation CAD Tools Mixed-Signal Testing Automatic Test Examples Emerging Technologies Summary Appendix 1. Acronyms and Abbreviations | | | Copyright © 1999-2008 All Rights Reserved.

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AUTOMATIC TESTING

AUTOMATIC TESTING This article describes the topic of automatic testing of electronic integrated circuits. Due to the variety of implementations and technologies, automatic testing takes several forms. Automatic testing first appeared in the form of automatic test equipment (ATE) to test newly manufactured integrated circuits. The automated operation of these devices facilitated the mass production of circuits. In ATE, the testing process consists of presenting a series of inputs to the circuits. Simultaneous with the presentation of inputs circuit outputs are compared against acceptable responses. In the event discrepancies appear, the devices were either scrapped or reconfigured into working circuits if the designs allowed. With the ever-increasing complexity of circuits, it was observed that some of the ATE capabilities could be integrated onto the same circuit to enable the circuit to either fully or partially test itself. In addition, built-in self-test circuitry is being integrated in increasingly complex chips conferring significant benefits in these applications. The science of automatic testing includes topics from several areas of knowledge. First, the defects must be classified according to models that accurately render the defect behavior of the circuit, giving test engineers a target for developing defect tests. Second, given a defect model, methodologies for determining test patterns must be examined. Indeed, circuits can be inherently easy to develop tests for, highly testable, while others may require special design practices to become easily testable. Built-in test circuitry facilitates the testing of a circuit. By adding special test structures, the circuit can be more easily testable. Third, in many cases, the number of tests to give acceptable test performance may be large, especially for circuits that are not designed to be testable. Fourth, simulation can assist the test engineer in assessing the efficacy of a particular test regimen. Fault simulations are used to determine what faults can be detected with the test regimen providing valuable feedback in the test design process. Two excellent references on topics related to automatic testing are (1,2). These works provide comprehensive treatment of testing methodologies. The ever-increasing complexity of integrated circuits and digital systems makes verifying that the circuit or system is fully functional more difficult. Circuit testers can control and observe system inputs and outputs, respectively, which may number in the thousands. The number of potential component failures in current systems can be in the range of billions. This mismatch between the number of inputs and outputs and the number of internal structures suggests that there are many challenges in testing these devices. If the direct effects

of the faults must be seen at the circuit outputs, it is likely that an enormous number of test patterns must be presented to the circuit, unless attention is paid to efficient generation of test patterns, design for test methodologies, and/or builtin self-test methodologies are employed. By allowing internal structures to automatically test themselves, the internal structures need only report that they are fault-free or faulty. Many vendors today supply modules and subsystems that can be included in larger designs. Because the design is considered intellectual property, many vendors do not want to release sufficient implementation details to enable construction of an effective test strategy. By incorporating Built-In Self-Test (BIST) capabilities in the subsystem, the vendor can supply a testable design without disclosing any details of the design. Importantly, the customer can achieve more acceptable testing results without needing to know the details of the design. Not surprisingly, economics plays a role in the manner in which testing approaches are applied. One study has shown (3) that in consumer electronics, BIST approaches may not be cost-effective. Testing affects the profitability of a design in several ways. BIST requires the addition of circuitry that is not necessary to maintain functionality. This additional circuitry increases the size of the chip. This increase in chip size reduces the number of chips that can be manufactured per wafer and also reduces the chip yields as a consequence of the increased die size. For high volume products, the costs can be enormous. For example, Intel calculated in 1995 for the Pentium processor, a 1% increase in chip area resulted in a $63 million increase in production costs. A 15% increase in chip area resulted in an almost $1 billion increase in production costs. A study done in Ref. 3 showed that high production chips that are part of consumer electronics typically have a useful design life of 2 years. For these chips, the addition of automatic test capabilities increased costs when all cost factors were taken into account. On the other hand, designs with longer useful design lives, say 5 years, benefit from an automatic test capability. This article is organized into sections including an introduction, a description of foundational testing paradigms, a description of commonly used automatic testing methodologies, CAD tool support, frontiers in automatic testing, and automatic testing case studies. In the section entitled ‘‘Testing Principles,’’ the general principles and methods for testing are introduced. This topic is covered in more detail in other encyclopedia articles. In ‘‘Economics of Test,’’ design for test methodologies are presented as they relate to automatic testing and in ‘‘Programmable Logic Arrays,’’ the subject of test pattern generation is discussed. In the section entitled ‘‘BuiltIn Self-Test,’’ these methodologies are discussed and in ‘‘CAD Tools,’’ the CAD tool support available in current tools is presented. In ‘‘Analog BIST,’’ the principles of automatic testing for analog systems are presented. In ‘‘Automatic Testing Case Studies,’’ several actual implementations that employ automatic testing are presented, and in the next section the frontiers of automatic testing are described.

TESTING PRINCIPLES In this section, several topics related to testing methodologies, techniques, and philosophy are discussed. Many auto-

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

AUTOMATIC TESTING

Bridging fault A G1

B C D E F

G2 G3

G H I

SA-1 G4

J

D

Q

Delay

Memory K

Figure 1. An illustration of fault models. Digital circuits are susceptible to many types of faults.

mated testing approaches are derived from the less restrictive testing methodologies. For a more in-depth discussion of testing techniques, the interested reader should see Refs. 1 and 2. Fault Modeling Circuits can fail in many ways. The failures can be a result of manufacturing defects, infant mortality, random failures, age, or external disturbances (4). The defects can be localized, affecting the function of one circuit element or distributed, affecting many or all circuit elements. The failures can result in temporary or permanent failure of the circuit. The quality and detail of the fault models can have an impact on the success of the test strategy. In addition, the fault model may have an impact on the overall test strategy. In order to develop effective testing methodologies, accurate models for circuit failures must be agreed upon and targeted by the testing approach. The fault models selected depend on the technology used to implement the circuits. Manufacturing defects exist as a consequence of the manufacture of the circuit. The introduction and study of manufacturing defects is a heavily studied topic because of its impact on the profitability of the device. Dust or other aerosols in the air can affect the defect statistics of a particular manufacturing run. In addition, mask misalignment and defects in the mask can also increase the defect densities. Figure 1 gives some example faults which are discussed in more detail in the following sections. Stuck-at Fault Models. Stuck-at fault models are the simplest and most widely used fault models in testing. The stuckat fault model requires the adoption of several fundamental assumptions. First, a stuck-at fault manifests itself as a node being stuck at either of the allowable logic levels, either zero or one, regardless of the inputs that are applied to the gate that drives the node. Second, the stuck-at fault model assumes that the faults are permanent. Third, the stuck-at fault model assumes that gates maintain their ordinary function in the presence of the fault. Significantly, the stuck-at fault model also models a common failure mode in digital circuits. The circuit shown in Fig. 1 can be used to illustrate the fault model. The output of gate G1 can be stuck-at 1 as a result of a defect. When the fault is present, the corresponding input to G4 will always be one. In order for the fault to manifest itself, a discrepancy must occur in the circuit as a conse-

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quence of the fault. To force the discrepancy, the circuit inputs are manipulated so that A ⫽ B ⫽ 1, with the discrepancy appearing at the output of the gate. This discrepancy may ultimately result in the system malfunction. A second example circuit is shown in Fig. 2, consisting of an OR gate (G1) driving one input in three AND gates (G2, G3, and G4). Consider the occurrence of a stuck-at 1 fault at the input to G1, the fault results in the output being 1 as a consequence of the fault. In this simple example, one can thus observe the indistinguishability between output and input stuck at 1 faults. For modeling purposes, these faults can be collapsed into a single fault. In the event gate input I2 has a stuck-at 0 or 1 fault, the situation is somewhat different. In this case, O1 ⫽ I3 ⫽ I4 and G3 and G4 will not be directly affected by the fault. Delay Fault Models. A delay fault is a fault where a part of the circuit operates more slowly, relative to other circuit structures when a fault is present. When such a fault is present, the circuit may operate correctly when operated at slower clock rates, but does not operate at speed under certain circumstances. Delay faults can be modeled at several levels (5). Gate delay fault models are modeled as excessive delay in a gate as a consequence of faults. The transition fault model is either a slow to transition from 0 to 1 or from 1 to 0. A path delay fault is present when the propagation delay through a series of gates is larger than some desired delay. Indeed, a current industry practice is to perform statistical timing analysis of parts. The manufacturer can determine that the parts can be run at a higher speed with a certain probability so that higher levels of performance can be delivered to customers. However, this relies on the statistical likelihood that delays will not be worst case (5). By running the device at a higher clock rate, devices and structures that satisfy worst-case timing along the critical path, may not meet the timing at the new higher clock rate. Hence, a delay fault can appear as a consequence of the manufacturing decisions. Assuming the

G2 I2

G1

O1

G3 I3

G4 I4

Figure 2. Illustration of input stuck-at faults. O1 stuck-at O forces the outputs of gates G2 , G3 , and G4 to be stuck-at 0.

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Clock

J J

∆

Delay fault

Q Q

∆

Figure 3. Illustration of a delay fault. The presence of a delay fault causes the wrong value to be clocked into the flip-flop.

indicated delay fault in Fig. 1, Fig. 3 gives a timing diagram showing manifestation of the fault. In this circuit, the delay fault causes the flip-flop input, J, to be delayed for a particular combination of inputs and input change(s), resulting in value being stored in the flip-flop being delayed by one clock period. Because of the nature of the delay fault, the circuit must be tested at speed in order to detect the delay fault because at slower clocks, the circuit will operate correctly since the circuit functions correctly at slower clocks. Furthermore, because the delay fault is dynamic, in order to detect the fault, the combinational circuit must receive an input change and the flip-flop must be clocked to make the delay fault observable. Bridging Faults. Bridging faults are the presence of an undesirable electrical connection between two nodes. This connection results in the circuit malfunctioning or behaving in a degraded fashion. Furthermore, bridging faults may manifest themselves in wired-and or wired-or fashions, changing the circuit function. In addition to degrading the signal, the bridging fault may be manifested as stuck faults when bridging faults occur between a node and the supply lines or as a sequential circuit when the bridging fault creates a feedback connection (5a). Bridging faults require physical proximity between the circuit structures afflicted by the bridging faults. Figure 1 gives an example of a bridging fault that changes the combinational circuit into a sequential circuit. CMOS Fault Models. CMOS technology has several fault modes that are unique to the technology (5a). Furthermore, as a consequence of the properties of the technology, CMOS offers alternative methods for identifying defective circuits. CMOS gates consist of complementary networks of PMOS and NMOS transistors configured such that significant currents may be drawn only when signal changes occur. When no signal changes occur, the normally working circuit draws very low leakage currents. Since the CMOS circuit should only draw currents when the circuit is switching, any significant divergence from a known current profile is indicative of faults. For example, the gates may logically function correctly, but as a consequence of the faults being present, the circuit may show abnormally large power supply currents. These changes in current draw characteristics can be used as a diagnostic for indicating the presence of faults and in possibly identifying the faults. Testing for faults based on this observation is called IDDQ testing. Bridging faults are common in CMOS circuits (6) and are ef-

fectively detected with IDDQ testing (7). IDDQ faults can have a significant impact on portable designs where the low current drawn by CMOS circuits is necessary. CMOS circuits also have an interesting failure mode where an ordinary gate can be turned into a sequential circuit. The fault is a consequence of a transistor failure, low quiescent currents, and capacitive gate inputs. In Fig. 4, if transistor Q1 is stuck open, the gate input to the inverter, G1 dynamically stores the prior value on node C when A ⫽ 0 and B ⫽ 1. In order to make this fault visible, C must be forced to 1 by setting A ⫽ B ⫽ 0 followed by setting B ⫽ 1 to store the value at the input of G2. Memory Faults. Semiconductor memories have structures that are very regular and very dense. As a result, they can exhibit faults that are not ordinarily seen in other circuits which can complicate the testing process. The faults can affect the memory behavior in unusual ways (8). First, a fault can link two memory cells in such a way that when a value is written into one cell, the value toggles in another cell. Second, the memory cell can only be written to 0 or 1 but cannot be written the opposite value. Third, the behavior of a memory cell may be sensitive to the contents of the neighboring cells. For example, a particular pattern values stored in surrounding cells may prevent writing into the affected cell. Fourth, the particular pattern of values stored in the cells can result in the value in the affected cell changing. The nature of these faults make their detection challenging. Crosspoint Faults. Crosspoint faults (1) are a type of defect that can occur in PLAs (Programmable Logic Arrays). PLAs consist of AND arrays and OR arrays with individual terms included in each through the programming of transistors that either include or exclude a term through the presence or absence of connections in the array. In field programmable devices, a transistor is programmed to be on or off, respectively, to represent the presence or absence of a connection. A crosspoint fault is the undesired presence or absence of a connection in the PLA. The crosspoint fault can result in a change in the logic function that cannot be modeled by the stuck fault model. A crosspoint fault with a missing connection in the AND array results in a product term of fewer variables while an extra connection results in more variables in the product term. For example, consider function f(A, B, C, D) ⫽ AB ⫹ CD implemented on a PLA. The existence of a crosspoint fault can change the function to f cpf (A, B, C, D) ⫽ ABC ⫹ CD. Fig-

A Capacitive input

B

C

D

Q1 Stuck-open

G1

G2

Figure 4. An illustration of a CMOS memory fault. CMOS circuits can suffer faults that impart sequential behaviors.

AUTOMATIC TESTING

A B C D

Crosspoint fault

Figure 5. An illustration of a crosspoint fault. The crosspoint fault results in the programmable logic array to evaluate the wrong function.

ure 5 diagrams the structure of the PLA and the functional effect of the crosspoint fault. Measures of Testing In order to gauge the success of a test methodology, some measure of the testing success and overheads are necessary. In this section, the measures of test coverage, test set size, hardware overhead, and performance impact are discussed. Test Coverage. Test coverage is the percentage of targeted faults that have been covered by the test regimen. Ideally, 100% test coverage is desired; however, this can be misleading if the fault model does not accurately reflect the types of faults that can be expected to occur (8a). For example, the stuck fault model is a popular and simple model for faults that works well in many situations. CMOS circuits, however, have several failure modes that cannot be modeled by the stuck fault model. A stuck fault test can be constructed that covers 100% of the stuck faults, yet may be only partially successful in identifying other faults. Fault coverage is determined through fault simulation of the respective circuit. In order to assess the performance of a test, a fault simulator must be able to accurately model the targeted fault to get a realistic measure of fault coverage. Size of Test Set. The size of the test set is an indirect measure of the complexity of the test set. The size of the test set impacts the test time which has a direct impact on circuit cost if expensive circuit testers are employed. In addition, the test set size is related to the effort, both in personnel and computationally, that was required to develop the test. The size of the test set depends on many factors including the ease with which the design can be tested as well as implementation of Design for Test (DFT) methodologies. Indeed, DFT methodologies may not necessarily result in shorter tests. Use of scan path approaches where flip-flops are interconnected as shift registers gives excellent fault coverages, yet the process of scanning into and out from the shift register can result in large test sets. Hardware Overhead. The addition of circuitry to improve testability or incorporate BIST capabilities can increase the

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size of a chip or system and as shown previously can have a disproportionate impact on circuit costs. In the event improved testability is a requirement, the increase in hardware can be used as a criteria for evaluating different designs. The ratio of the circuit size with test circuitry to the circuit without test circuitry is a straightforward measure of the hardware overhead. The additional circuitry for test can increase the likelihood that defects are present in the test circuitry. In addition, failure rates of circuits in service are a function of the size of the circuit, where larger circuits have higher failure rates. Impact on Performance. Likewise, the addition of test circuitry can have an impact on system performance. The impact can be measured in terms of reduced clock rate and higher power requirements. For example, scan design methods add circuitry to flip-flops that multiplex between normal and test modes which typically have larger delays as compared to circuits not equipped. For devices with fixed die sizes and PLAs, the addition of test circuitry may be at the expense of circuitry that improves the performance of operation. Testability. Testability is an analysis and metric that describes how easily a design may be tested for defects. In testing a circuit for defects, the goal is to supply inputs to the circuit so that it behaves correctly when no defects are present, but which malfunctions if a single defect is present. In other words, the only way to detect the defect is to force the circuit to malfunction. In general, testability is measured in terms of the specific and collective observability and controllability of nodes within a design. For example, a circuit which gives the test engineer direct access (setting and reading) to flip-flop contents is more easily testable than one does not, which would give a corresponding better testability figure. In the test community, testability is often described in the context of controllability and observability. Controllability of a circuit node is the capability of being able to set the node to a particular value. Observability of a circuit node is the ability of being able to observe the value of the node (either complemented or uncomplemented) at the circuit outputs. Estimates of the difficulties of controlling and observing circuit nodes form the basis for testability measures. Figure 6 presents a simple illustration of the problem and process. The node S is susceptible to many types of faults. The general procedure for testing for the correct operation of node S is to control the node to a value contrary to the fault value. Next, the observed value of the signal is communicated to the outputs of the system for observation. Detecting faults with redundancy of any sort requires special consideration in order to be able to detect all possible faults. For example, fault tol-

Rest of circuit Primary outputs Primary inputs

S

Figure 6. Representative circuit with fault. In order to test for faults on S, the node must be controlled by the inputs and observed at the outputs.

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AUTOMATIC TESTING

erant systems that employ triple modular redundancy (TMR) will not show any discrepancies at the circuit outputs when one fault is present (4). In order to make the modules testable, they must be somehow separated so that the redundancy does not mask the presence of faults. In addition, redundant gates necessary to remove hazards from combinational circuits result in a circuit where certain faults are untestable. Testability can be achieved by making certain internal nodes observable. Automatic Test Equipment Automatic test equipment tests integrated circuits by applying a set of inputs and comparing output responses with known good responses. The equipment can be used to determine whether a circuit works or not. If desired, the tests can be constructed to indicate what part of the circuit has failed. In the event the circuit outputs differ from the known good responses, the circuit is labeled as bad. Reference 8b gives a good overview of ATE. A block diagram of an automatic tester is shown in Fig. 7. Each of the major blocks will be discussed. Circuit Under Test (CUT). The circuit under test (CUT) is the device that is under test. Testing can be conducted on the device at several points in the manufacturing process. For example, the device can be tested immediately after manufacture, before the wafer has been broken up into individual dies. At the other end of the spectrum, the circuit can be tested after the die has been packaged. The circuit can also be tested after it has been placed into service. Bed of nails testers have some capacity to test devices that are an integral part of the circuit board. In order to achieve an accurate and reliable test, the tester must operate at the device speed and also check the timing of all parameters to specifications. In practice, the testers can test the device at speed; however, the testers can be extremely restricted in their capacity to check for exact timing. The problem lies in the manner in which outputs are checked. In most testers, the outputs are sampled at a regular rate. For example, the Teradyne model J971SP is capable of a peak data rate of 400 MHz, or 2.5 ns per pattern (http:// www.teradyne.com/prods/std/j971/j971.html). In addition, a tester capable of taking samples at this rate must be capable of accepting the outputs and incorporating them in a process that can determine whether the device is defective or not. Input Generator. The input generator can provide previously specified patterns or have some capacity to generate

Input generator

Inputs

Cut

Outputs

Output collector

Output analyzer

Good Defective

Feedback used for adaptive tests Figure 7. Block diagram of an automatic tester. The automatic tester is used to test integrated circuits.

patterns. The simplest and most straightforward implementation is in the form of a memory that holds patterns that have been specified by a test engineer. The memory architecture must be designed to be able to supply patterns at a rate consistent with the test rate. Alternatively, the patterns applied to the CUT can adapt depending on the output responses of the CUT. For example, in the event the CUT is defective, an adaptive test can be applied to identify the specific defect. Lastly, patterns can be generated in a pseudorandom fashion. Pseudorandom pattern generation has the benefit of requiring simple circuitry that has provable probabilistic defect coverage for combinational circuits which is a function of the number of pseudorandom patterns that have been applied. Output Collector. The output collector collects the output results for subsequent passage to the output analyzer. One form of output collector is a simple pass through operation. In this form, the outputs of the circuit are passed to the output analyzer without modification. In some testing applications, the output collector compacts the output responses into a signature that is indicative of whether or not defects are present in the CUT. In many digital circuits, Linear Feedback Shift Registers (LFSRs) are used to compute the signatures. Other applications may utilized different structures to compute the signatures. For example, in Digital Signal Processing (DSP) applications, a digital integrator is shown to compute a signature with provable fault detection capabilities (9). Output Analyzer. The purpose of the output analyzer is to determine whether the circuit is operating fundamentally defect free. In many automatic testers, the output analyzer consists of a memory containing all of the expected responses to the circuit. For each presentation of the input, the CUT outputs are compared to the previously determined good circuit outputs. A miscomparison results in the circuit being found to have one or more defects. The miscomparison usually does not indicate the specific location of the tests; however, additional tests may be required to identify the locations. In the event that the specific defect location is desired, additional likely adaptive tests would be necessary. Through a searching process, output results can be fed back to the input generator to emit tests consistent with the searching process. In the event output response compaction has been applied, relevant comparisons with the compacted signatures will be applied. Parametric Testing. Parametric testing tests the electrical characteristics of the signals. For example, circuit outputs are generally required to be able to sink and source particular current levels while maintaining acceptable logic levels. Such testing requires measurement of both voltage and current parameters. In addition, testers have the capability to perform some timing tests that are in addition to performance related to device clock frequency. Economics of Test Not surprisingly, economics plays a role in how testing approaches are applied (3). In the manufacturing process, defects will occur, so it is impossible to ignore testing entirely. The costs include design, manufacturing, testing, and maintenance costs. On the design side, the engineer must decide what, if any, test structures to include in the design. If these

AUTOMATIC TESTING

design structures are not in a library, they must be designed. In addition, the actual test regimen must be constructed. Complicating the matter, the costs associated with the test regimen can affect the costs associated with constructing the test set. Employing many design for test (DFT) approaches reduces the effort needed to develop test regimens. Since these costs are incurred in the design phase, they can be distributed over the manufacturing run, with a large manufacturing run minimizing the impact of the larger design costs. The manufacturing costs are direct costs and are incurred with the manufacture of each device. In general, adding DFT capabilities increases the die size of the device, reducing the number of manufactured dies. Assuming standard yield models and assuming that no redundant capacity is included to compensate for increased die defect rates, the yield of the individual dies is reduced. Using highly simplistic assumptions, some useful observations can be made. First, the wafer is assumed to be 15 cm in diameter, the die area is 1 cm2. This example assumes that the entire wafer area is available for dies makes no attempt to compensate for test dies, test regions, or dies on the perimeter. In this example, 706 dies can be manufactured on each wafer. Assuming DFT increases the die area by 10%, the number of dies on the wafer is reduced to 642. Assuming a fixed cost to manufacture each wafer, the apparent cost per die increases by 10%. More significantly, the defect yield models show that the fraction of good dies manufactured decreases nonlinearly with the increasing area. Assuming negative bilinear defect statistics and an average of 1 defect/cm2, the yield of the 1 cm2 die is 44.4% producing 313 working dies, while the yield of the 1.1 cm2 is 41.6% producing 267 working dies. The cost per working die manufactured is 17% higher for the circuit that employs test circuitry. Testing of the manufactured device is an essential aspect of the manufacture. The extensiveness of the testing performed and the design for test approaches used in the design can impact the testing cost. To determine whether or not the device is defect free, a series of test inputs are applied to the device and the responses are observed. In the event the observed behaviors differ, the device is marked as bad. DFT in some cases can simplify and reduce in number the set of test inputs and can reduce testing time proportionately. Furthermore, circuits with BIST capabilities can dramatically reduce or even eliminate the reliance on external test equipment. In addition, testing can be used to qualify a part according to a government or industry standard. For example, burn-in is the process of running a device just after manufacture in order to weed out the weaker parts. Failure of these parts is termed infant mortality due to the early failure and the increased failure rates of newly manufactured parts. Additional testing can be performed at the extremes of temperature, vibration, and humidity to receive qualification for devices used in military designs. Maintenance costs are related to the costs of the device once it is placed in service. While the device is in service, device failures can cause the system within which it is contained to fail. Indeed, without some sort of built-in self-test (BIST) capability, determining the cause and compensating for the failure can be difficult. For a device within the system, determining the difference between defect and design flaw may be extremely difficult. Incorporation of a built-in test capability can greatly enhance the maintainability because the

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device, in effect, may be able to indicate its failure and simplify the task of the equipment maintainers. DESIGN FOR TESTABILITY Design for testability methods are used to simplify and enhance the testing process through analysis and application of methodologies to facilitate easier testing. The understanding of DFT requires background in several areas. These include understanding how circuits fail, the models for circuit failure, and general methods for identifying circuit failures. Automated testing can be performed in several fashions which can have a great impact on design (1,2). First, the test can be performed either on-line or off-line. In an off-line test, the system is taken out of service to perform testing. Once the system is out of service, the CUT is either placed in an ATE or BIST circuitry is enabled and the test is performed. BIST approaches will be discussed in detail in the next section. Once testing has been conducted, the system continues its normal function. An on-line test requires the system to remain in service. In one approach, the system is tested at idle times, where the system is operational but has no tasks to perform. This type of test is nonconcurrent, because the test and the circuit function are mutually exclusive. On-line concurrent testing requires testing to be performed concurrent with ordinary circuit function. A simple on-line testing approach is parity checks of transmitted data, however which may have unacceptable fault latencies. Special design techniques may be necessary to support on-line concurrent testing with high fault coverage that achieve low fault latencies. Test Point Selection A simple method for improving the testability of a design is through the addition of judiciously selected test points to serve as auxiliary points for controlling and observing internal nodes of the circuit. The identification of these points can follow from a testability analysis of the entire design by determining the difficulty with which internal points may be tested. Circuit notes that are among the most difficult to test are selected as the test points. As test points are identified, the testability analysis can be repeated to determine both how well the additional test points improve testability and to determine whether additional test points are necessary. The disadvantages to employing test points is that this approach is an ad hoc method for identifying test points and the test points will require additional inputs and outputs to the system. Scan Design Methods Scan design methods are DFT methods that build on the test point selection methodology by identifying specific circuit structures that would serve as suitable points for test points. Furthermore, these test points are interconnected as a large shift register enabling direct controllability and observability at all stages of the shift register. The scan design methods use either the flip-flops that are part of the design or other ‘‘geographic’’ clues such as system partitions to define the shift register paths. A key feature of scan design methods is that large sequential circuits are broken into smaller pieces that are more easily tested. Taken to its fullest extent, the

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circuit is decomposed entirely into combinational and sequential parts. Historically, these approaches follow from techniques incorporated into the IBM System/360 where shift registers were employed to improve testability of the system (10). A typical application of a scan design is given in Fig. 8. Note the switching of the multiplexer at the flip-flop inputs controls whether the circuit is in test or normal operaiton. Differences between different scan design methods occur in the flipflop characteristics or in clocking. Scan Path Design. In scan path design (11), the circuit is designed to operate in one of two modes: normal and test. When the circuit operates in normal mode, all test circuitry is disabled and the circuit operates per its functional requirements. When in test mode, all flip-flops are reconfigured into a shift register whose contents can be scanned in or out through special test inputs and outputs to the circuit. The purpose of the shift register is to give direct controllability and observability to all the flip-flops in the shift register. In essence, the test mode decomposes the circuit into its sequential and combinational parts. The combinational logic can be tested with any of the well-known approaches for developing test patterns for combinational circuits. Relevant aspects of the design include the application of a race-free D flip-flop improving testability of the flip-flops. Level Sensitive Scan Design. One long-standing and successful DFT approach is IBM’s level sensitive scan design (LSSD) approach (12). Similar to the scan path approach, the circuit

d1 d0 Y

Boundary Scan Techniques. In many design approaches, the option of applying design for testability to some components is impossible. For example, standard parts that might be used in Printed Circuit Boards (PCBs) which are not typically designed with scan path in mind. As another example, more and more ASIC design consists of design using cores, subsystems designed by third party suppliers, in the design. The core subsystems are typically processors, memories, and other devices that until recently were individual VLSI circuits themselves. To enable testing in these situations, boundary scan methods were developed. Boundary scan techniques employ shift registers to achieve controllability and observability at the input/ output parameters of circuit boards, chips, and cores. An important application of boundary scan approaches is to test the interconnect between chips and circuit boards that employ boundary scan techniques. In addition, the boundary scan techniques provide a minimal capability to perform defect testing of the components at the boundary. The interface to the boundary scan is a test access port (TAP) that enables setting and reading of the values at the boundary. In addition, the TAP may also allow internal testing of the components delimited by the boundary scan. Applications of boundary scan approaches include BIST applications (13), test of cores (14), and hierarchical circuits (15). The IEEE has created and approved the IEEE Std 1149.1 boundary scan standard (16). This standard encourages designers to employ boundary scan techniques by making possible testable designs constructed with subsystems from different companies that conform to the standard.

D Q

Built-In Self Test

S

Combinational logic

can be operated on one of two modes: normal and test. A key difference between the approaches is in the structure of the flip-flops. In LSSD, two clock phases are used to clock flipflops to guarantee the detection of clock faults.

d1 d0 Y S

D Q

d1 d0 Y S

D Q

Clock Test Figure 8. Scan path test structure. All flip-flops can be configured into an externally loadable shift register. In this configuration, combinational logic can be tested directly.

Built-In Self Test (BIST) approaches add circuitry to a design to enable the circuit to test itself. The test can, depending on its design, be conducted autonomously or while the device is out of service. The necessity of requiring the device to test itself places constraints on the manner in which inputs are generated for the design and monitoring the outputs, when compared with a test used in conjunction with ATE. Furthermore, in cases where ATE testing is difficult, the device test can be composed of a combination of ATE testing and BIST approaches. Running chip tests on all devices can be expensive, especially when yields are low. Effective application of BIST can enable circuits to assess their own health, reducing the amount of time necessary on expensive automatic test equipment. Furthermore, BIST enables systems in service to be configured to run automated tests. The benefit of this type of test is that systems can determine their health and report a failure possibly before problems appear at the system level. Second, for systems that have built-in redundancy, the results from an automated test can be used to switch-out a failed component or module and insert a new module. BIST can require that the designer conform to a particular set of design rules and require additional circuitry be added to the system being designed. This can reduce design flexibility by restricting the types of designs that are possible as well

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as potentially restricting the functionality of the design so that the entire system can fit in one device. Despite this, BIST approaches confer great benefits. Test Pattern Generation and Built-In Test. The requirement for built-in test places great restrictions on the test generation process in two ways. First, the actual generation of test patterns must be self-contained within the circuitry itself. This implies the presence of circuitry that generates sequences of test patterns. While in theory, circuitry can be designed to produce any test pattern sequence, in practice the required circuit may be excessive or impossible to include. As a result, simpler circuitry must be employed in order to perform test pattern generation. Three classes of circuits are typically employed because they have good asymptotic performance and because they have the ability to produce any sequence of test patterns. The first type of circuit is a simple counter. The counter can be constructed asynchronously and will thus only require as many flip-flops as there are test inputs. Counter solutions may be impractical for two reasons. First, if the number of test inputs are large, the time required to count through the entire sequence can be too long. Second the counter may be unable to test for other types of faults, such as delay faults or CMOS faults. Researchers have investigated reducing the count sequence so that more reasonable test lengths can be achieved (22). The second type of circuit generates pseudorandom sequences with LFSRs. Theoretically, as the number of random test patterns applied to the circuit increases, fault coverage increases asymptotically to 100%. Much research effort has gone into the development of efficient pseudorandom sequence generators. An excellent source on many aspects of pseudorandom techniques is (17). Third, a special circuit can be constructed that efficiently generates the test patterns. In this case, the desired sequence of test patterns are examined and a machine is synthesized to recreate the sequence. Memory tests have shown some success in using specialized test pattern generator circuits (27). In order to determine whether a fault is present, the outputs of the circuit must be monitored and compared with outputs representative of fault-free behavior. Test pattern generation equipment solves this by storing the expected behaviors for the circuit given the sequence of inputs supplied by the tester. Similar to the problem of supplying test patterns in the context of automatic testing, it may be impractical to store or recreate the exact circuit responses. Duplication approaches (several are summarized in Ref. 4) can be employed to duplicate a subsystem to ensure that a copy of the expected circuits are available. By completely duplicating the system circuitry, the duplicated systems can be operated concurrently from the same set of inputs where any discrepancy between the duplicated systems results in the detection of a fault. While this approach may be applicable to systems requiring high reliability or fault tolerance, it would be an undesirable approach in most cases. Another widely used solution is to compress the circuit responses into a special code word, a signature, that is indicative of the presence or absence of faults. The signature represents the lossy compression of the circuit responses. The computation of the signature should achieve high probability of detecting the faults in the system while using the smallest quantity of resources to do so.

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Methods for Compressing Test Data Sets. As indicated, test set compression is essential to producing economical test cases for use in automatic testing. Compression methods utilize test hardware in a fashion that retains much of the fault detection capabilities, while minimizing testing resources. The compaction process can be measured with respect to the following attributes (25): space, time, function specificity, linearity, and memory. The test data set can be represented as a two-dimensional matrix where each row is associated with one measurement point and each column corresponds to a test pattern that is applied at a particular time. Compression is a transformation that reduces the size of this matrix. The compression may or may not reduce the effectiveness of the overall test; however, a small reduction in test coverage is often acceptable. Space and time compression occur when the number of rows and/or columns are reduced. The compression can be expressed mathematically as D ⫽ ⌽C, where D is the original test data matrix, C is the compressed test data matrix, and ⌽ is the compression transformation. The manner in which the transformation ⌽ is selected affects the matrix size as illustrated, but it may have implications in regards to the remaining three attributes. Function specificity occurs when the transformation relates the number of compactor stages to either the number of inputs or test patterns, or also if the compaction is related to the sequences of binary patterns or inputs. Linearity is a property that follows from using the exclusive OR function to derive ⌽, which can be shown to be a linear operator in the finite field GF(2) (26). For example, systems such as the LFSR would be considered a linear time compactor. Memory is the property that a bit in D is a function of both past and present bits in C. For example, space compression measures the reduction in test data width. For example, consider a test strategy constructed that uses 100 test points. Suppose further that the values from pairs of test points are exclusive or gates are exclusive together. If the resulting 50 signals are monitored, a space compaction of 50% is realized. Time compaction occurs when the number of columns is reduced by some process. For example, SISRs and MISRs can be used to compress the number of columns to 1. Signature Analysis. Signature analysis is the process of compressing output responses frequently used in BIST with a Single Input Shift Register (SISR) or Multiple Input Shift Register (MISR) to compute a signature, which is a compression of the output responses (17). The signature is a quantity that is representative of the condition of the system. Figure 9 gives the architecture of SISRs and MISRs. A signature for

Test input

... Test input

LFSR

LFSR

Signature

Signature

A. SISR

B. MISR

Figure 9. Signature generation architectures. The signature can be computed by sampling one signal or several at the same time.

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D Q

D Q

D Q

D Q

Figure 10. Linear feedback shift register. The LFSR is a key building block in the implementation of signature generation, pseudorandom pattern generation, and code generators/checkers.

the known good circuit is compared with the signature for the CUT where any discrepancies indicate the presence of a defect. SISR and MISR are linear sequential compaction schemes of the observed test point(s). The architecture of SISR and MISR are LFSRs at the core which are both forms of LSFRs. The signature, being a compression of output responses, gives no indication of the failure. Furthermore, the number of bits in the signature is far less than the number of test patterns. As a result, several different circuit conditions can result in the same signature, termed aliasing. In practice, if a fault is present, it is desired that the signature produced differs from the fault-free case. It is possible in some designs for the signature to be the same even though it was the result of compaction of an entirely different set of output results. In Ref. 18, the aliasing probability upper bounds were derived for signatures computed with SISRs. In addition in Ref. 19, methods for developing MISRs with no aliasing for single faults were developed. LFSRs have properties that are useful for generating effective signatures. First, the LFSR approach offers a simple and effective compaction approach for the detection of faults in the circuit. The LFSR consists of some number of flip-flops, N, an linear connections fed back to stages nearer the beginning of the shift register. The general structure of the LFSR used as an SISR is shown in Fig. 10. In addition, other types of circuits have shown the ability to effectively compute signatures. For example, DSP often results in modular design constructed from accepted DSP building blocks. In particular, digital integrator circuits have been employed to compute signatures (9). BILBO. The built-in logic block observer (BILBO) approach has gained a fairly wide usage as a result of its modularity (28). The BILBO approach is derived from scan path approach

where the scan circuitry and other functions are encapsulated in a BILBO register. In addition, connections within the BILBO register enable computation of a signature, suitable for fault detection. A four-bit BILBO register is shown in Fig. 11. BILBO registers operate in one of four modes. The first mode is used to hold the state for the circuitry as D flip-flops. In the second mode, the BILBO register can be configured as a shift register that can be used to scan values into the register. In the third mode, the register operates as a multiple input signature register (MISR). In the fourth mode, the register operates as a parallel random pattern generator (PRPG). These four modes make possible several test capabilities. One example application of BILBO registers is shown in Fig. 12. In test mode, two BILBO registers are configured to isolate one combinational logic block. The BILBO register at the input, R1, is configured as a PRPG, while the register at the output, R2, is configured as a MISR. In operation, for each random pattern generated, one output is taken and used to compute the next intermediate signature in the MISR. When all tests have been conducted, the signature is read and compared with the known good signature. Any deviation indicates the presence of faults in the combinational circuit. In order to test the other combinational logic block, the functions of R1 and R2 need only be swapped. Configuration of the data path to support test using BILBO registers is best achieved by performing register allocation and data path design with testability in mind (29). Memory BIST. Semiconductor memories are regular structures manufactured with the goal of maximizing the capacity for a given area of silicon. While in principle the memories can be tested as other sequential storage elements, in reality the overhead associated with utilizing scan path and similar test approaches would severely impact the storage capacity of the devices. The regularity of the structure, however, gives the capability of testing the memory with hardware structures outside the memory arrays proper. Among the test design considerations of memories is the number of tests as a function of the memory capacity. For example, a test methodology was developed (27) for creating test patterns. These test patterns could be computed using a state machine that is relatively simple and straightforward. The resulting state machine was shown to be implementable in random logic and as a microcode driven sequencer.

D Q

D Q

D Q

D Q

Q

Q

Q

Q

S Shift in

d1 Y d0

Figure 11. Four-bit BILBO register. The BILBO register can operate in one of four modes: simple register, shift register, pseudorandom pattern generator, or signature register.

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function is defined in terms of the original function in the following way Combinational logic

f dual (x1 , x1 , . . ., xn ) = f (x1 , x2 , . . ., xn )

R1 (BILBO)

PRPG

Combinational logic

MISR

R2 (BILBO)

Figure 12. Example BILBO architecture. BILBO registers are used in pairs to isolate combinational logic functions.

Programmable Logic Arrays With the increasing complexities of programmable logic arrays (PLAs) with sizes approaching 1 million devices, PLA test is becoming an important part of the design process. PLA test can be viewed from two perspectives. First, the ‘‘blank’’ device can be tested and deemed suitable for use in an application. Second, the programmed device may be subject to the testing process, itself. Self-Checking Circuits Self-checking circuits (SCCs) are circuits that, by their construction, have the inherent capability to detect whether a failure exists in their circuitry (4). Self-checking circuits are not employed in typical applications because of the overhead required which can be slightly more than 50% additional circuitry. SCCs enable automatic testing while the circuit is operational and can achieve high fault coverage without extensive test structures or regimens. The key feature of SCCs is that they employ complementary circuits and convey information using a codeword consisting of two bits. The pair of bits represents the true and complementary values of the signal being transmitted. Any fault results in the pair of signals being identical, allowing clear detection of the fault. A simple example of such a SCC is shown in Fig. 13. The dual of a

x1 x2 X1

Dual of f

f

xn

(1)

In short, the dual outputs the complement of the desired function given the complements of the inputs. In ASIC development, SCCs provide two levels of protection and detection of faults. First, if either the function or its dual has fault, then only that function is affected. As a result, if the fault is present, either the circuit will provide the correct output or it will give the incorrect output. In the event the incorrect output is supplied, an error will be detected because the dual function will still be providing the correct output. Second, in the event of a failure in the design tools, the function and its dual may be affected in different ways so that a tool failure will have a higher probability of detection. The final issue that must be addressed in SCCs is the checking circuitry. The checking circuitry must be designed to both detect incidences of illegal signal combinations and be self-checking, itself. SCCs are use in applications where fault detection is essential to the completion of the mission and are rarely used in common applications. Cases where SCCs might be used are space and aerospace applications. TEST PATTERN GENERATION Two general approaches can be used for developing tests that achieve high fault coverage. The first approach employs functional test and the second specifically targets defect tests. A test is an input or sequence of inputs that can be used to detect a fault in a circuit. For example, in Fig. 14, a test for G SA-1 is ABCDEF ⫽ 110X0X, where X is a don’t care. Note that by setting AB ⫽ 11, the expected value on node G is 0, while with the fault present the fault value is 1. In addition, setting CD ⫽ 0X and EF ⫽ 0X enables the propagation of the discrepancy due to the fault to the output of G4, where it can be detected by examining node J. Test pattern generation is the process of determining a set of test patterns that result in an effective test giving an acceptable test coverage (1). A good test requires testing of all aspects of the circuit for as many defects as are reasonably possible. The creation of the test is very much dependent on the type of defect model that is assumed for the device. For example, the stuck fault model may be used to developed test patterns. Even if the test engineer created a test that covered 100% of all stuck faults, defective CMOS devices may pass the test because the actual defects in the technology tend to show delay or bridging faults. Test patterns can be created in several ways. First, perhaps most intuitive source of test patterns come from func-

X2 x1 x2 Xn

xn

f

f

F Output

Inputs Figure 13. A self-checking circuit. Self-checking circuits are composed of complementary circuits of which only one malfunctions when a defect is present.

A=1 B=1 C=0 D=X E=0 F=X

G1 G2 G3

G H

SA-1 G4

J

I

Figure 14. Detection of fault in combinational circuit. The input ABCDEF ⫽ 110X0X detects the G stuck-at 1 fault.

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tional tests of the system under consideration. The second source of test patterns comes from a concerted attempt to exhaustively test for every defect in the circuit. The third approach is to create a random set of test patterns. Designs are often supported with DFT methodologies such as scan registers to decompose the system into sequential and combinational parts that can be tested largely independent of one another. The sequential part is often configured as a shift register which is straightforward to test. As a result, much effort has been expended on developing test patterns for combinational circuits. Several test generation approaches are immediately discussed. Functional Test A functional test can be used to determine whether the circuit meets computational and functional requirements. In addition, by exploiting known circuit structures with known testability characteristics. A designer will construct these tests in the process of debugging the design so that the functional characteristics of the system can be demonstrated. In theory, functional tests can be constructed to achieve very nearly 100% fault coverage; however, the number of tests may be prohibitive. For example, a functional test of a multiplication circuit might include tests computing several products. Functional tests can be used alone or in conjunction with defect tests to achieve the desired fault coverage. In the event DFT circuitry is incorporated, functional tests verify that the circuit function is achieved by operation in its normal mode by deactivating test circuitry. Defect Tests In defect testing, it is taken for granted that the system design meets functional requirements. In general, the goal of defect testing is to test and verify that all circuit structures and components are operating defect free and within manufactured tolerances. As a result, the actual test patterns presented to the system may bear no resemblance to circuit inputs that would ordinarily be encountered in the field. Defect tests can be constructed in an ad hoc fashion, provided the appropriate tools are available, such as an accurate fault simulator. Constructing effective tests can be eased with the introduction of DFT methods that improve the controllability and observability of internal circuit structures. For example, the introduction of test points and scan registers can aid the designer in efficiently achieving acceptable defect tests. In addition, algorithms exist for automatically determining a set of defect tests that under certain conditions and assumptions, can achieve 100% fault coverage. One such algorithm is the D-algorithm (20,21). The D-algorithm can be used to determine test vectors for combinational logic and achieves 100% fault coverage for such circuits, provided the circuits do not contain any redundancy, as what might be present for eliminating hazards or to achieve fault tolerance. The D-algorithm can be effectively applied to circuits that include a test configuration where all flip-flops are clocked by the same clock signal, test circuitry is present that reconfigures the circuit so that all flip-flops are a part of a long shift register, and a mechanism for shifting values into and out of the shift register are present. The test patterns can be used for BIST ap-

plications provided the patterns can be efficiently stored or recreated by test circuitry. Lastly, pseudorandom tests can be constructed by randomly creating test patterns that are applied to the circuit. The fault coverage is a function of the circuit and the number of different test patterns that are applied. Furthermore, the coverage asymptotically approaches 100% as the number of different test patterns that have been applied increases. The benefit of pseudorandom tests is that the tests can be easily created with simple circuit, desirable for BIST applications. Exhaustive Testing Exhaustive testing is the testing under all possible operating conditions for all faults. Because each possible operating condition is targeted all faults are guaranteed to be detected, provided they can be detected by any test. The problem with exhaustive testing is that the number of tests required to achieve exhaustive testing is in most cases intractably large. For example, an irredundant combinational circuit with four inputs may be exhaustively tested for all stuck faults with 16 test patterns, one for each input combination. A circuit of 64 inputs would require 264 ⫽ 1.8 ⫻ 1019 tests to be similarly tested. Given a tester that could present 109 patterns per second, the test would require over 500 years. Further complicating the process of exhaustive testing is the presence of sequential circuits and also several failure modes that require two or more consecutive patterns to test for individual faults. Pseudoexhaustive Testing In pseudoexhaustive testing, the circuit is partitioned into component blocks that can be tested exhaustively. This approach achieves some benefits of exhaustive testing in that all faults of the desired class are tested while reducing the scope of the test to a subcircuit of a more manageable size. In addition, counters (22) and LFSR circuits (17) are capable of generating exhaustive input patterns for some fault models. The circuit can be partitioned based on several criteria. One criteria for partitioning is to examine the dependence of outputs on the inputs. If an output is dependent on fewer than the total number of inputs, then select these inputs as input to the pseudorandom test (2). The D-Algorithm The D-Algorithm (20,21) is a test pattern generation algorithm that can be used to determine the set of test patterns to detect all detectable stuck faults in combinational circuits. While the types of circuits that are used in digital systems are not combinational, these circuits can be decomposed into combinational parts using scan design methodologies. The ‘‘D’’ in the D-Algorithm represents a discrepancy between the fault free and faulty circuit, where D is used both to represent the fault for which a test pattern is desired as well as the propagation of the discrepancy to the output of the circuit for detection of the fault. In the circuits, D and D will be used as logic values with the familiar 1 and 0 logic values. In the context of fault detection, D represents a discrepancy where the circuit node should be 1 yet is 0 due to the presence of a fault. In a complementary fashion, D represents a discrepancy where the circuit node should be 0 yet is 1 due to the presence of a fault. The theme of the algorithm is to assign D and D to

AUTOMATIC TESTING

circuit nodes to represent faults. Next, the discrepancy is propagated to the outputs by sensitizing gates to enable propagation of the discrepancy along all paths until the discrepancy appears at the circuit output(s). This process is termed the D-drive. Next, inputs of the remaining gates are set to support the propagation of the discrepancy to the circuit outputs which is termed the consistency operation. Backtracking in the consistency operation occurs whenever a node is required to be both 1 and 0. Among the significant features of the D-Algorithm is the ability to find a stuck fault test if one exists. In addition, the D-Algorithm can be extended to test for delay faults and nonfeedback bridging faults (21). Pseudorandom Test Pattern Generation While the D-Algorithm can be used to determine the test patterns for a particular circuit, as a result of searching, the D-Algorithm can be computationally expensive. A computationally less expensive yet but undirected approach uses test patterns generated in a pseudorandom fashion (17). The basic idea behind Parallel Random Pattern Generator (PRPG) is the assumption that many approximately equally desirable tests exist for a circuit. By randomly sampling the individual tests, probabilistically speaking, an acceptable test set can be found. LFSRs are simple circuits that can be used to generate pseudorandom test patterns. Weighted Test Patterns Test patterns constructed using PRPGs result in patterns where each bit has an equal chance of being either 1 or 0. For some circuits, this uniformity in the test patterns may not result in an effective set of tests. In particular, certain types of patterns are more productive in terms of the quantity of faults that can be detected. Adders and counters, for example, are effectively tested when patterns result in either carries generated or when carries could be generated if faults are present. One of the first applications of weighted test patterns assumed that the circuit had no DFT circuitry and that the tester changed one input at time. After presenting random set of test patterns, it was observed that some input changes resulted in a larger number of devices in the circuit changing. By changing the statistics of the inputs and making the inputs change in a pseudorandom frequency dictated by their importance, measured by internal gate signal changes, the benefits of weighted test patterns were demonstrated (23). Multiple Pattern Methods Under certain circumstances, a single pattern applied to a circuit is insufficient to test for some types of faults or to achieve certain testing goals. Multiple test patterns are necessary when it is desired to locate the pattern. Since one test pattern will detect the presence of several faults, additional tests are required to rule out other defects. In addition, delay faults require two test patterns to detect delay faults. The first pattern sets up the conditions and the second pattern makes the presence of the fault visible. The D-Algorithm can be easily enhanced to test for delay faults (21). In CMOS circuits, transistor faults can result in a combinational circuit operating as a sequential circuit. To detect this fault, the first pattern stores a value and the second pattern propagates the discrepancy to the output of the circuit (24).

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Test Pattern Generation for PLAs As indicated earlier, PLAs are susceptible to crosspoint faults where the function programmed into the PLA is changed by the addition or omission of a term in the AND array or OR array. These faults do not fit the standard stuck fault model, so a different strategy to test for crosspoint faults must be adopted. CAD TOOLS Support of automatic testing in the CAD tool is as important as understanding the test techniques given the high density and complexity of today’s digital systems. The inclusion of test support in the CAD tool facilitates integrating good test practices into the design process. Tool builders have recognized the importance of including testing approaches. Two leading companies in this respect are LogicVision, Inc. and Mentor Graphics. Furthermore, the development of hardware description languages that has resulted the widely used Verilog and VHDL greatly simplifies the process of adding automatic testing capabilities. VHDL is the VHSIC Hardware Description Language where VHSIC is very high speed integrated circuits (32). Reference 30 gives a good summary of CAD approaches. Fault Simulation Fault simulation is a simulation capable of determining whether a set of tests can detect the presence of faults within the circuit. A fault simulator is a logic simulator with the capability of keeping track of whether one or more faults can be detected given the inputs to the circuit. In practice, a fault simulator simultaneously simulates the fault-free circuit concurrently with circuits having faults. In the event that faults produce circuit responses that differ from the fault-free cases, the fault simulator records the fault that was detected. In order to validate a testing approach, fault simulation is employed to determine the efficacy of the test. Fault simulation can be used to validate the success of a test regimen and give a measure fault coverage achieved in the test. In addition, test engineers can use fault simulation for developing functional test patterns. By examining the faults covered, the test engineer can identify circuit structures that have not received adequate coverage and target these structures for more intensive tests. In order to assess different fault models, the fault simulator must be able to both model the effect of the faults and also to report the faults that were detected by a particular input sequence. In the test for bridging faults detectable by IDDQ testing, traditional logic and fault simulators are incapable of detecting such faults because these faults may not produce a fault value that can differentiate faulty from fault-free instances. In Ref. 31, a fault simulator capable of detecting IDDQ faults is described. Test Structure Libraries By incorporating DFT structures and techniques in libraries, the designer is given the ability to easily include accepted testing practices. Some testing practices can be incorporated in a fashion that is to some extent transparent to the design engineer. In doing so, DFT techniques can become a more in-

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tegral part of the design process. For example, scan design approaches can be incorporated in a design provided all flipflops operate off the same clock. Connecting flip-flops in a scan path architecture can be an option with specific details of the test structure being hidden from the designer unless it is immediately relevant to the design. Languages such as VHDL can offer DFT capabilities with the addition of libraries (32). MIXED-SIGNAL TESTING Analog systems have increased in complexity along with digital systems. With increased system complexity comes with it the necessity to perform defect and parameter testing. Furthermore, since both analog and digital circuitry require essentially the same manufacturing process, a common practice is to include both analog and digital circuitry in the same chip. With the increasing complexity of analog circuits and with the introduction of digital circuitry, testing becomes a more important issue. Analog circuitry presents special problems in testing because analog signals are continuous, making it impossible to develop a test for all possible cases. Second, complex digital circuitry can be included in a circuit that contains analog circuitry for which testing is desired. At the interface, the digital signals serve as actuators to the analog functionality. In general, however, ABIST (Analog Built-In Self Test) shares many of the same features and challenges of digital BIST. First, for nonconcurrent testing, the CUT must be switched to a special test mode where inputs are generated and output responses are compared with accepted norms for behavior. At the system level, ABIST is not unlike digital BIST. The CUT requires an input stimulus and the outputs must be monitored and compared against a measure indicative of the CUT fault status. Signal Generation Among the challenges of developing ABIST architectures is having the capability of injecting a test signal into the CUT (33). Digital systems are straightforward from the point of view that in principal, any pattern can be generated for input. Analog signals can take on an infinity of values and combinations. Indeed, it is impossible to test an analog device for all possible operating conditions and levels. With the selection of appropriate signals, a fairly complete test is possible. Ideally, having the signal generation capabilities of a signal generator from the lab bench along with the capability of programming the signal generator gives the ideal combination of capabilities for testing analog devices. Integrating these capabilities on analog chips, however, can be impractical due to the difficulty of creating a signal generator with sufficient capabilities to test the CUT. The simplest form of signal generator simply generates a sine wave with either fixed or variable frequencies. Such a signal generator is termed a single-tone signal generator. The frequency response of an analog device can be obtained with a programmable single-tone signal generator that scans the desired range of signals in order to obtain a frequency response. This approach can be ineffective at generating tests of nonlinear properties. For example, a two-tone signal generator can be used to test for nonlinearities by determining the magnitude of frequencies that result from mixing the original two tones.

Mixed Testing In some analog applications, both analog and digital circuits are present. For example, an A/D converter requires analog circuits to sample the analog input compare the analog signal levels to internal references. Digital circuits are then used to take the results of these comparisons and output a binary integer representative of the analog voltage level. For a complete test, both the analog and digital circuits must be tested, as well as the interfaces between the two. Parts of digital circuits can be tested using the techniques of purely digital circuits. In Ref. 34, a BIST approach was developed that incorporated digital DSP hardware to perform frequency response and other parameters of an analog to digital converter. AUTOMATIC TEST EXAMPLES Two examples of microprocessors that employ automatic testing methodologies are presented in this section. It is interesting to note the range of techniques that are employed even in the same design. Microprocessor CPUs present special challenges for automatic testing as a result of their enormous complexity, state of the art implementation methodologies, and the complications of mass production. Indeed, because microprocessors are manufactured in volume, the economics of employing testing methodologies are carefully weighed against the benefits. In today’s modern microprocessors, subsystem structures of every type, each with its own testing challenges, coexist and must be tested. The techniques employ a combination of both built-in test and the application of ATE. Failure Analysis in Intel Pentium and Pentium Pro Processors Intel incorporated several DFT approaches that enable device test and manufacturing failure analysis (35). Failure analysis is necessary to determine the cause of device failure. In a manufacturing setting, specific patterns of failures may be indicative of problems with the process. Thus, the identification of the specific failure mode is essential for adjusting the manufacturing process to reduce the incidence of a specific type of failure. Approaches such as e-beam probing can identify failures, but Intel engineers recognized that current manufacturing technologies reduced the effectiveness of e-beam probing for several reaons. First, the component geometries were becoming too small to be resolved. Second, layers of metalization impedes observation of signals at the first and second layers of metalizations. Third, flip-chip packaging complicates e-beam probing. Several DFT techniques were employed in the Intel Pentium processor in order to facilitate testing off the manufacturing line. The Intel Pentium has microcode that can be patched with externally loaded microinstructions, accomplished by down-loading the new microinstructions into a special memory. Special control logic transfers control to the microinstruction patches at desired points in the microprogram. The microinstructions are coded to aid in localizing the source of defects and can be used in conjunction with external probing methodologies. Another Pentium DFT capability allows external dumping of the contents of memory arrays, enhancing the observability of memories and control logic. Complementing these DFT techniques is a scan-out mechanism en-

AUTOMATIC TESTING

abling the sampling of internal control and datapath signals. The cache memories also support a direct access test mode whereby the memories are accessed as a pipelined memory. A more detailed test mode, the low yield analysis mode, enables extraction of dc parameters for individual memory cells that are useful in failure analysis. Dec Alpha Processor Several testing methodologies were employed in the Dec Alpha Processor to achieve several goals (36). First, the Alpha was designed to achieve extremely high performance, and thus the testing methodologies had to be incorporated in such a way to not significantly affect performance. Second, testability methodoligies were employed to ease the burden on chip tester technology. Third, the testability methodologies were designed to work in conjunction with repair methodologies of chip memories. On the Alpha, it was decided not use full scan path methodologies as a result of the size of the processor and because some of the logic was implemented using dynamic logic. It was further recognized that the instruction cache could be used to store programs valuable in the testing process. Upon initial wafer probe, the Alpha instruction cache was designed to undergo a built-in self-repair operation prior to being loaded with a special test program. The purpose of the test program is to determine failed bits in the cache memories and report failures for their subsequent masking through laser repair. In addition, the Alpha has a manufacturing test port that supports limited internal scan path capabilities the form of 27 linear feedback shift registers. A mostly IEEE 1149.1 compatible TAP enables boundary scan test capabilities.

133

tual property, supplying enough information to effectively test the cores would require the disclosure of the design. It is impossible to be able to construct an effective test regimen without some knowledge of the internal structure of the core. Along with the core, the core vendors will supply test vectors that test the core to achieve a given level of defect coverage. The difficulty is that this requires the test patterns be applied directly to the inputs and outputs of the core, which can be embedded deep within the design (14). Synthesis for DFT In many ways, effective application of testing methodologies requires attention at every stage of the design process (29). While the focus of testing is on the individual components and gates in the circuit, initially, the designer will rarely work in this domain, given the complexity of most designs produced today. More typically the designer will design at the behavioral level. Synthesis for DFT can facilitate the design of a testable circuit in several ways. First, in synthesis, test structures can transparently be compiled into the design making it more testable. Second, by adding datapaths that improve controllability and observability, the testability of the design can be improved. In Ref. 29, resource scheduling is used to enhance testability. Four rules were introduced to improve testability which can be applied to the design at the behavioral level. Rule 1: Whenever possible, allocate a register to at least one primary input or primary output. Rule 1 improves the controllability and observability of the design.

EMERGING TECHNOLOGIES IDDQ Test Patterns In IDDQ testing, the current profiles for CMOS circuits are used to test for defects in the circuits (7). CMOS circuits are particularly susceptible to bridging faults that are not always testable when developing tests according to the stuck fault model. IDDQ testing is generally considered to be an augmentation to other testing approaches and has been shown to improve fault coverage. In IDDQ testing, as test patterns are presented to the circuit, the quiescent current is monitored. If the current exceeds some threshold, defects are presumed to be present. Test patterns for IDDQ testing can be the same patterns used to perform fault testing according to other models, augmented with current profiles for the different patterns in the test set. Because CMOS circuits can draw different quiescent currents depending on the internal function of the circuit, adopting a threshold for each test will give a more accurate test. In addition, test patterns can be created specifically for IDDQ testing. Challenges of Core-Based Design In core-based designs, VLSI systems are constructed using complex components from libraries (37). Using simple to moderate complexity parts from a library has been a part of the industry for some time. The difference is that today, library components are of the complexity of entire systems from the past, such as CPUs and memories. Since the cores are supplied by third parties who consider their cores to be intellec-

Rule 2: Reduce the sequential depth from an input register to an output register. In Rule 2, the paths through which data is processed are designed so that the data is stored in no intermediate registers. In doing so, improved controllability and observability of a design results. Rule 3: Reduce sequential loops by —proper resource sharing to avoid creating sequential loops for acyclic data flow graphs, and —assign IO registers to break sequential loops in cyclic data flow graphs. Sequential data path loops reduce the testability of the circuit. By avoiding the creation of sequential loops and breaking sequential loops that are unavoidable, testability is improved. Rule 4: Schedule operations to support the application of Rules 1 to 3. In Ref. 29, application of Rules 1 to 4 are shown to significantly improve the testability of circuits compared to cases that do not employ these rules. Interestingly, this approach does not require test circuitry traditionally used to improve testability, such as the application of scan design approaches.

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SUMMARY

10. W. C. Carter et al., Design of serviceability features for the IBM system/360, IBM J. Res. Develop., 115–126, July 1964.

In this article, many aspects of automatic test were investigated. Automatic testing can be conducted by either external test equipment or can be incorporated in the circuitry of the system. Important issues in developing and using automatic test include knowledge of the types of failures that can be expected in the application technology. The types of failures can have a great impact on both the methodology for generating tests and also on the design of the systems. With the complexity of today’s VLSI circuits, many circuits are incorporating DFT and BIST approaches to ease testing burdens.

11. S. Funatsu, N. Wakatsuki, and T. Arima, Test generation systems in Japan, Proc. 12th Des. Automation Conf., 1975, pp. 114–122.

APPENDIX 1. ACRONYMS AND ABBREVIATIONS ABIST ATE BILBO BIST CUT DFT DSP LFSR LSSD MISR PCB PLA PRPG SCC SISR TAP

Analog Built-in Self-test Automatic Test Equipment Built-in Logic Block Observer Built-in Self-test Circuit Under Test Design for Test Digital Signal Processing Linear Feedback Shift Register Level Sensitive Scan Design Multiple Input Shift Register Printed Circuit Board Programmable Logic Array Parallel Random Pattern Generator Self-Checking Circuits Single Input Shift Register Test Access Port

BIBLIOGRAPHY 1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE rev. ed., Piscataway, NJ: IEEE Press, 1990. 2. P. K. Lala, Digital Circuit Testing and Testability, San Diego, CA: Academic Press, 1997. 3. J. M. Miranda, A BIST and boundary-scan economics framework, IEEE Des. Test Comput., 14 (3): 17–23, July–Sept 1997. 4. B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Reading, MA: Addison-Wesley, 1989. 5. M. Sivaraman and A. J. Strojwas, A Unified Approach for Timing Verification and Delay Fault Testing, Boston: Kluwer, 1998. 5a. N. K. Jha and S. Kindu, Testing and Reliable Design of CMOS Circuits, Boston: Kluwer, 1992. 6. J. Gailay, Y. Crouzet, and M. Vergniault, Physical versus logical fault models in MOS LSI circuits: Impact on their testability, IEEE Trans. Comput., 29: 1286–1293, 1980. 7. C. F. Hawkins et al., Quiescent power supply current measurement for CMOS IC defect detection, IEEE Trans. Ind. Electron., 36: 211–218, 1989. 8. R. Dekker, F. Beenker, and L. Thijssen, A realistic fault model and test algorithms for static random access memories, IEEE Trans. Comput.-Aided Des., 9: 567–572, 1996. 8a. K. M. Butler and M. R. Mercer, Assessing Fault Model and Test Quality, Boston: Kluwer, 1992. 8b. K. Brindley, Automatic Test Equipment, Oxford: Newnes, 1991. 9. J. Rajski and J. Tyszer, The analysis of digital integrators for test response compaction, IEEE Trans. Circuits Syst. II, Analog Digit., 39: 293–301, 1992.

12. E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, Proc. 14th Des. Automation Conf., New Orleans, LA, 1977, pp. 462–468. 13. A. S. M. Hassan et al., BIST of PCB interconnects using boundary-scan architecture, IEEE Trans. Comput., 41: 1278–1288, Oct 1992. 14. N. A. Touba and B. Pouya, Using partial isolation rings to test core-based designs, IEEE Des. Test Comput., 14 (4): 52–59, Oct– Dec 1997. 15. Y. Zorian, A structured testability approach for multi-chip modules based on BIST and boundary-scan, IEEE Trans. Compon. Packag. Manuf. Technol. B, Adv. Packag., 17: 283–290, 1994. 16. IEEE, IEEE Standard Test Access Port and Boundary-Scan Architecture, Piscataway, NJ: IEEE Press, 1990. 17. P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: Wiley, 1987. 18. S. Feng et al., On the maximum value of aliasing probabilities for single input signature registers, IEEE Trans. Comput., 44: 1265–1274, 1995. 19. M. Lempel and S. K. Gupta, Zero aliasing for modeled faults, IEEE Trans. Comput., 44: 1265–1274, 1995. 20. J. Paul Roth, Diagnosis of automata failures: A calculus and a method, IBM J. Res. Develop., 277–291, 1966. 21. J. Paul Roth, Computer Logic, Testing, and Verification, Potomac, MD: Computer Science, 1980. 22. D. Kagaris, S. Tragoudas, and A. Majumdar, On the use of counters for reproducing deterministic test sets, IEEE Trans. Comput., 45: 1405–1419, 1996. 23. H. D. Schnurmann, E. Lindbloom, and R. G. Carpenter, The weighted random test-pattern generator, IEEE Trans. Comput., C-24: 695–700, 1973. 24. BIST Test Pattern Generators for Two-Pattern Testing Theory and Design Algorithms, C. Chan and S. K. Gupta, IEEE Trans. Comput., 45: 257–269, 1996. 25. A. Ivanov, B. K. Tsuji, and Y. Zorian, Programmable BIST space compactors, IEEE Trans. Comput., 45: 1393–1404, 1996. 26. D. Green, Modern Logic Design, Reading, MA: Addison-Wesley, 1986. 27. M. Franklin, K. K. Saluja, and K. Kinoshita, A built-in self-test algorithm for row/column pattern sensitive faults in RAMs, IEEE J. Solid-State Circuits, 25: 514–524, 1990. 28. B. Koenemann, B. J. Mucha, and G. Zwiehoff, Built-in test for complex digital integrated circuits, IEEE J. Solid State Circuits, SC-15: 315–318, 1980. 29. M. Tien-Chien Lee, High-Level Tests Synthesis of Digital VLSI Circuits, Boston: Artech House, 1997. 30. M. Go¨ssel and S. Graf, Error Detection Circuits, New York: McGraw-Hill, 1993. 31. S. Chakravarty and P. J. Thadikaran, Simulation and generation of IDDQ tests for bridging faults in combinational circuits, IEEE Trans. Comput., 45: 1131–1140, 1996. 32. C. H. Roth, Jr., Digital Systems Design Using VHDL, Boston: PWS Publishing Company, 1998. 33. G. W. Roberts and A. K. Lu, Analog Signal Generation for BuiltIn-Self-Test of Mixed-Signal Integated Circuits, Norwell, MA: Kluwer, 1995. 34. M. F. Toner and G. W. Roberts, A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a

AUTOMATIC TEST SOFTWARE sigma-delta ADC, IEEE Trans. Circuits Syst. II, Analog Digit., 43: 608–613, 1992. 35. Y. E. Hong et al., An overview of advanced failure analysis techniques for Pentium and Pentium Pro microprocessors, Intel Technology J., 2, 1998. 36. D. K. Bhavsar and J. H. Edmondson, Alpha 21164 testability strategy, IEEE Des. Test Comput., 14 (1): 25–33, 1997. 37. R. K. Gupta and Y. Zorian, Introducing core based system design, IEEE Des. Test Comput., 14 (4): 15–25, Oct–Dec 1997.

LEE A. BELFORE, II Old Dominion University

AUTOMATIC TESTING FOR INSTRUMENTATION AND MEASUREMENT. See AUTOMATIC TEST EQUIPMENT.

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Wiley Encyclopedia of Electrical and Electronics Engineering Cad for Field Programmable Gate Arrays Standard Article Kai Zhu1 and D. F. Wong2 1Actel Corporation, Sunnyvale, CA, 2University of Texas at Austin, Austin, TX, Copyright © 1999 by John Wiley & Sons, Inc. All rights reserved. : 10.1002/047134608X.W1809 Article Online Posting Date: December 27, 1999 Abstract | Full Text: HTML PDF (118K)

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Abstract The sections in this article are Technology Mapping Partitioning Placement Routing Commercial CAD Software Future Trends in FPGA CAD Research and Development | | | Copyright © 1999-2008 All Rights Reserved.

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CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

Logic module row

Segmented channel

707

IO module

Figure 1. Row-based architecture consists of rows of logic modules separated by horizontal routing channels. The routing tracks in horizontal routing channels are segmented. Vertical routing resources are relatively limited compared with horizontal routing resources. IO modules are at the boundary.

CAD FOR FIELD PROGRAMMABLE GATE ARRAYS Field-programmable gate arrays (FPGA) are one of the most popular electronic devices that circuit designers use. Because of the high complexity of circuit designs, software tools have become indispensable to the circuit designer in implementing circuits on FPGAs. This article discusses the internal mechanism of computer-aided design (CAD) software tools used by circuit designers to implement circuits on FPGAs. FPGAs were first introduced into the market in the mid1980s to combine the field programmability of programmable logic devices and the high density of gate arrays. Compared to the traditional application-specific integrated circuit (ASIC) technology, FPGAs have the advantage of rapid customization with negligible nonrecurring engineering cost. The advantage of rapid turnaround with relatively low cost has led to increasing usage of FPGAs for a wide variety of applications, including rapid system prototyping, small volume production, logic emulation, and special-purpose reconfigurable computing.

Conceptually, an FPGA device can be visualized as composed of three types of basic components embedded in a twodimensional grid: logic modules, routing resources, and IO modules. A logic module can be customized to realize various logic functions for different circuit designs. IO modules are located around the periphery of an FPGA device. Routing resources consist of routing segments in both vertical and horizontal directions. Usually, adjacent routing segments in the same direction are grouped together to form routing channels. Interconnections between logic modules are realized by routing nets through the routing channels. Row-based and symmetrical array architectures are two popular architectures used in commercial FPGA products. In row-based architecture (see Fig. 1), logic modules are grouped into rows separated by horizontal channels. Compared to the horizontal routing resources, vertical routing segments are much more limited. In symmetrical array architecture (see Fig. 2), routing channels are distributed evenly in both horizontal and vertical directions. Logic modules are surrounded by the adjacent routing channels. Customization of logic modules and routing segments for implementing a particular circuit design is realized by programming a selected set of switches. A switch can be programmed into either a conductive state (on) or an insulative state (off). Physically, a switch can be implemented using an anti-fuse, or a pass transistor controlled by a static randomaccess memory (SRAM) cell, or other technologies. An FPGA device is reprogrammable if the device can be programmed multiple times. SRAM-based FPGAs are an example of reprogrammable FPGAs. Conversely, an FPGA device is one-time programmable if the device can be programmed only once. Anti-fuse-based FPGAs are one-time programmable. More description on architectural and physical details of FPGAs can be found in several references (1–3) (see PROGRAMMABLE LOGIC ARRAYS). The density of a state-of-the-art FPGA device is over 100K gates and continues to increase rapidly. It is practically not feasible to design circuits on FPGAs without using sophisticated CAD software tools. While there are FPGAs of different

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

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CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

Routing channel

Logic module

IO module

Figure 2. Symmetrical-array architecture consists of islands of logic modules surrounded by routing channels in both vertical and horizontal directions. Because of silicon area limitation, the intersecting vertical and horizontal channels in general are not fully connected.

architectures in both industry and academic research, the flows of the CAD software tool for any FPGA designs are similar and consist of several basic steps, as illustrated in Figure 3: • Design Entry. Specify a circuit design by using schematic capture or hardware design languages (such as VHDL, Verilog).

Design entry

Logic optimization Logic synthesis Technology mapping

Partitioning

Placement

Physical design

Routing

Delay extraction

Device programming Figure 3. A typical CAD flow for FPGAs goes through the following steps: design entry, logic synthesis, physical design, delay extraction, and device programming. Logic synthesis and physical design steps each can be divided into several substeps, as outlined by the dashed lines.

• Logic Optimization. Transform the circuit network into another equivalent circuit network which is more suitable for the subsequent technology mapping step. • Technology Mapping. Transform the technology-independent circuit network into a network of library cells of the target FPGA architecture so that the transformed network is functionally equivalent to the original circuit network. • Partitioning. Partition the network of library cells into several subcircuits so that each subcircuit can be fit into a given set of resources of FPGAs. • Placement. Assign cells of the circuit network to logic and IO modules on an FPGA device. • Routing. Assign nets of the circuit design to the routing segments on an FPGA device. Select the set of switches that need to be programmed into the on state. • Delay Extraction. Compute the routing delay with the physical routing information. Routing delay data will be used for post-layout circuit timing calculation and analysis. • Device Programming. Program the selected switches into on state. In the literature, logic optimization and technology mapping steps are also called logic synthesis and the software types for performing these steps are normally called front-end tools. On the other hand, the tasks of partitioning, placement, and routing are called physical design and programs for solving these problems are called back-end tools. This flow for FPGA designs is very similar to that used in traditional ASIC technologies. However, the algorithms used for solving the problems encountered in the FPGA design flow can be very different from the algorithms used in ASIC technologies. Very often, it is necessary to develop FPGA-specific algorithms in order to obtain effective as well as efficient solutions. The reason for having FPGA-specific algorithms is mainly because the resources in FPGAs are fixed and limited, and the architectural details of logic modules and routing resources vary significantly in different FPGA products. Strictly limited and fixed resources in FPGA devices post many constraints on feasible solutions. In comparison with the CAD problems in ASIC designs, the CAD problems in FPGA designs are generally more constraint driven than optimization driven. Finding a feasible solution for an FPGA CAD problem is usually more difficult than finding a feasible solution for an ASIC CAD problem. Practically, it is often acceptable to use as many logic modules and IO pins as available in an FPGA device as long as the utilization is under the resource limits and the solution is routable. Currently, FPGA architectures are still in constant evolution. There is not yet a universal architecture that is used for different FPGA products. FPGA CAD algorithms, especially physical design algorithms, strongly depend on the architectural details. It is generally necessary to develop architecturespecific algorithms for solving CAD problems in various stages of FPGA design flow in order to fully take advantage of architectural features in different FPGA products. In addition to these algorithmic differences, the primary advantage of quick turnaround of FPGAs dictates that CAD tools for FPGAs must run much faster than the CAD tools for

CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

ASIC. Thus, more restrictions are imposed on the efficiency of critical algorithms for solving FPGA CAD problems. This article will focus on the discussion of major FPGAspecific CAD problems in technology mapping, partitioning, placement, and routing. To keep the article concise, algorithmic details for solving the FPGA-specific CAD problems are omitted. In most cases, only the basic ideas of the algorithms are described and the references to the literatures that contain detailed descriptions are given. General background information on logic synthesis and physical layout can be found in the literature (see CAD FOR MANUFACTURABILITY OF INTEGRATED CIRCUITS).

709

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TECHNOLOGY MAPPING Details of technology mapping algorithms vary for different architectures. The basic strategy of most FPGA technology mapping algorithms, however, consists of two basic steps: decomposition and covering. In the decomposition step, logic gates in the original circuit networks are decomposed into a different set of logic gates so that the transformed network is more suitable for achieving the optimization objectives such as area or timing. In the subsequent covering step, logic gates in the circuit are covered by cells in the library of the target FPGA device where each cell can be implemented by using a logic module. The differences in FPGA technology mapping from the conventional approach result from the fact that the number of distinct logic functions that can be implemented with a logic module in most FPGAs is much larger than the typical library size for conventional ASIC technologies. It is therefore not practical to follow the conventional approach of enumerating all possible functions to determine the optimal selection of library cells. Logic modules in FPGAs can be broadly classified into two categories: lookup table (LUT) based and nonLUT based. Techniques used in technology mapping, especially in the covering step, are different for these two types of logic modules (4). LUT-Based Logic Modules A K-input LUT-based logic module can implement a total of K 22 distinct logic functions each with no more than K inputs. Examples of commercial FPGAs that use LUTs for logic modules include Actel’s ES6500, Altera’s Flex, Lucent’s ORCA, and Xilinx’s XC4000 product families. For values of K greater than 3, the size of the library for the library-based covering approach becomes impractically large. Many specialized algorithms have been developed to address the LUT-based FPGA technology mapping problem (5). An important optimization objective for LUT-based technology mapping is to minimize the area, that is, the number of LUTs used for covering a circuit network. One fast and effective approach for LUT area minimization is to formulate the decomposition and covering problems as the bin-packing problem (6). The bin-packing problem is to pack a set of objects of given sizes into the minimum number of bins of fixed capacity. The bin packing problem is NP-hard, but simple, fast, and effective heuristic algorithms for solving the problem exist. The technology mapping results generated by using this approach are significantly better than the conventional approach in terms of both run time and area.

a 0 b

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Figure 4. A multiplexor-based logic module in (a) can be represented by a binary-decision diagram (BDD) shown in (b). The BDD for a subcircuit represented by a BDD in (c) is isomorphic to a subgraph of logic module BDD in (b), as indicated by the shaded nodes.

Another important optimization objective is circuit performance. During logic synthesis steps, a commonly used performance metric is the maximum circuit level, i.e., the maximum number of cells on any path from a primary input to a primary output in a combinational circuit. It has been shown that the problem of minimizing the maximum circuit level for combinational circuits in the covering step can be solved optimally using the network flow technique (7). Furthermore, algorithms have been developed to achieve often a practically desirable balance between area and performance (5). Non-LUT-Based Logic Modules A K-input non-LUT-based logic module cannot implement every logic function with no more than K inputs. An example of a non-LUT-based logic module is the multiplexer-based logic module used in Actel’s ACT FPGA families (see Fig. 4). In the covering step for non-LUT-based FPGAs, an important operation is to determine whether a cover of the logic gate can be implemented by personalizing a non-LUT logic module. This problem is also known as the Boolean matching problem (8). For the logic module shown in Figure 4, the number of distinct logic functions implementable by a logic mod-

710

CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

ule is more than 700, and thus makes it impractical to apply a conventional library enumeration approach. A specialized technique for non-LUT-based logic module Boolean matching is based on a reduced ordered binary decision diagram (BDD) technique (9). Given a subcircuit logic function F and a logic module function G, BDDs for F and G, denoted as BDDF and BDDG, respectively, are constructed. Boolean matching of F on G is performed by detecting whether BDDF is isomorphic to any subgraph of BDDG. Figure 4 illustrates BDDs for a logic function F ⫽ xy ⫹ xz and the logic module shown in Fig. 4, G ⫽ (a ⫹ b)(cd ⫹ ce) ⫹ (a ⫹ b)(fg ⫹ fh). Function F can be implemented by G because BDDF is isomorphic to a subgraph of BDDG as induced by the shaded nodes in BDDG. Technology mapping and fast Boolean matching algorithms using the BDD isomorphism approach have been developed for multiplexer-based logic modules (10,11).

PARTITIONING In the partitioning step, a circuit is partitioned into a collection of subcircuits. Depending on the number of FPGA devices involved, FPGA partitioning could be either multiple-FPGA partitioning or single-FPGA partitioning. In multiple-FPGA partitioning, a circuit is partitioned between multiple FPGA devices so that each subcircuit can fit into a single FPGA device. An example where multipleFPGA partitioning is necessary is a logic emulation system. A logic emulation system verifies the functionality of a circuit design by implementing the circuit design on FPGAs running at a slower clock speed. Typically, a system-level design is too large for a single FPGA device and therefore must be implemented using multiple FPGAs. Single-FPGA partitioning partitions a circuit within a single FPGA device and is most commonly used for hierarchical architecture FPGAs. In a hierarchical architecture FPGA device, routing resources between logic modules are not uniformly distributed. Instead, logic modules are grouped into clusters where each cluster contains a number of logic modules. Routing resources between clusters are normally much limited compared to the routing resources within a single cluster. Hierarchical architecture has the advantage of smaller device die size than a flat architecture for the same device density, and therefore is most popular for supporting high-density FPGA devices. In the physical design flow for a hierarchical architecture FPGA, a circuit is usually first partitioned into subcircuits so that each subcircuit can fit into a single cluster. Then, subcircuits are placed and routed within individual clusters. Similar to the conventional partitioning problems, the most basic objective of FPGA partitioning is interconnection minimization between subcircuits. However, compared to the conventional partitioning problems, FPGA partitioning needs to satisfy more constraints in order to obtain a feasible partitioning solution. Finding a feasible partitioning solution is more difficult and important than in conventional partitioning problems. This is because the resources in an FPGA device, especially logic modules and IO ports (or the routing resources between clusters within a single FPGA device), are strictly limited. Consequently, FPGA partitioning problems are more resource-constraint driven than conventional partitioning problems.

Two most essential constraints for both multiple-FPGA and single-FPGA partitioning are IO constraint and capacity constraint. Capacity constraints for an FPGA device can be very complex. Driven by the demand of supporting systemlevel circuit designs, the FPGA device is becoming larger in terms of density as well as more heterogenous in terms of the types of resources. It is not uncommon to find a commercial FPGA device that contains different logic modules, complex IO modules, various speed grade clocks, embedded memory arrays, and dedicated resources designed for supporting special functions (e.g., wide input gates). Different types of resources on an FPGA device have different upper limits, and a feasible partitioning must satisfy the limitations for each of the different resources. To further complicate the capacity constraint, a logic function can be implemented by using different resources in an FPGA device. For example, a 2-input gate can be implemented using either a 2-input LUT or a 3input LUT logic module. Consequently, the capacity constraint of an FPGA device cannot be accurately captured by simple measurements such as gate count upper bounds. In addition to the limitation on each type of resource, capacity constraints for an FPGA device need to take into account multiple choices of logic function implementation. FPGA partitioning algorithms implemented in commercial CAD tools are usually based on traditional move-based approaches, such as Fiduccia–Mattheyses algorithm (12), with modification to incorporate FPGA-specific constraints into the algorithms. Starting with an initial feasible partitioning solution that satisfies the capacity constraints, the algorithms maintain the feasibility by allowing only the moves that do not violate capacity constraints. Initial feasible partitioning solution is usually not difficult to find if the device utilization is not close to the limitation. However, for partitioning problem where device utilization is approaching the resource limitations, finding an initial feasible partitioning solution can be challenging.

PLACEMENT In the placement step, each cell in the circuit netlist is assigned to a module on an FPGA device. The two most important issues for FPGA placement are routability and performance. Because of the fixed routing resources available on an FPGA device, routability is usually treated as a constraint in the placement process. Net length minimization, which is usually the most important optimization objective for conventional placement problems, is only of secondary importance in FPGA placement. Circuit performance in FPGA placement is also typically treated as a set of timing constraints as specified by the circuit designer. Placement algorithms that consider timing constraints are called timing-driven placement algorithms in the literature. Similar to the placement algorithms for ASIC technology, the placement steps in FPGAs consist of initial placement followed by placement optimization. Initial placement normally concentrates on general objectives, such as net length minimization, and uses constructive algorithms such as min-cut placement in order to achieve fast run time and reasonable quality. During placement optimization, initial placement results are further improved to ensure that the routing resource constraints are satisfied and other objectives, such as timing,

CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

are optimized. Despite similarity to the ASIC placement approach, there exist several FPGA-specific issues that most FPGA placement algorithms need to address, especially during placement optimization, which is very often based on simulated annealing techniques.

711

Logic module CLK CLK1

Global Routing for Channel Density Computation The numbers of routing tracks in routing channels are fixed for an FPGA device. A necessary condition for any feasible placement solutions is that the channel density in every channel cannot exceed the number of routing tracks available in the channel. Minimization of net length will tend to cause local congestion and produce a placement solution that is very difficult for subsequent global routing algorithm to generate a feasible routing. In order to calculate the channel density accurately, simulated annealing-based placement algorithms need to perform global routing iteratively for every move. Therefore, in addition to producing high-quality routing solutions, run time becomes a critical requirement for designing FPGA global routing algorithms. Such closely interleaved global routing and placement in FPGAs is different from the placement algorithms used in standard cell architectures, where channel heights can be adjusted and, therefore, global routing does not need to be embedded within the placement process. Fast Interconnection Delay Estimation Interconnection delay estimation for timing-driven placement for FPGAs is also very different from ASIC. Normally, an FPGA device contains routing tracks of various lengths in order to achieve delicate balance between routability and performance. Simple interconnection delay estimation models based on net length or fanout are no longer accurate enough for use within timing-driven placement algorithms. On the other hand, more accurate interconnection delay computation methods, such as the distributed RC model, are too computationally expensive for incorporating into simulated annealing-based placement algorithms. Therefore, special techniques for fast and sufficiently accurate interconnection delay estimation are essential for timing-driven FPGA placement. Fast interconnection delay estimation techniques have been successfully developed and used for channel-based FPGA architectures (13). Clock Skew Controlling clock skew is a critical issue in synchronous circuit designs, especially for high-speed system level designs. As long as other higher priority constraints are satisfied, it is always desirable to reduce clock skew to further improve circuit performance and fault-tolerant margin. FPGA architectures allow further clock skew reduction during placement. A typical FPGA device usually contains several clock networks. Clock pins on sequential elements such as flip flops are connected to the selected clock networks through programmable switches. Figure 5 illustrates connections between clock pin (CLK) and two clock networks (CLK1 and CLK2) in a rowbased FPGA architecture. The clock pin CLK can be connected to either CLK1 or CLK2, depending on circuit designs. Different sets of logic modules chosen for circuit placement in an FPGA device lead to different capacitance load distribu-

CLK2 Normal routing tracks Figure 5. A clock pin on a logic module can be connected to one of two clock network tracks (CLK1, CLK2) in the adjacent routing channels. The connection is established by turning on appropriate switches, represented by the circles.

tions on a clock network. Consequently, the clock skews on clock networks may vary with different placements and FPGA-specific placement algorithms can take advantage of this fact to further reduce clock skew where desired (14).

ROUTING Because of the high complexity involved in the routing problem, FPGA routing normally is performed in two phases: global routing and detailed routing. Global routing assigns each net a routing path by selecting a set of routing channels, but does not choose specific routing tracks and switches for each net. The goal of global routing is to create a problem that can facilitate the subsequent detailed router to select routing segments. Since routability is the most important issue, minimization of channel density is normally the optimization objective in FPGA global routing. Similar to the approach for conventional ASIC technologies, FPGA global routing problems are normally formulated as minimum steiner tree problems and solved by using steiner tree minimization algorithms. However, there exist two FPGA-specific issues in global routing. The first one is run time. As mentioned in the previous placement section, since global routing is embedded within the placement optimization process, run time of the FPGA global router is more restricted than the global routers used for ASIC technologies. The second issue is routability estimation. For an FPGA architecture where channel intersection areas are not fully populated with switches, routability in the intersection areas cannot be accurately measured with channel densities. Instead, connectivity architectural details within the channel intersection areas need to be considered in order to estimate the routability more accurately (15). The task of detailed routing is to assign each net to specific routing segments in the channels as restricted by the global router. Design of detailed routing algorithms depends heavily on FPGA routing architectures. Detailed routing algorithms for row-based and symmetrical-array-based architectures are significantly different. Detailed Routing for Row-Based Architectures Routing channels in row-based architectures are segmented. A routing track in the segmented channel is divided into several routing segments with various lengths by placing

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Row of logic modules

An “off” switch

A connection uses one segment

A routing track with two routing segments

A connection uses two segments with an “on” switch Figure 6. Routing in segmented channels. Switches in ‘‘off ’’ and ‘‘on’’ states are represented by open and solid circles, respectively. Switches can be turned on to connect adjacent routing wire segments on the same track in order to route longer connections.

switches between the adjacent routing segments (Fig. 6). Routing track segmentation is designed based on the net connection distribution statistics collected from a large pool of real circuit designs to achieve a delicate balance between routability and performance. Where desirable, two adjacent routing segments on the same track can be connected by turning on the switch in between to form a longer routing segment that can be used to complete a longer net connection. Most of the vertical routing segments are attached to the logic modules and provide routing resources similar to the feed throughs found in the standard cell architecture. Intersecting vertical and horizontal routing segments are fully populated with switches so that any vertical routing segments can be connected to any intersecting horizontal routing segments as necessary. Therefore, the detailed routing problem in rowbased architectures is reduced to solving segmented channel routing problems. Because switches can introduce significant delay to interconnections due to the relatively high fuse resistance, the number of switches allowed for completing a net connection is usually restricted in order to achieve high circuit performance. In a K-segment channel routing, the maximum number of segments used for routing any net connection is limited to K. For K equal to 1, the segmented channel routing problem can be solved efficiently by using a bipartite matching technique. However, for K greater than 1, segmented channel routing becomes an NP-complete problem (16), except for several special segmentations which, unfortunately, are not used in most commercial FPGA products. Efficient and effective heuristic algorithms have been developed in the commercial tools to solve the general segmented channel routing problem. Detailed Routing for Symmetrical-Array Architectures The intersecting vertical and horizontal routing tracks in a symmetrical-array-based architecture usually are not fully populated with switches. Consequently, the detailed routing problem for symmetrical-array-based architectures cannot be reduced to solving individual channel routing problems. A commonly followed approach is to explore the connectivity

Table 1. FPGA Logic Synthesis Tools Vendors and Their Products CAD Tool Vendor

CAD Tool Product Name

Cadence Designs Systems San Jose, CA Exemplar Logic Alameda, CA Synopsys Mountain View, CA Synplicity Mountain View, CA

FPGA Designer Galileo Logic Explorer FPGA Compiler Synplify

within the routing channels specified by the global router by using a search technique, such as maze router. The search approach is practically feasible due to the coarse granularity of the architecture, where the number of tracks in each channel is less than the number of tracks found in a segmented channel in a row-based architecture. Moreover, the tracks in symmetrical-array architectures are not as finely segmented as the segmentation found in the row-based architectures. The search space therefore is significantly limited. To improve the routability with the limited search space, the competition on the critical routing segments between different nets must be considered in the routing process. The critical routing segments contended by different nets can be identified based on the number of distinct nets that may use the routing segments for routing (17). COMMERCIAL CAD SOFTWARE Front-end logic optimization and technology mapping algorithms normally do not have strong dependence on FPGA architecture details. A small set of basic technology mapping algorithms can be used to support different FPGA products from different FPGA vendors. Consequently, front-end software tools used in FPGA designs are normally from independent CAD software vendors, instead of from FPGA companies. Table 1 lists several major CAD software companies that develop and market FPGA synthesis tools that can support various FPGA architectures (18). In addition to commercial tools, a number of FPGA logic synthesis tools developed at universities are in the public domain. Table 2 lists several such logic synthesis tools. Unlike synthesis and technology mapping algorithms, FPGA place and route algorithms are strongly tied to the architecture details of the individual FPGA product. Interactive evaluation between the physical design algorithms and architecture details during a new FPGA product development is

Table 2. FPGA Logic Synthesis Tools Developed at Universities Institute

CAD Tool Name

UC Berkeley UCLA University of Toronto

MIS-pga FlowMAP/RASP Chortle

CAD FOR FIELD PROGRAMMABLE GATE ARRAYS

critical to the success of product development. Currently, most FPGA vendors develop physical design software tools inhouse, and provide proprietary place and route tools together with silicon products to their customers. FUTURE TRENDS IN FPGA CAD RESEARCH AND DEVELOPMENT The goal of CAD tools is to help circuit designers use FPGA devices efficiently and effectively, and to help FPGA device architects design new FPGA architectures. Research and development of FPGA CAD tools therefore must be driven by the needs of FPGA users and designers. In this section we discuss several areas that are important for future FPGA CAD tool development. Run Time Reduction

713

vices, in order to support system-level designs that require both logic and memory. New CAD algorithms for logic synthesis and physical design may need to be developed in order to effectively integrate different functionalities on a single FPGA device. Another example where new algorithms are desirable is in hierarchical architectures. As FPGA capacity continues to increase, hierarchical FPGA architectures are more efficient compared with flattened architectures for achieving an appropriate balance between area, performance, and routability. Algorithms such as partitioning and clustering that were previously developed within other contexts will need to be modified in order to accommodate the special requirements of hierarchical FPGA architectures.

BIBLIOGRAPHY

Currently, the capacity of an FPGA device can far exceed 100K gates and is rapidly increasing. As FPGA devices become larger, the run time of CAD tools for completing an FPGA circuit design is getting longer, especially in the physical design stage. Making matters worse, the increase in run time of current CAD tools is greater than the increase in silicon gate capacity. It is no longer unusual to take more than a day to complete a design of a 100K FPGA device with current CAD tools. If the run time of CAD tools continues to increase at a faster rate than the increase in silicon capacity, the competitive advantage of fast turnaround provided by FPGAs will diminish. In order to maintain the fast turnaround advantage, it is necessary to reduce CAD tool run time, especially in the physical design stage.

1. S. D. Brown et al., Field-Programmable Gate Arrays, the Netherlands, Kluwer Academic Publishers, 1992.

Support of Different FPGA Architectures

7. J. Cong and Y. Ding, An optimal technology mapping algorithm for delay optimization in look-up-table based FPGA designs. Proc. IEEE Int. Conf. Comput.-Aided Des., pp. 48–53, 1992.

The demand for flexible CAD tools that are able to support different FPGA architectures is driven by two issues. The first is that new FPGA architectures continue to emerge to accommodate the requirements of new applications and technologies, and designing new FPGA architectures requires CAD tool support for architectural evaluation. The second issue is that developing new CAD tools is a time-consuming and hard to predict process, and very often this process is the bottleneck in the new FPGA product development. In order to address these issues, CAD tools should consist of a number of modular, independent point tools that can be easily modified and integrated to form a complete design flow to support new FPGA architecture development. The flexibility of integration of point tools is supported by carefully designed device and netlist databases that are used to transfer data between individual point tools. Each of the point tools must be able to support common features in different FPGA architectures and be flexible enough to support new architectural features. Innovative Algorithms Innovative algorithms are always in demand as FPGA architectures continue to evolve. For example, a new trend in FPGA architecture design is to integrate specialized functional modules implemented in ASIC together with FPGA in a single device. It is also becoming common to provide embedded memory arrays, especially on large capacity FPGA de-

2. S. M. Trimberger, (ed.), Field-Programmable Gate Array Technology, the Netherlands, Kluwer Academic Publishers, 1994. 3. A. El Gamal (ed.), Special section on field-programmable gate arrays, Proc. IEEE, 81 (7): 1993. 4. R. Murgai, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis for Field-Programmable Gate Arrays, New York: Kluwer Academic Publishers, 1995. 5. J. Cong and Y. Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Trans. Des. Autom. Electron. Sys., 1 (2): 145–204, 1996. 6. R. Francis, J. Rose, and Z. G. Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proc. 28th Des. Autom. Conf., San Francisco, CA, pp. 227–233, 1991.

8. B. Luca and G. De Micheli, A survey of Boolean matching techniques for library binding, ACM Trans. Des. Autom. Electron. Syst. 2 (3): 1996. 9. R. E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Trans. Comput., C-35: 677–691, 1986. 10. A. Bedarida, S. Ercolani, and G. De Micheli, A new technology mapping algorithm for the design and evaluation of fuse/antifuse-based field-programmable gate arrays, 1st Int. ACM/SIGDA Workshop FPGAs, pp. 103–108, 1992. 11. K. Zhu and D. F. Wong, Fast Boolean matching for field-programmable gate arrays, Proc. Eur. Des. Autom. Conf., pp. 352–357, 1993. 12. C. M. Fiduccia and R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proc. ACM/IEEE Des. Autom. Conf., pp. 175–181, 1982. 13. M. Chew and J. C. Lien, Fast delay estimation in segmented channel FPGAs, 2nd Int. ACM/SIGDA Workshop Field-Programmable Gate Arrays, Section 8, 1994. 14. K. Zhu and D. F. Wong, Clock skew minimization during FPGA placement, IEEE Trans. Comput.-Aided. Des. Integr. Circuits Syst., CAD-16: 376–385, 1997. 15. Y.-W. Chang et al., A new global routing algorithm for FPGAs, Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, pp. 380–385, 1994. 16. J. Greene et al., Segmented channel routing, Proc. 27th ACM/ IEEE Des. Autom. Conf., pp. 567–572, 1990.

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17. S. Brown, J. Ross, and Z. G. Vranesic, A detailed router for fieldprogrammable gate arrays, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., CAD-11: 620–627, 1992. 18. S. Schulz, Logic synthesis and silicon compilation tools, Integr. Syst. Des., 1996.

KAI ZHU Actel Corporation

D. F. WONG University of Texas at Austin

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Wiley Encyclopedia of Electrical and Electronics Engineering Cad For Manufacturability of Integrated Circuits Standard Article S. Duvall1 1Intel Corporation, Santa Clara, CA Copyright © 1999 by John Wiley & Sons, Inc. All rights reserved. : 10.1002/047134608X.W1805 Article Online Posting Date: December 27, 1999 Abstract | Full Text: HTML PDF (119K)

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Abstract The sections in this article are Concepts of CAD for Manufacturability The Role of CAD for Manufacturability in the Development Life Cycle Models and Methods for CAD for Manufacturability Research Directions in CAD for Manufacturability | | | Copyright © 1999-2008 All Rights Reserved.

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING When designing and building digital systems, we must ensure that the manufactured final product is exactly what was intended. As shown in Fig. 1, there are two processes in creating digital systems: design process and manufacturing process. Corresponding to these two processes, there are two key issues for ensuring digital systems behave as originally intended. The first is to make sure that what we are designing is correct, that is, the design is exactly the same as what we intend. The second is to make sure that what we are manufacturing is correct, that is, the product is exactly the same as what we have designed. The former process is called design verification and the latter is called manufacturing test and diagnosis. In this article we will give an overview of design verification and manufacturing fault diagnosis technology. DESIGN VERIFICATION As mentioned before, design verification is the process to ensure that what we are designing is exactly what is intended.

Specification

Design

Design verification

Manufacturing

Manufacturing test and diagnosis

Digital system Figure 1. Creating digital systems.

J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc.

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

This is one of the most important and sometimes the most time-consuming process in designing complicated systems. The specifications describe what we want, and verification is the process for checking whether the designs satisfy their specifications. The first step for verification is to describe both specification and design in mathematical ways so that we can formally apply logic to them. In the case of digital systems, Boolean functions and mathematical logics such as first-order predicate calculus are typically used, since behaviors of digital systems can be directly described by these types of logic. Once we have mathematical descriptions for specifications and designs, the next step is to verify that designs satisfy their specification via reasoning. Since verification ensures the correctness of designs with respect to specification, it is done by simulating designs and checking the appropriateness of outputs from simulations. However, this approach cannot be complete until we simulate all possible cases, which is impossible for large circuits with many input signals (i.e., all possible values of n inputs or 2n combinations). Formal verification is a process that tries to prove the correctness of designs mathematically. It implicitly checks all possible cases and guarantees the correctness of designs for all possible input combinations. Let us clarify the difference between formal verification and simulation with an example. Figure 2 is an example combinational circuit. It uses a gate called the NAND gate. NAND(x, y) gives a complement of the conjunction of x and y. It generates a 0 at its output only when both inputs are 1. Otherwise, it generates 1. The specification for the circuit is the EXCLUSIVE-OR function of x and y, which must be realized at the output of the circuit. Here EXCLUSIVE-OR is a logic function that gives the value 1 if and only if the two input values are different; otherwise it gives 0. The EXCLUSIVE-OR function of x and y is defined as x ⭈ y ⫹ x ⭈ y. Formal verification is done to make sure that the circuit in Fig. 2 realizes the EXCLUSIVE-OR function at the output. We can simulate the circuit and test for its correctness. Verification by simulation is sometimes called validation, since it does not guarantee the correctness of the design completely unless we can simulate all possible cases, which is mostly impossible for large circuits. What we can do is to test some but not all, cases. Since digital systems are described in mathematical logic or its extensions, their behaviors can be simulated by repeatedly computing logic functions. By simulating the functions of NAND in the circuit, we can obtain the values for the output of the circuit. We need to check all four cases of possible input combinations for two variables. On the other hand, formal verification of the circuit in Fig. 2 is to prove that its output is mathematically equivalent to

x

b a

y

z

the logic function EXCLUSIVE-OR of x and y. This can be checked by manipulating the Boolean formulas generated from the circuit in the following way: z ⫽ b ⭈ c, b ⫽ x ⭈ a, c ⫽ a ⭈ y, a ⫽ x ⭈ y z ⫽ x⭈x⭈y⭈x⭈y⭈y z ⫽ x⭈x⭈y ⫹ x⭈y⭈y z ⫽ x ⭈ (x ⫹ y) ⫹ (x ⫹ y) ⭈ y z ⫽ x⭈y ⫹ x⭈y

Definitions from the circuit Substitution DeMorgan’s law DeMorgan’s law Simplification

The last formula is the definition of the EXCLUSIVE-OR function of x and y. Since manipulation of all preceding formulas is independent of the values of x and y, the circuit is formally verified to be equivalent to the EXCLUSIVE-OR function of x and y. Formal verification of logic circuits using transformations of logic formulas like those just given is sometimes called theorem-proving-based verification, since it is trying to prove mathematically the correctness of designs by manipulating logic formulas. As can be seen from the previous example, an appropriate ordering of the application of various transformations, such as substitution, De Morgan’s law, and simplification, must be identified in order to obtain the goal formulas (i.e., formulas in the specification). Moreover, if the designs are not correct, transformations do not work and the verification process may not terminate. Therefore appropriate user guidance is essential, and so the verification process is interactive, that is, each transformation of the formulas is guided by users who are verifying the designs. There is a significant amount of research on the use of theorem-proving methods for formal verification (1). Although there has been much success, this method is not yet widely used because it is not completely automatic and needs human interaction. Automatic verification techniques perform an exhaustive case analysis for all combinations of values of variables, similar to the simulation of all possible cases. Typically, the techniques are based on case analysis. They first analyze the case for which the first chosen variable in the formula is 0 and then check the case for which that variable is 1, and so on. This case pattern may have to continue for all variables in the formula. Fortunately, in most cases, we can reach special cases where we can decide the value of the formula immediately. For example, suppose we analyze the formula, x1 ⭈ x2 ⭈ x3. When the variable x1 is set to 0, the entire formula immediately becomes 0 regardless of the values of the other variables. Further analysis is unnecessary for this case. Although this case analysis technique performs much better than exhaustive simulation, it is still very time consuming as its execution time grows exponentially in principle. Because of this, the case analysis technique cannot be applied to large circuits. Situations have, however, changed completely since a new data representation method for logic functions in computers, called binary decision diagrams (BDDs) (2–4), and its efficient manipulation algorithms were proposed in the 1980s. By using BDDs, significantly larger circuits can be verified in much less time.

c

Figure 2. An example circuit that realizes an EXCLUSIVE-OR function.

Binary Decision Diagram The binary decision diagram was proposed in the late 1980s and since then it has been widely used for various problems in

DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING x3

x3

x2

x2 x1

x1 1

0

1

x2

x1 0

1

x1 0

1

x1

x1 x2 + x3

x1

x1 x2

x1 1

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0

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x1 x2 0

Figure 3. Decision tree and its corresponding binary decision diagram.

1

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Or

And x2

computer science, especially in computer-aided-design areas. Here we briefly introduce BDD. BDDs are derived from binary decision trees. An example of a binary decision tree is shown in the left side of Fig. 3. It is basically an all-case analysis of the given logic function based on the values of variables. x1, x2, x3 are variables and 0 and 1 are constants. Each left edge indicates that the value of that variable is 0, whereas each right edge indicates that the value is 1 (unless constant values are added to edges as attributes). We first fix the ordering of variables. In this case the ordering is x3, x2, x1. On all paths from the root node to the leaves, all variables must appear only in this order. By traversing the edges from the root node, we can determine the value of the function. For example, the value of the function for x1 ⫽ x2 ⫽ x3 ⫽ 0 is 1 whereas the value for x1 ⫽ x2 ⫽ 0, x3 ⫽ 1 is 0. Please note that the sizes of binary decision trees are exponential with respect to the numbers of variables. BDD is derived from this tree by removing redundant nodes, as can be seen from the right side of the figure. Figure 4 shows ways to generate BDD from the binary decision tree. First, isomorphic subgraphs are merged as can be seen from the first transformation in the figure. For example, the left three nodes for x3 are isomorphic and are merged. Then any nodes with two edges going to the same nodes are deleted, as can be seen from the second transformation of the figure. If the two edges go to the same nodes, the function does not depend on the value of that variable for that particular case, and hence those nodes can be deleted. After these steps, binary decision trees become binary decision graphs, since there is sharing of subgraphs. As can be seen from Fig. 4, BDD is a lot smaller than the binary decision tree in general. An important fact is that sizes of BDDs can be polynomial for many useful logic functions, such as adders, parity functions, and most control circuits. Another key issue is that BDD is a canonical representation for logic functions with respect to the predetermined orderings of variables. That is, if the two logic functions are equivalent, their corresponding BDDs will be isomorphic as long as they are using the same ordering of variables. This is an important fact when we apply

x1 x2

x2

x3 0

x3 1

Removal of equivalent nodes x2

0

x3 1

0

x3 1

1

x1 x2 x3

x3 1

0

1

x1

x1 0

1

x2 x3 0

1

0

1

Figure 5. Using ‘‘apply’’ to manipulate logic operatons on BDDs.

BDD to verification problems. Because of these advantages BDD is now widely used. Although BDD can be obtained from binary decision trees as shown in Fig. 4, this is not an efficient way to generate BDDs, since sizes of binary decision trees are exponential with respect to the numbers of variables. So we need more efficient ways to generate BDD directly from logic circuit representation. This can be done by the procedure ‘‘apply’’ that computes logic operations directly on BDDs. Examples of apply processes are shown in Fig. 5. The apply procedure basically traverses the two given BDDs from the roots to the leaves in a depth-first order. For each step in the depth-first traversal of the two BDDs, it applies logic operations, such as AND and OR, on the two current nodes and generates a new node that corresponds to the results of logic operations. The amount of time for completion of this procedure is proportional to the product of the sizes of the BDDs that it traverses, and hence it is very efficient as long as the BDD sizes can be kept small. By using the apply procedure, we can generate BDD directly from logic circuits and do not have to generate binary decision trees. Although BDD is a very efficient and also effective way to manipulate logic functions, it surely has several drawbacks. One of the most important is the fact that sizes of BDDs are very sensitive to ordering of variables. Figure 6 shows an ex-

x1

Removal of redundant nodes

x2 x3 0

1

Figure 4. BDD is a canonical representation for logic functions.

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

x1 x2 x3 x4 x5 x6

1

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Best

1

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Figure 6. Ordering of variables is important for BDD.

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treme case. The two BDDs represent the same logic function that corresponds to the output of the circuit diagram in the figure. The left BDD uses the best ordering, x1, x2, x3, x4, x5, x6, whereas the right BDD uses the worst ordering, x1, x3, x5, x2, x4, x6. So, if we use bad ordering of variables, the resulting BDDs can be too large to be manipulated. Variable ordering for BDD is one of the most important problems in BDD-related research. It is known that to find the best ordering is NP-complete; so we have to use heuristic approaches for large logic functions (5). There are several good heuristics for giving good ordering (6–11). These heuristics are generally good for practical use, but sometimes BDDs cannot be built simply because of poor ordering. In that sense, the variable ordering problem for BDD is still a good research topic. Because BDDs are so widely used, several BDD packages are available in the public domain (12). They include a com-

1

0

plete set of useful routines for BDDs, and users can manipulate logic functions in BDDs by just using those routines appropriately. Practical Verification Technique For Combinational Circuits In order to compare the equivalence among combinational circuits, it is sufficient to generate BDDs from the circuits and to check if they are isomorphic, since BDD is a canonical representation for logic functions once ordering of variables is fixed. So, given a circuit, first of all, ordering of variables is determined by using appropriate heuristics. Then we generate BDDs for each gate in the circuit individually using the apply procedure as shown in Fig. 7. After this process, we get the BDD for the output of the circuit.

x1

x2

x2

x2 0

1

1

x1 0 0

Figure 7. Creating BDDs from circuits.

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

x1 x2

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Circuit 1

z

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BDD for output is 0?

x3 Circuit 2

x1 0

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x3

Use relationships (such as equivalence) among internal points

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225

Figure 10. Use relationship among internal signals to reduce the size of BDD for output.

0

Figure 8. Verification based on BDD.

We repeat this process on the other circuit to be compared and then check if the two BDDs obtained are isomorphic (13). An example verification based on this approach is shown in Fig. 8. In this case, both circuits give the same isomorphic BDD and so they are logically equivalent. In this approach the most important part is how to obtain ordering of the variables of BDDs, since it will determine whether we can verify circuits. If we can have a good ordering, the BDD size can be relatively small and we may be able to finish BDD construction. But if we use a bad ordering, the BDD construction process may not finish because of the prohibitively large size. By using a good heuristic for variable ordering, the state-of-theart verifier based on this approach can verify circuits having up to a couple of thousands of gates. How can we proceed if the circuits to be verified are much larger than a couple of thousands of gates? One way is to construct a ‘‘miter’’ as shown in Fig. 9 (14,15). The two circuits to be compared are connected by an EXCLUSIVE-OR gate. Then if the two circuits are equivalent, the output of the EXCLUSIVE-OR gate is always 0. So, we have only to build BDD for the output of the EXCLUSIVE-OR gate and check if it is a constant 0 or not. In so doing, we do not necessarily build a BDD for each circuit. Instead, we can construct a BDD for the output of the EXCLUSIVE-OR gate by traversing the circuit from output to input. Hence, even if the BDDs for the original two circuits are large, the BDD that we construct may not become large. Although this is a better approach, it may still not be sufficient to solve verification problems for

Circuit 1 Always 0, if equal

Circuit 2

Figure 9. Creating a miter to check the equivalence of two circuits.

large circuits, because the sizes of intermediate BDDs during construction of the BDD for the output may become too large. The approach just mentioned can, however, be significantly improved by using information on the relationship among values of internal signals in the two circuits. For the equivalence check of two combinational circuits, there are cases in which we can verify many larger circuits, for example, circuits having 100,000 gates or larger. One such case involves two similar circuits, for example, one circuit is a slight modification of the other. This occurs frequently in real designs, as designers try to improve the performance of circuits by modifying circuits partially or incrementally. If the two circuits are similar we can expect much signal value dependency among internal signals in the two circuits. For example, if the circuit optimization performed by designers consists of just inserting buffers to speed up a circuit, we will see much internal equivalence between the two circuits. By using internal equivalence we can partition circuits into smaller ones and will only need to check the equivalence among those partitioned circuits instead of the original large circuits. Also, we can use relationships among internal signals in order to reduce sizes of intermediate BDDs when constructing BDDs for the output of the EXCLUSIVE-OR gate from output to inputs (see Fig. 10). By appropriately using those relationships and reducing BDD sizes, we can verify circuits having more than 100,000 gates rather easily if the two circuits to be compared are similar. Since this approach can treat circuits of real-life sizes, it is becoming widely used (16,17). Formal Verification of Sequential Circuits So far we have discussed only combinational circuits. Now we describe techniques on how to verify sequential circuits formally. First we discuss comparison between two sequential circuits. Since sequential circuits generate output sequences of varying time units, we have to make sure that the outputs have the same values at all times. That is, as shown in Fig. 11, two sequential circuits are connected and we check to see if the values of the outputs are always same (18). Since there are only finite number of flip-flops, the number of possible states in the sequential circuits is finite. Therefore, when we have checked the values of the outputs for all possible states in the two circuits, we can finish verification. For each state, essentially the same procedure as for combinational verification is followed, using the method shown in the previous sections.

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Inputs

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Figure 11. Verification of sequential circuits.

A state-transition graph can be extracted from the sequential circuit. An example state transition graph is shown in the left side of Fig. 12. s0 is the initial state, which corresponds to the reset state of the original circuit. In this case, there are three additional states and state transitions that interconnect them. All possible behaviors are represented as are all possible state transitions starting from the initial state s0, as shown on the right side of the figure. This is also called a computation tree, because it represents all possible computations that can be done by the state-transition graph on the left side. Thus the goal of sequential verification is to ensure that the values of the outputs are equal to the specified values at each node of the computation tree. This can be checked by traversing the state-transition graph features one by one until a state that has been already traversed is reached. This is basically a depth-first search on computation trees. The time to complete this process, however, is exponential in the number of flip-flops, since there are 2n states in n flip-flop circuits. Hence this approach does not work for large circuits (19,20). Another method for traversing state-transition graphs is based on a width-first traversal on computation trees, as shown in Fig. 13. It maintains a set of states that have already been checked. First the set has just the initial state s0 in the case of Fig. 13. In the next step, it will have s1, s2, and s3 as well. Those are the states that can be reached directly by a single state transition from the state s0. Then, in the next step, we see that no more states can be added to the set, and therefore the search terminates and we have traversed everything. The key idea here is to process sets of states instead of each state individually. The next question is how to represent sets of states efficiently. One commonly used approach is to represent sets with their characteristic logic functions. We introduce new variables to encode each state in the state-transition graph.

s1

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Figure 13. Breadth-first search of state transitions.

Basically we need log2(numbers of states) new variables. Then we assign values of those variables so that each state has different values. This is a type of state assignment for the given state-transition graph. Then a set of states can be represented as a disjunction of values of the variables for those states. Let us see an example, shown in Fig. 14. Since there are four states, we need two variables for encoding of states. Suppose they are x and y, and we use the following state encoding: A B C D

(x, (x, (x, (x,

y) y) y) y)

⫽ ⫽ ⫽ ⫽

(0, (0, (1, (1,

0) 1) 0) 1)

From this, we can get the corresponding state-transition table as shown in Fig. 15. In the table, x and y are encoding variables corresponding to the present states and x⬘ and y⬘ are those corresponding to the next states. From this table, we can compute transition relations for the state transition graph as follows:

TR(x, y, x , y ) = x · y · x · y + x · y · x · y + x · y · x · y + x · y · x · y + x · y · x · y TR(x, y, x⬘, y⬘) is 1 if and only if there is a state transition from the state (x, y) to the state (x⬘, y⬘). Now we can traverse the state transition graph in Fig. 14 in a breadth-first order. Let us assume the initial state to be 兵A其. In the next step we get the set of states 兵A, B其. Then we get 兵A, B, C, D其 in the following step. This can be computed

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Figure 12. State-transition graph and its trace of transitions.

Figure 14. Symbolic manipulation of breadth-first traversal of the state-transition graph.

DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

Present x y

Next x’ y’

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Figure 15. State-transition table corresponding to the state transition graph.

using the transition relation and the state-encoding variables x, y. For example, in order to get the set of states 兵A, B, C, D其 from the set of states 兵A, B其, we compute as follows. 兵A, B其 can be represented as x ⭈ y ⫹ x ⭈ y ⫽ x and so we compute

x · TR(x, y, x , y ) = x · x · y · x · y + x · y · x · y + x · y · x · y + x · y · x · y + x · y · x · y = x + y x ⫹ y ⫽ x ⭈ y ⫹ x ⭈ y ⫹ x ⭈ y corresponds to the set 兵B, C, D其. By adding the original set 兵A, B其, the result is 兵A, B, C, D其. Since computing state transitions is now formalized as the manipulation of logic functions, this process can be efficiently automated by using BDDs. It is called the symbolic traversal of state-transition graphs and is now widely used. State-of-theart implementation of this approach can verify circuits having up to around 200 flip-flops, which may have 2200 states (21–24).

MANUFACTURING FAULT DIAGNOSIS Fault location for digital logic circuits is studied here. After testing is performed to determine whether a circuit is faulty, fault location or diagnosis is performed to locate the failure. Diagnosis may be performed with a view to improving the manufacturing process or may be intended for the identification and replacement of a faulty subcircuit. Efficient diagnosis has been known to yield rapid improvement. Given a defective chip and good design criteria, the aim of the diagnostic process is to identify a subset of faults that can explain all the errors observed while testing the chip. Techniques described in this article are typically used to reduce the time required for expensive failure analysis procedures that aim at the physical confirmation of the defect (e.g., under an electron microscope). The time reduction is achieved by reducing the number of candidates to examine by analysis at the logic level. We shall first review diagnosis techniques based on their classification of usage of precomputed information (as opposed to run-time analysis) in the diagnosis process. The techniques are broadly grouped under static (cause–effect), dynamic (effect–cause), and integrated techniques. Then, we briefly review work on important tools required for diagnosis, diagnostic fault simulation, and diagnostic test generation. After this, we review diagnosis techniques specifically designed to handle unmodeled faults. Specific techniques that are representative of their genre are explained in greater detail whenever possible.

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Diagnosis Strategies Diagnostic techniques can be broadly classified into three groups. The first group, called static (cause–effect) fault diagnosis, uses precomputed information in the form of fault dictionaries for matching with the faulty responses produced by defective circuits (25–33). Fault dictionaries store output information, produced by the circuit under consideration, on application of the given set of test vectors and under the influence of the set of modeled faults. In contrast, dynamic (effect–cause) diagnosis techniques detect the faulty behavior of the circuit while the test set is applied (34–40). Recent trends show the increasing popularity of integrated diagnosis techniques in which the focus is on using small amounts of precomputed information and coupling this with efficient dynamic algorithms to perform fault location (31,41). The main advantage of static fault diagnosis techniques occurs when multiple copies of the same design are being diagnosed (as in an integrated-circuit manufacturing process). Another significant advantage of the fault dictionary approach is that it is relatively simple to use. However, a common problem associated with these techniques is that it is typically infeasible to store all the precomputed information. (Typical full fault dictionaries can require several gigabytes of storage for even moderately large circuits containing 20,000 gates.) Hence, research in this direction has concentrated on providing compact fault dictionaries. The main motivation for dynamic diagnosis algorithms is that they do not require any precomputed information. This eliminates the storage problem with fault dictionaries and also relies to a lesser extent on the type of defects being diagnosed. However, this results in the fact that the time spent for diagnosing each single faulty unit is typically much larger than that required by static techniques. Hence, research in this area has concentrated on reducing the run times. Integrated techniques have been proposed to incorporate the advantages of both the static and dynamic techniques. The main advantage of integrated fault diagnosis is the flexibility provided in choosing the kind and amount of precomputed information. This, in turn, has an effect on the time required for performing diagnosis at run time. Static Fault Diagnosis. An example of a fault dictionary is shown in Fig. 16(a) for a circuit with six modeled faults, two vectors, and two primary outputs. A typical use of the information in this dictionary could be in the following manner: If the faulty response produced by a defective chip on the application of vectors v1 and v2 was 10 and 11, then the dictionary could be used to indicate fault 5’s presence in the defective chip. Techniques for handling situations when the faulty responses do not match with any of the stored responses (exactly) are discussed later in this article under the section Unmodeled Fault Diagnosis. Since fault dictionaries are typically prohibitively large to store, fault-dictionary compaction has been an important focus of research. Past work addressing the size problem has yielded solutions in two distinct directions. The first set of contributions provide fault-dictionary compaction targeting high modeled fault resolution (25,29–32), while the second set offers alternative representations for storing the full fault dictionary (30,31,33). Fault-Dictionary Compaction Research Pass/Fail Dictionary (29). This type of fault dictionary records the faults detected, potentially detected, and not de-

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

Faults

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Figure 16. (a) Matrix dictionary; (b) vector-based tree; (c) output-based tree.

tected for each vector. It does not record detections separately by output. It is created by a single full-fault simulation and is much smaller than a full-fault dictionary. But, as might be expected, this dictionary loses some diagnostic capability when compared with the full-fault dictionary. Compact Dictionary (29). One method of enhancing the diagnostic capability of the pass/fail dictionary is to add output information. Such an approach is used in the creation of the compact fault dictionary. The compact algorithm is computationally intensive, requiring multiple simulations of all vectors against some faults, plus a full-fault simulation to produce the vector dictionary and another to produce the final dictionary after extra columns are added. The dictionary produced is known to be considerably compressed, with no loss of modeled fault resolution (30). Sequential Dictionary (30). In this technique, a pass/fail dictionary is enhanced by a single full-fault simulation. An entry is added to the dictionary for any vector and output that distinguishes between any pair of faults not previously distinguished. This is computationally cheaper that the compact dictionary generation algorithm. There is no loss of modeled fault resolution. List Splitting Dictionary (30). This dictionary is created by using efficient list splitting. The lists correspond to faults that are not distinguished at each vector–output combination in the diagnosis process. However, it is not accurate for sequential circuits; hence the diagnostic resolution suffers. Drop on K Dictionary (30). While creating this dictionary, the fault simulator drops each fault after its Kth detection and creates an otherwise standard dictionary, including possible detections until each fault’s Kth definite detection. This technique assumes that K detections distinguish between most fault pairs and that some faults cause errors for many vectors, filling dictionaries with unneeded data. Simulation costs here are less than those for a full-fault dictionary.

First Failing Pattern Dictionary (30). This is a special case of the drop on K dictionary for K ⫽ 1. Detection Frequency Dictionary (30). A full-fault simulation is performed, and for each fault f, the number of vectors definitely (df) and potentially producing errors (pf) are counted. Each fault can cause errors numbering between df and df ⫹ pf. The list of faults that causes each possible number of errors forms an indistinguishability class for this dictionary. The resolution of this dictionary is poor in comparison with other schemes. Tree-Based Compaction Dictionary (32). Diagnostic experiment trees (as shown in Fig. 16) have also been used to identify information that is not diagnostically useful (for modeled faults) to provide compact dictionaries. An example of information that is eliminated corresponded to output information for faults after they were completely distinguished from other faults. Full-Fault-Dictionary Representation Research. A key problem with the compaction techniques that have been previously described lies in the fact that the information that they identify as diagnostically useful is useful only with respect to modeled faults. Hence, the diagnostic accuracy of such dictionaries in the presence of unmodeled faults may degrade. Thus there is a necessity for developing storage structures that enable efficient representation of the information in the full-fault dictionary. This approach is orthogonal to compaction, which has achieved storage savings by removing output information. Matrix Dictionary (42). Full-fault dictionaries need to store output information corresponding to each vector and fault pair. Conventionally, they have been stored using a matrix representation. For a circuit with v vectors, o outputs, and f faults, the size of the matrix dictionary is vof bits for combinational circuits and 2vof bits for sequential circuits.

DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

List Dictionary (31). List-based dictionaries have been proposed as an alternative to the matrix representation (31). The list dictionary records only information corresponding to detections. Tree-Based Fault-Dictionary Compaction and Representation. Diagnostic experiment trees (32,33,43) are powerful tools for modeling the information corresponding to a diagnostic experiment. Diagnostic experiment trees are labeled trees; hence the dictionary storage problem can be reduced to a labeledtree encoding problem. Two labeled trees that were used to represent the diagnostic experiment are shown in Figs. 16(b) and 16(c). Definition 1 [Vector-Based Diagnostic Experiment Tree TV(V, E)]. A diagnostic experiment tree in which each level represents the application of a test vector and in which each edge e 僆 E(TV) is associated with a list of outputs O(e) that is the set of all the primary outputs of the circuit is called a vectorbased diagnostic experiment tree. Definition 2 [Output-Based Diagnostic Experiment Tree TO(V, E)]. A diagnostic experiment tree in which each level represents a (test vector, output) pair rather than a test vector, and in which each edge e 僆 E(TO) is associated with a single primary output of the circuit is called an output-based diagnostic experiment tree. Example. Figures 16(b) and 16(c) show the vector-based and output-based diagnostic experiment trees corresponding to the full-fault dictionary shown in the matrix format in Fig. 16(a). The information embedded in the vector-based diagnostic experiment tree is fully exploited to identify output sequences that may be eliminated to produce highly compact dictionaries even while they retain high diagnostic resolution with respect to modeled faults. The compact storage structures developed for storing the information identified to be useful provide compaction of up to 2 orders of magnitude (32). For full-faultdictionary representation, it is shown that both of the labeled trees can be efficiently represented by disjointly storing the label information and the underlying unlabeled tree. The vector-based tree is encoded by the use of a compact binary code, while the regular structure of the output-based tree is exploited to provide a spectrum of eight alternative representations for the full-fault dictionary. It is worth noting that the currently known list and the matrix formats arise as special cases in this framework. The results give some of the best currently known storage requirements for full-fault-dictionary representation (33). Dynamic Diagnosis. Dynamic diagnosis techniques analyze the output responses produced by the failed chip at diagnosis time with the possible use of diagnostic fault simulation to derive a set of failures that best explain the set of observed responses. The approach does not require the storage of any precomputed information. We present a brief overview of dynamic diagnosis research with emphasis on work targeting large, practical circuits. The Deduction Algorithm (42). This analysis processes the response obtained from the faulty unit to determine the possible stuck-at faults that can generate that response, based on deducing internal values in the unit under test (UUT). Any line for which both 0 and 1 values are deduced can be neither s-a-0 (stuck-at-0) nor s-a-1 (stuck-at-1) and is identified as fault-free. Faults are located on some of the lines that cannot

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be proved normal. Internal values are computed by the deduction algorithm, which implements a line-justification process the primary goal of which is to justify all the values obtained at the POs (primary outputs), given the tests applied at the PIs (primary inputs). Backtracking is used either to recover from incorrect decisions or to generate all possible solutions. However, no results are available from this work for circuits of practical size. The Pair-Analysis Approach (34). In contrast to other techniques, this work considers pairs of vectors rather than single vectors. This gives the method an additional capability to encode polarity of different paths in the circuit by applying transitions on a limited number of inputs. The primary claim in this paper is that by the use of this technique, all faults can be diagnosed to their equivalence classes. This work is applicable only to combinational circuits. Sensitizing Input Pairs (45). A technique that has some similarity to the pair-analysis approach has been recently proposed. This is the first work that successfully provided analysis-based solutions to nontrivial sequential circuits. However, like other analysis techniques, it is still not possible to apply this technique to large circuits. Full-Scan Diagnosis Algorithms (35,36). This work targets full-scan designs. The heart of this work lies in an efficient vector parallel fault simulator that rapidly reduces the number of candidate faults based on the faulty responses and the expected failures due to the fault. Modeled Fault Simulation (38,46,47). A common dynamic diagnosis strategy that has been used to diagnose large circuit defects is to obtain expected output responses by the use of modeled fault simulation. However, due to the excessive fault-simulation costs, the time taken to perform the diagnosis may be large for repeated diagnosis of large circuits. Path Tracing (PT) (40). A strategy for dynamic diagnosis with reduced diagnostic fault simulation time performs fault dropping during diagnosis time with the help of critical path tracing. Faults are dropped when it is decided that they are on lines that do not influence any faulty output lines. Example Dynamic Diagnosis. An example of a diagnosis decision arrived based on path tracing is shown in Fig. 17. The output of gate e fails. The path trace starts from this output and proceeds to the inputs. Because gate e has two controlling inputs, the trace continues from one of them. Node B, which is part of the bridging fault A@B (node A shorted with node B), is included (along with other candidates on the paths traced) in the candidate set of faulty nodes by the path– trace procedure. Expert Systems and Artificial Intelligence Techniques. Diagnosis has been attempted in rule-based expert systems that utilize encoded empirical knowledge obtained from human experts. These systems are not entirely deductive and bear

1 0

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Figure 17. Path trace from failing output.

1/0

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

some resemblance to the fault-dictionary approach. In contrast, some artificial intelligence researchers have proposed techniques that are based on more detailed structural and behavioral models of the system being diagnosed. However, the most important problem with such techniques is that they target only small circuits and do not attempt to tackle the problems that arise with more elaborate designs. Integrated Diagnosis. The prohibitive size of fault dictionaries and the large run times required for dynamic diagnosis have given rise to integrated fault-diagnosis techniques, in which the focus is on storing a limited amount of essential information and utilizing this information effectively along with analysis or simulation at run time. We now provide an overview of this research. Dynamic Dictionaries. This approach involves two stages (31,41). The first stage identifies a small group of candidate faults, and then a small part of the full-fault dictionary is generated dynamically in the second stage for just those faults and for only a few of the vectors that detect them. Hence, two-stage fault isolation avoids the static cost normally associated with full dictionaries and most of the computation time that is required in a pure dynamic technique, while still providing most of the resolution. The limited dictionary used in the first stage of the two-stage process is a very small dictionary that can be generated by limited fault simulation. The diagnosis algorithm lists all candidate faults that have been observed by comparing observed errors with records in the limited dictionary. Then, in a second stage, a set of vectors is fully simulated against candidate faults, and a matching algorithm ranks all faults. Experimental results were provided for a variety of benchmark circuits and industrial implementations. It was also shown that the loss of resolution incurred was not significant. State-Information-Based Diagnosis. State-information-based diagnosis solves a crucial problem with traditional diagnostic techniques based on storage (48). Typically, such techniques store only primary output-based information, offering only a black-box view of the circuit and thus little diagnostic flexibility. This technique provides a solution by storing information corresponding to the internal nodes in the circuit, namely the state nodes. The selective storage of state information has been shown to improve the time for diagnostic fault simulation significantly. Experimental results on large circuits were presented. Level-Information-Based Diagnosis. Precomputed information tracking the diagnostic classes at each level of the diagnostic experiment tree, specifically targeting a reduction in the fault simulation costs to be incurred at diagnosis time, is the key contribution of this work (49). Fault simulation costs are modeled in terms of computations associated with each (fault, vector) pair. Tools for Diagnosis: Diagnostic Fault Simulation and Test Generation Diagnostic Fault Simulation. Diagnostic fault simulation is useful for determining the diagnostic capability of a given test set and for generating fault dictionaries and diagnostic information specific to a given test set. Diagnostic capability is reported using various diagnostic measures. Diagnostic test generation involves generating tests to distinguish between

fault pairs. Efficient generation of diagnostic test vectors can be assisted by a fast diagnostic fault simulator. Typically, diagnostic fault-simulation techniques have focused on simulation based on stuck-at faults and the developed measures are also for the same models. Rapid techniques are available both for combinational and sequential circuits, and we review the more general case of sequential circuits here. During fault simulation of a circuit starting from an unknown state, a good or faulty sequential circuit can produce a 0, 1, or X on each primary output for each test vector input, where X is an unknown value whose actual binary value depends on the initial state of the machine. If fault simulation indicates that a fault f i produces an output of 0 and another fault f j produces an output of 1 on the same primary output for the same input, then the faults f i and f j are said to be distinguished. However if a fault f i produces an output of 0 or 1 and another fault f j produces an output of X, then it is possible that the faults f i and f j may not be distinguished. Therefore, the pessimistic assumption is made that an output of 1 or 0 is indistinguishable (with respect to this test set) from an output of X. Diagnostic Measures. Camurati et al. (50) proposed two diagnostic measures. Diagnostic resolution (DR) is the fraction of fault pairs distinguished by a test set. Diagnostic power (DP) is the fraction of faults that are fully distinguished. A fault is fully distinguished if the test set distinguishes it from every other fault in the fault list. A third measure (51), which gives a more complete picture, is to identify sets of faultequivalence classes and report the number of these classes by size; this measure is applicable to combinational circuits and sequential circuits that start from a known reset state. This is extended to indistinguishable fault classes (38) to account for unknown values occurring at the outputs of sequential circuits during simulation. Another measure, the diagnostic expectation (30), is the average of indistinguishability class sizes over all faults. It is assumed that all faults are equally likely to occur. Distinguishability Matrix Approach. Early methods for performing diagnostic fault simulation for moderately large circuits (38) used a distinguishability matrix. The distinguishability matrix is an f ⫻ f matrix, where f is the number of faults. An entry of 1 indicates that the two faults specified at the intersection of the row and column are distinguished by some sequence of test vectors in the test set. It requires O( f 2) space, and the time complexity is O(vof 2), where v is the number of vectors in the set and o is the number of outputs in the circuit. List-Based Methods. Ryan, Fuchs, and Pomeranz (30) mention that a more efficient way to represent faults that are indistinguishable by a given test set is by using lists of faults. Jou and Chen (52) and Chen and Jou (53) represent pairs of indistinguishable faults using lists. This representation is a compact implementation of the distinguishability matrix. It is equivalent to storing only those entries of the distinguishability matrix with values of 0. Here, faults may appear in multiple lists. The indistinguishability relationship between all pairs of faults can be represented as an undirected graph, with the faults as nodes and the indistinguishability relationships between them as edges. Previous approaches essentially represent this graph as an adjacency matrix (38) or as incidence lists (52,53).

DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING

Later representations (39) avoided explicit storage of the indistinguishability relationship between all pairs of faults, but represent the indistinguishability relationship between classes of faults. Each fault is present in only one of the classes. This makes the representation more compact than those previously proposed (38,52,53). Although the worst-case space complexity is still O( f 2), experimental results demonstrated that the average memory usage is almost linear for the benchmark circuits. The representation also reduces the number of output response comparisons between faults and hence speeds up the simulation process. Diagnostic Test-Pattern Generation. Diagnostic automatic test pattern generation (DATPG) is critical to performing efficient fault diagnosis. In diagnostic test generation, the goal is to find a test sequence such that the circuit produces a different response under one fault than it does under another. Such techniques have been primarily targeted towards stuckat faults and for combinational circuits, although recent work has made progress towards both unmodeled faults and sequential circuits. The diagnostic test-generation problem for sequential circuits is more acute than its combinational circuit counterpart mainly because of multiple time frames that need to be handled. The problem is compounded by the unknown values in state elements; these unknown values may increase the number of fault pairs that need to be explicitly considered by a diagnostic test generator. Combinational Circuits. Work on DATPG for combinational circuits has been developed based on both functional (e.g., BDD-based) and structural techniques (PODEM-based) (50,54–57). DIATEST (56) is a combinational diagnostic testgeneration program that was developed based on the conversion of a conventional test generator into a diagnostic test generator. Complete results (with no aborted fault pairs) were provided on moderate-sized (on the largest standard public benchmark circuits) combinational circuits. Since equivalence identification, much like redundancy identification, is a computationally intensive operation in the DATPG process, techniques to identify combinational equivalences (57–61) have been proposed. Sequential Circuits. Formal techniques have also been used for sequential circuit diagnostic test generation (62,63); however, the drawbacks of these approaches are the assumption of a fault-free reset state and the inability to handle large circuits due to memory requirement problems. Simulationbased diagnostic test generation algorithms for large sequential circuits have also been presented (64), but there is a lack of indistinguishability identification. Later, a powerful method to modify a conventional sequential test generator into a sequential diagnostic test generator has been proposed (65). The method utilizes circuit netlist modification along with a forced 0/1 or 1/0 (66) value at a primary input in the modified circuit. Indistinguishability. There is also evidence (62,63,65,67,68) indicating that a main burden of diagnostic test generation is in proving indistinguishability. Another difficulty in solving this problem arises in sequential circuits because the terms distinguishable, indistinguishable, detectable, and undetectable take on different meanings with different test methodologies [multiple observation time (69,70) or conventional, gatelevel test generation with single observation time and threevalued simulation (42)]. Methods to characterize these rela-

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tions and identify them implicitly (without explicitly making a call to the diagnostic engine for each relation) have simplified the computational task of diagnostic test-pattern generation (67,68). Unmodeled Fault Diagnosis The fault model used to predict defect behavior plays an important role in diagnosis (47). In order for a fault model to be valid for diagnosis it should accurately model the corresponding defect, and such defects should occur in real circuits (71). It is worth noting that static (cause–effect) techniques are perhaps more dependent on the fault models than dynamic (effect–cause). Based on Modeled Faults. A typical approach for diagnosing unmodeled faults is to use the information available from the modeled faults in a controlled manner to make conclusions about the presence of unmodeled faults. Issues concerning accuracy and the time required to perform diagnosis govern the kind of matching algorithm being used. These schemes can range from dropping all faults whose response shows a definite mismatch with the observed faulty response (applicable to pure modeled fault diagnosis; fast) (31,35,36) to dropping few or no faults with the use of scoring schemes to obtain a set of candidate faults (applicable to arbitrary unmodeled fault diagnosis; slow) (31,38). Schemes studying the use of various combinations of matching schemes and fault models have also received research attention, and information corresponding to vectors showing failures and vectors showing no failures has been used to obtain separate matching parameters (31,47,72). This approach has been suggested to attain better diagnosis for unmodeled faults. An intuitive explanation for the better accuracies obtained using the separate handling of the failing (failures observed) and passing (good values observed) vectors is given from the fact that obtaining separate parameters makes it possible to explain observed failures as opposed to other matching schemes in which matching of an error is not distinguished from the matching of a good value. Bridging Fault Diagnosis. A common failure mode in current complementary metal-oxide semiconductor (CMOS) technologies is that of short circuits. Thus, many failures can be modeled as bridging faults and they have hence received extra attention. Techniques for diagnosing bridging faults have been primarily targeted at combinational circuits because of the large computational overheads associated with the simulation of bridging faults and the lack of a clear understanding of the complete effects of sequential bridging faults. Even for combinational circuits, only a limited set of realistic bridging faults that are extracted from the layout (73) are typically used because of the prohibitively large numbers of all possible bridging faults, even for small circuits. An additional complicating factor for these faults is that a short circuit (that may produce an intermediate voltage value) may be interpreted differently by logic gates downstream from the bridged lines due to variable input logic thresholds. This is known as the Byzantine generals problem. Several techniques have been proposed for bridging-fault diagnosis in combinational circuits. The most popular approaches are ones that use stuck-at dictionaries to diagnose bridging faults. The reason for this is that this avoids compu-

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tationally intensive bridging-fault simulation. Millman, McClusky, and Acken (74) presented an approach to diagnose bridging faults using stuck-at dictionaries. Chess et al. (46) and Lavo, Larrabee, and Chess (72) improved on this technique. These techniques enumerate bridging faults and are hence constrained to use a reduced set of bridging faults extracted from the layout. Furthermore, they need to either store a stuck-at fault dictionary or perform stuck-at fault simulation. Chakravarty and Liu (75) proposed a technique based on Iddq (quiescent current) using only good circuit simulation. Chakravarty and Gong (76) described a voltage-based algorithm that used the wired-AND (wired-OR) model. This work (76) implicitly considers all bridging faults. It is worth noting that wired-AND and wired-OR models that are assumed work only for technologies for which one logic value is always more strongly driven than the other. A deductive technique for combinational circuits that does not explicitly simulate faults has been proposed. However, this technique is not complete because it only reduces the candidate set of bridging faults and may end up with a potentially large set of candidates. BIBLIOGRAPHY 1. A. Gupta, Formal hardware verification methods: A survey, Formal Methods Syst. Des., 1 (2/3): 151–238, October, 1992. 2. S. B. Aker, Binary decision diagrams, IEEE Trans. Comput., C27: 509–516, 1978. 3. R. E. Bryant, Graph-based algorithms for boolean function manipulation, IEEE Trans. Comput., C-35: 667–691, 1986. 4. S. Minato, N. Ishiura, and S. Yajima, Shared binary decision diagram with attributed edges for efficient boolean function manipulation, Proc. 27th ACM/IEEE Des. Autom. Conf., 1990, pp. 52–57. 5. S. J. Friedman and K. J. Spowit, Finding the optimal variable ordering for binary decision diagrams, Proc. 24th ACM/IEEE Des. Autom. Conf., 1987, pp. 348–356. 6. M. Fujita, H. Fujisawa, and N. Kawato, Evaluation and implementation of boolean comparison method based on binary decision diagrams, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’88), 1988, pp. 6–9. 7. N. Ishiura, H. Sawada, and S. Yajima, Minimization of binary decision diagrams based on exchanges of variables, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’91), 1991, pp. 472–745. 8. T. Kakuda, M. Fujita, and Y. Matsunaga, On variable ordering of binary decision diagrams for the application of multi-level logic synthesis, Proc. Eur. Des. Autom. Conf. (EDAC ’91) , 1991, pp. 50–54. 9. S. Malik et al., Logic verification using binary decision diagrams in a logic synthesis environment, Proc. IEEE Int. Conf. Comput.Aided Des. (ICCAD ’88), 1988, pp. 6–9. 10. S. Minato, Minimum-width method of variable ordering for binary decision diagrams, IEICE Jpn. Trans. Fundam., E75-A (3): March, 1992. 11. R. Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’93), 1993. 12. K. S. Brace, R. L. Rudell, and R. E. Bryant, Efficient implementation of a bdd package, Proc. 27th ACM/IEEE Des. Autom. Conf., 1990, pp. 40–45. 13. J. C. Madre and J. P. Billon, Proving circuit correctness using formal comparison between expected and extracted behavior, Proc. 25th ACM/IEEE Des. Autom. Conf., 1988, pp. 205–210. 14. D. Brand, Verification of large synthesized designs, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’93), 1993.

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DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING 38. E. M. Rudnick, W. K. Fuchs, and J. H. Patel, Diagnostic fault simulation of sequential circuits, Proc. Int. Test Conf., 1992, pp. 178–186. 39. S. Venkataraman et al., Rapid diagnostic fault simulation at stuck-at faults in sequential circuits using compact lists, Proc. 32nd ACM/IEEE Des. Autom. Conf., 1995, pp. 133–138. 40. S. Venkataraman, I. Hartanto, and W. K. Fuchs, Dynamic diagnosis of sequential circuits based on stuck-at faults, Proc. VLSI Test Symp., 1996, pp. 198–203. 41. P. Ryan, S. Rawat, and W. K. Fuchs, Two-stage fault location, Proc. Int. Test Conf., 1991, pp. 963–968. 42. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital System Testing and Testable Design, New York: Computer Science Press, 1990. 43. Z. Kohavi, Switching and Finite Automata Theory, New York: McGraw-Hill, 1978. 44. F. C. Hennie, Finite-State Models for Logical Machines, New York: Wiley, 1968. 45. N. Yanagida, H. Takahashi, and Y. Takamatsu, Multiple fault diagnosis in sequential circuits using sensitizing sequence pairs, Proc. Int. Symp. Fault Tolerant Comput., 1996, pp. 86–95. 46. B. Chess et al., Diagnosing of realistic bridging faults with stuckat information, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’95), 1995, pp. 185–192. 47. R. C. Aitken and P. C. Maxwell, Better models or better algorithms? Techniques to improve fault diagnosis, Hewlett-Packard J., February, 46 (1): 110–116, 1995. 48. V. Boppana, I. Hartanto, and W. K. Fuchs, Fault diagnosis using state information, Proc. Int. Symp. Fault Tolerant Comput., 1996, pp. 96–103. 49. V. Boppana and W K. Fuchs, Integrated fault diagnosis targeting reduced simulation, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD ’96), 1996, pp. 267–271. 50. P. Camurati et al., A diagnostic test pattern generation algorithm, Proc. Int. Test Conf., 1990, pp. 52–58. 51. K. Kubiak et al., Exact evaluation of diagnostic test resolution, Proc. 29th ACM/IEEE Des. Autom. Conf., 1992, pp. 347–352. 52. J. M. Jou and S.-C. Chen, A fast and memory-efficient diagnostic fault simulation for sequential circuits, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD’94), 1994, pp. 723–726. 53. S.-C. Chen and J. M. Jou, Diagnostic fault simulation for synchronous sequential circuits, IEEE Trans. Comput.-Aided Des., 16: 299–308, 1997. 54. P. Camurati et al., Diagnostic oriented test pattern generation, Proc. Eur. Des. Autom. Conf., (ECAD’90), 1990, pp. 470–474. 55. J. Savir and J. P. Roth, Testing for, and distinguishing between failures, Proc. Int. Symp. Fault Tolerant Comput., 1982, pp. 165–172. 56. T. Gru¨ning, U. Mahlstedt, and H. Koopmeiners, DIATEST: A fast diagnostic test pattern generator for combinational circuits, Proc. IEEE Int. Conf. Comput.-Aided Des. (ICCAD’91), 1991, pp. 194–197. 57. I. Hartanto, V. Boppana, and W. K. Fuchs, Diagnostic fault equivalence identification using redundancy information & structural analysis, Proc. Int. Test Conf., 1996, pp. 294–302. 58. E. J. McCluskey and F. W. Clegg, Fault equivalence in combinational logic networks, IEEE Trans. Comput., C-20: 1286–1293, 1971. 59. A. Goundan and J. P. Hayes, Identification of equivalent faults in logic networks, IEEE Trans. Comput., C-29: 978–985, 1980. 60. B. K. Roy, Diagnosis and fault equivalences in combinational circuits, IEEE Trans. Comput., C-23: 955–963, 1974. 61. A. Lioy, Advanced fault collapsing, IEEE Des. Test Comput., 9 (1): 64–71, 1992.

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MASAHIRO FUJITA VAMSI BOPPANA Fujitsu Labs of America

DETECTION ALGORITHM, RADAR. See RADAR TARGET RECOGNITION.

DETECTION THEORY. See CORRELATION THEORY. DETECTORS. See DEMODULATION PHOTODETECTORS QUANTUM WELL.

DETECTORS, IONIZATION. See IONIZATION CHAMBERS. DETECTORS, MICROWAVE. See MICROWAVE DETECTORS.

DETECTORS, SUBATOMIC-PARTICLE. See PARTICLE SPECTROMETERS.

DETECTORS, THERMOPILE. See THERMOPILES.

234

DIAGNOSIS OF SEMICONDUCTOR PROCESSES

DETECTORS, ULTRAVIOLET. See ULTRAVIOLET DETECTORS.

DEVICE AND PROCESS MODELING. See MONTE CARLO ANALYSIS.

DEVICE MODELS. See NONLINEAR NETWORK ELEMENTS. DEVICES, DIAMOND. See DIAMOND BASED SEMICONDUCTING DEVICES.

DEVICES, FIBER-OPTIC. See FIBEROPTIC SENSORS. DEVICES, ORGANIC. See ORGANIC SEMICONDUCTOR DEVICES.

DEVICES SUPERCONDUCTING. See SUPERCONDUCTING ELECTRONICS.

DEVICES, SURFACE MOUNT. See SURFACE MOUNT TECHNOLOGY.

DIAGNOSIS. See FAULT DIAGNOSIS. DIAGNOSIS FAULT LOCATION. See DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING.

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Wiley Encyclopedia of Electrical and Electronics Engineering Electrical and Timing Simulation Standard Article Chandu Visweswariah1 1IBM Thomas J. Watson Research Center, Yorktown Heights, NY Copyright © 1999 by John Wiley & Sons, Inc. All rights reserved. : 10.1002/047134608X.W1807 Article Online Posting Date: December 27, 1999 Abstract | Full Text: HTML PDF (148K)

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Abstract The sections in this article are Spice Timing Simulation Switch-Level and Logic Simulation Static Timing Analysis Sensitivity Analysis Circuit Optimization Conclusion | | | Copyright © 1999-2008 All Rights Reserved.

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ELECTRICAL AND TIMING SIMULATION

229

Inaccuracy level

Logic simulation

Switch-level simulation

Timing simulation

10%

“Exact” simulation

1%

ELECTRICAL AND TIMING SIMULATION