Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs
Jesús Ruiz-Amaya • Manuel Delgado-Restituto Ángel Rodríguez-Vázquez
Device-Level Modeling and Synthesis of HighPerformance Pipeline ADCs
2123
Jesús Ruiz-Amaya Instituto de Microelectrónica de Sevilla C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain
[email protected] Ángel Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla Universidad de Sevilla and CSIC C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain
[email protected] Manuel Delgado-Restituto Instituto de Microelectrónica de Sevilla C/ Américo Vespucio Isla de la Cartuja 41092 Sevilla Spain
[email protected] ISBN 978-1-4419-8845-4 e-ISBN 978-1-4419-8846-1 DOI 10.1007/978-1-4419-8846-1 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011930262 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
To the memory of Fernando, Jesus’s beloved brother
Preface
Device-level modeling and synthesis of high-performance pipeline ADCs Digital computing and signal processing are present in most current communications systems. The proliferation of these systems, compared with their analog counterparts, is a result of their robustness to supply and processing variations, their low sensitivity to noise and, above all, the improvements in their technological scaling [1–5]. These properties have made the design and test automation of such systems easier, favouring the development of Computer-Aided Design (CAD) tools and automatized methodologies. In spite of the benefits of digital processing, a communications system cannot be fully digital as the actual signals are inherently analog and as a result, there is a need for circuits which can interface with the digital world. Analog-to-Digital Converters (ADCs), which acquire and digitize the signal, fall into the category of circuits required. As Fig. 1 shows, numerous approaches can be found, depending on the field of application of the converter. The design of these analog circuits is a major challenge for designers due to rapidly-evolving digital systems, which require increasingly accurate and fast converters, while the current trend to integrate them into adverse digital technologies is also a contributing factor. Hence the importance of developing design methodologies and CAD tools [6–16] which can assist designers in shortening the time-to-market of final products and reducing the complexity of such a challenge. In this monograph, a thorough design methodology for ADCs, and more specifically pipeline converters, will be presented. The main motivations for this book are that: (1) on the one hand, pipeline converters cover a wide field of broadband applications such as Digital V ideo Broadcasting (DVB), Power Line Communications (PLC) or V ery high bit-rate Digital Subscriber Line (VDSL) communications and (2) their inner structure is complex, comprising very accurate Switched-Capacitor (SC) circuits, other sub-ADC topologies such as flash architectures, digital circuits, numerous auxiliary building blocks and a meticulous timing. These two reasons make a design methodology for pipeline converters even more attractive and necessary. The main contributions of this design methodology are: vii
viii
Preface ENOB
Instrumentation
ΣΔ il e ob ,m s io tion ud ca , a ni ch mu ee m Sp co
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
Algorithmic, ΣΔ, SAR
Biomedical applications, sensors
Pipeline Interpolative Folding
Broadband wireline communications
Ultrawideband, RF communications
Algorithmic, ΣΔ, SAR 100
1k
10k
100k
Flash
1M
10M
100M
1G
Frequency
Fig. 1 Field of application of ADCs
• The development of an accurate and fast behavioural simulator for pipeline ADCs. It includes efficient and accurate behavioural models for the basic building blocks of pipeline converters. In addition, it provides high flexibility, low computational cost, and user-friendliness since it has been integrated into the Matlab-Simulink interface. To the best of our knowledge, these behavioural models are the most accurate and thorough models reported to date, taking into account not only small-signal effects but also other important large-signal phenomena. In fact, our behavioural models show a maximum deviation of 0.3 bits of effective resolution with transistor-level simulations. • The above behavioural simulator has been combined with an optimization algorithm for synthesis purposes. Both genetic and simulated annealing approaches have been used. • A complex synthesis procedure for the mapping of the high-level converter specifications onto transistor-level specifications has been developed. This procedure is able to reduce the design parameter space to only three design variables, from which the remaining parameters are meticulously determined. This reduction of the design parameter space is combined with a set of processing routines in Matlab which optimize the sizing of remaining parameters and provide accurate estimates of transistor-level parameters. These routines use look-up table techniques for a better characterization and estimation of technology parameters. As a result, an efficient and accurate transistor-level synthesis tool of pipeline converters will be implemented. It will be able to map the high-level specifications of the pipeline converter directly onto transistor-level parameters. To do so we will combine the proposed behavioural simulator to evaluate the converter performance, and the Matlab routines to reduce the design parameter space and estimate the parasitics and dimensions of the transistors at electrical level; with an optimization algorithm for
Preface
ix
the selection of the most suitable pipeline architecture in terms of power consumption and area. Against other design methodologies and CAD tools, it will be shown that several advantages are achieved with our proposed synthesis tool: (1) the proposed behavioural modelling will extend previous approaches, considering both one- and two-stage Miller Compensated (MC) OTA macromodels and including small- and novel large-signal effects, (2) the required bottom-up iterations for the fine tuning of the converter performance will be drastically reduced thanks to actual transistor-level parameters (such as parasitic capacitances, transconductances, saturation currents, etc.) and closed-loop operation conditions will be intrinsically considered in the design flow; (3) optimum architecture selection will be guaranteed since all required architectures will be synthesized at transistor level thanks to the efficiency and speed of the proposed tool; (4) the typical oversizing carried out by most designers due to uncertainty of other design methodologies will not be necessary since the accuracy of the behavioural models proposed will allow us to estimate both the resolution and power consumption of the converter with precision. It is worth mentioning that although this design methodology will be developed specifically for pipeline ADCs, it can easily be extended to other converter approaches such as Sigma-Delta (), algorithmic or Successive Approximations Register (SAR) architectures. The book is organized into seven chapters.
Chapter 1: Pipeline ADC Overview This chapter will present a brief introduction to ADCs, offering a description of the fundamentals of analog-to-digital conversion and the main error mechanisms inherent to the conversion process. The main metrics which characterize the ADC performance will also be summarized. The basic operation principles of pipeline converters will then be described and the practical implementation of its basic building blocks discussed.
Chapter 2: Design Methodologies for Pipeline ADCs A brief review of the conventional design methodologies for analog-to-digital converters is offered in this chapter. A novel synthesis tool will be proposed for the improvement of these conventional design methodologies. This tool will be composed of a behavioural simulator, a set of Matlab routines, and an optimizer. The main advantages of this synthesis procedure will be highlighted.
Chapter 3: Pipeline ADC Electrical-Level Synthesis Tool The proposed synthesis tool, which has been integrated into the Matlab-Simulink interface, will be presented in this chapter. Brief descriptions will be offered for the
x
Preface
basic components, that is, the behavioural simulator, the set of Matlab routines and the optimizer.
Chapter 4: Behavioural Modelling of Pipeline ADCs The key to the proposed synthesis tool is a behavioural simulator which allows us to accurately estimate the performance of the ADC. This behavioural simulator includes a set of behavioural models which describe the effect of the main non-idealities of the practical implementation of the basic building blocks in the pipeline converter. This chapter will be devoted to presenting these behavioural models and illustrating the impact of these non-idealities on the performance of the ADC.
Chapter 5: Case Study: Design of a 10bit@60MS Pipeline ADC The design methodology will be applied to synthesize a 10bit@60MS/s pipelineADC in a 0.13μm 6-metal technology at 1.2 V voltage supply. The high-level converter specifications will be directly mapped to transistor-level specifications, verifying target fulfilment by means of transistor-level simulations. The design of auxiliary building blocks will also be detailed. The layouts of all basic building blocks will be presented and post-layout verifications will be carried out. The converter designed will only consume about 23 mW, including internal reference voltage generators and digital circuits, which provide excellent performance when compared with state-of-the-art pipeline converters. In addition, these specifications will be fully satisfied on all required technological corners.
Chapter 6: Experimental Results and State of the Art The prototype will be tested in the laboratory. The test procedure and the measured performance will be presented and compared with similar state-of-the-art pipeline converters in this chapter.
Chapter 7: Conclusions and Future Lines of Research The final chapter of this work draws conclusions and suggests future lines of research.
Table of Contents
1
Pipeline ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A/D Conversion: Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 A/D Conversion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 A/D Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pipeline Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Analog Building Blocks Implementation . . . . . . . . . . . . . . . . . 1.3 Current Trends in Pipeline Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 State-of-the-Art Technology in Pipeline Converters . . . . . . . .
1 1 1 2 3 7 11 11 13 15 20 25
2
Design Methodologies for Pipeline ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Top-Down Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Key Elements in a Top-Down Design Methodology . . . . . . . . . . . . . . 2.2.1 Simulator and Circuit Modelling . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Power and Area Estimators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Synthesis Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Proposed Synthesis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 29 32 32 33 33 34
3
Pipeline ADC Electrical-Level Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . 3.1 Synthesis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Snyrcos: The Behavioural Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Low Computational Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 User-Friendliness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 39 41 41 41 43 44
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3.3 Low-Level Mapping Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 One-Stage OTA Mapping Procedure . . . . . . . . . . . . . . . . . . . . 3.3.2 Two-Stage MC OTA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Optimization Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44 46 54 62
4
Behavioural Modelling of Pipeline ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Non-Idealities in SH and MDACS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Ideal Performance of the MDAC . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Capacitors Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Dynamic Limitations: Small-Signal Effects . . . . . . . . . . . . . . 4.1.4 Dynamic Limitations: Large-Signal Effects . . . . . . . . . . . . . . . 4.1.5 Switch-on Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 Thermal Noise in the MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 Jitter Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 Behavioural Model of the MDAC . . . . . . . . . . . . . . . . . . . . . . . 4.2 Non-Idealities in Sub-ADCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65 65 67 68 69 75 83 89 96 96 99
5
Case Study: Design of a 10bit@60MS Pipeline ADC . . . . . . . . . . . . . . . . 5.1 Design Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Transistor-Level Synthesis of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Redesigning for Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Electrical-Level Design: Detailed Description . . . . . . . . . . . . . . . . . . . 5.4.1 SH Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 MDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Sub-ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Clock-Phase Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Reference Voltage Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Common-Mode Voltage Generator . . . . . . . . . . . . . . . . . . . . . . 5.4.7 Reference Current Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Converter Electrical-Level Verification . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 SH Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 MDAC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Sub-ADC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.4 Reference Current Generator Layout . . . . . . . . . . . . . . . . . . . . 5.6.5 Reference Voltage Generator Layout . . . . . . . . . . . . . . . . . . . . 5.6.6 Clock-Phase Generator Layout . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.7 ADC Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 SH & MDAC Post-Layout Verification . . . . . . . . . . . . . . . . . . 5.7.2 Remaining Building Block Post-Layout Verification . . . . . . . 5.7.3 Converter Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . 5.8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105 105 105 106 109 113 116 116 122 123 131 134 145 148 149 151 152 153 155 156 156 158 158 160 161 163 165 166
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6
Experimental Results and State of the Art . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Static Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Dynamic Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171 171 171 177 177 179
7
Conclusions and Future Lines of Research . . . . . . . . . . . . . . . . . . . . . . . . 185
Appendix A: Technology Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Appendix B: Thermal Noise in SC Circuits Overview . . . . . . . . . . . . . . . . . . 193 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Chapter 1
Pipeline ADC Overview
This chapter provides a brief introduction to pipeline converters. Before describing their inner structure and basic operation principles, a designer must know the ideas underlying the analog-to-digital conversion process. For this purpose, Sect. 1.1 provides a brief overview of the fundamentals of analog-to-digital conversion. Subsequently, pipeline converters will be introduced in Sect. 1.2, emphasizing their main characteristics and describing their basic building blocks. As conclusion to the chapter, an overview of the current trends for the enhancement of pipeline converters will be provided.
1.1 A/D Conversion: Fundamentals An analog signal is continuous in time and in amplitude. As a result, it is defined for an infinite set of values which cannot be processed by a digital system. Therefore, first it must be adapted for its subsequent digital processing. In particular, an analog signal must be discretized in time and in amplitude, or in other words, sampled and quantized respectively. These two processes are graphically illustrated in Fig. 1.1, where the resulting digital signal (vq (nT s )) is defined only for a finite set of values in time and amplitude. We will explain both processes in detail in the following subsections.
1.1.1
Sampling Theory
The sampling process converts a continuous-time signal into a discrete-time signal. According to the Nyquist theorem [17], if the signal is bandlimited to a certain frequency f b , and the samples are taken at a sampling frequency f s at least two times the signal bandwidth f b , i.e.: fs ≥ 2fb
(1.1)
the signal is uniquely determined. Therefore, the analog signal could be reconstructed from these samples without loss of information. Converters in which the J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_1, © Springer Science+Business Media, LLC 2011
1
2
1 Pipeline ADC Overview v (t)
t
Sampling vs (nTs)
t
Quantization
vq (nTs)
t
Fig. 1.1 Analog-to-digital conversion process
sampling frequency employed is up to twice the signal bandwidth are known as Nyquist converters. Pipeline converters are in fact Nyquist converters.
1.1.2
Quantization
Once the analog signal has been sampled, the samples obtained must be quantized so they can be codified digitally. As a result, the amplitudes of the analog samples are discretized. Obviously, this process entails a loss of information given that the amplitude of the samples is approximated using the closest discrete value. The difference between the actual amplitude of the sample and its discrete value is known as quantization error. The distance between the discrete amplitudes defines the so-called quantization step () or Least Significant Bit (LSB). If this distance is kept constant between all discrete amplitudes, it is said that a uniform quantization is employed. Henceforth, we will assume a uniform quantization. Frequently, quantized amplitudes are codified using an N—bit binary code. Thus, the higher the number of binary bits employed, the greater the number of discrete amplitudes that can be used. Therefore, given a certain range of continuous amplitudes,
1.1 A/D Conversion: Fundamentals
3 xq (nTs)
y FS/2
111
εq
110 101 100 –FS/2 t1
t2
t3
t4
t
011 5
t6
t
t
t7 FS/2
010 001
Δ
b
–FS/2
000
εq
c t
a
FS/2
–FS/2
xs (nTs)
Fig. 1.2 3-bit uniform quantization process: a sampled input signal, b input-output quantization characteristic and c sampled and quantized signal
called input full-scale range (FS), and a certain number of binary bits N to codify them, the quantization step will be determined by the following expression: FS (1.2) 2N These concepts are graphically illustrated in Fig. 1.2 for a 3-bit quantization process. =
1.1.3 A/D Conversion Errors As shown above, however well it has been carried out, analog-to-digital conversion entails a quantization error. In general, three main error mechanisms can be distinguished in any analog-to-digital conversion depending on their nature: the quantization error, the noise error, and the static and dynamic errors. Let us consider each type of error separately. 1.1.3.1
Quantization Error
This error results from the discrepancy between the actual amplitude of the analog signal and the corresponding discrete amplitude after the quantization procedure.
4
1 Pipeline ADC Overview
Taking into account the ideal input-output characteristic of a quantization process, it is possible to determine the quantization error. For the purpose of illustration, Fig. 1.2 shows the quantization error characteristic of a 3-bit quantization process, where the input transition values which define the thresholds for changing from one output code to the next are denoted by t j . As can be inferred, the quantization error is delimited by [−/2, /2] and depends on the input signal. If the following conditions are met: a) b) c) d)
the input-output characteristic does not overload, the input-output characteristic presents a large number of levels, the quantization step is small, and the probability distribution of pair input samples is given by a smooth probability density function,
then the quantization error can be assumed to be white noise with a uniformlydistributed probability density f unction (pdf ) [18, 19]. These propositions are generally satisfied in pipeline converters, so from now on the quantization error will be assumed to be white noise. Figure 1.3 shows both an ideal input-output characteristic for a 3-bit quantization process and the quantization error. If the quantization error is assumed to be uniformly distributed, and given that it is delimited by [−/2, /2], the following definition for the quantization error can be affirmed:
1/ if −/2 < εq < /2 0 otherwise
p(εq ) =
(1.3)
y 111 110 101 100 –FS/2
t1
t2
t3
t4
t5
011
t6
t7
FS/2
x
p(εq)
010 001 Δ
a
000
c
–Δ ⁄ 2
Δ⁄2
εq
εq Δ ⁄2 FS/2 –FS/2
x –Δ ⁄ 2
b Fig. 1.3 3-bit uniform quantization process: a input-output quantization characteristic, b quantization error and c pdf
1.1 A/D Conversion: Fundamentals
5 q
which is depicted in Fig. 1.3c. Under these assumptions, the total error power (Pn ) introduced by the quantization process can be evaluated as follows: ∞ Pnq
=
/2 εq2 p(εq )dεq
=
−∞
−/2
εq2
dεq =
2 12
(1.4)
From Eq. (1.4) it can be inferred that the lower the quantization step, the lower the error power of the quantization noise. 1.1.3.2
Noise Error
The analog-to-digital conversion is carried out by electronic circuits. These circuits generate noise which disturbs the input analog signal. The degradation added to the input signal imposes a minimum signal level that the circuit is able to process with acceptable quality. In fact, noise is usually one of the most limiting factors affecting the performance of ADCs. Among the different types of noise, low-frequency noise such as flicker or burst noise will be ignored since these could be interpreted as an offset component when compared with the signal bandwidth in pipeline converters. Therefore, only wideband noise, that is, jitter and thermal noise, will be considered. Let us consider each component separately. Jitter Noise The sampling instant is generally determined by the edge of a clock signal. However, due to the imperfections of real circuits, the clock edge can vary from cycle to cycle. Therefore, an uncertainty presents itself in the sampling instant. This causes a sampling error as shown in Fig. 1.4, where the desired sampling instant is t but owing to circuit imperfections the actual sampling instant is t + t. The error can be approximated as follows: x(t) = x(t) − x(t + t) ≈ t
dx(t) dt
(1.5)
x(t)
Δx(t) t edge uncertainty clk t t + Δt
Fig. 1.4 Clock-jitter dependence on the clock edge
t
6
1 Pipeline ADC Overview
Assuming a sinusoidal input signal with amplitude A and frequency f i , this error is maximum at the zero crossing: x(t) |max
d cos (2πfi t) = t · A · = A · t · 2π fi dt t=0
(1.6)
The error depends on the frequency and amplitude of the input signal but is independent from the sampling frequency. If the clock signal instant is assumed to be a random noise normally distributed with zero mean and variance σjit2 , error power can be computed as [20]: Pnjit =
σj 2 (A · 2πfi )2 2
(1.7)
From Eq. (1.7) it can be inferred that the higher the input signal frequency and amplitude, the higher the jitter noise.
Thermal Noise This type of noise results from the random motion of electrons in a conductor. Therefore, it is present in all electronic circuits and must be evaluated correctly in order to determine the effective resolution of the converter. Furthermore, thermal noise acquires greater importance in data converters due to the sampling process. In these circuits, the noise sources normally present a wide-band spectrum and become undersampled by the converter. The circuit noise is therefore folded back several times in base band (aliasing), increasing the power noise considerably and limiting the resolution of the circuit. This error will be considered in detail in Chap. 4 for pipeline ADCs. We will denote the total thermal noise power by Pnth .
1.1.3.3
Static and Dynamic Errors
In addition to noise, the electronic circuits which carry out the analog-to-digital conversion can introduce other types of errors as a result of their imperfections. For instance, the input-output characteristic can be affected by a certain gain or offset error, which can be interpreted as static error. This is illustrated in Fig. 1.5, where the ideal converter input-output characteristic is affected by a factor gain α and an offset deviation voff . The limited dynamics of the real circuits can also cause a settling error which makes it impossible to achieve the final output value required in the time available. These kinds of effects can be interpreted as dynamic errors and can induce nonlinearities in the input-output characteristic of the converter. In general, these errors will be defined as static and dynamic errors and the power error introduced by them will be denoted as PS&D .
1.1 A/D Conversion: Fundamentals
7
Fig. 1.5 Gain and offset errors during the quantization process
y 111 110 101 Voff 100 –FS/2
t1
t2
t3
t4
011
t5
t6
t7
FS/2
x
010 001 α 000
1.1.4 A/D Characterization So far, the main error mechanisms in the analog-to-digital conversion process have been presented. One of them, the quantization error, is independent as an initial approach to the converter architecture and is inherent to the analog-to-digital conversion process. The remaining error mechanisms, i.e., noise, and static and dynamic errors, are dependent on the practical implementation of the converter. In any case, these error mechanisms degrade the resolution of the analog signal under conversion. In order to quantify this degradation, a set of performance metrics is required. In this section, we will define the main metrics of data converters. Depending on the nature of the characterization, it is possible to distinguish two main categories of metrics: those which characterize static performance and those which determine dynamic performance. Let us consider both categories separately.
1.1.4.1
Static Performance
Metrics which evaluate the static performance of the converter measure the deviations of the actual input-output characteristic with respect to the ideal characteristic. Generally, input waveforms at very low frequencies are used to remove the dynamic effects and to obtain the actual converter transitions from histograms or statistical analysis [21, 22].
INL/DNL Integral Non-Linearity (INL) is defined as the difference between the actual transitions (t˜j ) with respect to their ideal values (t j ), once the gain and offset errors have
8
1 Pipeline ADC Overview y
y Missing code INLj+1 INLj
tj+1 = tj+2
Δ DNLj+1 tj
a
tj
tj+1
tj+1 tj+2 tj+2
x
b
tj
tj
tj+1
tj+1 tj+2 tj+2
x
Fig. 1.6 a DNL/INL definitions and b missing code
been removed. It is usually normalized in terms of LSB, i.e.: INLk =
t˜j − tj
(1.8)
On the other hand, Differential Non-Linearity (DNL) is defined as the difference between the actual quantization step and its ideal value. Again, it is usually normalized in terms of LSB, that is: DNLk =
tj − tj t˜j +1 − t˜j t˜j +1 − t˜j − +1 = −1
(1.9)
Note that from the above definitions, the DNL can also be defined from the INL as follows: DNLk =
t˜j +1 − t˜j t˜j +1 − tj +1 t˜j − tj −1= − = INLj +1 − INLj
(1.10)
When measuring the performance of data converters it is interesting to detect whether any digital code is missing. This means that two transition voltages coincide, i.e., t˜j +1 = t˜j . Taking this into account and in accordance with the definition of DNL provided in Eq. (1.9), it is possible to detect a missing code when DNLk = −1. Therefore, one method that makes it possible to speedily guarantee that no missing codes are produced is to maintain the absolute value of the DNL lower than 1. An equivalent condition could be obtained from Eq. (1.10), if the absolute value of the INL is lower than 1/2. These concepts are graphically illustrated in Fig. 1.6. 1.1.4.2
Dynamic Performance
The INL and DNL metrics are not sufficient to characterize converter performance, especially for high-speed applications. The main reason for this lies in the lowfrequency input signals which are used to characterize converter performance. This
1.1 A/D Conversion: Fundamentals
9
removes the output code dependence on the input signal and, as a result, signaldependent distortion is avoided. Spectra-based analyses are frequently used to improve the characterization of the data converter, especially dynamic performance. These analyses typically use an input full-scale sinusoidal signal, and analyze the spectrum resulting from performing a Fast Fourier T ransform (FFT ) of an output bit sequence of the data converter. Figure 1.7 displays a 1024 point FFT of a 10 bit 100 MS/s ADC converting a 48 MHz input sine wave. The spectrum includes the quantization error, the thermal noise, and static and dynamic errors caused by the converter. In accordance with the relationship between the input signal power and the different error sources, several dynamic measurements can be defined. Let us summarize the most useful dynamic metrics. SNR The Signal-to-Noise Ratio (SNR) is defined as the ratio between the input signal power (Pin ) and the error power due to the noise sources (Pn ). Therefore, this error power must include both the quantization noise and the noise contributions due to jit q converter non-idealities, such as thermal or jitter noise, i.e., Pn = Pn + Pnth + Pn . In summary: Pin Pin SNR = = q (1.11) jit Pn Pn + Pnth + Pn SFDR The Spurious-Free Dynamic Range (SFDR) is defined as the ratio between the input signal power (Pin ) and the higher spurious component (Pmax ): s SFDR =
Pin Psmax
(1.12)
–50 Power/frequency (dB/Hz)
Input sine wave
–100 Noise floor
–150
–200
Fig. 1.7 Output spectrum of a 10 bit 100 MS/s ADC
0
10
20
30
Frequency (MHz)
40
50
10
1 Pipeline ADC Overview
HDk The Harmonic Distortion with respect to the k-th harmonic (HDk ) is the power ratio between the k-th harmonic (Phk ) and the fundamental input tone (Pin ), defined as: HDk =
Pin Phk
(1.13)
THD The T otal Harmonic Distortion (THD) is defined as the ratio between the distortion harmonic components and the input signal power (Pin ), i.e.: THD =
Nh
HDk
(1.14)
k=1
where N h stands for the number of harmonics to be considered. SNDR The Signal-to-Noise Distortion Ratio (SNDR) is defined as the ratio between the input signal power (Pin ) and all error power contributions, including both noise sources and distortion due to non-idealities. Therefore, this metric is one of the most representative specifications of converter performance. Pin
SNDR = q Pn
+
Pnth
+
jit Pn
+
Nh
(1.15) Phk
k=1
ENOB The Effective Number Of Bits (ENOB) provides the number of bits which would be required for an ideal converter to produce the same SNDR level as the converter being characterized. Given that in an ideal converter neither distortion nor noise are presented, the SNDR will be determined only by the quantization noise and input signal powers, i.e.: SNDR |ideal ADC =
Pin Pq
(1.16)
taking into account Eq. (1.4) and assuming a full-scale input signal amplitude, the SNDR of an ideal ADC with N bits will be given by: Pin A2 /2 3 (F S/2)2 /2 SNDR ideal ADC = = 2 (1.17) = · 22N = 2 N Pq /12 2 (F S/2 ) /12
1.2 Pipeline Fundamentals
11
By expressing Eq. (1.17) in decibels: SNDR |ideal ADC = 6.023 · N + 1.763
(1.18)
it can be inferred from Eq. (1.17) that the SNDR of a converter is increased by 6.023 dB per additional bit. Considering this definition, the ENOB of a converter can be determined from its SNDR as follows: ENOB =
1.2
SNDRdB − 1.763 6.023
(1.19)
Pipeline Fundamentals
Once the underlying ideas of the analog-to-digital conversion have been presented, the fundamentals for the converter under discussion in this book, the pipeline converter, can be described. This kind of converter provides interesting speed and power advantages when compared with other architectures. Hence, pipeline converters are one of the most attractive approaches for medium-high resolution (8–14 bits) and medium-high speed (10–200 MHz) applications. Firstly, an initial overview of the basic operation principles of a pipeline converter will be provided. Then, their basic building blocks will be shown and typical implementations described. Finally, a brief discussion about the main trends in the design of pipeline converters will be presented.
1.2.1
Operation Principle
A pipeline converter is composed of a Sampled and Hold (SH) circuit at the front, which samples the input signal, and a cascade of basic building blocks, called stages. Each stage performs a specific nj -bit coarse quantization of the sampled input and generates the difference between this sampled value and the value obtained by encoding the solved bits back to analog domain. This difference, known as residue, is amplified so the less significant bits that follow can be extracted at the next stage. Finally, the bits solved by the stages are all re-ordered and processed by the so-called Digital Correction Logic (DCL) block to obtain the N-bit output of the converter. The pipeline architecture thus described is illustrated in the block diagram in Fig. 1.8a. As illustrated in Fig. 1.8b, the inner structure of a pipeline stage typically comprises five blocks: a sub-ADC (usually a flash A/D converter) which obtains the coarse quantization bits from the input signal, a binary encoder which codes the solved bits from the sub-ADC to binary, a sub-DAC which encodes these solved bits back to analog domain, a substractor, and an SH residue amplifier with gain Gj ≤ 2nj to obtain the residue. The last three blocks are implemented in practice by a single subcircuit which is referred to as Multiplying Digital-to-Analog Converter
12
1 Pipeline ADC Overview SH
vi
Stage 1
Stage 2
n1
Stage L
...
n2
nL
DIGITAL CORRECTION LOGIC N
a j-th Stage
+ – sub ADC Coarse quantization
b
Nj
T2B
Gj Gj
sub DAC MDAC
Amplified residue generation
nj
Fig. 1.8 Pipeline converter: a basic block diagram and b detail of a single stage
(MDAC). The usual operation of a pipeline stage requires two consecutive clock phases: • In the first phase, known as sampling phase, the input signal is sampled and stored in the MDAC while the sub-ADC obtains the N j -bit thermometric code. This thermometric code is processed by the binary encoder to generate the nj -bit length output code of the stage. • In the second phase, known as the amplification phase, the MDAC obtains the residue and amplifies it with a gain Gj to be processed by the following stage. The last stage of the pipeline ADC must only provide the least significant bits of the conversion and, therefore, does not require an MDAC. It should be noted that, because of the aforementioned timing scheme, adjacent stages must operate in opposite phases and, therefore, the time elapsed since the input signal is sampled by the first MDAC until the output word is finally obtained is L + 1 half-clock cycles. Nevertheless, the output rate of the converter coincides with the clock frequency. This timing and mode of operation of a typical pipeline converter is shown in Fig. 1.9. As can be inferred from the inner structure of a pipeline converter, the required number of analog components is approximately proportional to the number of bits resolved. Therefore, this architecture is more attractive for obtaining resolutions higher than other Nyquist approaches such as flash converters [3, 23, 24]. The latter architectures increase the number of analog components exponentially along with the number of bits. Also, higher speed can be achieved when compared with oversampled
1.2 Pipeline Fundamentals
13
SH vi
vo
Stage 1
v1
Stage 2
v2
Stage 3
(n +1⁄ 2)Ts 2nTs
Sampling vi
-------
-------
-------
Holding vo
Sampling vo
-------
-------
Residue amp. v1
Sampling v1
-------
Residue amp. v2
Sampling v2
(2n+1⁄ 2)Ts 3nTs
4 half cycles required to obtain output word
nTs
Input voltage is sampled n1 bits solved from stage 1 n2 bits solved from stage 2 n3 bits solved from stage 3 t
Fig. 1.9 Timing scheme of a 3-stage pipeline converter
or algorithmic architectures [20, 25], since their operation is extended along the entire Nyquist bandwidth.
1.2.2
Redundancy
As explained above, MDACs use a gain Gj ≤ 2nj for the residue amplification, where nj is the number of solved bits of the corresponding stage. For illustration purposes, Fig. 1.10a shows the input-output characteristic of a 2-bit MDAC with residue amplification gain equal to 4 and an FS input range of V ref . Ideally, the transition voltages of the sub-ADC are −V ref /2, 0 and V ref /2 which delimit four input voltage segments, each corresponding to a given output digital code. Assuming that the output residue voltage is coded with an ideal 3-bit sub-ADC, the Analog-to-Digital (AD) conversion characteristic in Fig. 1.10b is obtained. The non-idealities of the basic building blocks can deteriorate the ideal inputoutput characteristic of the MDAC and degrade the AD conversion characteristic considerably. For instance, the offset in the comparators of the sub-ADC can cause deviations in the transition voltages. These deviations have a disastrous impact on the input-output characteristic as shown in Fig. 1.11a, as the amplified residue voltage exceeds the input range of the next stage. As a result, the sub-ADC of the next stage saturates, causing missing codes (Fig. 1.11b).
14
1 Pipeline ADC Overview Digital output
y Vref 11xxx
10xxx 4 01xxx
00 –Vref
–Vref
01 –Vref /2
10 0
00xxx
11
Vref /2
Vref
vi –V ref
–Vref /2
0
Vref /2
Vref vi
Fig. 1.10 Input-output characteristic of a: a 2-bit MDAC with gain 4 and b resulting characteristic with a 3-bit residue codification
y
Digital output
Vref 11xxx
10xxx
01xxx
00 –Vref
–Vref
01
–Vref /2
10 0
00xxx
11 Vref /2
Vref
vi –V ref
–Vref /2
0
Vref /2
Vref vi
Fig. 1.11 Input-output characteristic of a: a 2-bit MDAC with gain 4 and and deviations on transition voltages of the sub-ADCs of Vref /4, −Vref /4 and −Vref /4; and b resulting characteristic with a 3-bit residue codification
To overcome residue saturation or overranging, a residue amplification gain lower than 2nj can be used to ensure that the residue voltage does not exceed the FS input range of the next stage. This technique is known as redundancy [26]. A typical value selected for the residue amplification gain in an nj -MDAC is 2nj −1 . A unitary redundancy is said to be applied for this value. The input-output characteristic of a 2-bit MDAC with unitary redundancy is depicted in Fig. 1.12. In addition, the unitary
1.2 Pipeline Fundamentals Fig. 1.12 Input-output characteristic of a 2-bit MDAC with unitary redundancy
15 y Vref
2
00
01
10
–Vref –Vref
–Vref ⁄ 4 0 Vref ⁄ 4
Vref
vi
redundancy allows us to remove a transition voltage, simplifying the implementation of the sub-ADC. Obviously, this redundancy requires a higher number of output bits, either increasing the number of bits-per-stage or increasing the number of stages, to obtain the same final converter resolution. Despite this disadvantage, the unitary redundancy provides several advantages: • It provides enough margin to avoid the residue overranging. • It simplifies the digital correction logic hardware implementation. In fact, it can be observed that the digital output word is built by, firstly, synchronizing the solved bits-per-stage using shifters, and, secondly, overlapping the LSB of the j-stage with the MSB of the j + 1-th stage for all stages using unitary redundancy [26]. This last operation can be performed by means of adders. A basic block diagram of the procedure carried out by the DCL block is illustrated in Fig. 1.13.
1.2.3 Analog Building Blocks Implementation The basic operation principles and fundamentals of pipeline converters have been described in the previous section. A functional description of their basic building blocks was discussed. However, no relevant information about the implementation at physical level has yet been provided. The specific aim of this section is to present the better-known architectures for the basic building blocks of a pipeline converter, which are the sub-ADC, the MDAC and the SH. Note that a physical-level knowledge of the basic building blocks is crucial for the understanding of the main error mechanisms which degrade the converter performance, as will be shown in Chap. 4.
16
1 Pipeline ADC Overview Bits from 1st stage ...
Bits from 2nd stage ...
Z–1/2
Z–1/2 ... Z–1/2
Z–1/2
Z–1/2 ... Z–1/2
Z–1/2
Z–1/2 ...
Z–1/2
Z–1/2
Z–1/2 ... Z–1/2
Z–1/2
Z–1/2 ...
Z–1/2
Bits from 3rd stage ...
Z–1/2
Z–1/2 ... Z–1/2
Bits from 4th stage ...
...
... ... ... ... ... MSB
...
...
... LSB
Fig. 1.13 Digital Correction Logic to obtain the digital output word in a 4-stage pipeline converter with unitary redundancy
1.2.3.1
Sub-ADC
As mentioned in Sect. 1.2, the sub-ADC performs a low quantization of the analog input voltage. Since the number of bits to solve per stage is generally lower than 4–5 bits, flash architectures are commonly used. Such architectures usually employ a resistor ladder to obtain the transition voltages and a comparator by each transition to determine whether the analog input voltage is above or below the corresponding tap voltage. In addition to this, a thermometer-to-binary encoder is used to translate the solved bits from comparators to binary code. Note that 2nj regions between the reference voltages (V ref ,−V ref ) can be defined with nj binary bits. These 2nj regions can be delimited by 2nj − 1 transition voltages. However, one transition voltage can be removed when unitary redundancy is used. Therefore, 2nj − 2 transition voltages are required in an nj -bit sub-ADC with unitary redundancy. For illustration purposes, both a generic nj -bit and a 2-bit sub-ADC with unitary redundancy are shown in Fig. 1.14. The comparators could be implemented with a single amplifier stage [3]. However, a regenerative comparator is usually preferred when reducing the decision time. This kind of comparator is commonly built by crosscoupling a pair of inverters to form a latch which provides fast response time thanks to positive feedback. The main disadvantage of a regenerative comparator is its high sensitivity to mismatch, which translates into a high offset. In order to reduce this sensitivity, a preamplifier is usually placed before the latch. The comparator using these components, called a preamplified regenerative comparator, is illustrated in Fig. 1.15a. Further enhancement can be achieved by using input-offset cancellation techniques as shown in Fig. 1.15b. Although this architecture is relatively more complex
1.2 Pipeline Fundamentals
Comparator Bank
Resistor ladder
btT .. . btj+1
tj+1
btj
tj
.. . bt1
Ru
a
Vref bn
j
bt2
t2
. . .
bt1
t1 b2 b1
b2 b1
Ru –Vref
n
–Vref
vin Thermometer to Binary Encoder
vin
Thermometer to Binary Encoder
Vref
17
T = 2 j –2
b
Fig. 1.14 Flash architecture for implementing a: a generic nj -bit sub-ADC and b 2-bit sub-ADC using unitary redundancy Input Offset Cancellation Scheme φs tj
–
vin
+
xbtj OA
φa tj φs
btj vin latch
a
Cin –
xbtj
OA
btj
+
b Clock phases φs φa
latch
Fig. 1.15 Schematic of a: a preamplified regenerative comparator and b input-offset cancellation technique
due to the SC front-end, it introduces two additional advantages: (1) it removes the preamplifier offset contribution and (2) it capacitively decouples the input preamplifier common mode.
1.2.3.2
SH
The SH circuit carries out the sampling of the analog input signal. Conventional SH approaches are implemented using SC circuits. Three main architectures can be distinguished as shown in Fig. 1.16 [27]. For simplicity, only Single Ended (SE) configurations are depicted. In all cases, the basic operations are (1) the sampling of the input signal during one clock phase and (2) the transferring of the signal charge onto the feedback capacitor by using an opamp in feedback configuration during the
18
1 Pipeline ADC Overview CFB
vin
φs φa
φs
vin φs
Cs φs
– OTA +
CFB
Cs
vout
φs
φa
φs
φa
– OTA +
vout φs
b
a vin
φs
φa Cs φs
– OTA +
c
vout φs
Clock phases φs φa
Fig. 1.16 SC SH schematics: a Charge distribution, b Correlated Double-sampling and c Fliparound
Table 1.1 Key parameters for the SH topologies in Fig. 1.16
Topology
Gain factor
Flip-around
1
Charge distribution
Cs CFB
Correlated Double-sampling
1+
Cs CFB
Feedback factor CFB COTA + CFB CFB COTA + CFB + Cs CFB COTA + CFB + Cs
other non-overlapping clock phase. These architectures differ in the feedback and gain factor as summarized in Table 1.1†1 . The topology selection will depend on the requirements and application. For instance, flip-around topology is a good choice for high-speed applications since it provides a higher feedback factor; whereas the charge distribution or correlated double-sampling architectures are better for applications which require the input signal to be scaled. The flip-around topology is also insensitive to capacitor mismatch given its single-sampling capacitor, whereas the remaining architectures are sensitive. Regarding aperture errors, it can be observed that the flip-around and charge distribution topologies are less sensitive than the correlated double-sampling topology. The former only use a sampling SC branch, which eliminates the aperture error between different branches caused by switch imperfections and signal-dependent delays.
1
C OTA is the parasitic capacitance at the amplifier input node.
1.2 Pipeline Fundamentals
1.2.3.3
19
MDAC
The MDAC must generate and amplify the residue voltage. This operation requires the digital-to-analog conversion of the code from the sub-ADC, its substraction from the analog input signal and its amplification to cover the FS input range of the next stage. Again, SC approaches are used to implement this circuit. Depending on the digital-to-analog codification used, two categories can be distinguished: thermometer and what we will term pseudo-thermometer MDACs. Both topologies are illustrated in Fig. 1.17. For simplicity, only SE configurations are depicted. All architectures use unitary redundancy, so the residue amplification gain is reduced to 2nj −1 . As can be inferred from the schematics, the MDACs use two non-overlapping clock phases. During the first clock phase, φs , called the sampling phase, the analog input voltage is sampled by both sampling capacitors (C s ) and feedback capacitor (C FB ). During the second clock phase, φa , called the amplification phase, the sampling capacitors are connected to the reference voltages (V ref , 0, −V ref ) in accordance with the switch gate signals while the feedback capacitors establish the Operational T ransconductance Amplifier (OTA) closed-loop operation. Note that the gate signals which control the switches during the amplification phase are obtained directly from the thermometer φs
vin
φa
Vref –Vref bt1 xbt1 φs
φa
bti
bt2 xbt2 φs
Cs
φa
φs
Cs
xbti
Clock phases φs φa
CFB
φa Cs
φs
a
i = [1,…,2nj – 2]
CFB = 2Cs
T = 2nj – 2
φs
vin Vref
vout
+ –
OA φs
φa
–Vref bu1 bm1
bd1
φa
φs Cs
buk bmk bdk φs
φa
Clock phases φs φa
CFB
Cs φs
b
k = [1,…,2nj –1 – 1]
M = 2nj –1– 1
CFB = Cs
– +
OA
vout φs
Fig. 1.17 SC MDACs schematics: a thermometer and b pseudo-thermometer approaches
20
1 Pipeline ADC Overview
Table 1.2 Output voltage for the MDACs in Fig 1.17 MDAC Therm.
Pseudo-therm.
Output voltage T T Vref T Cs + CFB Cs vin − Vref Di = 2nj −1 vin − Di CFB CFB 2 i=1 i=1 M M MCs + CFB Cs b¯ k = 2nj −1 vin − Vref b¯k vin − Vref CFB CFB k=1 k=1
Code Di = bti − xbti b¯k = buk − bdk
Table 1.3 Switch gate signals for a 3-bit thermometer and pseudo-thermometer MDAC bti i ∈ [1, 6]
bdk k ∈ [1, 3]
bmk k ∈ [1, 3]
buk k ∈ [1, 3]
Di i ∈ [1, 6]
bi i ∈ [1, 3]
000000 100000 110000 111000 111100 111110 111111
111 011 011 001 001 000 000
000 100 000 010 000 001 000
000 000 100 100 110 110 111
−1 −1 −1 −1 −1 −1 +1 −1 −1 −1 −1 −1 +1 +1 −1 −1 −1 −1 +1 +1 +1 −1 −1 −1 +1 +1 +1 +1 −1 −1 +1 +1 +1 +1 +1 −1 +1 +1 +1 +1 +1 +1
−1 −1 −1 0 −1 −1 +1 −1 −1 +1 0 −1 +1 +1 −1 +1 +1 0 +1 +1 +1
bits of the sub-ADC (bt i , xbt i ) in the thermometer architecture. However, the switch gate signals in the pseudo-thermometer topology must be generated by means of a specific encoder, known as a switch encoder, as follows: buk = btj · btj +1 bmk = btj · xbtj +1 bdk = xbtj · xbtj +1
k ∈ [1, 2nj −1 − 1] j = 2k − 1
(1.20)
According to these gate signals, the final output voltage can be evaluated by applying the charge conservation principle between clock phases. This leads to the output voltages summarized in Table 1.2. Note that both MDAC architectures could be easily modified to include input-offset cancellation techniques as shown in Fig. 1.15b. For illustration purposes, the gate signals which control the amplification switches for a 3-bit MDAC are summarized in Table 1.3 both for thermometer and pseudothermometer architectures.
1.3
Current Trends in Pipeline Converters
Nowadays, there is a trend for integrating the ADCs in adverse deep sub-micron technologies with low power supplies. This makes the design of converters a major challenge since analog devices do not benefit from this technological scaling. For instance, as the supply voltage is scaled down, the voltage available for representing the signal is reduced; therefore, to maintain a specific dynamic range on a lower
1.3 Current Trends in Pipeline Converters
21
supply voltage, the thermal noise in the circuit must also be proportionately reduced. There is, however, a trade-off between noise and power consumption. In fact, this trade-off usually forces the designers to increase the power consumption of the converters. Hence, numerous techniques have been reported in the bibliography for the enhancement of pipeline converters and the reduction of the total power consumption. An overview of some of those techniques and current trends in the design of these Nyquist converters will be given here. 1) Stage Scaling-down Requirements In principle, the major design challenge is satisfied once the first stage in a pipeline converter has been designed. Thus, this first stage could be of further use when implementing the following stages. This would simplify the design of a pipeline converter considerably. However, this entails an unnecessary waste of power consumption since the requirements for the subsequent stages can be relaxed as coarse bits from the previous stages are solved. Therefore, the first technique for reducing the power consumption in a pipeline converter is to scale down the specifications of the stages according to the remaining resolution to be solved [28, 29]. In fact, most pipeline converters committed to the reduction of power consumption use this scaling-down stage technique. We have used this technique in our proposed design methodology. For illustration purposes, Fig. 1.18 plots the power consumption of the stages in the 5-stage pipeline converter prototype included in this monograph, a full description of which is provided in Chap. 5. As can be inferred, the power consumption of the stages is scaled down from the first to the last stage. 2) Opamp Sharing Technique As explained in Sect. 1.2, the MDAC operates at two non-overlapping clock phases, called sampling and amplification phases. During the sampling phase, the input voltage is sampled and the OTA is reset, whereas during the amplification phase the residue is obtained with the OTA operating in a closedloop operation. Therefore, the OTA is only really required during the amplification phase. In addition, when a given stage is sampling, the next stage is amplifying. This gives rise to the so-called opamp sharing technique [30–36]. The idea is to share the amplifier between two consecutive stages, in such a way that the same OTA is used as residue amplifier for two different stages. Thus, the OTA is always in active
Fig. 1.18 Stage scaling-down in the 5-stage pipeline converter in Chap. 5
22
1 Pipeline ADC Overview
mode and is never reset. This technique requires the addition of two more switch sets, which enable the OTA to commutate between the two stages. The advantage afforded by this is that the number of amplifiers required is halved and power consumption is significantly reduced. However, this technique has two main drawbacks. First, the additional switches introduce a series of resistances which, in combination with the amplifier input capacitance, affect the settling behaviour of the stage. Second, the non-zero input voltage of the amplifier due to the OTA finite DC gain and offset voltage is never reset. Thus, every input sample is affected by the finite-gain error component from the previous sample. This can degrade the performance of the pipeline converter. In order to overcome these problems some improvements have been proposed in the literature. In [30], a Feedback Signal Polarity Inverting (FPSI) technique was proposed, where the first residue signal is inverted during the next phase to reduce the error to 1/3 for a 2-bit MDAC with unitary redundancy. Nevertheless, the effect of the error reduction becomes less significant as the resolved number of bits-perstage increases. In [32], only the second stage in two-stage amplifiers is shared, so that the first stage can be reset. Such a partial opamp sharing scheme requires the same number of preamplifiers so it has no significant power and area advantage. In [36], the OTAs are shared between stages but are reconfigured by using dual inputs and scaling the bias currents. In this way, the non-zero input voltages can be reset. In summary, the opamp sharing technique has a high potential to reduce the power consumption of pipeline converters but some drawbacks are still to be overcome. 3) Removing the SH Circuit The main purpose of the SH circuit is to sample the input signal. However, it is possible to appreciate that both the MDAC and the sub-ADC also perform a sampling procedure. Therefore, the use of an SH circuit could be avoided [35, 37] with the MDAC and sub-ADC carrying out the sampling procedure alone. This can reduce power consumption considerably since the SH usually has a very large power dissipation and contributes substantially to the distortion and noise of the entire ADC. Nevertheless, removing the SH circuit introduces a major drawback: if a mismatch between the value sampled by the MDAC and the sub-ADC occurs, an error is induced which can drastically degrade the resolution of the whole ADC. This error, called aperture error, is more notable at high input frequencies where small discrepancies between the MDAC and sub-ADC sampling instants can induce higher discrepancies between their respective sampling values. Therefore, special care must be taken when the SH circuit is removed. In order to reduce the aperture error, a careful match between the MDAC and sub-ADC signal paths can be pursued as in [37]. Here, all input signal sampling switches are matched, using the same V gs and dimensions and controlling the RCdelay introduced by the layout parasitics. A modified sampling scheme can also be used in the first stage to avoid the matching requirement between the MDAC and sub-ADC paths as in [35]. Here, additional time between non-overlapping clock phases is generated to allow the sub-ADC to sample the value previously sampled by the MDAC during the sampling phase. Discrepancies between sampled values
1.3 Current Trends in Pipeline Converters
23
are thus removed. The drawback is that the time available for amplifying the residue is reduced and, as a result, the speed requirement for the MDAC is increased. 4) Switched-opamp Technique Analog circuits present serious limitations at low power supply voltages. For instance, the reduced voltage supply forces us to use a low input signal range and, as a result, system noise must be proportionally reduced to maintain the same dynamic range. But worse still is the fact that the functionality of some analog devices is fully degenerated at very low power supply voltages. This is the case of MOS switches which require a minimum V gs to allow the signal flow. Some techniques may be applied to overcome this problem. The first entails the use of low V T transistors as switches; however, these require special technology and may suffer leakage of the stored charge. The second is the use of bootstrapped switches [38–42] which increases the complexity and the overall on-chip capacitances. The third approach is the so-called Switched-Opamp (SO) technique [43–45] where problematic switches affected by insufficient voltage overdrive, such as the sampling switches, are removed. Obviously, this involves switching off the amplifier during the sampling phase to remove the driving capabilities over the next stage. Figure 1.19 shows an SO 2-bit MDAC with unitary redundancy [44]. As can be appreciated, all switches are connected to well-known reference voltages and do not suffer from high voltage swings. The common input and output modes of the amplifier are set to V dd and V dd /2 respectively. The SO MDAC operation is as follows: (1) during the sampling phase, the sampling capacitor (4C u ) samples the input signal provided in the previous stage, the feedback (2C u ) and reference capacitors (C u ) are reset, and the OTA outputs are in a high-impedance state and pulled to V dd by the attached switches; (2) during the amplification phase, the OTA is switched on, the preceding stage pulls its MDAC output to V ss , the reference capacitors are connected to the corresponding reference voltages and the charge is distributed to obtain the residue
Vss
Clock phases φs φs
Vref –Vref bt1 φs
xbt1 φa
Cu
bt2 φs
xbt2 2Cu
φa Cu
vi
+ –
φs
Vdd
Fig. 1.19 SO 2-bit MDAC
vo
OA
4Cu
φs
Vss
24
1 Pipeline ADC Overview
voltage. In fact, applying the charge conservation principle: 4Cu [(Vdd − Vss ) − (Vdd − vi )] + 2Cu [(Vdd − vo ) − (Vdd − Vss )] + · · · + Cu [(Vdd − b¯1 Vref ) − (Vdd − Vss )] + Cu [Vdd − b¯2 Vref ) − (Vdd − Vss )] = 0 (1.21) where b¯i = bti − xbti i = 1, 2. From Eq. (1.21), the input-output characteristic of the SO MDAC in Fig. 1.19 can be obtained as follows: vo = 2vin −
2
b¯i Vref
b¯i = bti − xbti
(1.22)
i=1
which corresponds with the ideal input-output characteristic of a conventional 2-bit MDAC with unitary redundancy. Note that the SO MDAC, as well as operating on a very low power supply, reduces power consumption since the OTA is switched off during the sampling phase. Therefore, the SO approach can be interpreted as a power consumption reduction technique. In fact, in [32] a partially SO technique is applied simply due to the benefits of the power reduction and conventional MOS switches used. In spite of the advantages of the SO technique, several drawbacks are encountered. On the one hand, the operating speed is limited due to the slow transients from the opamp being switched on and off. In addition, the SO MDACs suffer from lower feedback factors, which makes them inherently slower. For instance, the feedback factor of the 2-bit SO MDAC in Fig. 1.19 is ideally 1/4 whereas a conventional 2-bit SC MDAC provides a feedback factor of 1/2. On the other hand, fully SO converters require specific input interface circuits to get the signal into the converter due to the lack of the series switch-connecting stages. This increases the converter complexity as well as the power consumption. 5) Pseudo-differential Architectures Fully Differential (FD) amplifiers are the preferred choice for analog designers due to their improved dynamic range, better common-noise rejection, reduced harmonic distortion and increased output voltage swing against their SE counterparts. These FD architectures are based on differential pairs with tail current sources. Thanks to these tail current sources, FD architectures provide a high Common-Mode Rejection Ratio (CMRR). However, the greatest power consumption is due to these current sources. Alternatively, PseudoDifferential (PD) architectures remove these tail current sources [46]. This makes these architectures more attractive for low voltage and low power consumption applications, given that the voltage drop across the tail current source is avoided and DC current bias disappears. In fact, PD architectures have been successfully applied in the implementation of pipeline converters [47, 48]. Nevertheless, this technique presents a major drawback: removing the tail current sources results in larger common-mode
1.3 Current Trends in Pipeline Converters
25
gain giving rise to serious problems from common-mode and offset voltages of the SE paths. 6) Calibration Techniques In recent years, numerous pipeline converters using calibration techniques to correct the non-linearities of their basic building blocks have been reported [49–60]. These calibration algorithms enable a relaxation of the requirements for the basic building blocks since their non-linearities are compensated and, as a result, power consumption is reduced. In spite of this advantage, the complexity of design and additional power consumption required by the calibration circuits can limit the use of these techniques. In fact, the calibration techniques are mainly used for resolution above 12 bits where the requirements for the analog components are difficult to satisfy without the aid of an additional technique.
1.3.1
State-of-the-Art Technology in Pipeline Converters
To conclude this chapter, a detailed review of the ICs reported in the last few years will be presented. These have been characterized in terms of ENOB, sampling rate, output bits, technology, voltage supply, active area, technique used to enhance the converter performance, publication year and a common Figure Of Merit (FOM) to quantify the ‘quality’ of the IC performance: Power FOM pJ /conv = ENOB (1.23) 2 · fs This FOM gives some idea of the energy required per conversion step. Therefore, the lower the FOM, the better the converter performance. Regarding the techniques, abbreviations have been applied for simplicity. These are summarized in Table 1.4. The IC review is summarized in Table 1.5, where the reported ENOB has been obtained for the Nyquist frequency whenever possible. For the purpose of illustration, Fig. 1.20 shows the FOM versus the sampling rate for most of the ICs in Table 1.5. As can be inferred, the best FOM performance is about 0.5 pJ/conv.
Table 1.4 Abbreviations for the pipeline techniques
Abbreviation
Technique
CAL CONV
Calibration Conventional design using scaling down stage requirements Opamp sharing Other techniques Pseudo-differential Removing SH Switched-opamp
OPSH OTH PSD RSH SWO
Bits
14 10 15 8 10 10 10 8 13 10 10 12 10 10 10 10 5 10 14 8 13 14 10 15 11 10 10 8
Ref
[52] [37] [51] [61] [36] [35] [62] [63] [64] [65] [34] [66] [67] [68] [69] [70] [71] [33] [50] [32] [72] [53] [73] [54] [74] [75] [76] [77]
11.34 9.03 11.5 7.03 9.03 9.16 8.51 5.85 10.84 8.66 8.80 10.26 8.53 8.84 8.51 9.09 3.96 9.26 10.41 7.68 10 11.6 9.01 11.49 9.09 8.18 8.45 6.10
ENOB (bits)
100 50 20 10 100 30 50 100 43 205 50 75 100 60 25 30.4 600 170 40 200 180 20 20.48 50 70 125 12 240
fs (MS/s) 90 nm 0.18 μm 0.18 μm 90 nm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 90 nm 0.18 μm 0.35 μm 90 nm 0.35 μm 0.13 μm 0.35 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.25 μm 0.18 μm 0.35 μm 0.6 μm 0.18 μm 0.18 μm 90 nm 0.18 μm
Process
Table 1.5 Pipeline ICs reported in the last few years 1.2 1.8 1.8 0.5 1.8 1.8 1.8 1 1.8 1 1.8 3 1 1.5 1.2 3.3 1.8 3.3 2.8 1.8 3.3 2.8 1.5 5 1.8 1.8 1.2 1.8
Supply (V) 1 0.86 3.91 0.86 1.28 0.7 1.1 2.04 3.6 1 1.43 7.9 4.03 5.76 0.8 1.47 0.27 0.85 1.15 0.15 15 1.15 1.3 3 1.2 0.66 0.3 1.36
Area (mm2 ) 250 12 280 2.4 31 21.6 27 30 268 61 18 284 30 28.9 4.8 52 70 180 72.8 30 756 34.8 19.5 350 49 40 3.3 104
Power (mW) 0.97 0.46 4.83 1.83 0.59 1.26 1.48 5.19 3.41 0.74 0.81 3.1 0.81 1.05 0.53 3.13 7.50 1.73 1.34 0.73 4.10 0.56 1.85 2.44 1.28 1.10 0.79 6.30
FOM1 (pJ/conv) CAL RSH, OPSH, OTH CAL RSH OPSH RSH,OPSH RSH SWO CAL CONV OPSH CAL OTH OTH OTH CONV CAL OPSH CAL SWO RSH CAL CONV CAL CONV OTH SWO CONV
Technique
2009 2009 2008 2008 2008 2008 2008 2007 2007 2007 2007 2007 2007 2007 2006 2006 2006 2006 2006 2006 2006 2006 2006 2005 2005 2005 2005 2005
Year
26 1 Pipeline ADC Overview
Bits
15 10 8 12 12 8 12 10 15 14 10 12 13 10 15 10 12 10 10 10 14 14 9 12 10 8 10 10
Ref
[56] [31] [45] [55] [78] [79] [57] [58] [59] [60] [80] [81] [82] [83] [84] [85] [86] [47] [30] [87] [88] [89] [44] [90] [91] [92] [92] [29]
11.92 9.09 7.68 11.5 9.34 6.49 11.15 9.00 11.67 9.84 8.38 11.83 9.54 8.18 12 8.18 10.84 8.68 9.29 6.35 12.5 11.83 8.01 10.34 9.51 6.98 8.63 8.84
ENOB (bits)
Table 1.5 (continued)
40 30 200 80 110 220 20 80 40 30 150 50 16.38 100 20 220 75 30 80 25 10 75 14 54 40 80 14.3 20
fs (MS/s)
Supply (V) 2.5 3 1.8 2.5 1.8 2.5 3.3 1.5 2.1 3 1.8 2.5 1.3 1.8 3.3 1.2 3 2 3 1.4 5 3 1.5 2.5 3 3 1.5 3.3
Process 0.25 μm 0.25 μm 0.18 μm 0.25 μm 0.18 μm 0.25 μm 0.35 μm 0.13 μm 0.18 μm 0.18 μm 0.18 μm 0.25 μm 0.25 μm 0.18 μm 0.18 μm 0.13 μm 0.35 μm 0.3 μm 0.18 μm 0.35 μm 0.5 μm 0.35 μm 0.5 μm 0.25 μm 0.35 μm 0.5 μm 0.6 μm 1.2 μm 13.68 1.36 0.15 22.6 0.86 2.25 7.5 0.3 20 15.96 2.2 5.55 12.24 2.5 11.22 1.3 7.9 3.12 1.85 2.24 12.54 7.8 1.3 1 2.6 10.3 5.75 10.56
Area (mm2 ) 370 60 30 755 97 230 254 33 400 350 123 780 78 45 233 135 290 16 69 21 220 318 8.2 295 55 268 36 35
Power (mW) 2.39 3.66 0.73 3.25 1.36 11.67 5.58 0.81 3.07 12.72 2.46 4.27 6.39 1.55 2.84 2.12 2.11 1.30 1.38 10.28 3.8 1.16 2.27 4.22 1.89 26.47 6.36 3.81
FOM1 (pJ/conv) CAL OPSH SWO CAL OTH CONV CAL CAL CAL CAL CONV CAL CONV OTH CAL CONV CAL PSD SWO OTH CAL CONV SWO CAL CONV CAL CONV CONV
Technique
2005 2005 2005 2005 2005 2004 2004 2004 2004 2004 2004 2004 2004 2004 2004 2004 2003 2003 2003 2003 2003 2001 2001 2001 2001 2000 1999 1995
Year
1.3 Current Trends in Pipeline Converters 27
28
1 Pipeline ADC Overview 7 Calibration Opamp sharing Removing SH Switched opamp Pseudo-differential Conventional Others
6
FOM (pJ/conv)
5
4
3
2
1
0 0
50
100 150 Sampling Rate (MS/s)
Fig. 1.20 FOM versus sampling rate for the ICs in Table 1.5
200
Chapter 2
Design Methodologies for Pipeline ADCs
As explained in Chap. 1, the design of ADCs in adverse digital technologies is a major challenge for designers. This challenge becomes more significant with the scaling of technology which brings about new obstacles (leakage currents, increment of the relative variability of technological parameters, low power supplies, etc). In order to overcome this challenge, designers need to develop robust design methodologies or have access to CAD tools which will allow them to simplify the design procedure. This chapter deals with this issue. Firstly, a brief overview of a conventional top-down design methodology will be given, describing the different hierarchical levels into which the design procedure is split. This will be followed by an explanation of the tools required and needs for supporting the top-down design methodology. Finally, we will present our proposed design methodology, emphasizing the improvements with respect to the conventional ones.
2.1 Top-Down Design Methodology The design process of an ADC starts with the converter specifications (ENOB, f s , FS, etc.) and ends with the physical layout. During this design procedure, the designers must explore numerous alternatives, study several trade-offs, identify design constraints and dependences and optimize the design in terms of power consumption and silicon area. Obviously, this is a major challenge which generally requires the development of robust and systematic design methodologies. One of the most common approaches is what is known as the top-down design methodology, where the converter design is split into several abstraction levels. Thus, initially the design process is tackled from a functional point of view (top abstraction levels) and refined downwards (low abstraction levels). Accordingly, the converter specifications are translated from the top to the bottom abstraction levels. There are several advantages to this hierarchical decomposition [93]: (1) the possibility to perform system architectural exploration and better overall system optimization at a high level before starting detailed circuit implementations; (2) the fact that it allows the proper identification and understanding of the trade-offs and dependences between the different J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_2, © Springer Science+Business Media, LLC 2011
29
30
2 Design Methodologies for Pipeline ADCs
CONVERTER SPECIFICATIONS ENOB, fs, Vdd, FS... System Level
SPECIFICATIONS Stage 1
Number of stages, resolution-per-stage
...
Stage 2
n1
nL
N
ΣΔ
g1´
High-level specifications mapping
Circuit Level p1
Switches: ron,CP,…
Capacitors: Cu,...
High-level Performance evaluator
p2 bt2
CFB p1
– OTA + p1
bt1
tj
Ru
Low-level specifications mapping
Transistor Level
b1 b2
Bottom-up iterations
Cascade, single-loop, multibit,...
Ao,GBW,PM,CP,…
Pipeline
DIGITAL CORRECTION LOGIC
ΣΔ
OTAs:
Stage L
n2
Thermometer to Binary Encoder
Pipeline:
SH
W,L,vdsat,ib,...
Layout
Low-level Performance evaluator
Fig. 2.1 Top-down design methodology for ADCs
hierarchical levels and (3) the fact that the converter design is reduced to find the specifications for each hierarchical level, allowing a much less time-consuming modular design. Figure 2.1 shows a conventional top-down design methodology for ADCs. As can be inferred, the design procedure is split into four hierarchical levels†1 :
1
Note that more hierarchical levels could be considered.
2.1 Top-Down Design Methodology
31
• A system level, where architectural aspects such as the type of converter, the topology, etc. are discussed. At this level, the basic building blocks of the converter can be considered a black box and described at functional level. • A circuit level, where the basic building blocks are described in greater detail using simple and efficient models which take into account the major non-idealities of the actual circuit implementation. • A transistor level, where the basic building blocks are described up until electrical level by using complex non-linear differential equations and very accurate models. • A layout level, where the physical implementation of the transistors is considered. Obviously, the converter performance evaluation will be much more difficult the closer we get to the bottom hierarchical levels. In fact, specific simulators will be required at the different abstraction levels: (1) a high-level performance evaluator for circuit- and system-level simulations, providing low CPU times and medium accuracy, and (2) low-level performance evaluator for transistor and layout levels, requiring high CPU times but providing high accuracy. Let us explain the top-down design methodology in Fig. 2.1 in detail. The starting point is provided by the converter specifications, i.e., the ENOB, sampling rate, voltage supply, FS input range, etc. The objective is to satisfy these converter specifications with minimum power consumption and area. According to these specifications, the converter architecture (pipeline, , algorithmic, flash, SAR, . . .) must be selected. At this system level, we must also determine the converter topology, that is to say, the number of stages and resolution-per-stage for a pipeline converter, the single-loop, cascade or multibit approach for converters, etc. Once the architecture has been selected, the converter specifications must be mapped onto high-level specifications for the basic building blocks of the ADC (high-level mapping procedure), such as the switch-on resistances (r on ), the values for the capacitors (C u ), the OTA DC gain (Ao ), Gain-Bandwidth Product (GBW ), phase margin (PM), etc. These circuit-level specifications must then be translated onto physical dimensions, or in other words, onto transistor-level specifications (low-level mapping procedure). To complete the top-down design methodology, the physical layout must be carried out. Although a top-down design methodology attempts to implement a modular design in which every hierarchical level is in principle independent from the remainder, some bottom-up iterations are inevitable. This is due to the trade-offs and dependences between the specifications at different hierarchical levels. For instance, the specifications at circuit level depend on the parasitics from the layout. Hence, a top-down design methodology must be refined with several bottom-up iterations and verifications to satisfy converter specifications. This procedure can therefore take a long time. The more efficient and robust the design methodology, the less time required. Note that in this design methodology, four key elements are required: (1) procedures to map the specifications from each abstraction level to the subsequent one; (2) verification tools or simulators which allow us to guarantee that the converter specifications are being satisfied; (3) a set of models to characterize converter performance in a specific way and (4) power and area estimation models. These key elements will be discussed in the next section.
32
2.2
2 Design Methodologies for Pipeline ADCs
Key Elements in a Top-Down Design Methodology
The main components required in a top-down design methodology have already been presented. This section will examine the most common approaches for the implementation of these components, emphasizing the practical aspects which limit the feasibility of the design methodology.
2.2.1
Simulator and Circuit Modelling
As explained in Sect. 2.1, performance evaluators are required to verify whether the converter specifications are satisfied, and also a set of models which allow us to characterize the operation of the converter. Depending on the abstraction level, two main categories can be distinguished: low- and high-level simulators. 2.2.1.1
Low-Level Performance Simulator
Traditionally, SPICE[94] and Spectre[95] simulators have been the most common solutions for evaluating the performance of electronic circuits at transistor level. These simulators numerically solve a system of non-linear differential-algebraic equations which characterize the electronic circuit by using conventional numerical analysis techniques such as numerical integration or Newton-Rapshon iterations. Although these are general-purpose circuit simulators, their numeric algorithms are very slow and their required CPU time quickly increases along with the size of circuit. Therefore, they are used to evaluate the performance of the ADC in the final steps of the design procedure (low abstraction levels) and not for exploration purposes or preliminary estimations. 2.2.1.2
High-Level Performance Simulator
In order to evaluate the performance of the ADC at higher abstraction levels, where fast simulations are required for exploration purposes, more specific and faster alternatives have been developed. In particular, two main types of high-level performance simulators can be distinguished: a) Equation-based simulators [13, 96], where the converter performance is evaluated by means of simple equations which refer to fundamental limits of different topologies and contemplate trade-offs between power consumption, resolution, speed, etc. Relatively short computation times are required, although the accuracy of the results depends on these equations. Furthermore, equations are obtained through exhaustive analysis of converter topologies. These therefore are closed simulators as equations must be changed every time the topology is changed. b) Behavioural modelling-based simulators [97–99], where the basic building blocks of the converter are characterized in a more abstract mathematical way by
2.2 Key Elements in a Top-Down Design Methodology
33
their input-output behaviour. These higher-level models describe the behaviour of the circuit by means of relatively simple equations which allow a fast evaluation of the performance of the circuit. Obviously, this is achieved to the detriment of the accuracy. Nevertheless, a good speed-accuracy trade-off can be obtained if the major non-idealities of the real circuit implementation are modelled with sufficient accuracy. One of the main problems encountered when using this technique is the lack of systematic methods for the creation of behavioural models and the fact that it generally requires a huge research effort.
2.2.2
Power and Area Estimators
The objective of the design methodology is to satisfy the converter specifications with minimum power consumption and area. For this purpose, power and area estimators must be developed. Again, two categories of estimators can be distinguished according to the abstraction level: low- and high-level estimators. 2.2.2.1
Low-Level Estimators
At low abstraction levels, the circuits are described at transistor level where non-linear and complex models, such as BSIM3 models [100], are used. These models provide detailed information about the power consumption and area, so highly accurate estimations can be obtained. 2.2.2.2
High-Level Estimators
At higher abstraction levels, behavioural models or macromodels are used to describe the behaviour of the circuit at a functional level. Hence, the power and area are estimated by means of simple equations based on experienced designer knowledge. For instance, the power consumption of an amplifier is commonly estimated from the required transconductance (gm ), the transistor overdrive voltage (V dsat ) and the voltage supply (V dd ) as follows [1–5]: P = (gm vdsat ) · Vdd · ηt
(2.1)
where ηt is a scaled factor which depends on the amplifier topology. Obviously, this kind of expression provides rough estimations but is enough for exploration purposes.
2.2.3
Synthesis Procedures
Apart from a simulator, a set of models for the basic building blocks and power and area estimators, synthesis procedures for carrying out high- and low-level
34
2 Design Methodologies for Pipeline ADCs
Fig. 2.2 Basic block diagram of a simulation-based optimization procedure
Specifications
Performance evaluator
Initial design point
New design point No
Optimal?
Optimization procedure
Yes
End
specifications mapping are required in a top-down design methodology. The most flexible approach consists in using an optimization core combined with an evaluation engine as shown in Fig. 2.2 [93, 101, 102]. The aim is to satisfy the specifications required by using the evaluation engine as performance evaluator and the optimization core as a search engine for the selection of design parameters. Thus, at each iteration of the optimization procedure, the circuit performance is evaluated at a given point of the design parameter space. According to such an evaluation, a movement in the design parameter space is generated and the process is repeated again until the optimum power consumption and area values for the design parameters are found. Typical optimization algorithms are simulated annealing or genetic algorithms. They can also be combined with deterministic algorithms for fine tuning. In general, simulation-based optimization procedures are used to map both the converter specifications onto circuit-level specifications (high-level specifications mapping) and those circuit-level specifications onto transistor-level specifications (low-level specifications mapping). The difference between the high-level and lowlevel synthesis procedures lies in the performance evaluator. In high-level synthesis procedures, high-level performance simulators such as behavioural [97, 101, 102] or equation-based simulators [13, 96] are used, whereas low-level performance simulators like SPICE or Spectre are used in low-level synthesis procedures [15, 103–106].
2.3
Proposed Synthesis Procedure
In this monograph, a top-down design methodology has been developed to synthesize pipelineADCs at transistor-level. It is able to map the converter specifications directly onto transistor-level specifications by combining an accurate behavioural simulator, a simulated annealing optimization core and a set of Matlab routines for the reduction
2.3 Proposed Synthesis Procedure
35
of the design parameter space, accurate estimation of parasitics, transistor dimensions and power consumption. In order to show the advantages of the design methodology proposed, we will provide a detailed explanation of how a pipeline converter can be synthesized following a conventional top-down design methodology. The main problems encountered with this design methodology will then be discussed and our proposed solutions will be presented. As shown in Fig. 2.1, the first step in a top-down design methodology is to select the most suitable converter topology in terms of power consumption and area. Specifically, in a pipeline converter we must select the number of stages and the resolution-per-stage. Typically, this task is reserved for experienced designers who decide which is the best solution in accordance with the knowledge acquired from previous designs. Once the topology has been selected, the converter specifications must be mapped onto high-level specifications for the basic building blocks (high-level specifications mapping). A simulation-based optimization procedure is normally used for this purpose. As performance evaluator, a behavioural simulator is the most common approach as it provides fast performance evaluations and an acceptable resolution. In order to achieve this speed, the basic building blocks are described using simple models and parameters. For instance, the switches are modelled by single switch-on resistances (r on ) and the OTAs are typically described by 1-pole macromodels as shown in Fig. 2.3. Thus, the OTA behaviour is characterized by a single transconductance (gm ) with a maximum output current (io ); an output resistance (1/go ) which defines the DC gain (Ao = gm /go ) and the input (C p ) and output parasitics (C o ). However, some design parameters, such as the parasitic capacitors or currents, cannot be arbitrarily sized since they are very much dependent on the OTA topology and technology. Therefore, they must be initially estimated or related together with other design parameters. Note that this can pose serious limitations since the feasibility of the design methodology can be extremely constrained by a suitable estimation of these parameters. In any case, and in accordance with these descriptions and constraints, the synthesis procedure tries to obtain the values for the design parameters which satisfy the converter specifications with the minimum power consumption and area. At this level, power consumption and area are estimated roughly since they are usually approximated by simple equations as in Eq. (2.1). Next, these high-level specifications must be translated onto transistor level (lowlevel specifications mapping). The capacitors and the switch-on resistance values can be easily mapped onto electrical dimensions. However, the transistor-level mapping of the OTA parameters is not trivial. The design parameters obtained in the vo
+
+ vi
vo
vi
– – Fig. 2.3 OTA 1-pole macromodel
Cp
gmvi
go
Co
36
2 Design Methodologies for Pipeline ADCs
high-level mapping procedure, that is, transconductances (gm ), saturation currents (io ), DC gains (Ao ) or equivalent load capacitances (C eq ), are related to the OTA closed-loop operation. However, these design parameters are traditionally translated onto open-loop specifications[1–5], such as Gain Product Bandwidth (GBW ), Margin Phase (PM), slew-rate (SR), etc. A simulation-based synthesis procedure can subsequently be used once more to map these open-loop specifications onto transistor-level specifications. In this case, a general purpose electrical simulator like SPICE or Spectre is employed as performance evaluator. Note that the simulation of these building blocks in open-loop configurations can be carried out quickly even if electrical simulators are used, since they are normally based on DC and AC analysis. Another possibility is to design the OTA by hand. However, these synthesis procedures present a serious problem: if the final transistor-level parameters differ from those estimated during the high-level specifications mapping, converter performance can be degraded and a new redesign (or bottom-up iteration) is required. In addition, the fulfilment of the open-loop specifications does not guarantee achieving the target performance when the feedback loop around the OTAs is closed. For illustration purposes, let us assume that an OTA with specific open-loop parameters Ao , GBW, PM, SR and C eq has been synthesized. If the final transistor-level implementation of the OTA presents parasitic capacitances different to those estimated from the high-level mapping procedure, the closed-loop operation can deteriorate noticeably. This is due to the fact that the parasitic capacitances can define the feedback factor to a great extent, in turn modifying the equivalent load capacitance and, as a consequence, possibly slowing down the closed-loop operation of the OTA. Furthermore, the closed-loop operation of the OTA might even become unstable if two-stage topologies are considered. Therefore, a good estimation of the transistorlevel specifications is essential when reducing bottom-up iterations and accurately predicting the converter performance. As the final step of the conventional design methodology, the layout of the basic building blocks is carried out. Against top-down design methodologies which follow the procedure described above, we propose a novel design methodology which presents several advantages: 1) The optimum topology selection is guaranteed and does not require experienced designer knowledge since all converter topologies desired can be quickly explored and synthesized at transistor level. 2) The behavioural models developed for the basic building blocks provide high accuracy and efficiency since they take into account the major non-idealities of their actual circuit-level implementation, including both small- and large-signal effects which can cause noticeable degradation of the converter performance. Hence, our behavioural simulations show a worst-case deviation from the transistor-level simulations lower than 0.3-bit accuracy. In addition, accurate descriptions have been developed both for one- and two-stage MC OTA topologies. 3) The converter specifications are directly mapped onto transistor-level specifications by intrinsically considering the closed-loop operation of the SC circuits. Therefore, intermediate open-loop design parameters are not used. Furthermore, the mapping procedure proposed reduces the design parameter space to only three
2.3 Proposed Synthesis Procedure
37
design variables. From these design variables, the remaining parameters are optimally sized and several constraints are applied. Thus, the optimization results are found quickly. 4) Transistor-level parasitics, as well as sizes for transistors and power consumption are accurately estimated thanks to a set of Matlab routines. These routines include valuable information on the technology using look-up table techniques. 5) The bottom-up iterations are drastically reduced since the parasitics and transistorlevel parameters are well estimated from the beginning. In fact, only fine tuning is required after the post-layout parasitics are established. 6) Both high- and low-level specifications mapping are combined in a single synthesis procedure, which basically allows us to consider the dependences between the different abstraction levels and improve the synthesis results. In addition, the converter design time is drastically reduced since intermediate specifications, mapping procedures or user iterations are not required.
Chapter 3
Pipeline ADC Electrical-Level Synthesis Tool
As explained in the previous chapter, the design methodology proposed consists of three key components: a behavioural simulator to evaluate the performance of the ADC, a set of Matlab routines to map the high-level specifications onto transistorlevel specifications, and an optimization algorithm to find the most suitable solution in terms of power consumption and silicon area. The chapter will be organized as follows. Firstly, the proposed design methodology to synthesize pipeline ADCs will be presented, emphasizing the role of each component. This will then be followed by a brief description of the key components of the synthesis tool.
3.1
Synthesis Procedure
Figure 3.1 illustrates the basic flow diagram of the proposed synthesis procedure, which is part of a simulation-based synthesis methodology. It uses the high-level specifications of the converter, that is, the ENOB, sampling rate (f s ), voltage supply (vdd), etc. as a starting point. In accordance with these converter specifications, a database of feasible converter candidates is generated. If desired, the design space of topologies can be restricted by imposing, for instance, a given number of pipeline stages or a maximum number of solved bits-per-stage. Then, using an iterative procedure for each candidate, the optimization algorithm will try to find the values for certain design variables which satisfy these high-level specifications with minimum power consumption and silicon area. In our proposed methodology, the design variables have been reduced to three parameters: the unitary capacitors in the MDACs and SH (C uj ), the time constants for the OTAs (τuj )†1 and the overdrive voltage of the MOS transistors that form these amplifiers (vdsat j ). Note that there is a batch of these design variables for each pipeline stage. At each iteration, a set of Matlab routines maps the values of the design variables onto transistor-level sizes and biasing conditions, extracting the values for all 1
These will be defined later on.
J. Ruiz-Amaya et al., Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs, DOI 10.1007/978-1-4419-8846-1_3, © Springer Science+Business Media, LLC 2011
39
40
3 Pipeline ADC Electrical-Level Synthesis Tool Converter specifications ENOB, fs, Vdd, …
Candidate topologies
Initial design point Cuj, vdsatj, τuj
Transistor-level mapping 00 Performance evaluation
End
Yes
Fig. 3.7 Fig. 3.11
New design point Cuj, vdsatj, τuj
No
End? Optimization
OPTIMIZATION
Optimization summary
Fig. 3.1 Proposed simulation-based synthesis methodology
parameters required by the basic building block behavioural models. A performance evaluation of the ADC is carried out from these values. A new movement in the design variable space is carried out in accordance with this evaluation. The procedure is repeated until the optimization algorithm ends. After this, the final design is stored in a database and a new entry, which includes the most salient features of the converter (power consumption, effective resolution, etc.) is created in a summary file. This procedure is repeated for each of the candidate topologies. It is worth stressing that all the topologies are synthesized up to transistor level and, therefore, the optimum ADC architecture in terms of power consumption can be selected from the synthesized candidates. As can be inferred, the three basic components in this design procedure are the behavioural simulator, the Matlab routines and the optimization algorithm. In order to ensure an efficient and accurate synthesis procedure these basic components must meet certain requirements. This issue and a brief description of the basic components will be outlined in the following sections.
3.2 Snyrcos: The Behavioural Simulator
3.2
41
Snyrcos: The Behavioural Simulator
The behavioural simulator developed is SNYRCOS (Simulink-based Nyquist-Rate Converters Simulator). It acts as performance evaluator within the synthesis procedure. In order to carry out this function efficiently some properties must be fulfilled: • accuracy, to obtain suitable agreement with the electrical results; • flexibility, to easily compose arbitrary pipeline architectures or even other types of converters or topologies; • low computational cost, to reduce the CPU time required for evaluating the performance of the ADC; • user-friendliness, to ensure intuitive and easy-to-use operation for any designer not familiar with the tool. Note that there are strong trade-offs between these properties. For instance, high accuracy can usually be ensured at the expense of computational cost, that is, the more accurate the behavioural models, the more complex they are and therefore, the longer the CPU time required for their evaluation. In order to simplify these tradeoffs, we decided to develop the behavioural simulator using the Matlab-Simulink interface. The implementation on this interface provides numerous advantages: • it is a widely-used platform, familiar to a large number of engineers. • it has direct access to very powerful tools for signal processing and data manipulation. • it has full flexibility for the creation of new architectures. • it enables high flexibility for the extension of the block library. The next subsections will be devoted to highlighting the characteristics and properties of the behavioural simulator developed under the Matlab-Simulink interface.
3.2.1 Accuracy As shown above, the behavioural simulator is used to evaluate the performance of the pipeline ADC. An accurate estimation of this performance is therefore essential for suitable agreement with the electrical results. The accuracy of the behavioural simulator will be determined by the behavioural models developed. As will be shown in the next chapter, these behavioural models present excellent agreement with the electrical results, so accuracy is guaranteed.
3.2.2
Low Computational Cost
Special attention must be paid to the way in which the behavioural models are implemented. Matlab provides numerous mechanisms, but the complexity of the models developed and the iterative nature of the synthesis procedure force us to use a
42
3 Pipeline ADC Electrical-Level Synthesis Tool
mechanism which allows us to reduce the computational cost efficiently. For instance, modelling and simulation of Ms in the Matlab-Simulink platform were reported in [107, 108]. Although highly intuitive, the implementation of the behavioural models of each basic building block requires several sets of elementary Simulink blocks using Matlab functions. This implies longer computation time. To overcome this problem, our behavioural models have been implemented in Matlab using the so-called S-functions [109]. These functions are C-written general-purpose source files which allow us to model dynamic systems both in continuous and discrete time. The result is a notable saving in simulation time, compared to using Matlab functions or M-files to code the models. For example, the simulation over 256 clock periods of a pipeline architecture considering all non-idealities takes under 2 s†2 using the simulator proposed. If analogous models are implemented using M-files, the simulation time increases by almost two orders of magnitude. This low computational cost is comparable with that obtained using hard-coded dedicated simulators [13, 110, 111]. Let us explain the implementation procedure in the Matlab-Simulink interface by means of S-functions.
3.2.2.1
Implementation Procedure
Model implementation follows a set of steps, which are illustrated in Fig. 3.2: a) Definition of a computation model. Given a set of non-idealities of the building blocks, a computation model which allows us to calculate the output samples, including the effect of all these non-idealities, must be defined. For the purpose of illustration, Fig. 3.2a shows the basic flow diagram of the behavioural model for the MDAC, which will be detailed in the next chapter. b) Implementation of the computation model into an S-function. To do so, SIMULINK provides different S-function templates which can accommodate the C-coded computation model of both DT and CT systems. These templates are composed of several routines (or callbacks) which perform the different tasks required at each simulation stage. These tasks include: variable initialization, computation of output variables, update of state variables, etc. among others. Figure 3.2b shows some significant sections of the S-function file associated with the MDAC. c) Compilation of the S-function. This is done using the mex utility provided by MATLAB [112]. The resulting object files are dynamically linked into SIMULINK when needed. d) Incorporation of the model into the SIMULINK environment. This can be done by using the S-function block of the SIMULINK libraries [113]. Figure 3.2c illustrates this process for the MDAC. A block diagram containing the S-function block is created including the input/output pins. The dialogue box is used to specify the name of the underlying S-function. In addition, model parameters are also included in this box, which can be used to modify the parameter values. 2
In a 2.4GHz@3GB RAM Intel Core2Duo computer.
3.2 Snyrcos: The Behavioural Simulator
43 #define S_FUNCTION_NAME mdac_therm2
MDAC beh. model
static void mdlInitializeConditions(SimStruct *S) { ... /* Initialize Capacitors */ work[0]=0;
Initialize capacitances
for(i=M;i>=1;i--) { work[i]=cuj*gauss(1,stdc); work[0]=work[0]+work[i];
Compute parasitics, capacitances, feedback factors, time constants
}
} static void mdlOutputs(SimStruct *S, int_T tid) { ... /*COMPUTE THE MDAC OPERATION*/ if (phi==1) { /*Evaluate transient response */
Yes
No
Sampling?
if (ota==1)
/*1 pole model*/
{ trans_1p_samp(M,cuj,cij,cfj,bja,cpaj,claj,avnl1,avnl2,avnl3,...); } Δ Δ = νij + unif – , 2 2
νij,eq
else
/*2 poles MC model */
{ trans_2p_samp(M,cij,cfj,bja,bcj,cpaj,cl1aj,cl2aj,cijnext,avnl1,...);} } else { /*Evaluate transient response*/ Transient evolution
Transient evolution
if(ota==1) /*1 pole model */ { trans_1p_amp(M,cuj,cij,cfj,bja,cpaj,claj,avnl1,avnl2,avnl3,...); }
Stored sampled voltages
b
End
else
/*2 poles MC model /
a +
In
Bits
Σ
Res –
G
DAC MDAC
1 In1 2 In2 mdac1 From
1 Out 1 mdac_therm2 1 z S-Function
Unit Delay 1
mdac1 Goto
c
Fig. 3.2 Implementation procedure of the behavioural models into the Matlab-Simulink interface
3.2.3
Flexibility
The implementation in the Matlab-Simulink interface provides high flexibility since the behavioural models are compiled and integrated into Simulink blocks. Thus, arbitrary pipeline architectures can be built by simply interconnecting the Simulink blocks. For illustration purposes, Fig. 3.3a shows the implementation of a 3-stage pipeline architecture. In actual fact, other converter topologies related to pipeline architectures, such as time-interleaved ones, could be implemented. Figure 3.3b illustrates the implementation of a two-channel time-interleaved converter. In addition, the Matlab-Simulink interface provides endless extension possibilities. On the one hand, anyone who has become accustomed to the Matlab designer could add his or her own Simulink blocks to the pipeline library and extend the
44
3 Pipeline ADC Electrical-Level Synthesis Tool + In ADC
Sine Wave
Σ
Res –
+
G
In ADC
DAC
Σ
Res –
Mdac G
DAC
Bits Quantizer
Stage2
stage 1
ADC
Bits
Bits
SH
In
1/z
1/z I-
DAC
y
ldeal DAC
1/z
a
Overlap Bits1
ADC channel 1
d1 d2 d3
d1, d2, d3... clk
DAC
y
Ideal DAC
Mux
b
ADC Channel 2
Fig. 3.3 Building architectures in Matlab-Simulink interface: a a 3-stage pipeline architecture and b a two-channel time-interleaved converter
simulation possibilities. On the other hand, new analyses can be carried out by simply programming the post-processing routine in the user-friendly Matlab language. Finally, the behavioural simulator can be integrated with numerous toolboxes from Matlab, increasing the possibilities for analysis or optimization.
3.2.4
User-Friendliness
Implementation in the Matlab-Simulink interface provides a user-friendly environment. A Graphical User Interface (GUI) has been developed in order to complement this environment. With this interface a user can create a new architecture, post-process the simulation results or even seek help online. Figure 3.4 shows some captures of this GUI.
3.3
Low-Level Mapping Routines
A set of Matlab routines has been developed to enhance the synthesis procedure. These routines have a double purpose: • On the one hand, they must map the high-level specifications of the converter onto electrical-level specifications, in other words, onto transistor sizes and biasing
3.3 Low-Level Mapping Routines
45
Fig. 3.4 GUI of the behavioural simulator
conditions. In order to estimate these electrical-level parameters accurately, the target technology is characterized using look-up tables obtained from batches of electrical-level simulations. • On the other hand, the routines must find constraints and dependences between the electrical-parameters which allow us to reduce the design variable space, thus improving the results of the optimization procedure. First let us tackle the issue of the reduction of the design variable space. In principle, any parameter which describes the performance of the basic building blocks or components of a pipeline architecture could be identified as a design variable. However, some parameters maintain strong dependences on each other. These dependences prevent them from being freely sized. For instance, the maximum output current in a MOS differential pair depends on the required transconductance and overdrive voltage; the switch parasitic capacitances depend on the switch-on resistances required, etc. Therefore, all these dependences and constraints must be identified and the remaining degrees of freedom in the design variable space determined. For this reason, the proposed Matlab routines set these constraints and dependences simply by using three design variables as reference: the unitary capacitors, the overdrive voltages and the time constant of the OTAs. These have been conscientiously selected to efficiently reduce the design parameter space, determine dependences and define constraints and admissible ranges over the remaining parameters. An improvement in the synthesis results is thus achieved. Two procedures have
46
3 Pipeline ADC Electrical-Level Synthesis Tool
been distinguished, depending on whether one- or two-stage MC OTA topologies are used. These procedures will be widely detailed below.
3.3.1
One-Stage OTA Mapping Procedure
The first step is the identification of all parameters involved in the synthesis procedure. As explained above, any parameter which describes the behaviour of the basic building blocks in the pipeline converter could be considered a design variable. According to the basic block diagram of the pipeline stage in Fig. 1.8b, two basic building blocks can be distinguished: the sub-ADC and the MDAC†3 . Both circuits are described in our proposed behavioural models with the parameters summarized in Table 3.1, where it has been assumed that OTAs are characterized by the one-stage macromodel in Fig. 3.5. Variables σr , σc , bpc and swj are technological parameters and are therefore known. Other statistic parameters such as μoff , σoff , μhys , σhys and V offj will be initially assumed to be zero. Once the synthesis procedure is finished, maximum permissible values for these parameters will be obtained using Montecarlo Table 3.1 Parameters involved in the one-stage OTA mapping procedure Building block
Component
Parameter
sub-ADC
Resistor ladders Comparators
Unitary ladder-resistor (Ru ) and std. deviation σr Offset mean (μoff ) and std. deviation (σoff ) Hysteresis mean (μhys ) and std. deviation (σhys ) Unitary capacitor (Cf u )
MDAC
Capacitors
Unitary capacitor (Cuj ) std. deviation (σc ) and bottomplate parasitic capacitances factor (bpc ) Transconductances (gmj ), saturation currents (ioj ), DC-gain (Aoj ), offset (Vofj ) and equivalent input noise (Vnj ) input OTA OTA (CPJ ) and output (coj ) parasitic capacitances Sampling (rusj ), amplification (ruaj ), input (risj ) and output (rosj ) reset switch-on resistances and switch parasitic capacitances factor (swj )
OTAs
Switches
vij
voj
+
+ voj
ioj vij
–
OTA C pj
gmj (vij–vofj)
goj
OTA
Coj
– ioj
– Fig. 3.5 One-stage macromodel for the OTA 3
Note that the SH circuit can be easily extrapolated to an MDAC by just removing the impact of the capacitive DAC.
3.3 Low-Level Mapping Routines
47
analysis. Finally, it will also be assumed that the unitary resistor (Ru ) and capacitor (C fu ) in the sub-ADC are initially determined by electrical design considerations. Therefore, only the parameters related to the MDAC circuit are to be determined. Let us consider the pseudo-thermometer MDAC circuit in Fig. 1.17b, where the amplifier will be characterized by the single-pole network in Fig. 3.5, defined by a transconductance gmj which provides a maximum output current, ioj , an output conductance goj which determines the DC gain (Aoj = gmj /goj ), an input-referred offset voltage (V ofj ), and input/output capacitances denoted as CpjOTA and CojOTA respectively. Replacing this model in Fig. 1.17b, the equivalent circuits of Fig. 3.6a, b are obtained for the sampling (φs on) and amplification phases (φa on) respectively. In these figures, switches have been replaced by their respective switch-on resistances r usj , r uaj , r isj , r osj . C ij , i = 1, . . . , M j and C fj model the sampling and feedback capacitors respectively. r us, j + 1 , C q, j + 1 and C S, j + 1 stand respectively for the switch-on resistance, overall input capacitances of the quantizer and MDAC in the following stage. C pj and C lj stand respectively for the sum of all the capacitances at the input and output terminals of the OTA. These last capacitances can be expressed as: Cpj = CpjOTA + CpjSWC Clj = CojOTA + CojSWC vij
rusj
Cfj
rusj
C1j
(3.1)
vij rusj
...
vij
CMj
voj
vaj Cpj
risj
rosj
gmj (vaj – vofj)
goj
Clj
a
ruaj
C1j = … = CMj = Cfj = Cuj
C1j
b1j Vref ruaj
...
bMjVref
CMj
Cpj
vaj
Cfj
ruaj
voj
gmj (vaj – vofj)
goj
rus,j +1
Cq,j +1
rus,j +1
CS,j +1
Clj
b Fig. 3.6 Equivalent circuits for the MDAC in: a sampling and b amplification phases using a one-stage OTA macromodel and considering non-zero switch-on resistances
48
3 Pipeline ADC Electrical-Level Synthesis Tool
Where CpjSWC and CojSWC agglutinate the parasitics of switches and capacitors as well as any other external capacitances loading the input and output node respectively. As can be inferred, there are still plenty of parameters to be determined. However, in the proposed mapping strategy a reduced set of parameters is used to derive the remainder. These parameters selected also act as optimization variables in the synthesis procedure featured in Fig. 3.1a. These are the unitary capacitances C uj , the time constant of the OTAs τuj , and the overdrive voltages of the transistors composing these amplifiers, vdsat j . Another variable involved in the mapping process, the Least Significant Bit of the stage, LSBj , is imposed by the resolution-per-stage of the pipeline architecture to be synthesized. Based on these variables, the parameters in Fig. 3.6 should satisfy some constraints which guide the mapping algorithm to be described later. These constraints are derived below.
3.3.1.1
Mapping Constraints
Switch-on Resistances As will be explained in the next chapter, the time constants at the input and output nodes of the single-stage OTA during the sampling phase of the MDAC (Fig. 3.6a) are given to first order as: τsj ≈ rusj Cuj + risj Ceqsj τosj ≈ rosj Cij
(3.2)
where Ceqsj = Cpj +
Mj
Cij + Cfj
(3.3)
i=1
stands for the equivalent capacitive load during the sampling phase. Analogously, the time constant of the MDAC during the amplification phase (Fig. 3.6b) is approximately given by†4 : τaj ≈
Ceqaj + ruaj Cuj + rus,j +1 Cu,j +1 gmj (1 + βj εgaj )
(3.4)
where Ceqaj = Cpj +
Mj i=1
Cij +
Ctj βj
(3.5)
stands for the equivalent amplifier load, Ctj = Clj + CS,j + 1 + Cq,j + 1 is the total capacitance load at the output node, and εgaj , βj are a gain error factor and a feedback 4
The RC time constant introduced by the next sub-ADC is neglected.
3.3 Low-Level Mapping Routines
49
factor respectively, defined as: βj = Cfj
⎛ ⎝Cfj + Cpj +
Mj
⎞ Cij ⎠
(3.6)
i=1
εgaj = 1/(βj Aoj )
(3.7)
The first term in Eq. (3.4) represents the time constant of the amplifier, i.e.: τuj =
Ceqaj gmj (1 + βj εgaj )
(3.8)
which is one of the control variables in the mapping algorithm. For proper operation, the time constants τsj and τosj should be much lower than τuj and the time constant τaj should also be dominated by this term. Therefore, the switch-on resistances in Fig. 3.6 can be determined as: risj = [τuj /n − rusj Cusj ]/Ceqsj rosj = τuj /(nClj ) ruaj = τuj /(2Cuj n)
(3.9)
with a scaling factor of n 1 (a value of 5–10 is enough for most practical purposes). Additionally, it has been assumed that: rusj Cuj = rua,j −1 Cua,j −1
(3.10)
where rua,j −1 and Cua,j −1 model, respectively, the switch-on resistance during the amplification phase and the unitary capacitor of the previous j − 1-th stage, and parameters r ua, 0 and C ua, 0 correspond to the SH stage at the pipeline front-end. Therefore: rusj = (rua,j −1 Cua,j −1 )/Cuj
(3.11)
Amplifier DC Gain It can be observed that the output voltage of the MDAC when only the DC-gain error is considered is as follows: ldeal − voj ,n = voj
εga,j 1 vldeal = vldeal 1 + εga,j oj 1 + εga,j oj
(3.12)
Therefore, the error introduced due to the finite DC gain of the OTA will be determined by the difference between the real and the ideal output voltage, that is: εga,j ldeal ldeal = vldeal ≈ εga,j voj (3.13) εvoj = voj ,n − voj 1 + εga,j oj
50
3 Pipeline ADC Electrical-Level Synthesis Tool
The error voltage resulting from the finite OTA DC gain depends on the output voltage. The worst case corresponds to the maximum output voltage, which is 2V ref , so: εvmax = 2εga,j Vref oj
(3.14)
This error must be lower than half the quantization error at the output of the stage. Note that this quantization error depends on the remaining bits determining it in the cascade of stages. Thus, given an N-bit pipeline converter with a cascade of L stages resolving b1 , b2 , b3 , . . . , bL bits and assuming unitary redundancy, the remaining bits to solve at the output of the j-th stage will be: ⎧ N j = 0 (SH) ⎨ j (3.15) Bj = (bj − 1) j = 1, . . . , L − 1 ⎩N − k=1
According to this definition, the LSB at the j-th stage output can be determined as follows: LSBj =
2Vref 2B j
(3.16)
From there, the half quantization error will be: εqj =
Vref LSBj = Bj 2 2
(3.17)
From the above considerations: < εqj εvmax oj
(3.18)
Thus, taking into account Eqs. (3.7), (3.14), (3.17) and (3.18), a minimum value for the OTA DC gain is obtained: Amin oj >
2Bj +1 βj
(3.19)
Noise Requirements for the OTA The noise contribution of the amplifier (Pnoj ) must be lower than the quantization noise (Pqj ) so that its effective resolution is not noise-limited, that is: Pnoj < Pqj
(3.20)
Assuming that Bj bits must still be solved at the output of this stage, the quantization noise can be determined as follows [20]: Pqj =
LSB2j 12
(3.21)
3.3 Low-Level Mapping Routines
51
In addition, the noise contribution of the amplifier at the MDAC output can be obtained according to the following expression [114]: Pnoj = G2j BWnvn
OT Aj
Snvn
OT Aj
(3.22)
where Snvn OTAj and BWnvn OTAj stand for the amplifier noise Power Spectral Density (PSD) and noise equivalent bandwidth during the amplification phase respectively, and Gj models the amplification gain of the MDAC. According to the time constant of the amplifier τuj , the noise equivalent bandwidth can be approximated using the following expression [1, 4, 114]: BWnvn OTAj ≈ 1/(4τuj )
(3.23)
Substituting Eq. (3.23) into Eq. (3.22), a maximum value for the noise PSD of the amplifier can be extracted by establishing a relation with Eqs. (3.21) and (3.22): OTAj max LSB2j τuj vn < (3.24) Pnoj < Pqj → Sn 3G2j Ignoring flicker contributions, the equivalent input noise of a one-stage OTA can be modelled as [1]: Snvn
OTAj
≈ξ
8KT (1 + ηj ) 3gmj
(3.25)
where ηj is a topology-dependent noise factor and ξ amounts to 1 for single-ended and OTA 2 for fully-differential amplifiers. Hence, by compelling the upper limit on S vn n j , min a minimum value for the transconductance, gmj , can be derived: min =ξ gmj
8KTG2j LSB2j τuj
(1 + ηj )
(3.26)
It is worth emphasizing that Eqs. (3.19) and (3.25) simply impose minimum values for the amplifier gain and noise PSD respectively. Thus, they could be considered starting points for the optimization procedure. In practice, the powers relating to error gain and noise are additive so ultimately the optimization algorithm will determine the values required to satisfy the specifications.
3.3.1.2
Mapping Procedure
We must bear in mind that the objective of this procedure is to map the converter specifications onto the transistor-level parameters and extract the values required for the behavioural model parameters. To do so, the design parameter space has been efficiently reduced by means of a set of constraints and a meticulous selection of the design variables. From the resulting sizing of the mapping procedure, a behavioural
52
3 Pipeline ADC Electrical-Level Synthesis Tool
simulation will evaluate the ADC performance taking into account all non-linearities of the basic building blocks, while the optimization algorithm will solve the noisespeed-power trade-offs using a suitable selection of the design variables as explained in Fig. 3.1. Next, we will detail the mapping procedure. Figure 3.7 shows the basic flow diagram of the synthesis procedure. The input variables are the unitary capacitors, C uj , the time constant for the OTAs, τuj , and voltage
From Fig. 3.1
Design variables Cuj, τuj, νdsatj, LSBj
(Cpj, Clj)
Initialize parasitic capacitances
(βj, Ceqaj, Ceqsj, Ctj)
Compute feedback factor and eq. loads
Compute: - Switch resistances from Eq. (3.9),Eq. (3.11) - Minimum DC gain from Eq. (3.19) - Maximum noise PSD from Eq. (3.24)
Determine extrinsic parasitic capacitances
OTA sizing
(rusj, ruaj, risj, rosj) (Aoj)min v
SWC
(Cpj
(Cpj, Clj)
Determine new switch resistances, minimum DC gain and maximum noise PSD
No
Δ
2
(3.30)
Critically-Damped Response As will be explained in the next chapter, a critically damped response is imposed for the two-stage MC OTA. For this purpose, a new constraint must be considered over the pole systems. It can be demonstrated that the closed-loop poles for the MDAC during the amplification phase (Fig. 3.10), when switch-on resistances are neglected, are determined by the next expression: p1,2 = −αj ± iωdj
(3.31)
where αj = ξj ωnj and ωdj = ωnj 1 − ξj 2 with:
gm2j 1 (1 + εg2j ) − gm1j (1 − εg1j ) ξj = βj 2Ceqaj ωnj g g m1j m2j 2 ωnj = (1 + εgj ) Ccj Ceqaj
(3.32)
Where εgj , εg1j , and εg2j are gain-error factors defined as: εgj = 1/(βj Ao1j Ao2j ) εg1j =
1 βj Ao1j
1 + Cpj +
Mj
Cij + Ctj /βj /Ccj
(3.33)
i=1
εg2j = 1/(Ao2j βcj ) with ⎛ Ceqaj = ⎝Cpj +
Mj i=1
⎞ Cij +
Co1j Ctj ⎠ 1 + βj βcj βj
(3.34)
standing for the equivalent amplifier load. In order to achieve a critically-damped response, ωdj = 0, or in other words: ξj =
gm2j 1 (1 + εg2j ) − gm1j (1 − εg1j ) =1 βj 2Ceqaj ωnj
(3.35)
58
3 Pipeline ADC Electrical-Level Synthesis Tool
Eq. (3.35) imposes a constraint between the transconductances. In fact, Eq. (3.35) is satisfied if the transconductances ratio is: Rj =
gm2j βj (1 − εg1j ) 2βj Ceqaj (1 + εgj ) = + gm1j 1 + εg2j Ccj (1 + εg2j )2 (1 + εg2j )(1 + εg1j )Ccj × 1+ 1+ (1 + εgj )2 βj Ceqaj
(3.36)
As can be inferred, the factor Rj only depends on the capacitances and error gains. If this relation is satisfied, it can be deduced that the system poles are determined by the next expression: αj =
2gm1j (1 + εgj ) 1−ε − Rjg1j Ccj
1+εg2j βj
(3.37)
Therefore, given a certain requirement for the time constant of the amplifier, τuj , or in other words, over the system pole (αj = 1/τuj ), and assuming a critically-damped response, a specific value is required for the first-stage transconductance: 1 − εg1j 1 + εg2j Ccj αj − βj Rj (3.38) gm1j = 2(1 + εgj ) Noise Requirements for the OTA Again, the noise contribution of the amplifier (Pnoj ) must be lower than the quantization noise (Paj ). We should bear in mind the expressions for these noise powers: Pqj =
LSB2j
(3.39)
12 v
Pnoj = Gj 2 BWn n
OTA
j
Snvn
OTAj
(3.40)
Assuming a double-pole (αj ) closed-loop transfer function, i.e., a critically-damped closed-loop response, the noise equivalent bandwidth can be approximated using the following expression: BWnvn
OTAj
≈ αj /8
(3.41)
Substituing Eq. (3.41) into Eq. (3.40), a maximum value for the noise PSD of the amplifier can be extracted by relating Eqs. (3.39) and (3.40): Pnoj < Pqj → Snvn
OTAj
j max 2LSB2 < 3αj Gj 2
(3.42)
3.3 Low-Level Mapping Routines
59
Neglecting flicker noise and the contribution of the second stage, the equivalent input noise of a two-stage MC OTA can be modelled as [1]: v
Snn
OTA
j
≈
8KT (1 + ηj ) 3gm1j
(3.43)
Where ηj is a topology-dependent noise factor. Hence, by compelling the upper limit OTA min , can be derived: on S vn n j , a minimum value for the transconductance, gm1j j
min gm1j =
4KTG2 αj (1 + ηj ) LSB2j
(3.44)
Analogously, Eqs. (3.30) and (3.43) simply impose minimum values for the amplifier gain and noise PSD, respectively. Thus, they could be considered to be starting points for the optimization procedure. In practice, the powers relating to error gain and noise are additive so the optimization algorithm will ultimately determine the values required to satisfy the specifications. It is worth noticing that although mapping constraints relies on small-signal considerations, the behavioral models employed for performance evaluation and hence for guiding the optimization process, accounts for nonlinear behaviors.
3.3.2.2
Mapping Procedure
Taking into account these constraints and dependences, a complex procedure is carried out to size the pipeline stages automatically. Figure 3.11 shows the basic flow diagram of the synthesis procedure. The input variables are the unitary capacitors, C uj , the time constant for the OTAs, τuj = 1/αj , and voltage overdrive for the transistors, vdsat j , together with the required LSBj of the stages. The procedure begins by guessing initial values for the parasitic capacitances (C pj , C o1j , C lj ). From these values and taking into account that the remaining capacitors, (sampling, feedback and load capacitances) are known, the feedback factors (βj , βcj ) and equivalent capacitances (C eqsj , C eqaj , C tj ) are computed. From there, switch-on resistances (r usj , r uaj , r isj , r os1j , r os2j ), minimum DC gain (Amin oj ) and maximum noise PSD for the v
OTA
OTA (Snn j|max ) are computed according to Eqs. (3.28), (3.30) and (3.42) respectively. Once the resistance values are known, extrinsic parasitic capacitances are SWC SWC , Co2j ). Then, the OTAs are fully sized at electrical level. computed (CpjSWC , Co1j From this sizing, real values for the intrinsic parasitic capacitances can be obtained OTA OTA (CpjOTA , Co1j , Co2j ), and new values for the parasitics initially guessed are computed. From these new values, switch-on resistances, required finite DC gain, and noise PSD are computed once again. If discrepancies () are higher than a user-defined tolerance value (δ) the procedure is repeated until convergence is achieved. The OTA sizing routine is depicted in Fig. 3.12. The inputs for this procedure are the unitary capacitor (C uj ), the time constant for the OTA (τuj = 1/αj ), the voltage overdrive for the transistors (vdsat j ), the extrinsic parasitic capacitances (CpjSWC , CojSWC ),
60
3 Pipeline ADC Electrical-Level Synthesis Tool Design variables Cuj, αj, vdsatj, LSBj
From Fig. 3.1
(Cpj, Co1j, Clj)
Initialize parasitic capacitances
(βj, βcj, Ceqaj, Ceqsj, Ctj)
Compute feedback factor and eq. loads
(rusj, ruaj, risj, ros1j, ros2j)
Compute: - Switch resistances from Eq. (3.28) - Minimum DC gain from Eq. (3.30) - Maximum noise PSD from Eq. (3.42)
OTAj max
v Snn
SWC
(Cpj
Determine extrinsic parasitic capacitances
OTA sizing
min
Aoj
SWC
SWC
, Co1j , Co2j )
Fig. 3.12
(Cpj, Co1j, Clj)
Compute new parasitic capacitances
Determine new switch resistances, minimum DC gain and maximum noise PSD
No
Δ
