Advanced Production Testing of RF, SoC, and SiP Devices

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Author: Joe Kelly | Michael D. Engelhardt

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Advanced Production Testing of RF, SoC, and SiP Devices

For a complete listing of the Artech House Microwave Library, turn to the back of this book.

Advanced Production Testing of RF, SoC, and SiP Devices Joe Kelly Michael Engelhardt

artechhouse.com

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. . p. cm. — (Artech House microwave library) Includes bibliographical references and index. ISBN 1-58053-709-X (alk. paper) 1. . 2. . I. . II. Title III. Series. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library.

Cover design by Igor Valdman

ISBN 10: 1-58053-709-X ISBN 13: 978-1-58053-709-4

© 2007 ARTECH HOUSE, INC. 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

To Kathleen, who has supported me with all of this —Joe Kelly

To my two children, Franz and Katrin Engelhardt, whose curiosity and open mind help me to enjoy life —Michael Engelhardt

Contents

1

Preface

xvii

Acknowledgments

xix

Concepts of Production Testing of RF, SoC, and SiP Devices

1

1.1

Introduction

1

1.2 1.2.1 1.2.2

Test and Measurement Production Testing Characterization Testing

2 2 3

1.3 1.3.1 1.3.2

Production Test Systems Rack-and-Stack System Automated Test Equipment

3 3 4

1.4 1.4.1

The Peripherals of Production Testing The Test Floor and Test Cell

4 4

1.4.2

Handlers

5

1.4.3 1.4.4 1.4.5

Load Boards Contactors Wafer Probers

6 6 7

1.5

The Test Program

7

1.6

Calibration

8 vii

viii


1.7

Reducing Test Costs

9

1.7.1 1.7.2

Multisite Testing Outsourcing of Production Testing

9 9

1.7.3

Built-In Self-Tests

10

1.8 1.8.1

Testing RF, SoC, and SiP Devices Testing RF Low-Noise Amplifiers

10 11

1.8.2 1.8.3 1.8.4

Testing RF Power Amplifiers Transceivers Testing Receivers

11 12 14

1.8.5 1.8.6 1.8.7

Testing Transmitters Testing PLLs and VCOs Testing Modern Standards

15 15 16

1.8.8

Summary References

18 18

2

Tests and Measurements I: Fundamental RF Measurements

21

2.1

S-Parameters

21

2.1.1

Application of S-Parameters in SoC Testing

23

2.2 2.2.1

PLL Measurements Divider Measurements

24 25

2.2.2 2.2.3

VCO Gain Measurement PLL Settling Time

26 26

2.3 2.3.1

Power Measurements RF Output Power Measurement

27 28

2.3.2 2.3.3 2.3.4

Spur Measurements Harmonic Measurements Spectral Mask Measurements

29 30 31

2.4

Power-Added Efficiency References

31 33

3

Tests and Measurements II: Distortion

35

3.1

Introduction

35

3.2

Linearity

36

Contents

ix

3.3

Distortion in SoC Devices

36

3.4

Transfer Function for Semiconductor Devices

37

3.5

Harmonic Distortion

38

3.5.1

Measuring Harmonic Distortion

40

3.6 3.6.1

Intermodulation Distortion Second-Order Intermodulation Distortion

42 42

3.6.2 3.6.3 3.6.4

Third-Order Intermodulation Distortion Higher-Order Intermodulation Distortion Products Example of Harmonic and Intermodulation Distortion Products

44 46 46

3.6.5

Intermodulation Distortion Products of a ZIF Receiver

48

3.7 3.7.1

Measuring Intermodulation Distortion The Intercept Point, Graphically

48 48

3.7.2 3.7.3 3.7.4

The General Intercept Point Calculation Input- and Output-Referencing of Intercept Points Example: Calculating the IP3 of an RF LNA

49 50 52

3.8

Source Intermodulation Distortion

52

3.9

Cross Modulation

53

3.10 3.10.1

Gain Compression Conversion Compression in Frequency-Translating Devices

54 56

Minimizing the Number of Averages in Distortion Measurements

56

References

56

4

Tests and Measurements III: Noise

59

4.1 4.1.1 4.1.2 4.1.3

Introduction to Noise Power Spectral Density Types of Noise Noise Floor

59 59 61 65

4.2 4.2.1 4.2.2

Noise Figure Noise Figure Definition Cascaded Noise Figure

66 66 68

3.11

x


4.2.3

Noise Power Density

69

4.2.4 4.2.5

Noise Sources Noise Temperature and Effective Noise Temperature

69 69

4.2.6

Excess Noise Ratio

70

4.2.7 4.2.8 4.2.9

The Y-Factor Mathematically Calculating Noise Figure Measuring Noise Figure

71 72 72

4.2.10 4.2.11 4.2.12

Direct Measurement of the Noise Figure Measuring Noise Figure Using the Y-Factor Method Measuring Noise Figure Using the Cold Noise Method

73 73 77

4.2.13 4.2.14 4.2.15

Noise Figure Measurements on Frequency-Translating Devices Calculating Error in Noise Figure Measurements Equipment Error

78 79 79

4.2.16 4.2.17 4.2.18

Mismatch Error Production Test Fixturing External Interfering Signals

80 80 81

4.2.19

Averaging and Bandwidth Considerations

81

4.3 4.3.1

Phase Noise Introduction

82 82

4.3.2 4.3.3 4.3.4 4.3.5 4.3.6

Phase Noise Definition Spectral Density-Based Definition of Phase Noise Phase Jitter Thermal Effects on Phase Noise Low-Power Phase Noise Measurement

84 86 86 87 87

4.3.7 4.3.8 4.3.9

High-Power Phase Noise Measurement Trade-Offs When Making Phase Noise Measurements Making Phase Noise Measurements

87 88 88

4.3.10 4.3.11 4.3.12 4.3.13

Measuring Phase Noise with a Spectrum Analyzer Phase Noise Measurement Example Phase Noise of Fast-Switching RF Signal Sources Measuring Phase Noise Using the Delay Line Discriminator Method References Selected Bibliography

90 91 93 93 94 95

Contents

xi

5

Advances in Testing RF and SoC Devices

97

5.1

Introduction

97

5.2

System-Level Testing

98

5.3

RF Wafer Probing

99

5.4

SiP Versus SoC Architectures

99

5.5

Designers’ New Responsibilities

100

5.6

RF Built-In Self-Test (BIST)

102

5.7

Test System Architecture

103

5.8 5.8.1

Testing Wide Bandwidth Devices New Test Methodologies

104 105

5.8.2

Calibration

106

5.9

Conclusion References

106 107

6

Production Test Equipment

109

6.1

Introduction

109

6.2

Tuned RF Receivers Utilizing a Digitizer

110

6.2.1 6.2.2 6.2.3

Description of Tuned RF Receivers Utilizing a Digitizer 110 Comparison to Benchtop RF Instruments 111 Tuned RF Receiver Parameters 112

6.3

Modern IC Power Detectors

114

6.3.1 6.3.2 6.3.3

Overview of IC Power Detectors Basic IC Power Detector Circuit Operation Quantitative Comparison of IC Power Detectors

114 115 120

6.3.4

Types of Power Detectors Used in Production

120

6.4 6.4.1 6.4.2

Production Testing Using Digital Channels and PMU Digital Channel and PMU Components Using a Digital Pin as a Crystal Reference Frequency

121 122 124

6.5 6.5.1

Digitizers (ADCs) Digitizer Components

125 126

6.6 6.6.1

Arbitrary Waveform Generators Overview of Arbitrary Waveform Generator

126 126

xii


6.6.2

Creating AWG Waveform Files

128

6.7

Use of DSP in Production Test Equipment

130

6.8

Communicating with ATE Hardware

131

6.8.1 6.8.2 6.8.3

131 132

6.8.4 6.8.5

General-Purpose Interface Bus VMEbus eXtensions for Instrumentation Peripheral Component Interconnect eXtensions for Instrumentation Summary of ATE Communication Interface Standards LAN eXtensions for Instruments

133 134 134

6.9

Summary

136

References

136

7

Cost of Test

139

7.1

Introduction

139

7.2

Parameters Contributing to the COT

141

7.2.1 7.2.2 7.2.3

Shifts and Hours Per Shift Utilization Yield

141 141 141

7.2.4 7.2.5 7.2.6

Depreciation of the Test System Test Time Handler or Prober Index Time

141 142 142

7.2.7

Additional Cost Parameters

142

7.3

Basic COT Model

143

7.4 7.4.1 7.4.2

Multisite and Ping-Pong COT Models Ping-Pong Testing Multisite Testing

145 146 148

7.4.3

Additional Variables for Multisite and Ping-Pong Testing 151

7.5 7.5.1 7.5.2

COT Considerations When Using Test Houses Guaranteed Volume or Usage Availability of Testers

152 153 153

7.6

Accuracy and Guardbands

153

7.7

Summary References

156 157

Contents

xiii

8

Calibration

159

8.1 8.1.1

Overview Calibration Methods

159 161

8.2 8.2.1 8.2.2

Calibration Procedures DPS Calibration Digital Calibration

164 164 165

8.2.3 8.2.4

Analog Calibration RF Calibration References

168 169 173

9

Contactors

175

9.1

Introduction

175

9.2

Types of Contactors

177

9.2.1 9.2.2 9.2.3 9.2.4

Spring Pin Contactor Elastomer/Interposer Contactor Cantilever Contactor Short Rigid Contactor

178 178 178 179

9.2.5

Summary of Contactor Types and Their Properties

179

9.3 9.3.1

Contactor Properties Electrical Properties

180 180

9.3.2 9.3.3

Thermal Properties Mechanical Properties

188 191

9.4

Load Board Considerations

195

9.5

Handler Considerations

195

9.6

Overall Equipment Effectiveness

196

9.6.1

The Contactor and OEE

197

9.7 9.7.1

Maintenance and Inspection of Contactors Contactor Cleaning

198 198

9.8

Manual Hold-Downs

199

9.9

Cost Considerations

199

Acknowledgments References

199 200

xiv


10

Handlers

201

10.1

Introduction

201

10.2

Handler Types

202

10.2.1 10.2.2 10.2.3

Gravity-Feed Handlers Pick-and-Place Handlers Turret Handlers

202 202 203

10.2.4

Strip Test Handlers

204

10.3

Choosing a Handler Type

205

10.4 10.4.1 10.4.2

Throughput Number of Sites Index Time

207 208 209

10.5 10.5.1 10.5.2

Testing at Various Temperatures Tri-Temp and Slew Time Methods of Heating and Cooling

212 212 213

10.5.3 10.5.4

Thermal Soaking of Devices Handler Design Considerations for Thermal Testing

213 213

10.6

Contacting the Device to the Load Board

214

10.7

Handler Footprint

215

10.8

Tester Interface Plane

215

10.9 10.9.1 10.9.2

Device Input and Output Binning Loading and Unloading of Devices

215 216 218

10.10

Conversion and Changeover Kits

218

References

219

11

Load Boards

221

11.1

Introduction

221

11.2 11.2.1 11.2.2 11.2.3 11.2.4

Materials Material Properties The Test Engineer’s Role in Material Selection Layers Hybrid Load Boards

223 223 229 229 230

Contents

xv

11.3

Electrical

231

11.3.1 11.3.2

Signal Routing and Traces Grounding

231 234

11.3.3

Device Power Supplies

237

11.3.4 11.3.5 11.3.6

Components Connectors Cables

238 244 245

11.3.7

Vias

245

11.4

Mechanical Design Considerations for Load Boards

246

11.4.1 11.4.2

Keep-Out Areas Other Mechanical Design Considerations

247 247

11.5

Thermal Design Considerations for Load Boards

248

11.6 11.6.1

Load Board Verification Time Domain Reflectometry

248 248

11.7

General Debugging and Design Considerations

249

11.7.1 11.7.2 11.7.3 11.7.4

Probe Points Reference Designators Component Layout Schematic and Layout Reviews

249 249 250 250

11.7.5

Start with an Evaluation Board References

250 250

12

Wafer Probing

253

12.1

RF Wafer Probing

254

12.2

Yield of MCM Justifies Wafer Probing

254

12.3

Probe Cards

255

12.4 12.4.1 12.4.2 12.4.3

Types of Probe Cards Cantilever Needle Probes Coplanar Probes Membrane Probes

256 256 257 258

12.5 12.5.1 12.5.2

Selecting a Probe Card Frequency Range Number of Pins

258 258 259

xvi


12.5.3

Impedance Control

259

12.5.4 12.5.5

Decoupling and Current Limitations Inductance

259 260

12.6

Tester to Wafer Prober Interface

260

12.6.1 12.6.2

Soft Docking Hard Docking

260 261

12.6.3

Direct Docking

262

12.7 12.7.1

Calibration Methods for Measurements with Wafer Probing Scalar Loss Calibration

262 262

12.7.2

S-Parameter-Based Calibration

262

12.7.3

Calibration with Calibration Substrates References

263 263

Appendix A: Power and Voltage Conversions

265

Appendix B: VSWR, Return Loss, and Reflection Coefficient

271

Appendix C: RF Coaxial Cables

275

Appendix D: RF Connectors

277

Appendix E: Decimal to Hexadecimal and ASCII Conversions

283

Appendix F: Numerical Prefixes

287

About the Authors

289

Index

291

Preface This book is intended to be a follow-up to Production Testing of RF and Systemon-a-Chip Devices for Wireless Communications, by Keith Schaub and Joe Kelly (Artech House, 2004). That book was a first of its kind, covering many of the topics surrounding production radio-frequency (RF) and system-on-a-chip (SoC) testing. On publication of the book, numerous questions were received as to why more in-depth detail about some of the other less-known areas of testing, such as load boards and contactors, was not included. Frankly, these topics could be considered to be more generalized production testing items, necessary for all aspects of testing (digital, memory, and so forth). Looking into these inquiries, we realized that there were no books or complete works available that covered the advanced topics of RF and SoC testing and the peripherals associated with that testing. We agreed to take on this project together and we hope to create a source to help advance the area of production testing. To help with our endeavor, we received invaluable input from some industry-leading companies such as Verigy, Johnstech International, Delta, and Aetrium. Like the 2004 publication, this book is intended for a wide variety of audiences including SoC applications engineers, engineering managers, product engineers, and students, although other disciplines can benefit as well. Because many of the topics on peripheral testing equipment and needs overlap with many different forms of semiconductor testing, the audience also includes test engineers involved with all types of semiconductor testing. Chapter 1 is an overview of the concepts presented in the book. We designed the content of this chapter to enable a semitechnical reader to gain

xvii

xviii


knowledge about the topics that are presented in depth throughout the rest of the book. Chapters 2 through 5 present many different aspects of production measurements and also provide enough background to build the reader’s knowledge base to a level of competence to implement these tests in a production environment as well as perform them on benchtop instruments to perform correlation. Chapter 6 presents the many aspects of equipment that is used in both ATE test systems and rack and stack instrumentation. Instrumentation for all aspects of front-end RF/SoC testing is overviewed (RF receivers, digitizers, AWGs, and digital subsystems). Chapter 7 discusses the topic of test costs and how recent changes in industrial models have impacted costs. Models that discuss many factors (beyond simply test time and number of sites) are presented. Because a production measurement is only as good as the calibration of the test system hardware, Chapter 8 describes how calibration is performed on each of the pieces of hardware that make up a test system. Additional emphasis on RF measurement calibration is also presented. Considered possibly the most important piece of the production testing setup, contactors are discussed in Chapter 9. Materials for and construction of contactors are presented, and the trade-offs that need to be considered when choosing a contactor for the various different types of devices that are being tested are discussed. Chapters 10 and 12 discuss handlers and prober interfaces to the test setup. An in-depth presentation of the requirements for developing and fabricating a load board to interconnect the DUT to the test system is found in Chapter 11. Materials, components, and circuit designs are discussed and provided. Often overlooked, the cost of producing a load board can be more than one may think. There are many reasons behind this, and this chapter aims to enlighten readers so that they become more aware of how project funds are being spent. Appendixes are included to provide useful information on topics such as power and voltage conversions, descriptions of VSWR, return loss, and reflection coefficient, guides to RF coaxial cabling and connectors, and more. We look forward to any feedback from you, the reader. Enjoy.

Acknowledgments For their gracious help in bringing together the content of this book, the authors would like to thank Bert Brost of Johnstech International, Inc., Kevin Brennan of Delta, Orville Wright of Aetrium, and Lee Ritchey of Circuit Speed. We also thank Lawrence Roberts of Cree for writing Chapter 6 on production test equipment. Also, this book could not have accomplished this without the expert-quality reviews done by our coworker and friend, Linda Miquelon. The authors would also like to thank the following people for their support throughout our careers (in alphabetical order). • Agilent Technologies: Robert Bartz, Bill Cash, Bob Cianci, Ron

• • • • • • • •

Hubscher, Miklos Kara, Peggy Kelley, Doug Lash, John McLaughlin, Gene Mead, Darrin Rath, Jake Sanderson, Jason Smith, Phil Spratt, David We, Jeff Xu, and Kai Yick Conexant: Max Thornton Corad Technology: Michael Lugay and K. N. Chui DSP Group: Behrouz Halliyal Epcos: Mike Alferman, Ulrich Bauernschmitt, Stefan Freisleben, Joachim Gerster, and Wolfgang Till Intel: Udaya Natarajan, Leonid Sassoon, and Binh Truong Karsten Schefer Keithley Instruments: Mike Millhaem Maxim Semiconductor: Ted Sato

xix

xx


• Philips: Lan Ho, Tim Jones, Richard Myers, Sultan Sabuktagin, and • • • • • • •

•

Khoi Tran Qualcomm: Farzin Fallah, Osbaldo Oscala, Joerg Paulus, and Pat Sumner RF Micro Devices: Igor Emelianoff Rutgers University: Ahmed Safari and Daniel Shanefield Silicon Wave: Brian Pugh and Phong Van Pham University of Texas at Austin: Kimberly Tran U.S. Army Research Laboratory: Arthur Ballato and John Vig Verigy: Don Blair, Jeff Brenner, Scott Chesnut, Eric Chiu, Bill Clark, Greg Erdmann, Frank Goh, K. A. Goh, Troy Heistand, Thomas Herbst, Daniel Ho, Craig Kanetake, Hiroshi Kikuyama, Ginny Ko, Adrian Kwan, Edwin Lowery, H. L. Lye, Roger McAleenan, Kathleen Miller, Linda Miquelon, Steve Moore, Pam Myers, Roger Nettles, Satoshi Nomura, Laurent Ollivier, Don Ong, Ariana Salagianis, Bob Smith, Oscar Solano, Eng-Keong Tan, Tim Tan, Hubert Werkmann, Roger White, and Juergen Wolf Other: Keith Schuab and Karsten Schefer

1 Concepts of Production Testing of RF, SoC, and SiP Devices 1.1 Introduction This book present concepts surrounding production testing of radio-frequency (RF), system-on-a-chip (SoC), and system-in-a-package (SiP) devices. These devices have become the driving forces behind wireless and mobile communications for the consumer market. Because testing is the final stage before a semiconductor device becomes part of a product, an understanding of how to test these devices is necessary to reduce the overall cost of the semiconductor manufacturing process. The common theme throughout this book is RF testing. Whether testing stand-alone RF devices, receivers, transmitters, or fully integrated transceivers, a thorough understanding of the basic concepts of RF and the details of testing with RF signals is a necessity. Until the late 1980s when the pager (a basic RF receiver device) was introduced to the consumer market, the concept of production testing of RF devices was not of concern because of the low volumes and specialty markets for these devices. Since that time, however, the consumer communications market has grown tremendously and our understanding of how to make the most of production testing of the semiconductor devices used in these products has risen significantly. Add to that the fact that the cost of silicon processing has been reduced significantly, and it becomes apparent that production testing is not

1

2


only a critical part of the overall fabrication process, but is now beginning to play a major role in the overall cost of manufacturing the devices. In the early 1990s RF technology emerged in the form of cordless and wireless (cellular, mobile) phones. It was apparent that the industry was expanding, and as a result—or perhaps the cause of—the prices of semiconductor devices dropped significantly, especially when compared to the RF devices that had previously only been used for military applications [1]. It is exactly this phenomenon that mandated finding clever, low-cost methods of testing RF-containing devices. This chapter provides an overview of the concepts involved in production testing of RF, SoC, and SiP devices to enlighten the reader about what is involved in setting up and running a test cell. Each of the topics highlighted in this chapter is covered in depth in the other chapters of this book.

1.2 Test and Measurement The testing and measurement of parameters of electronic devices has been around since before the invention of the transistor. Traditionally they were performed on specialized benchtop setups (bench testing) in a laboratory environment. Testing of a device under test1 (DUT) can be performed in a number of ways. For the purpose of this discussion, testing of semiconductor devices will be grouped into two categories: production testing and characterization testing. 1.2.1

Production Testing

Production testing is a special case of test and measurement. In the context of this book, production testing of RF, SoC, and SiP devices is to be considered the act of performing numerous tests in a short amount of time on high volumes of parts. The primary objective is to have high throughput and low overhead, or low test costs, such that the production testing does not adversely impact the marketable value of the device [1]. Quality of testing and test coverage is also key to avoiding returns and avoiding false yield fallout, which causes trade-offs in the high-volume manufacturing environment. In production testing, the optimum goal is to use the shortest test possible to pass the good parts and fail the bad parts. Many stages are often used to get a device to the fully mature production test stage, with each stage having fewer and fewer tests that target the most significant areas of concern or possible failure. When a test program reaches the full production testing stage, the 1. The term unit under test (UUT) is a general production testing term that is sometimes used when discussing testing of electronic devices.


3

minimum number of tests should be used that provide a high level of confidence in the final product. 1.2.2

Characterization Testing

In contrast to production testing, during the early stages of production and preproduction runs, the test program is often conservatively written, so that the part is overtested (redundant test coverage). This is attributed to the number of people who are involved in the development of the device, where each has a specified set of tests to run to satisfy their individual criteria. This methodology may initially give important feedback to the design engineers and help them build their confidence in the device, but as the test program matures (usually over a period of many weeks), tests are removed or test methodologies are changed, such that the final production test program may not resemble the initial test plan [1]. A large number of tests are used in a test program for other reasons also. In the early stages of the product life cycle, the design, product, and manufacturing engineers of the DUT seek awareness of potential production flaws and tolerances. This is best achieved by feeding back excessive quantities of information from the tests. Even as the product matures, and the test list is reduced, a test program may include provisions to periodically run extensive tests on a full lot or just every nth part [1]. Also during the design validation phase, characterization might require validation at certain specification limits such as operating at the power supply’s lower and upper levels; usually, however, production worst-case parameters can be chosen to limit the production test time.

1.3 Production Test Systems On a laboratory bench, equipment is placed in a random fashion and wires are bundled in every manner in an effort to facilitate many different types of testing procedures. In contrast, production test systems, or testers, are an attempt to group numerous instruments into one locale, providing easy access through a common interface (the load board). These instruments are often optimized to work together and usually controlled by a computer or some form of common processor. The two types of test systems are rack-and-stack systems and automated test equipment (ATE). 1.3.1

Rack-and-Stack System

Similar to the laboratory configuration mentioned earlier is the rack-and-stack tester. This is a suitable configuration for a production tester during the characterization and prototype stages of a device because the equipment that is

4


contained in the rack can be quickly reconfigured to meet changing needs. Rack-and-stack configurations are often custom to a specific part. This is an advantage and a disadvantage. The custom tailoring is advantageous in that it can enable the fastest possible test times and makes it easy to add a new instrument. It can also be a disadvantage, however, in that it reduces the flexibility of the architecture. Often, the tester has to be significantly rebuilt before another product can be tested. The computer programs that run the hardware can also be somewhat difficult because there may be interfacing to the equipment via various buses or protocols [1]. 1.3.2

Automated Test Equipment

ATE is a tester that is designed as a complete stand-alone solution for optimal production testing of devices. This is the primary advantage of ATE. Many of the larger test equipment manufacturers produce ATE systems. Optimally designed systems are flexible and, with respect to RF and SoC devices, can also test a multitude of parts. The manufacturers of ATE consider market factors when designing testers of this type. They focus on usability and flexibility in architecture, and ease of programming for the user. A fundamental discriminating factor between ATE and rack-and-stack systems is that ATE often has card-based instruments. This eliminates the displays common to boxed instruments because, ideally, all interfacing is controlled through a common processor. By eliminating the instrument displays, the instruments can be more densely situated and optimally designed to eliminate the signal losses commonly associated with RF instrumentation.

1.4 The Peripherals of Production Testing Once the test equipment is chosen, an efficient means to route the signals from the test equipment to the DUT must be determined. In this endeavor, many pieces fit into this puzzle, such as the test floors and cells, handlers, load boards, contactors, wafer probers, and so forth. The following sections describe these key items. 1.4.1

The Test Floor and Test Cell

The test floor is where all of the production testing takes place. The test floor is usually a cleanroom or near-cleanroom environment, free of dirt as well as electrical noise and where electrostatic discharge (ESD) precautionary measures are taken to avoid prematurely damaging potentially good devices. The term test cell refers to the area surrounding a test system, along with the peripheral equipment. At a minimum, an ideal test cell consists of the test


5

system, a handler or wafer prober, an ESD-safe table for organizing tested and untested lots of devices, and provisions for air and vacuum (for running the handler or wafer prober). Additionally, if low-noise measurements are being performed, an electromagnetically shielding enclosure, or screen room, may be needed [1].

1.4.2

Handlers

When production testing of any packaged semiconductor device is performed, one of the major capital investments is the handler. The handler is a robotic tool for placing the DUT into position to be tested [personal communication with Kevin Brennan, director of marketing, Delta Design, 2006]. It communicates with the tester and provides the temperature stimulus and the means to handle the DUT while it is being tested. To demonstrate the significance of the handler, consider that in 2006 a test system could cost up to a few million dollars. Although the test handler may cost less than 10% of this amount, it is the handler that determines how much the tester will be used. Expressed differently, if a handler could offer twice the productivity, then only half the number of multimillion-dollar testers would be needed [2]. While the handler communicates with the tester, it also provides signals to inform the tester when the DUT is ready for test and receives binning information from the tester after the DUT is tested. The communication between handler and tester is controlled by specific software. After the test is performed, the handler then places the DUT into an appropriately selected pass bin or fail bin. Modern test systems offer enhanced and plentiful resources to enable multisite, parallel, and concurrent testing. Modern handlers have to follow in their footsteps to be able to handle these architectures. Otherwise, the multisite-capable tester is useless. The two major handler types are gravity-feed and pick-and-place handlers. Gravity-feed handlers work best for packages that are mechanically robust and can withstand friction on a sliding surface. A gravity-feed handler usually feeds the DUTs into a slider via transportation tubes. When the DUT gets to the slider, it slides down to the load board by means of gravitational force. Because smaller, lighter packages pose a problem with friction, some handlers integrate air blowers into the channel along the gravity slider to assist in acceleration of the DUT onto the load board [1]. Pick-and-place handlers can work with almost all types of packages. Typically using suction, this handler moves the DUT from a transportation tray to the load board contactor. The precision movement in these handlers is controlled through stepper motors. Pick-and-place handlers often employ numerous vacuum solenoids, rather than electrically controlled switches, which

6


minimizes the introduction of electrical noise to the production testing environment [1]. 1.4.3

Load Boards

A load board is defined as a printed circuit board assembly that is used to route all of the tester resources to a central point, allowing the tester to drive and receive signals from the DUT. This assembly may also be referred to as a DUT interface board (DIB). The load board is independent of the tester and is almost always unique to each DUT that is tested due to factors such as required external circuitry or pin count and pin location. One of the most time-consuming elements of developing a full production test solution is the design and fabrication of the load board. The DC power supply, digital control, mixed signal, and RF signal lines must all coexist and be routed among each other on a common board. This inevitably requires a multilayered load board to be fabricated. The process of creating a load board involves design, layout, fabrication, assembly and test, and possibly multiple iterations of each step. The load board fabrication process is very similar to the fabrication of the actual DUT, although not as complicated, and ample time for this effort should be included in the project schedule [1]. Many companies provide load board services that range from consulting to full turnkey delivery of load boards. Depending on your budget, it is often a wise investment to engage these companies, because you will benefit from their experiences with circuit design and the interfaces among the numerous test systems and peripherals. 1.4.4

Contactors

Contactors are the link between the DUT and the rest of the test system. Physically, they sit atop the load board. The load board routes signals to and from the test system, so the contactor can be considered an extension of the load board, routing signals between the load board and DUT. They perform the important task of providing a test site for the device in order for the critical performance characteristics of the device to be transferred to the test system. This information, ultimately, determines whether the device passes or fails. In addition, depending on the capabilities of the contactor, it may help determine “how good” the device is. Because of its nature as an interconnect, the test contactor as it relates to the system interface is frequently one of the key areas to consider for improvement. There are various types of contactor technologies, corresponding to the style of package to be tested. Contactors are mechanical and therefore exercised with each DUT that is placed onto the load board and have a limited lifetime. A


7

contactor is usually a removable assembly that is mounted on the load board. When selecting a contactor it is important to make sure that the contactor is easy and fast to replace, because it will need to be replaced frequently on the production test floor [1]. For engineering and characterization purposes, a contactor with a clamp, or hold-down, on it is desirable so that a test engineer can manually place a DUT onto the load board. This is critical during load board debugging because impedance matching can be performed on the load board without having to work around the handler [1].

1.4.5

Wafer Probers

Another method of interfacing to the DUT is via wafer probing equipment. Wafer probing ensures that the chip manufacturer avoids incurring the significant expense of assembling and packaging chips that do not meet specification by identifying flaws early in the manufacturing process [1]. In the area of RF testing, traditionally, wafer probing has been avoided at the production testing stage if at all possible. Early designs of wafer probes and wafer probe interfaces were unable to handle the parasitic capacitances and inductances seen at RF frequencies. Noise pickup was an additional problem. However, with the increasing costs of more complex packages, the advent of the SiP, and the sale of known-good die (KGD), it has become clear that probing is becoming more necessary. Furthermore, because various functioning die are incorporated into the final package, in a worst-case scenario, a low-yield inexpensive die could jeopardize the entire package, making more expensive die in the package (plus the package) useless. This need has driven the advancement of RF wafer probing technology. In the early 1990s, only production microwave and high-speed integrated circuits (ICs) for expensive modules or packages were being fully RF probed before assembly. By the late 1990s, consumer devices for wireless communications began to be wafer probed routinely [3].

1.5 The Test Program A test program (also called a test plan or test flow) is a computer program that tells the test system how to configure its hardware to make the needed measurements. This program can be developed in many ways, ranging from low-level C/C++ code to a graphical interface for ease of use. Within this program, instructions to the hardware and information, such as how to determine if the DUT has passed or failed the test (known as limits), are provided [1].

8


The sequence of tests is arbitrary and normally goes back to the each particular company’s device test philosophy. For instance, most companies conduct all of the dc tests at the beginning of the test flow. Some companies, however, want to do all of the dc testing at the end because it is believed that when the device was stressed during previous ac tests, the later dc tests might show failures due to device damage as a consequence of those previous tests [1]. Another possibility that is seen frequently is to arrange the tests in such a sequence that those tests with the highest failure rates are conducted at the beginning of the test flow. This method results in shorter test times if the test program is developed so that the test flow execution is stopped at the first failure. This methodology has the most benefit for low yielding devices.

1.6 Calibration All measurements that are performed on any kind of equipment have errors due to inaccuracies in the measurement technique as well as the equipment itself. The purpose of calibration is to reduce (or in theory eliminate) the measurement error that is related to the measurement equipment. Two kinds of errors contribute to measurement errors: random errors and systemic errors. Random errors can only be characterized with probabilities and by means of statistics. A good example is the contribution of thermal noise. Unless the measurement is executed at absolute zero (0 kelvin), the measurement will always include a contribution from thermal noise. Repeating the same measurement over and over will yield very similar results, plus or minus the random contribution of the noise. Obviously, random errors cannot be calibrated out due to the fact that they are random. The test engineer, however, will have to consider the effects of random error when he or she evaluates the results of a measurement. The other type of error in a measurement is a systemic error. Systemic errors can be corrected because it is possible to characterize the exact amount of their contribution to a measurement. For instance, when an RF measurement is performed, the loss between the test head and the digitizer is always the same for one specific frequency and therefore can be calculated out of the measurement result. Numerous papers and books have been written describing the multitude of methods used to calibrate for RF power measurements [4–6]. Another (but not always necessary) type of calibration is termed de-embedding. Although used mostly for wafer probing, it can also be performed for packaged part testing. De-embedding calibration requires the use of additional “standards” that are replicas of the device (wafer probing) or package (package testing). There are at least four standards consisting of a short, open, 50-Ω load,


9

and through connections. With RF probing, it becomes necessary to perform this additional calibration to compensate for every component all the way to the probe tip. These standards can be readily produced though a combination of the device designer’s knowledge of the device and the help of probe card models supplied by the probe card manufacturer. In contrast, for packaged devices, special standards must be designed and fabricated in the “package type” that is used for the device. This is a custom and expensive operation that is not highly utilized for a final production solution because it adds another process step, which increases the already high cost of testing. Most ATE testers provide the ability to perform de-embedding calibration of both die and packaged parts [1]. Finally, ATE and rack-and-stack testers should be subject to an overall calibration. This is usually performed with a frequency that is based on the ATE’s manufacturing process and experience. Also, whenever periodic maintenance or replacement of any tester hardware occurs, it should be followed by calibration. With RF frequencies, the mistake of forgetting to torque a connector properly can make accurate assessment of DUT performance impossible [1].

1.7 Reducing Test Costs Reducing the costs involved with testing is often considered to be the most important factor with production testing. The acronym COT, meaning cost of test, is widely heard among individuals in the semiconductor industry ranging from test engineers all the way up to CEOs. It is clear that it is a very important topic. Many factors impact COT and they are addressed in Chapter 7. A few key items that impact COT are presented in the following sections. 1.7.1

Multisite Testing

An easy way to reduce COT (i.e., increase throughput using the same number of test systems) is to perform multisite testing. In this case, multiple contactors are used on the load board to allow, at best, full parallel testing of multiple DUTs. Oftentimes, complete parallel testing is not possible, but rather a percentage of full parallelism is obtained due to tester hardware limitations or DUT operation. Regardless, it is worth exploring the possibilities of multisite testing as a means to possibly reduce COT. 1.7.2

Outsourcing of Production Testing

Traditionally called test houses, facilities that own a large variety of test systems and peripheral test equipment offer a pay-per-use business model allowing individual semiconductor manufacturers to reduce capital expenditures on test equipment, real estate, and support personnel. The products and services offered

10


by these facilities have expanded significantly during the past few years. These companies now offer everything from assembly of SiPs in packages, to custom packages (as well as, of course, testing). In extreme cases, some facilities even offer complete services from semiconductor manufacturing all the way to production testing of packaged parts. This allows a company to thrive solely on the intellectual property (IP) of its chip design. In addition to reducing capital costs for a semiconductor manufacturer, the use of outsourcing allows a very simple COT calculation for the manufacturer where the personnel responsible for operating and maintaining the test systems are absorbed into the hourly rate of the test facility. With this, a good portion of COT is simply an hourly rate. Chapter 7 also discusses this in detail. It is important to note that there are some liabilities associated with outsourcing your testing program. Although the test facilities have personnel that are capable of test program development, it is still necessary to have at least some expertise inside a company that can establish contract specifications that make sense, ask appropriate questions, monitor progress, and work as a partner with the test house to overcome problems [1].

1.7.3

Built-In Self-Tests

While built-in self-tests (BISTs) have been used for many years in digital circuit design and testing, it is in its infancy when applied to RF circuits. The focus of BIST is on transistor-level defects, a level of granularity not traditionally observed by RF test engineers. Through its use, test costs can be reduced by reducing the externally applied signals (requiring less external hardware). This can allow for tremendous possible testing opportunities in multisite testing. BIST can also reduce the quantity of tests that are needed. For example, currently, in an SoC transceiver, digital signals of the device are monitored and analyzed to determine whether the device is in the transmitting or receiving state. A BIST designed into the device could potentially indicate status and eliminate the need for tests such as “turn-on time” or “lock time” [1].

1.8 Testing RF, SoC, and SiP Devices The focus of testing in this book is on RF, SoC, and SiP devices, which make up the front-end transceiver architecture used in the modern communications equipment that is overtaking the market in volume. This includes the signals from the antenna to the analog baseband portion of the chip, and the pertinent tests needed to characterize these in a production environment. In the subsequent sections, the front end will be broken into sections that are still tested as


11

DUTs, although they may even be in a package with other portions. Chapters 2 through 5 discuss the details of these measurements. 1.8.1

Testing RF Low-Noise Amplifiers

The RF low-noise amplifier (LNA) is an RF-to-RF device, meaning that it has an RF input and an RF output. The LNA is the first active component in the receiver chain, and it has a few critical parameters that can determine how the overall receiver chain will perform. The low-noise amplifier is often the most critical device in the receiver chain of a wireless device. The LNA must amplify the extremely weak signals received by the antenna with large amounts of gain, while simultaneously minimizing the amount of added noise. Because it is the first device that is “seen” by the incoming signal, it is critical that its additive noise be extremely low (see the Friis equation in Chapter 4). The noise figure of an LNA is likely the most significant measure of how well a receiver will work. Thus the noise figure (NF) of the LNA is often tested in production. From a design point of view, the difficult task is to provide high gain while minimizing the introduction of noise. These two items are mutually exclusive. The most common tests performed on an LNA are gain, VSWR, thirdorder intercept point (IP3), and NF (see Chapters 2 through 4). Gain is important because it determines the amount of amplification the LNA will perform on the incoming, often low-level, signal. VSWR gives an indication of the amount of reflection that occurs at the input of the LNA. Reflected signals at the input of the LNA do one of two things, both of which are undesirable: 1. Reflect some of the incoming signal back into the duplexer where it can leak into the transmitted signal; 2. Reflect some of the incoming signal, reducing the expected signal strength. 1.8.2

Testing RF Power Amplifiers

The RF power amplifier (PA) is required at the output of the transmitter chain and, until recently, was the one device that remained a stand-alone discrete device. Now, due to advances in materials and design as well as many low-power applications, the PA is being integrated more frequently. PAs are used at the output of a transmitter to boost the signal level so that it can reach its final destination, which may be far away. Testing of PAs is necessary to ensure that the signal levels are not too large and are able to be controlled. Common tests on a PA are gain, carrier and image suppression, and sometimes gain flatness, over frequency as well as power level. A PA sometimes has the ability to adjust the gain directly or through the use of a

12


variable attenuator at its output. The most important test to be done on a PA is the adjacent channel leakage ratio (ACLR) test. Historically, this was also referred to as the adjacent channel power ratio. This test is important to ensure that the signal does not leak into the adjacent channel to its intended channel. This is required by the Federal Communications Commission and many other regulating agencies around the world. 1.8.3

Transceivers

A transceiver is a device that transmits and receives. Many current SoCs and SiPs are actually simply front-end transceivers. They may also be simply either only the receiver or only the transmitter. In any case, specific types of tests are performed on them. Furthermore, whether the final application of these devices is as a mobile phone or a wireless LAN device, the tests are fundamentally the same. Transceiver architectures are almost always either of the superheterodyne or the zero-IF type. Because they are frequency-translating devices, performing either upconversion or downconversion on input signals, the testing methodologies differ from those of traditional RF-to-RF devices such as LNAs. 1.8.3.1 The Superheterodyne Architecture

The superheterodyne transceiver is considered the classic radio architecture in which the received signal is downconverted to baseband frequency in two stages. The incoming RF signal is first downconverted to an intermediate frequency (IF). This allows image suppression and channel selection by filtering out any unwanted signals. The filtering is commonly accomplished by use of surface acoustical wave (SAW) or ceramic filters. The filtered IF signal is then further downconverted to the baseband frequency, which is then digitized and demodulated in a DSP. Because the radio has two stages of downconversion, it is generally more complex and more expensive due to the extra components such as discrete SAW filters and voltage-controlled oscillator (VCO)/synthesizers. Figure 1.1(a) shows the superheterodyne receiver [1]. 1.8.3.2 The Zero-IF Architecture

In contrast, the homodyne, or zero-IF (ZIF), radio transceiver is a direct-conversion architecture, meaning that it utilizes one mixer stage to convert the desired signal directly to and from the baseband without any IF stages and without the need for external SAW filters. A block diagram of a ZIF radio is shown in Figure 1.1(b), where it can be noted that there are fewer components than in the superheterodyne radio. It is also common to integrate the LNA, VCO, and baseband filters onto one single die. ZIF transceivers are not a new concept and they have been used for years in cellular and pager applications. They are also

ADC

LNA

Phase splitter

VGA

LO

90°

Duplexer

ADC LO

DSP

DAC 0 0° PA

Phase splitter

VGA

LO

90°


0°

DAC (a)

13

Figure 1.1 (a) Superheterodyne transceiver architecture and (b) ZIF transceiver architecture.

14


ADC 0° LNA

Phasesplitter splitter phase

LO

90°

Duplexer

ADC DSP

DAC 0° PA

phase splitter Phase

LO

90° DAC (b)

Figure 1.1 (continued)

beginning to emerge in WLAN applications, which play an important role in the SoC market [1]. 1.8.4

Testing Receivers

The receiver is the portion of a transceiver that takes the incoming RF signal from the antenna all the way down to analog baseband (I and Q). Many of the traditional tests that are performed on LNAs are also performed on receivers. These are items such as gain, NF, IP3, and so forth. However, due to the downconverting architecture of receivers, there is frequency translation of the signal from RF to baseband. This can cause some anomalies in the measurement results. These anomalies are sometimes overlooked, however, and the results are taken to be analogous to their RF-to-RF counterparts. An important test item for receivers is sensitivity. The term sensitivity is an extension of the discrete RF device noise figure. With the discrete RF device, noise figure is a measure of sensitivity. The higher the noise figure, the harder it will be for a device to receive low-level signals. The all-encompassing term sensitivity is used with a receiver because it is possible to measure the full functionality of the SoC device. One such example sensitivity test is to provide modulated


15

RF signals to the input of the receiver. The baseband output is then analyzed at different input power levels to determine when the data becomes corrupted because of noise introduced during the receiver downconversion process. 1.8.5

Testing Transmitters

The counterpart to the receiver, the transmitter, performs upconversion on analog baseband signals to produce an RF output from a device. As noted earlier, the transmitter is followed by a power amplifier to produce the necessary power for transmission of the signal to a base station [mobile telephony, local-area network (LAN), and so forth]. Similar to a receiver, the transmitter architecture can be either superheterodyne or ZIF, although the ZIF architecture is more prevalent today. Many of the same tests that are performed on PAs are also performed on transmitters. However, usually the tests are more extensive because the complete transmitter portion of a transceiver often has much more control of output power levels and these must be tested. 1.8.6

Testing PLLs and VCOs

The phase-locked loop (PLL) and VCO are the low- and high-frequency components of the circuit used to generate the local oscillator (LO) signal that is used in upconversion and downconversion. The PLL circuit is a frequency synthesis and control circuit. In general, it provides multiple, stable frequencies on a common time base within the same system. A basic PLL consists of a reference oscillator, phase detector, loop filter, and a VCO. While discrete PLL devices are available, the context within this book will be limited to testing of PLLs and VCOs that are contained within a transceiver. The key items within a PLL/VCO circuit that are tested in production are the N or R dividers, the VCO, and the response time of the PLL circuit. Although direct access to the dividers is not necessary for normal operation of the PLL, on some devices, the output of the N divider is routed to the package to allow testing of the divider output. Because of the increase of multiple chips in a single package and the limitations on available package pins, this is becoming less common. To test the VCO for proper operation, either VCO gain (KVCO) or direct RF frequency measurement is performed. Direct RF frequency measurement can be somewhat time consuming and is therefore typically reserved for characterization testing only. The overall response time of the PLL circuit is often a critical parameter. In production SoC testing, a measure of this “lock” time, called synthesizer lock time, is a common measurement.

16


Finally, a critical measure of the quality of the output of this circuit is the measure of VCO phase noise, which measures the amount of noise that may be introduced to the device during upconversion and downconversion via the LO.

1.8.7

Testing Modern Standards

Even though there are different approaches to production testing, at this time most device testing is typically done with continuous-wave (CW) signals (instead of modulated signals). Such tests are basically the same for all different standards. The only differences in testing different standards are in the stimulus parameters such as power level, frequency, tone spacing, and so forth. The requirements of power levels, tone spacing, and so on are specified in the test plan document with inputs from the systems engineer to make sure that that specific device is following at least the IEEE standards. Most device manufacturers go slightly beyond the IEEE standard to provide some kind of margin in their devices. Table 1.1 Various Protocols Requiring Modulated Signals During Production Testing Frequency Range (MHz)

Channel Modulation Bandwidth (MHz) Data Rate (Mbps) Format

802.11b (WLAN)

2,400–2,500

22

11

CCK

802.11a/g (WLAN)

2,400–2,500 (g) 5,000–6,000 (a)

16.8

54

OFDM, 52 subcarriers (4 pilots and 48 data channels)

802.16a (WIMAX)

2,000–11,000; three most common: 2,500, 3,400, 5,800

1.25–20

Up to 75

OFDM, 256 subcarriers (200 actually used; 192 of them are data channels)

802.15 (UWB)

3,100–10,600

528

53.3–480

OFDM

GSM

3 bands: 890–960, 1,710–1,880, 1,850–1,990

0.200

0.270

GMSK

CDMA2000

450, 800, 1,700, 1,900, 2,100

1.25

0.060 to 0.100

CDMA

Bluetooth

2,400–2,500

1

1

FSK


17

Even though currently it is sufficient to test most devices with CW signals to guarantee the device performance in its final application, each one of the standards that is listed in Table 1.1 [7–14] typically has one or more tests that make the standard unique and might require modulated signals. For instance, the IEEE 802.11b spec specifies a spectral mask test, which requires complementary Table 1.2 Production Tests on RF, SoC, and SiP Devices Parameter

LNA PA

Transmitter

Receiver PLL/VCO

ACPR/ACLR

—

X

X

—

—

Bandwidth

X

X

X

X

—

Carrier suppression

—

—

X

—

—

Charge pump current

—

—

—

—

X

Dynamic range

—

X

—

X

—

Error vector magnitude (EVM)

—

—

X

X

—

Gain

X

X

X

X

—

Gain flatness over frequency

—

X

X

X

—

Gain flatness over power

—

X

X

X

—

Insertion loss

—

—

—

X

—

Isolation

X

—

—

—

—

I/Q amplitude balance

—

—

—

X

—

I/Q dc offset

—

—

—

X

—

I/Q phase balance

—

—

—

X

—

LO frequency

—

—

—

—

X

N-/R-counter frequency

—

—

—

—

X

Noise figure

X

—

—

X

—

Output power

—

—

X

—

—

Phase noise

—

—

—

—

X

Power-added efficiency (PAE)

—

X

—

—

—

Power/gain compression (e.g., P1dB)

X

X

X

X

—

Power/gain linearity

—

X

—

—

—

X

X

—

X

—

Return loss

X

X

RF-LO rejection

—

—

Second-order intercept point (IP2)

X

X

X

X

—

Spurious output

—

X

X

—

—

Third-order intercept point (IP3/TOI)

X

X

X

X

—

Total harmonic distortion

—

X

—

X

—

18


code keying (CCK) modulated signals as well as a wide bandwidth receiver. Other standard specific tests that require modulated signals are ACLR [commonly performed for code division multiple access (CDMA) devices], bit error rate tests (commonly performed on Bluetooth devices), or error vector magnitude (EVM), which is frequently measured on devices that use orthogonal frequency division modulation (OFDM) such as Worldwide Interoperability for Microwave Access (WiMAX). A device-specific test is a test that is not performed because it is required according to the IEEE specification, but performed by the vendor to guarantee correct design of the device. In most cases those tests are added after the device has been fully characterized and it was determined that the device had deficiencies on some of the design parameters. A good example for such a test would be the “image reject test,” which is commonly performed on the downconverting mixer of the receive chain. 1.8.8

Summary

Table 1.2 lists tests that are commonly performed on the various devices or portions of devices that have been introduced. These tests make up the majority of tests performed on modern RF, SoC, and SiP devices. As always there are exceptions. As new technologies arrive, new tests or variations of older tests are encountered. The important thing is to understand the fundamentals of test and measurement and with that, all tests can be efficiently and effectively implemented.

References [1]

Schaub, K., and J. Kelly, Production Testing of RF and System-on-a Chip Devices for Wireless Communications, Norwood, MA: Artech House, 2004.

[2]

Gray, K., “Current Trends in Test-Handler Technology,” Evaluation Engineering, Vol. 36, No. 5, 1997.

[3]

Gahagan, D., “RF (Gigahertz) ATE Production Testing On-Wafer: Options and Tradeoffs,” Proc. 1999 Int. Test Conf., 1999, p. 388.

[4]

Wong, K., and R. Grewal, “Microwave Electronic Calibration: Transferring Standards Lab Accuracy to the Production Floor,” Microwave Journal, Vol. 37, No. 9, 1994, pp. 94–105.

[5]

Dunsmore, J., “Techniques Optimize Calibration of PCB Fixtures and Probes,” Microwaves & RF, Vol. 34, No. 11, 1995, pp. 93–98.

[6]

Fitzpatrick, J., “Error Models for Systems Measurement,” Microwave Journal, Vol. 22, No. 5, 1978, pp. 63–66.


19

[7] Agilent Technologies, “Ultra Wideband Communication RF Measurements,” Application Note 1488, 2004. [8] Agilent Technologies, “WIMAX Concepts and Measurements,” Application Note, 2004. [9] Agilent Technologies, “WIMAX Signal Analysis.” Application Note, 2004. [10] Agilent Technologies, “Wireless Test Solutions,” Application Note 1313, 2002. [11] OFDM Alliance, “Multi Band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3A,” 2004. [12] OFDM Alliance, “Ultrawideband: High Speed, Short Range Technology with FarReaching Effects,” 2004. [13] Scourias, J., “A Brief Overview of GSM,” University of Waterloo, 1995. [14] CDMA Development Group, http://www.cdg.org/technology/cdma_technology/a_ross/ index.asp, 1996.

2 Tests and Measurements I: Fundamental RF Measurements 2.1 S-Parameters One of the most frequently used methods to describe the functionality of RF devices is to use scattering parameters, or in short S-parameters. S-parameters are used to describe how a device alters voltage waves that are applied to its ports. For instance, an amplifier should increase the amplitude of the voltage wave that was applied to the input of the device. Therefore, the S-parameter measurement of an amplifier’s gain compares the output amplitude of the amplifier to the amplitude of the voltage wave that was applied to stimulate the amplifier. First, let’s look into how S-parameters are defined [1]. Figure 2.1 shows the signals that are applied to obtain S-parameters in the case of a two-port device. When we talk about SoC testing, in most cases we are talking about two-port devices, that is, devices in which we observe one output relative to one input. The simplest example of an active two-port device would be an amplifier. The a1 signal in Figure 2.1 is the voltage wave that is applied to the input of the device. Likewise, the a2 signal is a voltage wave that is applied to the output of the device; b1 is the voltage wave that can be measured at the input of the device; and b2 is the voltage wave that can be measured at the output of the device. For two-port devices we have four S-parameters, which are defined as follows:

21

22


b2

a1 Two port device

a2

b1

Figure 2.1 S-parameter definition for a two-port device showing incident and reflected signals.

S 11 =

b1 with a2 = 0 a1

(2.1)

S 21 =

b2 with a2 = 0 a1

(2.2)

S 12 =

b1 with a1 = 0 a2

(2.3)

S 22 =

b2 with a1 = 0 a2

(2.4)

Under the assumption that the output of the two-port device is terminated (a2 = 0), S11 is called the input reflection coefficient. Under the same assumption, S21 is called the forward transmission coefficient. Also, S22 is the output reflection coefficient if the input of the device is terminated (a1 = 0) and S12 is the reverse transmission coefficient if a1 is assumed to be zero. The term terminated or matched means that the load that is provided to the input of the second port is the complex conjugate of its input impedance. Likewise, the load that is provided to the output of the second port has to be the complex conjugate of the output impedance. For instance, if the impedance of port 2 is Z2 = R + jX, then the load that is applied to that port should have the characteristics of ZL = R − jX. In other words, the load has to be selected so that there is a maximum transfer of power from the two-port device to the load. It is important to note that S-parameters are not scalar numbers but vectors; since we are applying voltage waves and observing the device’s response by


23

measuring the reflected or transmitted waves, we have to compare the magnitudes and phase information in the calculations. Therefore, S-parameters can be listed in a magnitude–phase notation or in real–imaginary notation. The more common way is to specify magnitude and phase. In RF and SoC testing, the phase is typically not of importance, and the test engineer concentrates only on the magnitude portion of the measurement. Because S-parameters are obtained by dividing two numbers of the same units (volts), S-parameters themselves do not have a unit. However, instead of simply showing S-parameters as a number without units we translate those ratios into a logarithmic scale and therefore talk about S-parameters in decibels (dB). As mentioned earlier, S-parameters are obtained by calculating the ratios between reflected to incident and transmitted to incident voltage waves. To transform those unitless ratios into decibels, we have to use the following equations:

2.1.1

S 11 [dB] = 20 × log S 11

(2.5)

S 21 [dB] = 20 × log S 21

(2.6)

S 12 [dB] = 20 × log S 12

(2.7)

S 22 [dB] = 20 × log S 22

(2.8)

Application of S-Parameters in SoC Testing

2.1.1.1 Input Match

Probably the most widely used application for S-parameters in SoC testing is to determine the input match of the device. The input match of the device indicates how much of the power that is applied to the device is reflected. Obviously this number should be low because the goal is to get as much of the applied power into the device as possible. Assuming that the rms value of the applied voltage wave is 0.1V and the rms value of the reflected voltage wave is 0.02V (if the device output is perfectly matched), the magnitude of the input reflection coefficient is S 11 = 0.02 01 . = 0.2

(2.9)

To get this number into decibels, we have to calculate S 11 = 20 × log (0.2 ) = −14 dB

(2.10)

24


Considering that most device data sheets specify a maximum input match of around –10 dB this would be an acceptable number for most devices. 2.1.1.2 Output Match

On modern SoC devices, an output match measurement is performed to measure the output matching of the power amplifier. The point of this measurement is to determine how much of the power is actually absorbed by the load and not reflected. Values less than –10 dB are typically considered acceptable as an output match. Often, the output match measurement is simply called the S22 measurement. 2.1.1.3 Gain Measurement

In many cases the S21 measurement can be used as a gain measurement. There are various definitions of gain in the RF world, and if some conditions of matching are met, the differences between those various gain definitions can be neglected. For instance, if the input and output of a device are matched, S21 can be used as a gain measurement because all of the input power is absorbed by the device, and the output power coming from the device is applied to the load. Gain is one of the key parameters of amplifiers. If a single amplifier is measured, the gain value is typically on the order of 20 dB even though there are applications where this number could be significantly lower or higher. Another key parameter on top of the gain measurement is the gain flatness of the device. For instance, a Bluetooth device works over a bandwidth of 100 MHz. It is important to make sure that the gain of the transmitter is the same whether the measurement is taken at 2.400 or at 2.499 GHz. The maximum allowed gain deviation over frequency is called gain flatness. In the preceding example of a Bluetooth transmitter, the typical gain flatness would be specified as, for instance, 1 dB. That means that if the gain over the whole 100-MHz band is observed, the difference between the highest gain and the lowest gain must not be more than 1 dB.

2.2 PLL Measurements The purpose of the PLL in each SoC device is to provide the mixer in the receiver chain with the correct frequencies to downconvert the received signals into the baseband and to provide the mixer of the transmitter chain with the correct frequencies to upconvert baseband signals into the device’s transmitting spectrum. Before we talk about measurements that test the functionality of a PLL in a SoC device, it is important to understand the basic functionality of a PLL. Figure 2.2 shows a basic block diagram of a PLL.


fref ref

/R

Phase Phase Detector detector

fout=

Loop Filter filter

VCO

25

Nfref R

/N

Figure 2.2 PLL circuit used to generate LO frequencies used in upconversion and downconversion in SoC devices.

As can be seen in Figure 2.2, a PLL consists of two programmable dividers, a phase detector, a loop filter, a VCO, and a feedback loop. The phase detector frequency can be calculated by dividing the reference frequency by R: f PD =

f ref R

(2.11)

The RF output frequency of the PLL, which is often termed fout, can be calculated as, f out =

N ⋅ f ref R

(2.12)

More theory about PLLs can be found in [2]. We now focus on some key measurements of PLLs in SoC devices. 2.2.1

Divider Measurements

As can be seen in (2.12), the output frequency of a PLL is determined by the values of the two dividers N and R. Depending on the device and the application, the range of those dividers can be quite large, for instance, from 1 to 65,535. Stepping through all of those values is obviously not practical in a production test. To guarantee that all divider settings work, in most cases test modes have been built into the device that allow the test engineer to verify the functionality of the dividers with just a few tests. A test mode is a device state in which the test engineer can access functions that are not intended for use in the final application. The purpose of a test mode is to allow measurements that are otherwise not possible to perform, for instance, by routing an internal signal to a pin that is used for other functions during normal operation. Another frequently applied approach in divider testing is to program the divider into one state that will generate a certain RF frequency. After verifying that this setting indeed generates an RF tone at the expected frequency, the divider is reprogrammed by flipping all bits and the RF tone is measured again

26


at a different frequency. For instance, the divider might first be programmed to the value 011111111111, which corresponds to the divider setting 2047 and generates a frequency f1. Next, the divider is reprogrammed to the value 2048 (binary number 1000000000), which generates a frequency at f2. This approach makes sure that all bits in the dividers are toggled once and can be verified with two RF power measurements whose frequencies can be calculated using (2.12). 2.2.2

VCO Gain Measurement

The VCO has to be able to cover the whole frequency band in which the device operates. For instance, a Bluetooth radio covers the frequency band from 2.4 to 2.48 GHz. That means that the PLL in the Bluetooth radio has to be able to cover a frequency range of at least 80 MHz under the worst operating conditions such as the supply voltage being at the lower limit. PLL gain measurements can be performed by programming the dividers such that the PLL tunes to the lower frequency limit. Because the voltage that controls the VCO is dc in the case for which the VCO has settled, a simple voltage measurement is performed at the input of the VCO. Next, the dividers are programmed such that the PLL tunes to the upper frequency where the voltage at the input of the VCO is measured again. The change in RF frequency divided by the change in dc voltage is defined as the gain of the VCO,1 or KVCO: K VCO =

∆f ∆V

(2.13)

where ∆f is the change in frequency and ∆V is the change in voltage applied to the VCO. As an example, assume that a VCO operates between 850 and 900 MHz. The frequencies in Table 2.1 are measured in response to the applied voltages in Table 2.1. Using (2.13), the VCO gain is calculated to be 27.8 MHz/V. Assuming that the VCO is linear in this operating range, this means that the output frequency of the VCO changes by 27.8 MHz for every 1-V change at its input. 2.2.3

PLL Settling Time

The PLL settling time is the time that it takes the PLL to change from one frequency to another. Obviously this is a very important parameter for standards 1. Some modern SoC devices have VCOs that are designed with tunable capacitors in order to cover a wider frequency band. If that is the case, the test engineer has to make sure that the capacitor setting is not changed while the VCO gain is measured with the method described earlier.


27

Table 2.1 Applied Voltage and Measured Frequency at VCO Output for a Common VCO VCO Parameter

State 1

State 2

Voltage applied to VCO (V)

0.4

2.2

Measured VCO output frequency (MHz)

850

900

that require frequency hopping such as Bluetooth. Measuring the PLL settling time can be challenging and is always dependent on the architecture of the test system that is used. It requires powerful capabilities in terms of trigger requirements for the digital, analog, and RF subsystem and, depending on the rate of frequency changes, the bandwidth of the test system digitizer and the tester’s ability to change the frequencies of the tester local oscillator. Reference [3] explains in detail one way to perform a PLL settling time measurement.

2.3 Power Measurements Most parameters that are used to specify a SoC receiver are related to RF power. The exception is the reflection coefficient, as discussed earlier, in which S-parameters are used. The specification of the receiver includes minimum detectable RF power as well as the maximum allowed input power, power levels of interfering tones, and so forth. Likewise, the output of the transmitter is specified mostly in terms of RF power: the maximum RF output power under certain conditions, the change in RF power if gain steps are part of the SoC transmitter, the distribution of RF power over the frequency band, and so forth. Reference [3] gives an excellent overview of how RF power is defined. It is important for the test engineer to understand the concept of measuring and applying RF power in dBm. The dBm unit is another example of translating unitless numbers into the logarithmic scale. The letter m indicates that the RF power is referenced to 1 mW. To convert power from the linear scale (watts) into dBm, the following formula has to be applied:  P [W ]  P [dBm ] = 10 × log    0.001W 

(2.14)

Let’s assume that we have an RF amplifier that has an output power of 3W; we can calculate the power in dBm using (2.14):

28


P = 10 × log

3W = 34.8 dBm 0.001W

(2.15)

When RF power is measured, it is important to specify the measurement bandwidth. The higher the measurement bandwidth specified, the larger the frequency band that can be measured. However, the downside is that the wider the measurement bandwidth chosen, the more noise integrated into the measurement. This might not be a problem for measurements that have strong signals (i.e., signals that are way above the noise floor of the measurement equipment). However, for signals that are weak, special care must be taken in the correct selection of the measurement bandwidth. As a rule of thumb, the sensitivity of an RF power measurement goes up 3 dB if the measurement bandwidth is cut in half. This might make it tempting to always select the smallest possible measurement bandwidth. It is important to know, however, that the smaller the measurement bandwidth, the longer the time required to execute the measurement. Therefore, because a short test time is one of the key objectives for every test engineer, the right compromise has to be found between small measurement bandwidth in order to perform accurate measurements of low-power signals and a wider measurement bandwidth to save test time. The following sections focus on basic measurements that involve measuring RF power on SoC devices. More advanced concepts of measuring RF power such as distortion measurements are covered in Chapter 3. 2.3.1

RF Output Power Measurement

When a test program for a transmitter or an amplifier is developed, the RF output power measurement is most likely the test that is implemented first. Without an output signal from the device, no other tests can be developed. Most RF measurements in SoC devices are performed with CW tones, which means that the RF power is concentrated into an infinitely small bandwidth (at least in theory). Remember the earlier discussion about measurement bandwidth selection. In the case of a power amplifier or transmitter output, the power level will be relatively high, say, between –10 and +35 dBm, so a good starting point for the test engineer might be the default bandwidth of the measurement equipment.2 When modulated power has to be measured, it is important to understand the minimum required bandwidth for the measurement. For instance, the channel bandwidth for a modulated 802.11b signal is 22 MHz. This is a system-specific number that can be found in the data sheet of the device. If the measurement 2. Care has to be taken when high-power levels are measured. To avoid overdriving the measurement receiver, the RF signal might have to be attenuated or an attenuator might have to be switched into the measurement path of the test system.


29

bandwidth of the test system is less than that of the signal, the result of the measurement will be a lower reading than anticipated. On top of that, of course, it is mandatory that all required measurement parameters, such as sampling rate, are set up correctly to allow the measurement to be performed. Many modern modulation formats use pulsed power. This is the case, for instance, for the IEEE 802.11a standard, which uses OFDM. In the case of modulated power, the measurement will yield typically just an average power. To determine the pulsed power, additional parameters such as duty cycle or measurement filter type have to be specified. More specific information about measuring modulated or pulsed power can be found in [3].

2.3.2

Spur Measurements

As mentioned in Chapter 1, most tests in RF SoC devices are still performed with CW signals despite the test system’s ability to apply and measure modulated or pulsed power. A typical measurement that falls into this category is a spur measurement. A spur is an RF tone that is in the frequency band of interest even though it is not intended to be there. For instance, in the transmitting spectrum of an RF SoC device, there are typically more spectral components than desired or expected after applying the correct stimulus at the input of the device. Many factors can contribute to the creation of spurs. One main contributor is the PLL in the system where a phase detector operates at one specific frequency. Even though the design engineer tries to minimize the spurs that are created by the phase detector, they can never be completely avoided. Other spurs that are commonly seen are the spectral components from the reference frequency or a fraction of the reference frequency. Every wireless standard has some form of requirement in terms of what bandwidth it is allowed to occupy and how much energy it is allowed to leak into other channels, or the maximum allowed power per spur. Figure 2.3 shows an example where the modulated spectrum can be seen on the left side. However, a powerful spur in the spectrum can also be seen. This spur was created by the reference input crystal oscillator and its impact was not considered during the design phase. Even though all other parameters were within specification, this spur in the transmitting spectrum required a redesign of the device. Finding the exact frequency of a spur is normally done during characterization of the device. During production testing, a simple power measurement is then performed at exactly that frequency and, according to the power level, the device is then judged as either good or bad. A more serious problem is the occurrence of random spurs. Random spurs are spurs that are present at some frequencies in one DUT but are not present at the same frequencies in another DUT. One of the reasons they are there is due

30

Advanced Production Testing of RF, SoC, and SiP Devices −10 −20 −30 −40 −50 −60 −70 −80

0

200

400

600

800

1000 1200 1400

1600

Figure 2.3 Spurs in the transmitting spectral output of an SoC device.

to manufacturing variations. During device characterization the engineer has to decide whether the existence of the spurs is serious enough that they have to be measured during production testing or if their power levels are so low that they are not a problem. If random spurs have to be measured during production testing, the whole spectrum has to be scanned and evaluated for spurs. Because random spurs are nondeterministic, the test engineer has no other choice than to scan the whole frequency spectrum where the device radiates RF power. Needless to say, this is a lengthy test and the goal is always to avoid searching for random spurs. 2.3.3

Harmonic Measurements

Harmonic measurements and spur measurements have in common that they are done by performing power measurements of unwanted tones. For spur measurements, however, the whole spectrum has to be scanned and characterized in order to determine the frequencies where those measurements should be performed. For harmonic measurements, the frequencies are known to the test engineer without characterizing the spectrum since they are multiples of the main tone. Even though there are exceptions, harmonic measurements are in most cases done for the transmitter only. The creation of the harmonics is due to fact that the output amplifier of the transmitter is driven close to saturation or eventually even into saturation. This can be described as compression in the frequency domain or clipping in the time domain. Harmonics are created every time the transmitting amplifier is compressed, and the power level of those harmonics increases when the amplifier is driven more into saturation. If harmonic measurements are performed, the test engineer focuses in most cases on odd harmonics because odd harmonics


31

have significantly higher power levels than even harmonics in the case that an amplifier is driven into compression. Assuming that a device has its fundamental tone at 2.5 GHz, the third harmonic is at 7.5 GHz and the fifth harmonic is at 12.5 GHz. The even harmonics are at 5 GHz (second harmonic) and 10 GHz (fourth harmonic). Because most testers that are used to test SoC devices cannot measure frequencies above 10 GHz and the main focus is on odd harmonics, the harmonic measurement in the preceding example would be performed at 7.5 GHz to measure the power level of the third harmonic. 2.3.4

Spectral Mask Measurements

Whenever a device is designed, it is the goal of the design engineer to concentrate the power of the signals into the bandwidth of interest. This is not only due to the desire to be as energy efficient as possible, but also because the amount of power that can be transmitted outside of the desired bandwidth is limited by the specification for each standard. The idea is to reduce interference by limiting radiation of RF frequencies beyond the necessary bandwidth [4]. For instance, the IEEE 802.11b standard specifies that the maximum power level in a frequency band that is 11 to 22 MHz away from the carrier has to be at least 30 dB below the carrier power [5].3 Figure 2.4 shows the spectral mask plot for an 802.11b modulated carrier. The IEEE 802.11b standard also specifies that for offsets that are greater than 22 MHz, the power levels have to be 50 dB below the carrier level. In the case of Figure 2.4, we can see that the device is passing the criterion that the frequency band be between 11 and 22 MHz, but is failing the criterion that the frequency band be 22 MHz or more away from the carrier: At an offset of 22 MHz, the difference between the carrier power and the power at the offset frequency is only 47.55 dB.

2.4 Power-Added Efficiency Power-added efficiency (PAE) is a measurement that is done almost exclusively on power amplifiers and describes how efficiently the device is working. PAE is the change in RF power divided by the dc power consumption of the device. It is defined as follows: PAE =

∆P RF P DC

(2.16)

3. There are more conditions attached, for instance, in terms of the measurement bandwidth, which has to be 100 kHz when the spectral mask measurement is performed.

32


Figure 2.4 A spectral mask plot for a WLAN 802.11b modulated carrier, as output from the transmitting portion of an SoC device.

As an example, assume that a DUT (RF power amplifier) is subject to the following conditions: Input power is +2 dBm and it has a dc operating voltage of 3V. As a result, the DUT draws 2,250 mA of current and outputs +34 dBm of RF power. As mentioned earlier, the dBm unit is the common way of specifying power in the RF world. Because the dBm unit is in the logarithmic scale we will have to calculate the corresponding power in watts: P in

P out

 2    10 

W

= 0.001 × 10

= 0.0015W

W

= 0.001 × 10  10  = 2.5118 W

 34   

P DC = 3 V × 2.25A = 6.75W PAE =

2.5118 − 0.00158 = 37.2% 6.75

(2.17)

(2.18) (2.19) (2.20)

This means that about 37% of the dc power is actually used to amplify the RF signal. The remaining 63% is dissipated as heat. Because the power amplifier is the device that has the highest current consumption in a mobile phone, for instance, systems and design engineers pay a lot of attention to PAE because this


33

is the main factor that causes the battery to drain and therefore reduces a mobile phone’s usable time before it has to be recharged.

References [1]

Agilent Technologies, “S-Parameter Design,” Application Note 154, 2000.

[2]

“Phase-Locked Loops,” http://www.uoguelph.ca/~antoon/gadgets/pll/pll.html.

[3]

Schaub, K., and J. Kelly, Production Testing of RF and SoC Devices for Wireless Communications, Norwood, MA: Artech House, 2004.

[4]

“Spectral Mask,” http://en.wikipedia.org/wiki/Spectral_mask.

[5]

http://standards.ieee.org/getieee802/download/802.11b-1999.pdf.

3 Tests and Measurements II: Distortion 3.1 Introduction A lot of changes have been made to the methodologies used for testing for distortion in modern RF-containing SoC devices. Many excellent resources are available describing the types of distortion and how to test them. With the recent integration of RF front ends into SoC transceivers, especially in the area of wireless communications, some changes have been made to the fundamentals of distortion testing. In particular, the rise of homodyne, or ZIF, architectures has led to the importance of distortion mechanisms and products that have traditionally been ignored due to past architecture types. This chapter is aimed at enlightening the SoC production test engineer to distortion testing techniques required as the levels of integration continue to increase. However, it can also serve as an updated review of the fundamentals of distortion and distortion testing for all electronic devices in general. This chapter takes concepts from traditional RF and traditional mixed-signal testing and unites them in one discussion. With the integration levels of today’s SoC devices for wireless communications, it is necessary to have a full understanding of how these traditional analog measurements are performed, regardless of whether they are at RF frequencies or baseband frequencies. The concepts used in performing RF frequency distortion measurements are the same as those used in performing lower frequency distortion tests. Nonlinear properties such as harmonic and intermodulation distortion occur in all real devices. The methods used to determine these properties, and other distortion properties, in devices will be shown in this chapter. Numerous papers have been written on various types of distortion tests ranging from audio frequencies to several gigahertz, but when one considers the 35

36


basic phenomenon of distortion, it all leads to the same result: degradation of desired signal.

3.2 Linearity Distortion occurs due to the nonlinear behavior of a device. All devices, whether RF or otherwise, exhibit nonlinear behavior. At times it is part of proper operation, as in the case of a high-efficiency power amplifier, mixer, or frequency doubler. At other times, nonlinear behavior is undesired and a problem that deteriorates the intended performance of a DUT. Fundamentally, the linearity of a system has two requirements [1]: 1. All frequencies in the output of a system will be relative to the input by a proportionality, or weighting factor, independent of power level. 2. No frequencies will appear in the output, that were not present in the input. However, because semiconductor devices are based on diodes and transistors, there is nonlinear device behavior between the input and output signals. This is known as distortion.

3.3 Distortion in SoC Devices When signals are sent through a device, the occurrence of distortion is inevitable. The problem with distortion—and it does not matter which type of distortion because it nets the same result—is that distortion products take away from the intended, or fundamental, signal. For example, assume all of the desired power coming from a DUT was contained in a single tone at the fundamental frequency when the device was operating at low power levels. When the device power level is increased and distortion occurs, the power begins to be seen at the distortion products (e.g., second and third harmonics), taking away from the power intended to be at the fundamental frequency. Distortion can occur in any of the following most common forms: harmonic distortion, intermodulation distortion, or gain compression. Testing techniques for the presence of distortion consist of the application of single-tone (gain compression and harmonic distortion), two-tone (intermodulation distortion), and multitone (cross modulation) stimuli to the DUT while analyzing the output spectrum.


37

3.4 Transfer Function for Semiconductor Devices Because semiconductor devices are made of diode structures, a derivation of voltage behavior in diode-based devices is presented here and will be used in the subsequent harmonic and intermodulation distortion explanations [2]. Most literature starts from the statement that the transfer function can be represented as a power series, but this discussion will begin with fundamentals. The definition of the current through a diode is I out = I S (e αV in − 1)

(3.1)

where IS is a constant (saturation) current of a diode, α is a constant dependent on temperature and the design of the diode structure, and Vin is the combined ac and dc voltage across the diode. If the total input voltage is generalized to contain both dc and ac components, then V in = V 0 + v in

(3.2)

)

I out = I S (e α (V 0 +v in ) − 1

(3.3)

where V0 is a dc voltage and vin is a small signal ac voltage. Because vin is small, a Taylor Series (or power series) expansion can be used to rewrite (3.3) as I 0 = I 0 + v in

dI out dv in

+ V0

1 2 d 2 I out v in 2 dv in2

+K

(3.4)

V0

From (3.3), dI out dv in

= αI S e αV 0

(3.5)

V0

and each successive derivative is just a constant, α, multiplying the exponential, d N I out dv inN

= α N I S e αV 0 V0

(3.6)

38


It is often easier to work in terms of voltages rather than currents since they are simpler to measure. If the current through a diode is measured as a voltage across some resistance R, then from Ohm’s law, (3.4) becomes v out = a 0 + a 1 v in + a 2 v in2 + a 3 v in3 + K

(3.7)

where a0, a1, a2, a3, …, are constants that have absorbed R and the derivatives. The term a0 is a dc term describing the dc parameters of a diode. An amplifier, when working in the linear region, is described by the linear term a1. The higher order terms are used to describe either the proper operation of nonlinear devices, or the undesirable, nonlinear distortion found in many SoC devices. Equation (3.7) is the fundamental equation that has been used to describe all effects of distortion on devices ranging from audio frequencies to RF applications for many years. The two common distortion tests, for harmonic distortion and for the various forms of intermodulation distortion, involve applying a single-tone sinusoid and two combined sinusoids to the device and analyzing the response. Mathematically this is described by acquiring the solutions to (3.7) for each case. These are discussed in the following sections.

3.5 Harmonic Distortion Consider what happens if the input voltage waveform to a DUT is a single-tone frequency, v in = A cos( ωt )

(3.8)

v out = a 0 + a 1 A cos ωt + a 2 A 2 cos 2 ωt + a 3 A 3 cos 3 ωt + K

(3.9)

Then (3.7) becomes

Considering only the first three components and applying trigonometric identities show that each higher-order term can be rewritten as a multiple of the fundamental frequency ω; for example, cos 2 ωt = and

1 (1 + cos 2 ωt ) 2

(3.10)


cos 3 ωt =

39

1 (3 cos ωt + cos 3 ωt ) 4

(3.11)

Therefore, v out = a 0 + a 1 A cos ωt + a3 A 3 4 v out

(3.12a)

(3 cos ωt + cos 3 ωt )

3a 3 A 3  a2 A 2  a A2 = a0 + + a1 A +  cos ωt + 2 cos 2 ωt + 2 4  2  (3.12b)

a3 A 3 4

a2 A 2 (1 + cos 2 ωt ) + 2

cos 3 ωt

Amplitude

Harmonic distortion occurs when some of a DUT’s intended power is transferred from a desired frequency to a higher order multiple of the fundamental frequency. These higher order terms are called harmonics and are classified by their order. The order is an integer and is taken to be m. All of the higher order terms can be written in terms of the fundamental frequency and from that it is immediately noticed that each higher order term is really the fundamental frequency ω multiplied by the order (e.g., 2ω, 3ω, and so forth) of the term. Thus, for any vin = cos(ωt), the output will consist of all harmonics, mω, where m is an integer going from minus infinity to infinity. Figure 3.1 shows the first few harmonic distortion products for a fundamental signal having frequency, f1, where f = ω/2π. Note that if the frequency axis could be extended infinitely, the harmonic distortion components would continue indefinitely, equally spaced, but decreasing in amplitude. Harmonic distortion typically occurs at higher power levels, but because no devices are perfect, harmonic distortion can even be generated at low power

DUT …

f1

f1 Frequency

2f 1

3f 1

Figure 3.1 Harmonic distortion products due to a single-tone input, f1, to a DUT.

40


levels. It has been rarely tested for in traditional, pure-RF devices for wireless communications because RF frequencies are so high already and the second and third harmonics are far from the frequency band of interest. On receiver devices, the harmonics will be filtered due to the finite bandwidth of the receiver. However, on transmitting devices, there is a little more concern, because it is important to ensure that signal transmission is minimal at other frequencies that may be used for other purposes. Harmonic distortion is defined and tested by application of a single-tone (frequency) sinusoidal waveform, as in the preceding derivation. Even-order harmonics result from αj with even j. In (3.12b) it is important to note that the amplitude of the nth harmonic consists of a term proportional to An. 3.5.1

Measuring Harmonic Distortion

The two primary ways to quantify the harmonic distortion content of a DUT are (1) total harmonic distortion and (2) signal, noise, and distortion, both of which are discussed in the following sections. 3.5.1.1 Total Harmonic Distortion

A standardized measure of harmonic distortion is total harmonic distortion (THD). THD is the relative power contained in all harmonics of a signal expressed as a percent of the fundamental signal power. It is a measure of how well the device converts energy to the desired fundamental signal versus the undesired harmonic signals. Harmonic distortion is specified (and tested) at a specified output power of the DUT. It is defined as follows: THD(% ) =

P 2 + P 3 + P4 + K P fundamental

× 100%

(3.13a)

where P2, P3, P4, … are the power, in watts, of the second, third, fourth, and so on harmonics, respectively. Pfundamental is the power of the desired fundamental signal. Alternatively, in units of volts, as when measuring a digitized analog baseband signal,

(V 2 ) 2 + (V 3 ) + (V 4 ) + K 2

THD(% ) =

V fundamental

2

× 100%

(3.13b)

where V2, V3, V4, … are the voltage amplitudes of the second, third, fourth, and so on harmonics, respectively. Vfundamental is the voltage amplitude of the desired


41

fundamental signal. In either case, an ideal device with no distortion would have 0% THD. If a measurement receiver, or digitizer, does not have adequate bandwidth, THD measurements are measured by making several simple power measurements because the fundamental and harmonic frequencies are often far apart. 3.5.1.2 Signal, Noise, and Distortion

Signal, noise, and distortion (SINAD) is a measure of the quality of a received signal and is really just another variation of THD. The definition of SINAD in decibels is: S + N + D  SINAD[dB] = 10 log 10    N +D 

(3.14)

where S is the signal power (watts), D is the distortion power (watts), and N is the noise power (watts). Ideally, the distortion and noise powers would be zero. For zero noise and zero distortion (or noise and distortion that approach zero), the SINAD equation would reduce to:  S +0+0  SINAD[dB] = 10 log 10  =  small + small 

(3.15)

10 log 10 ( VeryBigNumber )

and the end result would be a large number that would indicate that the device converts energy very efficiently, has almost zero distortion, and adds almost zero noise. If the measured distortion value of one DUT versus another device is higher, then the overall SINAD result will be lower, indicating that the first device is not as efficient. This happens because the distortion is both added to the numerator, but then divided by the denominator. The same thing happens for the noise. As an example, let S = 1 and consider that there is zero noise and that the distortion power is 1/10 of the signal power; then .S  S + 0 + 01 SINAD[dB] = 10 log 10  =  0 + 01 .S 

10 log 10 (11) = 10.4

Now, doubling the distortion to 1/5 of S yields

(3.16)

42


 S + 0 + 0.2S  SINAD[dB] = 10 log 10  =  0 + 0.2S 

(3.17)

10 log 10 (6 ) = 7.78

Equation (3.17) yields a result that is smaller than (3.16) by 2.6 dB. This gives a good indication that the distortion plus noise power has increased by approximately two times or that the fundamental power has decreased by two times. In any case, the efficiency has been reduced in terms of power by a factor of two [3].

3.6 Intermodulation Distortion The single-tone description of the previous section only yields harmonic distortion products and only reveals part of the distortion story for wireless communication systems and SoC devices. Modern wireless systems use multiple tones and multiple modulation formats to squeeze as much information as possible into the channel bandwidth. In a communications system this means that signals in one channel can cause interference with signals in adjacent channels. As the spectrum becomes busier and the channels become more tightly spaced, minimizing intermodulation distortion becomes more important [4]. Consider a more complicated input waveform placed into (3.8), say, a two-tone signal: v in (t ) = A cos ω1t + B cos ω 2t

(3.18)

where ω1 and ω2 are two arbitrary frequencies. Then (3.9) becomes v out = a 0 + a 1 ( A cos ω1t + B cos ω 2t ) + a 2 ( A cos ω1t + B cos ω 2t ) + 2

(3.19)

a 3 ( A cos ω1t + B cos ω 2t ) + K 3

The following sections will expand the various terms in (3.19). 3.6.1

Second-Order Intermodulation Distortion

In this case of a two-tone sinusoid, the a0 and a1 terms are straightforward. Because the expansion of the higher order terms of (3.19) becomes quite lengthy, each of the components will be treated separately, then grouped by frequency and combined afterward. First, however, the following additional


43

trigonometric identity is needed to obtain individual single-frequency cosine functions: cos α cos β =

1 [cos( α + β ) + cos( α − β)] 2

(3.20)

The second-order term of (3.19) is expanded as follows: v in2 (t ) = ( A cos ω1t + B cos ω 2t )

2

v in2 (t ) = A 2 cos 2 ω1t + 2 AB cos ω1t cos ω 2t + B 2 cos 2 ω 2t

(3.21a) (3.21b)

Using trigonometric identities to restate the frequencies as multiples of ω1, we obtain v in2 (t ) =

A2 (1 + cos 2 ω1t ) + AB cos( ω1 + ω 2 )t + 2 B2 (1 + cos 2 ω 2t ) AB cos( ω1 − ω 2 )t + 2

(3.21c)

The result in (3.21c) describes both harmonic and intermodulation distortion. When expanded, it contains single-frequency terms (harmonic distortion) and terms with multiple frequencies (intermodulation distortion). Intermodulation distortion is the nonlinear product caused by application of multiple input frequencies to a device interacting with each other. It has a more pronounced effect at elevated power levels. As with harmonic distortion, intermodulation distortion occurs at different output frequencies than those put into the device. In communication systems the end result is that intermodulation distortion from signals in one channel can cause interference in other channels. Characterizing intermodulation distortion becomes more important as channels become more tightly spaced within the frequency spectrum. Note that with second-order intermodulation distortion there are four distortion products, at the following frequencies: 2ω1, 2ω2, ω1 − ω2, ω1 + ω2. The term second order comes from the fact that there are four combinations of the coefficients of ω1 and ω2 that, when added, give the value of two. Figure 3.2(a) shows second-order distortion products resulting from the application of two tones to a device. Traditionally, second-order intermodulation products have been of little concern for wireless communications


Amplitude

44

DUT

f1−f2 f2−f1

f1 f2

…

f1 f 2

2f1 2f2

Amplitude

Frequency (a)

DUT

f1 f2

3f1−2f2 f1 f2 3f1−2f2 2f1 2f2 2f1−f2 2f1−f2 Frequency (b)

… 3f1

3f2

Figure 3.2 Intermodulation distortion products due to a two-tone input, f1 and f2, to a DUT [5]: (a) second-order products and (b) third-order products.

devices because of their architecture. The superheterodyne architecture (see Chapter 1) that has been used from the beginning of wireless communications devices converts the frequencies that are input to lower frequencies, but far from dc, thereby never having to worry about the second-order product interference. More recently, the homodyne, or ZIF, architecture has eliminated the intermediate frequency, converting the received RF signals to near-dc frequencies. This means that closely spaced frequencies at RF will be closely spaced after they are converted via a homodyne receiver. This holds for second-order products, as well as any other higher, even-ordered intermodulation products, although for most communications devices, orders higher than two are relatively insignificant. 3.6.2 Third-Order Intermodulation Distortion

The third-order term of (3.19) is expanded as follows: v in3 (t ) = ( A cos ω1t + B cos ω 2t ) v in3 (t ) = ( A cos ω1t + B cos ω 2t )

3

( A 2 cos 2 ω1t + 2 AB cos ω1t cos ω 2t + B 2 cos 2 ω 2t )

(3.22a)

(3.22b)


v in3 (t ) =

A3 3 A 2B (3 cos ω1t + cos 3 ω1t ) + 4 2 (1 + cos 2 ω1t ) cos ω 2t + 3 AB 2 (1 + cos 2 ω 2t ) cos ω1t + 2 B3 (3 cos ω 2t + cos 3 ω 2t ) 4

45

(3.22c)

A3 v (t ) = [3 cos ω1t + cos 3 ω1t ] + 4 B3 [3 cos ω 2t + cos 3 ω 2t ] + 4 (3.22d) 1 3 A 2B   cos ω 2t + (cos( 2 ω1 + ω 2 )t + cos( 2 ω1 − ω 2 )t ) + 2 2   3 in

3 AB 2 2

1   cos ω1t + 2 (cos( 2 ω 2 + ω1 )t + cos( 2 ω 2 − ω1 )t )

 3 A 3 3 AB 2  3A3 v in3 (t ) =  + cos 3 ω1t +  cos ω1t + 2  4  4  3 A 2 B 3B 3  3B 3 cos 3 ω 2t + +   cos ω 2t + 4  4  2 2

(3.22e)

2

3A B 3A B cos( 2 ω1 + ω 2 )t + cos( 2 ω1 − ω 2 )t + 4 4 3 AB 2 3 AB 2 cos( 2 ω 2 + ω1 )t + cos( 2 ω 2 − ω1 )t 4 4 Figure 3.2(b) graphically shows the distortion products of (3.22e) arising from two fundamental signals being put into a device. There are six third-order distortion products, as shown. A few of these products are far from the fundamental (desired) frequencies and it is common practice to design filtering into a device to remove these products. Two terms of (3.22e), 2ω1−ω2 and 2ω2−ω1, however, are very close to the fundamental input frequencies. It is these two terms that have traditionally (in heterodyne device architectures) been the most troublesome and therefore tested exhaustively for. Specifically, the third-order products occur at the following frequencies: 3ω1, 3ω2, 2ω1 + ω2, 2ω2 + ω1, 2ω1 − ω2, and 2ω2 − ω1 (notice the six terms). Note that the two products that are only dependent on a single frequency (only

46


ω1 or only ω2) are third-order harmonic distortion products. The first four terms are again relatively far away from the fundamental frequencies ω1 and ω2, so they are often outside of the normal frequency response of the device or can easily be filtered. 3.6.3

Higher-Order Intermodulation Distortion Products

Second- and third-order intermodulation distortion products have been discussed. These are the most prevalent types tested for in communications front ends. Although the products may be small, there are an infinite number of intermodulation distortion products. Sometimes intermodulation distortion products having orders greater than three may be of interest. This is true mainly for high-power applications such as baseband power transmitter devices. Another possibility for which higher order intermodulation products may be of concern is that as device performance is moved to lower signal levels through lower device noise floors, the higher order intermodulation distortion products may become visible and impact the low-level signals. As with the even products, the higher-order odd products follow the same behavior as third-order products, making troublesome interference in many device architectures. A term called spectral regrowth is sometimes used to describe intermodulation distortion [6]. 3.6.4

Example of Harmonic and Intermodulation Distortion Products

From (3.21c), it can be stated that for any two-tone input waveform, vin(t) = A cos ω1t + B cos ω2t, the output can be written in terms of all harmonics of the form mω1+nω2, where both m and n are positive and negative integers. The “order” of the distortion products can then be defined by order = m + n

(3.23)

To demonstrate the impact of harmonic and intermodulation distortion, an example is provided in which two test tones (fundamentals), f1 = 100 MHz and f2 = 101 MHz are input to a DUT. (These are just two arbitrarily chosen, close-spaced frequencies, and could have been in any frequency range, that is, 1 MHz, 1 GHz.) The same methodology follows for all frequencies. Table 3.1 summarizes all of the harmonic and intermodulation distortion products that have been discussed. Table 3.2 shows the distortion products that arise due to the chosen test frequencies discussed earlier. Depending on the type of architecture of the device, this table shows how the various types of distortion impact it.


47

Table 3.1 Two-Tone Harmonic and Intermodulation Distortion Products and Their Locations

Number of Distortion Products Order

Distortion Product Frequencies (Relative to Fundamental Two-Tone Input, f1 and f2)

Total Harmonic Intermodulation Harmonic Intermodulation

2

4

2

2

2f1, 2f2

f 1 + f 2, f 2 – f 1

3

6

2

4

3f1, 3f2

2f1 ± f2, 2f2 ± f1

4

8

2

6

4f1, 4f2

2f1 ± 2f2, 2f2 – 2f1, 3f1 ± f2, 3f2 ± f1

5

10

2

8

5f1, 5f2

3f1 ± 2f2, 3f2 ± 2f1, 4f1 ± f2, 4f2 ± f1

6

12

2

10

6f1, 6f2

3f1 ± 3f2, 3f2 – 3f1, 5f1 ± f2, 5f2 ± f1, 4f1 ± 2f2, 4f2 ± 2f1

7

14

2

12

7f1, 7f2

4f1 ± 3f2, 4f2 ± 3f1, 5f1 ± 2f2, 5f2 ± 2f1, 6f1 ± f2, 6f2 ± f1

N

2N

2

2N – 2

Nf1, Nf2

Table 3.2 Location of Distortion Products for Input Tones of 100 and 101 MHz Frequency of Distortion Product (MHz) Order Harmonic

Intermodulation

2

200, 202

1, 201

3

300, 303

99, 102, 301, 302

4

400, 404

2, 199, 203, 401, 402, 403

5

500, 505

98, 103, 299, 304, 501, 502, 503, 504

6

600, 606

3, 198, 204, 399, 400, 405, 601, 603, 604, 605

7

700, 707

97, 104, 298, 305, 499, 506, 701, 702, 703, 704, 705, 706

Harmonic distortion products are found at much higher frequencies and, as discussed earlier, are mostly only of concern to neighboring channels or frequency bands. If necessary, filtering can remove their presence. Intermodulation distortion products affect devices quite differently. In the case of heterodyne transceiver architectures, the odd-order intermodulation products are of concern. In the case of more recent usage of homodyne (ZIF) architectures, the even-order products are of more concern because they arise in the baseband signals (near dc) where filtering is not often possible for the intended signal would be filtered out.

48

3.6.5


Intermodulation Distortion Products of a ZIF Receiver

Consider a two-tone test signal applied to the input of an RF-to-baseband front-end ZIF receiver. In this DUT, the input RF signal is downconverted directly to a baseband analog signal. In the case of second-order intermodulation distortion, Table 3.1 can be used to show that a second-order product exists at f 1MD2 = f tone1 − f tone2

(3.24)

For the calculations showing the impact of third-order intermodulation distortion products, it is now necessary to consider the LO frequency used in downconverting the signals. As an example, one of the third-order products falls at f 1MD3 = 2 f tone2 − f tone1 − f LO

(3.25)

This tone falls in the baseband region and could possibly cause interference with the desired operation in a multichannel environment, if not adequately characterized.

3.7 Measuring Intermodulation Distortion A figure of merit known as the intercept point has been established to describe and quantify intermodulation distortion. It is the point at which the intermodulation distortion product power level equals (intercepts) that of the fundamental. Almost always, the intercept point is beyond the linear operation of the device and, therefore, the intercept point is a fictitious point. The various intercept points are each related to the order of distortion being discussed. For example, the third-order intercept point quantifies third-order intermodulation distortion. The intercept point of a device cannot be measured directly, because it is typically at a very large power level. Instead, the measurement is performed at lower, typical operational power levels and extrapolated to determine the intercept point. The intercept point is always referenced to either the input or output power. This is discussed in Section 3.7.3. 3.7.1

The Intercept Point, Graphically

Figure 3.3 is a plot of the output power from a DUT versus the input power applied to it. The small-signal gain, second-order intercept point (IP2), and third-order intercept point (IP3) are shown on the graph.1 It is of fundamental 1. Traditional RF measurement theory often refers to the third-order intercept point with the abbreviation TOI.


49

IP2

e =3) er (slop

3rd ord

orde r (s l 2nd

Lin

ea

r(

slo

pe

ope

=

=2)

1)

Ouput power (dBm)

IP3

Input power (dBm)

Figure 3.3 Output power versus input power, demonstrating the concept of intercept points.

importance is to observe that, in Figure 3.3, the slope of the small-signal gain is 1. The slope of the second-order intermodulation distortion product power level is 2, and that of the third-order product is 3. This means that with a 1-dB reduction of the input power, the fundamental tone will reduce by 1 dB, whereas the third-order product power will reduce by 3 dB. (The converse is also true.) Notice that it is physically impossible to measure either of the intercept points directly. As the input power is increased toward either fictitious intercept point, the DUT becomes nonlinear. The output signal starts clipping, and the extra energy is diverted into the higher order harmonics. The linear portion of the small-signal gain line must be extended to find the crossing point of the second- and third-order products. Notice that the IP3 point intercepts the linear curve before the IP2 point. The graph highlights that a high IP3 number is desired. The higher the IP3 number, the less distortion the device exhibits under normal operating power levels. 3.7.2

The General Intercept Point Calculation

In a general sense, for any order of intermodulation distortion product, the intercept point (dBm) is calculated by measuring the power levels of the output of a DUT resulting from the application of a two-tone signal. There are many variations of the calculation, but they are all interrelated, as described in next section. One such calculation is

50


IPN = P Fundamental,Output +

(P

Fundamental,Output

− P IMDN

N −1

)

(3.26)

where PFundamental,Output is the power (dBm) of either of the two input tones, N is the order of the distortion product, and PIMDN is the power level (dBm) of the distortion product as measured at the respective frequency at the output of the DUT. Sometimes the value in parentheses in (3.26) is represented as a single variable. Whichever way it is represented, it is simply a difference in power, having units of dBc (dB below “carrier”). Assuming that the frequency response of the device is flat across the frequency spacing of the two tones, the output power of either of the two tones could be used as the value for PFundamental,Output. Extending (3.26), the equation for calculating the second-order intercept point is IP2 = P Fundamental,Output + (P Fundamental,Output − P IMD2

)

(3.27)

and for the third-order intercept point is IP3 = P Fundamental,Output +

(P

Fundamental,Output

2

− P IMD3

)

(3.28)

Keep in mind that the title of this section uses the term calculation. This is done because the intercept point is an indirect measurement where the intermodulation distortion product power level is what is measured, then the intercept point is calculated from that value. Note that PFundamental,Output is the power level of one of the output tones. This assumes that the two tones have power levels equal to each other at the output of the DUT. Often this is not the case. To handle this situation of uneven output power levels of the two tones, the average power between the two tones at the output can be used. Alternatively, both can be used to arrive at two different values of IP3 and then the lower, or worse, value of IP3 is reported.

3.7.3

Input- and Output-Referencing of Intercept Points

Equations (3.26) to (3.28) used the output power levels of the device as the reference point of their calculation. This is the common approach to this calculation. When done in this fashion, the intermodulation products are termed output-referenced. For completeness, these equations can be rewritten as


51

OIP2 = P Fundamental,Output + (P Fundamental,Output − P IMD2

)

(3.29)

and OIP3 = P Fundamental,Output +

(P

Fundamental,Output

− P IMD3

)

2

(3.30)

The only difference between these two sets of equations is the name on the left-hand side of the equations. The standard convention (which is almost always the one that is used) is that the intercept point (regardless of order) for any intermodulation distortion measurements on the transmitter/upconversion chain of a DUT (such as a power amplifier) is output referenced, and for any receiver/downconversion chain of a DUT (such as an LNA) measurements, it is input referenced. The interesting thing is that for a given intercept point measurement, the only difference between input referencing and output referencing is the small-signal gain of the DUT. In practice, the gain can simply be measured, or the equations can be rearranged. In this case gain is represented as G = P Fundamental,Output − P Fundamental, Input

(3.31)

where G is the gain of the DUT (dB) and PFundamental,Output is, again, the power (dBm) of either of the two input tones, but now it is the power that is applied to the DUT. Thus,

)

IIP2 = P Fundamental, Output + (P Fundamental,Output − P IMD2 − G

(3.32)

or

)

(3.33)

) −G

(3.34)

IIP2 = P Fundamental, Input + (P Fundamental,Output − P IMD2 and IIP3 = P Fundamental, Output + or

(P

Fundamental,Output

2

− P IMD3

52


IIP3 = P Fundamental, Input +

(P

Fundamental,Output

− P IMD3

2

)

(3.35)

where IIP indicates input referencing. It must be emphasized that the gain value used in (3.32) and (3.34) has to be the small-signal gain (measured during linear mode of operation of the DUT). If this gain is measured when the device is in compression and used in the calculation of the intercept point, then the intercept points will mistakenly be reported to be worse than their actual values. 3.7.4

Example: Calculating the IP3 of an RF LNA

Consider an RF low-noise amplifier that has had its gain measured as 20 dB. The first step in the distortion measurement is to apply a two-tone signal to the input of the DUT. Consider the two tones to be 2,140.10 and 2,140.30 MHz, with both having a power level of –30 dBm. Using the equations for determining the frequencies of second-order intermodulation distortion products in Table 3.1, these input tones will generate a product at 400 kHz that is very far away from the operational capability of this device, so there is no need to measure IP2. Again, using Table 3.1, a third-order intermodulation distortion product falls at 2140.50 MHz, which is in the operational bandwidth of the LNA and must be measured. The next step is to measure the power of the third-order intermodulation product, PIMD3. In this example, accept that it was measured to be –84 dBm. Because this is an LNA, it would be most appropriate to represent the result as input referenced. Using (3.35), the result is IIP3 = −30 +

( −10 − ( −84 )) 2

= +7 dBm

(3.36)

3.8 Source Intermodulation Distortion The residual intermodulation distortion that is due to the hardware involved in sourcing the two-tone signal (sources, tone combiner circuitry, and so forth) is called source intermodulation distortion (SIMD). Most often, any SIMD contribution comes from poor isolation between the two sources that supply the input tones. It is important to be aware of the amount of this contributed distortion from the measurement setup. To measure the SIMD, simply remove the DUT and connect the two-tone source directly to the measurement equipment and


53

measure the power at the frequencies where the intermodulation distortion products are expected [7]. One would think that this is only of concern in LNA and PA testing where the output of the device is in the same frequency range as the input signals. However, keep in mind that for a frequency-translating device like a front-end receiver, any SIMD will also be downconverted. In many intermodulation distortion measurement setups where multiple power levels need to be applied to the DUT (as in characterizing power-out versus power-in to establish the nonlinear characteristics), attenuators are often used between the two-tone output and the DUT. The reason for this is so that the sources can stay at a constant power level and, hence, a constant value of SIMD. The power levels can be adjusted simply by adjusting the attenuators. This eliminates changes in the source settings and eliminates the possibility of the SIMD changing. The contribution of error due to SIMD can be calculated from the following formula [7]: error = 20 log 10 (1 ± 10 SIMD − MIMD 20 )

(3.37)

where SIMD and MIMD are the relative (dBc) values of intermodulation distortion products at the expected product frequencies for the source and measurement (DUT), respectively. Using this equation, and an error of ±3 dB leads to the rule of thumb that the SIMD should be at least 30 dB below that of the expected DUT IMD. In practice, SIMD of >40 dB below that to be measured is better.

3.9 Cross Modulation Cross modulation, sometimes called XMOD, is a type of distortion caused by the intermodulation/interaction between more than two tones in the same operational bandwidth. Historically, this measurement was not too common except in cable television devices, such as line amplifiers where up to hundreds of simultaneous signals are transmitted across the same wide bandwidth of operation (which can be greater than 1 GHz). Recent multicarrier digital modulation formats, such as orthogonal frequency division multiplexing (OFDM) for WiMAX or WLAN, use multiple carriers within the same bandwidth. This makes them susceptible to the effects of cross-modulation distortion products. Reference [8] provides an in-depth analysis of how cross modulation impacts the performance of CDMA receivers based on transmitter leakage through duplexers into the LNA front end.

54


The measurement of cross modulation is performed by turning on all tones/carriers except one, and then measuring the power at the frequency of the carrier that is not turned on. Any power at this frequency is due to cross modulation between all other carriers.

3.10 Gain Compression

Output power (dBm)

Id

ea

l li

ne

ar

ou

tp

ut

The a1 term of (3.9) is a linear term corresponding to the gain of a DUT. Under lower power level (i.e., small-signal) conditions, the output of the DUT is related to the input by the proportionality factor, or gain a1. As the power level is increased, a distortion mechanism termed gain compression can come into play where the output begins to saturate, no longer following the linear gain. If only the a1 (linear) term of (3.9) is considered and it is converted to logarithmic scale and plotted as in Figure 3.4, the slope of the trace is unity. This plot, however, is that of a real device, which does not follow (3.9) at higher input power levels. At some point, the output power deviates from the unity sloped curve, moving to a saturation region (the dashed line shows the extrapolation of the linear trace). The measure of saturation, which is sometimes called first-order distortion, is gain compression and it is described by the standardized

1 dB compression point

Lin

ea

r(

slo

pe

=1

)

∆ = 1 dB

Actual device output

Input power (dBm)

Figure 3.4 Output power versus input power, demonstrating the concept of gain compression.


55

measure called the 1-dB compression point, or P1dB. While mixers exhibit compression, the measurement was traditionally most often made on amplifiers; hence, the term “gain” compression. Wireless devices must operate over a wide dynamic range. The upper bound of the dynamic range is often specified with the 1-dB compression point. P1dB can be referenced to the input power level or the output power level (the projections onto the input or output axes of Figure 3.4). These are termed input referred and output referred, respectively. The P1dB of receivers are usually input referred, and the P1dB of transmitters are usually output referred. The equation describing the gain, in dB, at the 1-dB compression point is G 1 dB = G 0 − 1

(3.38)

where G0 is small-signal gain. The output power can be rewritten in terms of the compression as follows: P1 dB ( output ) − P1 dB ( input ) = G 1 dB = (G 0 − 1)

(3.39)

Given (3.39), the 1-dB compression point can be found by measuring the difference in the output power minus the input power. When that difference is 1 dB less than the small-signal gain, the 1-dB compression point has been determined. For production testing, test time must be considered. The 1-dB compression point can be found using a brute-force approach whereby the input power starts at a low level and is linearly swept upward in small steps, until the 1-dB compression point is found. A much more efficient method is the one in which, first, the gain is measured at a power level where the DUT is known to be linear. Then, a binary search routine is used to vary the input power to find the 1-dB compression point within some stated resolution. A variation on gain compression that is often used in production testing of wireless SoC devices is to operate the DUT at the P1dB point and then to perform another type of measurement. An example, using a Bluetooth device, is to overdrive the receiver to the 1-dB compression point and perform a bit error rate (BER) test under this condition to ensure integrity. To show that the input-referred and output-referred compression points are related, consider a DUT with nominal small-signal gain of 28 dB that has had the input-referred P1dB point determined to be –19 dBm. Rearranging (3.39), P1 dB ( output ) = P1dB ( input ) + G 1dB = −19 + 28 − 1 = 8 dBm

(3.40)

56


3.10.1 Conversion Compression in Frequency-Translating Devices

A mixer, although considered a nonlinear device, has the same compression behavior. The only difference is that the input and output of the mixer, taken to be RF and IF, respectively (for example), are at different frequencies. The same algorithms apply, using power measurements at the RF and IF ports of the DUT. As RF input power is increased, IF output power increases. However, at some power level, the IF output power begins to increase at a lesser rate than the RF input power, and eventually the IF power level deviates from its linearly expected value by 1 dB. This point is the conversion compression point.

3.11 Minimizing the Number of Averages in Distortion Measurements Many distortion measurements involve measuring low-level signals and comparing them to a high-level (e.g., carrier) signal. A common mistake in production measurements is to set up the entire measurement hardware for the needs of the low-level signal acquisition. Consider that a low-level distortion signal such as the third-order product can, at times, be very near to the measuring equipment’s noise floor. Often, the inclination is to set up the entire measurement to accurately acquire the low-level signal. This can require multiple averages and oversampling. If N is taken to be the number of averages, then the test time can be increased, linearly, up to N times the single acquisition test time. For the low-level signal, it could be necessary to do this. However, doing this for the acquisition of the high-level signal, which is significantly above the measurement noise floor, leads to wasted test time and, ultimately, increased cost.

References [1]

Oliver, B., “Distortion and Intermodulation,” Hewlett Packard Application Note 15.

[2]

Pozar, D. M., Microwave Engineering, Reading, MA: Addison-Wesley, 1990.

[3]

Schaub, K., and J. Kelly, Production Testing of RF and System-on-a Chip Devices for Wireless Communications, Norwood, MA: Artech House, 2004.

[4]

“Theory of Intermodulation Distortion Measurement (IMD),” Maury Microwave Application Note 5C-043, 1999.

[5]

Texas Instruments, “Understanding and Enhancing Sensitivity in Receivers for Wireless Applications,” Technical Brief SWRA030, 1999.

[6]

Bain, D., “RF Distortion: Reducing IM Distortion in CDMA Cellular Telephones,” RF Design, December 1996, pp. 46–53.


57

[7]

Barkley, K., “Two-Tone IMD Measurement Techniques,” RF Design, June 2001, pp. 36–52.

[8]

Ko, B., et al., “A Nightmare for CDMA RF Receiver: The Cross Modulation,” Proc. First IEEE Asia Pacific Conf. on ASICs, August 23–25, 1999, pp. 400–402.

4 Tests and Measurements III: Noise 4.1 Introduction to Noise Noise is unwanted fluctuations superimposed on a desired signal. Noise determines the accuracy and repeatability with which we can measure the signal. During the past few years, improvements in the performance of wireless communications systems have led to the need for tighter specification limits on noise and, thus, a better understanding of it. Noise is an unfortunate entity that will always be present when performing measurements, for example, an amplifier’s output power level is dominated by the noise of the amplifier at very low input power levels [1]. Typically, noise is associated with being undesirable, and that is the case when noise interferes with a particular parameter that one is attempting to measure, such as a current or voltage signal. In this case noise disrupts the accuracy of the measurement. However, when working with very low-level signals in wireless communications, the need to measure noise levels makes understanding noise desirable. Noise figure and phase noise are two parameters of wireless and SoC devices that warrant an understanding of the behavior of noise. 4.1.1

Power Spectral Density

Noise, being a random process, is characterized as nondeterministic. As a result, when analyzing noise in either the time or frequency domain, statistical approaches must be used. At RF frequencies the analysis is best accomplished using frequency-domain analysis; hence, this discussion will focus on that. The seemingly obvious approach to characterizing noise in the frequency domain is to simply take the Fourier transform of the noise signal. However, 59

60


this is not possible because the random noise waveform cannot be defined as a simple exact time-domain function. To solve this problem, the power spectral density (PSD) is introduced as Sx (f

) = Tlim →∞

[

E XT (f

)

2

]

2T

(4.1)

where E is the expected value and XT(f ) is the Fourier transform of a random noise waveform, x(t), evaluated over the time interval –T < t < T [2]. An alternative definition states the PSD as being the plot of power of a signal as a function of frequency as shown in Figure 4.1. The power within a certain frequency range is calculated as follows: f2

P f1

f2

= ∫ S x f ( x )df

(4.2)

f1

The total power in a signal is calculated by integrating over all frequencies: ∞

Ptotal =

∫S

x

f ( x )df = x 2 (t )

(4.3)

−∞

where x 2 (t ) is a voltage or current signal and Ptotal is stated as the power across a 1-Ω resistor. As a result of this definition, the units of PSD are volts2/Hz (or

Figure 4.1 Power spectral density for a Gaussian distributed signal.


61

more commonly, dBm/Hz when discussing RF frequencies, specifically), which makes specifying the bandwidth a necessity when stating the power of a noise waveform. PSD will be used in the following sections to describe the characteristics of different types of noise. The concepts of PSD are also used when discussing noise figure and phase noise measurements. 4.1.2

Types of Noise

Noise can arise for many reasons. However, within the context of making electronic measurements, noise can be grouped into two types, fundamental and nonfundamental. Fundamental noise consists of that known as “white” noise, thermal noise, shot noise, quantization noise, and 1/f noise. Additionally, in test and measurement systems, nonfundamental noise can arise from electromagnetic coupling, cooling-induced current flow in semiconductors, ground loops due to differing potential reference points, or oscillations in amplifiers. The principal difference between these two noise types is that nonfundamental noise can be reduced or eliminated, but fundamental noise cannot. The figure of merit, noise figure, when measured at RF frequencies, encompasses mainly shot and thermal noise. Noise exists in many forms, but within the context of testing, the following are the dominant types and their relevance to testing will be discussed briefly: • Thermal noise; • Shot noise; • 1/f noise; • Quantization noise; • Quantum noise; • Plasma noise. 4.1.2.1 Thermal Noise

Thermal noise (Johnson noise) is broadband noise resulting from the random motion of electrons due to temperature. The kinetic energy of this random motion is proportional to temperature. This random motion of electrons (charge) produces a voltage across a resistance. It is usually the dominant fundamental noise found in circuits at room temperature. It was discovered by Johnson [3] and the mathematical description was derived by Nyquist [4]. As line a in Figure 4.2 shows, thermal noise is of the general class of “white” noise described by equal PSD per hertz and flat energy across the entire frequency spectrum. White noise gets its name from the analogy with white


Power (dBm)

62

c b a

Frequency (Hz)

Figure 4.2 Power spectral density of various types of noise: (a) thermal noise, (b) shot noise, and (c) 1/f noise.

light, which also has equal power density across all frequencies in the optical band. True white noise cannot exist, because by definition it would require infinite bandwidth, which would also imply infinite energy. A practical description of white noise considers the noise to have a flat power density over some finite bandwidth. Because the power density of white noise is flat, it is by definition independent of frequency. This means that white noise signal power, for a given bandwidth, does not vary, no matter what center frequency is chosen, across the entire frequency spectrum. Therefore, white noise in one part of the spectrum is uncorrelated with white noise in another part of the spectrum. A few fundamental equations describing thermal noise must be introduced at this point. These are the foundation for noise figure measurements to be discussed later. In 1928 Nyquist derived a formula to describe thermal noise: v 2 = 4 hfBR

[e

hf kt

− 1]

(4.4)

where v 2 is the mean-square open-circuit thermal noise voltage across a resistor, h is Planck’s constant (6.626 × 1034 J-sec), f is frequency (in hertz), k is Boltzmann’s constant (1.38 × 10–23 J/K), T is absolute temperature (in kelvin), R is resistance (in ohms), and B is the bandwidth (in hertz) over which the noise is measured. The derivation of this equation involves extensive statistical thermodynamics and is beyond the scope of this book. Equation (4.4) is valid for any frequency, however it is often tedious to work with. Considering that, at microwave frequencies, hf < kT, the first two terms of a Taylor series expansion can be substituted into (4.4) as


e hf

kT

63

− 1~ hf kT

(4.5)

Substituting (4.5) into (4.4) leads to v 2 = 4 kTBR

(4.6)

which is no longer valid over the entire frequency spectrum, due to the approximation of (4.5). However, for most microwave/RF work, the approximation and (4.6) are valid and a lot easier to work with. As a worst-case example, consider the case where f = 100 GHz and T = 100K. In this case, hf (6.5 × 10–23) is still 100 times less than kT (1.4 × 10–21). Almost all RF noise calculations are based on (4.6), which is called the Rayleigh-Jeans approximation and is valid unless very high frequencies or very low temperatures are used. Consider a noise resistor delivering some noise power, Pn, to a load resistor, of equal resistance (for maximum power transfer) as shown in Figure 4.3. Using the voltage in (4.6), the noise power, in bandwidth B, delivered to the load resistor is calculated as follows: Pn = i 2R

(4.7a) 2

 v  Pn =   R  2R 

(4.7b)

P n = kTB

(4.7c)

Solving (4.7c) for Pn at room temperature (typically accepted to be T = 290K) gives Pn = 400.2 × 10–23 W in a 1-Hz bandwidth. Placing this into more useful units gives Pn = –174 dBm in a 1-Hz bandwidth, or Pn = –174 dBm/Hz.

Pn

R Noisy resistor

R vn

Figure 4.3 Lumped-element noisy resistor circuit.

64


This is theoretically the lowest possible noise level of any system at room temperature because this value is based solely on kinetic energy due to thermal agitation of the molecules that make up matter. Note also that (4.7c) is completely independent of frequency. Thermal noise power is dependent only on temperature and bandwidth. 4.1.2.2 Shot Noise

Shot noise, also known as Schottky noise (because Schottky described it mathematically in 1928 [5]), is noise due to random fluctuations of charge carriers across a potential barrier in electronic devices. Typically electrical current charge carriers are electrons, which can be considered moving in a flow on a microscopic level. Because electrical current flow can be considered to be comprised of discrete particles, there is some random fluctuation in their movement through an electronic device. The power spectral density of shot noise is approximately broadband and flat as shown in Figure 4.2(b). The word approximately is used because there is a roll off of this type of noise at approximately 1015 Hz because the charge carriers have a finite travel time within the device. For the frequencies of interest in RF and SoC testing (

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