Advanced MEMS Packaging (Electronic Engineering)

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Author: John Lau | Cheng Lee | C. Premachandran | Yu Aibin

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Advanced MEMS Packaging

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Advanced MEMS Packaging John H. Lau Chengkuo Lee C. S. Premachandran Yu Aibin

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Copyright © 2010 by The McGraw-Hill Companies, Inc. All rights reserved. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. ISBN: 978-0-07-162792-4 MHID: 0-07-162792-8 The material in this eBook also appears in the print version of this title: ISBN: 978-0-07-162623-1, MHID: 0-07-162623-9. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps. McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. To contact a representative please e-mail us at [email protected]. Information contained in this work has been obtained by The McGraw-Hill Companies, Inc. (“McGraw-Hill”) from sources believed to be reliable. However, neither McGraw-Hill nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw-Hill nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw-Hill and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc. (“McGraw-Hill”) and its licensors reserve all rights in and to the work. Use of this work is subject to these terms. Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent. You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited. Your right to use the work may be terminated if you fail to comply with these terms. THE WORK IS PROVIDED “AS IS.” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. McGraw-Hill and its licensors do not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free. Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom. McGraw-Hill has no responsibility for the content of any information accessed through the work. Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages. This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise.

About the Authors John H. Lau earned a Ph.D. in theoretical and applied mechanics from the University of Illinois. He has also earned three master’s degrees. He currently is a visiting professor at the Hong Kong University of Science & Technology (HKUST). His research interests cover a broad range of enabling technologies for 3D IC and system-in-package integration for RoHS-compliant electronics, optoelectronics, photonics, and MEMS packaging. Prior to joining HKUST, Dr. Lau was the director of the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics in Singapore for 2 years and a Senior Scientist/MTS at Agilent/Hewlett-Packard in California for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has authored or co-authored more than 400 peer-reviewed technical publications, books, book chapters, and papers. Dr. Lau has received awards from ASME and IEEE, and is a Fellow of both organizations. Chengkuo Lee received a Ph.D. in precision engineering from the University of Tokyo, and has also earned two master’s degrees. He worked as a researcher in several labs and then managed the MEMS device division at the Metrodyne Microsystem Corporation in Taiwan. Dr. Lee co-founded Asia Pacific Microsystems, Inc., in Taiwan, and served as vice president. He is now an assistant professor in the Department of Electrical and Computer Engineering at National University of Singapore and a senior member of the technical staff at the Institute of Microelectronics in Singapore. He has authored or co-authored about 200 conference papers, extended abstracts, and peer-reviewed journal articles, and holds eight U.S. patents in the MEMS and nanotechnology fields. C. S. Premachandran earned a master of technology degree in solid state technology from the Indian Institute of Technology, Madras. He has held managerial/ executive positions at Indian Telephone Industries, Sun Fiber Optics, and Delphi Automotive Systems. Since 1998 he has worked as a member of the technical staff in

the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics, Singapore. He has authored or co-authored more than 50 conference papers and journal articles and holds 10 U.S. patents. He is a Senior Member of IEEE. His research interests are in MEMS and biosensor, optical, and advanced packaging. Yu Aibin received a Ph.D. in electrical and electronic engineering from Nanyang Technological University in Singapore. He is a senior research engineer in the Microsystems, Modules, and Components Laboratory at the Institute of Microelectronics in Singapore. His research interests include advanced packaging and MEMS design, fabrication, and packaging. Dr. Yu has authored or co-authored more than 60 technical publications.

Contents Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi 1

2

3

Introduction to MEMS . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Commercial Applications of MEMS . . . . . . . . 1.3 MEMS Markets . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Top 30 MEMS Suppliers . . . . . . . . . . . . . . . . . . 1.5 Introduction to MEMS Packaging . . . . . . . . . . 1.6 MEMS Packaging Patents since 2001 . . . . . . . 1.6.1 U.S. MEMS Packaging Patents . . . . . 1.6.2 Japanese MEMS Packaging Patents . . . 1.6.3 Worldwide MEMS Packaging Patents . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 2 2 5 5 6 6 21

Advanced MEMS Packaging . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Advanced IC Packaging . . . . . . . . . . . . . . . . . . 2.2.1 Moore’s Law versus More Than Moore (MTM) . . . . . . . . . . . . . . . . . . . 2.2.2 3D IC Integration with WLP . . . . . . . 2.2.3 Low-Cost Solder Microbumps for 3D IC SiP . . . . . . . . . . . . . . . . . . . . 2.2.4 Thermal Management of 3D IC SiP with TSV ....................... 2.3 Advanced MEMS Packaging . . . . . . . . . . . . . . 2.3.1 3D MEMS WLP: Designs and Materials . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 3D MEMS WLP: Processes . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47 47 47

Enabling Technologies for Advanced MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 TSVs for MEMS Packaging . . . . . . . . . . . . . . . 3.2.1 Via Formation . . . . . . . . . . . . . . . . . . . 3.2.2 Dielectric Isolation Layer (SiO2) Deposition . . . . . . . . . . . . . . . . . . . . . .

27 43

47 49 52 58 67 68 72 76 81 81 81 82 86

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Contents 3.2.3

3.3

3.4

3.5

3.6

3.7

Barrier/Adhesion and Seed Metal Layer Deposition . . . . . . . . . . . . . . . . . 3.2.4 Via Filling . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Cu Polishing by Chemical/ Mechanical Polish (CMP) . . . . . . . . . 3.2.6 Fabrication of an ASIC Wafer with TSVs ...................... 3.2.7 Fabrication of Cap Wafer with TSVs and Cavity . . . . . . . . . . . . . . . . . Piezoresistive Stress Sensors for MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Design and Fabrication of Piezoresistive Stress Sensors . . . . . . . 3.3.2 Calibration of Stress Sensors . . . . . . . 3.3.3 Stresses in Wafers after Mounting on a Dicing Tape . . . . . . . . . . . . . . . . . 3.3.4 Stresses in Wafers after Thinning (Back-Grinding) . . . . . . . . . . . . . . . . . . Wafer Thinning and Thin-Wafer Handling . . . . 3.4.1 3M Wafer Support System . . . . . . . . . 3.4.2 EVG’s Temporary Bonding and Debonding System . . . . . . . . . . . . . . . 3.4.3 A Simple Support-Wafer Method for Thin-Wafer Handling . . . . . . . . . . . . . Low-Temperature Bonding for MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 How Does Low-Temperature Bonding with Solders Work? . . . . . . . . . . . . . . . 3.5.2 Low-Temperature C2C Bonding . . . . 3.5.3 Low-Temperature C2W Bonding . . . 3.5.4 Low-Temperature W2W Bonding . . . . MEMS Wafer Dicing . . . . . . . . . . . . . . . . . . . . . 3.6.1 Fundamentals of SD Technology . . . 3.6.2 Dicing of SOI Wafers . . . . . . . . . . . . . 3.6.3 Dicing of Silicon-on-Silicon Wafers . . . 3.6.4 Dicing of Silicon-on-Glass Wafers . . . RoHS-Compliant MEMS Packaging . . . . . . . . 3.7.1 EU RoHS . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 What Is the Definition of X-Free (e.g., Pb-Free)? .................. 3.7.3 What Is a Homogeneous Material? . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 What Is the TAC? . . . . . . . . . . . . . . . . 3.7.5 How Is a Law Published in the EU RoHS Directive? . . . . . . . . . . . . . . . . .

87 89 91 92 93 93 93 95 98 101 104 104 105 108 111 112 113 122 124 126 126 129 130 130 133 133 134 134 135 135

Contents 3.7.6 3.7.7 3.7.8 References 4

5

EU RoHS Exemptions . . . . . . . . . . . . Current Status of RoHS Compliance in the Electronics Industry . . . . . . . . . Lead-Free Solder-Joint Reliability of MEMS Packages . . . . . . . . . . . . . . . . . ..................................

Advanced MEMS Wafer-Level Packaging . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Micromachining, Wafer-Bonding Technologies, and Interconnects . . . . . . . . . . . 4.2.1 Thin-Film Technologies . . . . . . . . . . . 4.2.2 Bulk Micromachining Technologies . . . . . . . . . . . . . . . . . . . . 4.2.3 Conventional Wafer-Bonding Technologies for Packaging . . . . . . . . 4.2.4 Plasma-Assisted Wafer-Bonding Technologies . . . . . . . . . . . . . . . . . . . . 4.2.5 Electrical Interconnects . . . . . . . . . . . 4.2.6 Solder-Based Intermediate-Layer Bonding . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Wafer-Level Encapsulation . . . . . . . . . . . . . . . 4.3.1 High-Temperature Encapsulation Process . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Low-Temperature Encapsulation Process . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Wafer-Level Chip Capping and MCM Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Wafer-Level MEMS Packaging Based on Low-Temperature Solders: Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Case Study: In/Ag System of Noneutectic Composition . . . . . . . . . 4.5.2 Case Study: Eutectic InSn Solder for Cu-Based Metallization . . . . . . . . . . . 4.6 Summary and Future Outlook . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optical MEMS Packaging: Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Actuation Mechanisms and Integrated Micromachining Processes . . . . . . . . . . . . . . . . 5.2.1 Electrostatic Actuation . . . . . . . . . . . . 5.2.2 Thermal Actuation . . . . . . . . . . . . . . . 5.2.3 Magnetic Actuation . . . . . . . . . . . . . .

135 138 138 149 157 157 158 158 159 168 172 172 175 176 177 178 180

182 183 193 202 203 209 209 211 212 215 219

ix

x

Contents 5.2.4 5.2.5

Piezoelectric Actuation . . . . . . . . . . . . Integrated Micromachining Processes . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Optical Switches . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Small-Scale Optical Switches . . . . . . . 5.3.2 Large-Scale Optical Switches . . . . . . 5.4 Variable Optical Attenuators . . . . . . . . . . . . . . 5.4.1 Early Development Work . . . . . . . . . 5.4.2 Surface-Micromachined VOAs . . . . . 5.4.3 DRIE-Derived Planar VOAs Using Electrostatic Actuators . . . . . . . . . . . . 5.4.4 DRIE-Derived Planar VOAs Using Electrothermal (Thermal) Actuators . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 3D VOAs . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 VOAs Using Various Mechanisms . . . . . . . . . . . . . . . . . . . . . 5.5 Packaging, Testing, and Reliability Issues . . . . 5.5.1 Manufacturability and Self-Assembly . . . . . . . . . . . . . . . . . . . 5.5.2 Case Study: VOAs . . . . . . . . . . . . . . . . 5.5.3 Case Study: Optical Switches . . . . . . 5.6 Summary and Future Outlook . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Optical MEMS Packaging: Bubble Switch . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 3D Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Boundary-Value Problem . . . . . . . . . . . . . . . . . 6.3.1 Geometry . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Materials . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Boundary Conditions . . . . . . . . . . . . . 6.4 Nonlinear Analyses of the 3D Photonic Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Creep Hysteresis Loops . . . . . . . . . . . 6.4.2 Deflections . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Shear-Stress Time-History . . . . . . . . . 6.4.4 Shear-Creep-Strain Time-History . . . 6.4.5 Creep-Strain Energy-Density Range . . . . 6.5 Isothermal Fatigue Tests and Results . . . . . . . 6.5.1 Sample Preparation . . . . . . . . . . . . . . 6.5.2 Test Setup and Procedures . . . . . . . . . 6.5.3 Test Results . . . . . . . . . . . . . . . . . . . . . 6.6 Thermal Fatigue Life Prediction of the Sealing Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . .

219 221 224 225 233 237 238 240 242

252 254 258 261 264 269 275 285 286 297 297 297 302 302 302 305 306 306 307 307 307 308 309 309 309 312 314

Contents 6.7 Appendix A: Package Deflection by Twyman-Green Interferometry Method . . . . 6.7.1 Sample Preparation . . . . . . . . . . . . . . 6.7.2 Test Setup and Procedure . . . . . . . . . 6.7.3 Temperature Conditions . . . . . . . . . . 6.7.4 Measurement Results . . . . . . . . . . . . . 6.8 Appendix B: Package Deflection by Finite-Element Method . . . . . . . . . . . . . . . . . . . 6.9 Appendix C: Finite-Element Modeling of the Bolt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 Description of the Bolted Model . . . . 6.9.2 Responses of the Bolted Photonic Switch . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8

Optical MEMS: Microbolometer Packaging ..... 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Bolometer Chip . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Thermal Optimization . . . . . . . . . . . . . . . . . . . 7.3.1 Final Temperature Stability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Structural Optimization of the Package .... 7.5 Vacuum Packaging of Bolometer . . . . . . . . . . 7.5.1 Ge Window . . . . . . . . . . . . . . . . . . . . . 7.6 Getter Attachment and Activation . . . . . . . . . 7.7 Outgassing Study in a Vacuum Package . . . . 7.8 Testing Setup for Bolometer . . . . . . . . . . . . . . . 7.8.1 Package Testing . . . . . . . . . . . . . . . . . . 7.8.2 Image Testing . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bio-MEMS Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Bio-MEMS Chip ........................ 8.3 Microfluidic Components . . . . . . . . . . . . . . . . 8.3.1 Microfluidic Cartridge . . . . . . . . . . . . 8.3.2 Biocompatible Polymeric Materials . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Microfluidic Packaging .................. 8.4.1 Polymer Microfabrication Techniques . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Replication Technologies . . . . . . . . . . 8.4.3 Overview of Existing DNA and RNA Extractor Biocartridges . . . . . . . 8.5 Fabrication of PDMS Layers . . . . . . . . . . . . . . 8.6 Assembly of PDMS Microfluidic Packages . . .

314 315 316 317 317 317 320 320 322 325 327 327 329 330 334 335 340 342 344 346 347 347 350 352 353 353 355 357 357 359 362 362 362 363 364 364

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Contents 8.6.1

Microfluidic Package without Reservoirs . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Development of Reservoir and Valve . . . . . . . . . . . . . . . . . . . . . . . 8.7 Self-Contained Microfluidic Cartridge ..... 8.7.1 Microfluidic Package with Self-Contained Reservoirs . . . . . . . . . 8.7.2 Pin-Valve Design . . . . . . . . . . . . . . . . . 8.7.3 Fluid Flow-Control Mechanism . . . . 8.8 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 Substrate Fabrication . . . . . . . . . . . . . 8.8.2 Material Selection for the Reservoir Membrane . . . . . . . . . . . . . . . . . . . . . . 8.9 Permeability of Material . . . . . . . . . . . . . . . . . . 8.10 Thermocompression Bonding . . . . . . . . . . . . . 8.10.1 Bonding of PMMA to PMMA for the Channel Layer . . . . . . . . . . . . . . . . . . . 8.10.2 Polypropylene to PMMA for Reservoir and Channel Layer . . . . . . 8.10.3 Tensile Test . . . . . . . . . . . . . . . . . . . . . . 8.11 Microfluidic Package Testing . . . . . . . . . . . . . . 8.11.1 Fluid Testing . . . . . . . . . . . . . . . . . . . . 8.11.2 Biologic Testing on a Biosample . . . . 8.12 Sample Preparation and Setup . . . . . . . . . . . . 8.12.1 Pretreatment of the Cartridge ..... 8.12.2 PCR Amplification . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Biosensor Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Review of Optical Coherence Tomography (OCT) . . . . . . . . . . . . . . 9.2 Biosensor Packaging .................... 9.2.1 Micromirror . . . . . . . . . . . . . . . . . . . . . 9.2.2 Single-Mode Optical Fiber and GRIN Lens . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Upper Substrate . . . . . . . . . . . . . . . . . 9.2.4 Lower Substrate . . . . . . . . . . . . . . . . . 9.3 The Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Configuration of the Probe . . . . . . . . 9.3.2 Optical Properties and Theories ... 9.3.3 Evaluations of Parameters . . . . . . . . . 9.4 Optical Simulation . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Optical Model of the Probe . . . . . . . . 9.4.2 Effect of Mirror Curvature on Coupling Efficiency . . . . . . . . . . . . . .

366 370 371 371 374 375 377 377 381 381 384 385 387 390 391 391 392 394 394 394 395 397 397 398 401 401 401 403 404 404 404 406 410 412 412 415

Contents 9.4.3 Effect of Lateral Tilt of a Flat Micromirror on a Curved Sample . . . . 9.4.4 Effect of Vertical Tilt of a Flat Micromirror on a Curved Sample . . . 9.4.5 Effect of Vertical Tilt of a Flat Micromirror on a Flat Sample . . . . . . 9.5 Assembly of the Optical Probe . . . . . . . . . . . . 9.5.1 Fabrication of SiOB . . . . . . . . . . . . . . . 9.5.2 Probe Assembly . . . . . . . . . . . . . . . . . . 9.5.3 Probe Housing .................. 9.6 Testing of the Probe ..................... 9.6.1 Optical Alignment . . . . . . . . . . . . . . . 9.6.2 Axial Scanning Test Result . . . . . . . . . 9.6.3 Probe Imaging .................. 9.6.4 Optical Efficiency Testing . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

11

Accelerometer Packaging . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Wafer-Level Package Requirements ....... 10.2.1 Electrical Modeling . . . . . . . . . . . . . . . 10.2.2 Package Structure . . . . . . . . . . . . . . . . 10.2.3 Extraction Methodology of the Interconnection Characteristics . . . . . 10.3 Wafer-Level Packaging Process . . . . . . . . . . . . 10.3.1 Method 1: TSV with Sacrificial Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Method 2: TSV without Sacrificial Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Method 3: TSV with MEMS Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Wafer Separation Process . . . . . . . . . . . . . . . . . 10.4.1 Process Integration . . . . . . . . . . . . . . . 10.5 Sacrificial Wafer Removal . . . . . . . . . . . . . . . . 10.6 Wafer-Level Vacuum Sealing ............. 10.7 Vacuum Measurement Using a MEMS Motion Analyzer ....................... 10.8 Reliability Testing: Vacuum Maintenance ... 10.9 Wafer-Level 3D Package for an Accelerometer . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radiofrequency MEMS Switches . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Design of RF MEMS Switches . . . . . . . . . . . . . 11.2.1 Design of Capacitive Switches . . . . .

417 419 420 421 421 422 425 427 427 427 429 431 433 435 435 437 438 438 442 448 450 450 452 458 460 462 464 467 469 471 473 475 475 475 475

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Contents 11.2.2 Design of Metal-Contact Switches . . . . 11.2.3 Mechanical Design of RF MEMS Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Fabrication of RF MEMS Switches . . . . . . . . . 11.3.1 Surface Micromachining of RF MEMS Switches . . . . . . . . . . . . . . . . . . 11.3.2 Bulk Micromachining of RF MEMS Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Characterization of RF MEMS Switches . . . . 11.4.1 RF Performance . . . . . . . . . . . . . . . . . . 11.4.2 Mechanical Performance . . . . . . . . . . 11.5 Reliability of RF MEMS Switches . . . . . . . . . . 11.5.1 Reliability of Capacitive Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 Reliability of Metal-Contact Switches . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13

RF MEMS Tunable Capacitors and Tunable Band-Pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 RF MEMS Tunable Capacitors . . . . . . . . . . . . 12.2.1 Analog Tuning of RF MEMS Capacitors . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Digital Tuning of RF MEMS Capacitors . . . . . . . . . . . . . . . . . . . . . . 12.3 RF MEMS Tunable Band-Pass Filters . . . . . . . 12.3.1 Analog Tuning of a MEMS Band-Pass Filter . . . . . . . . . . . . . . . . . . 12.3.2 Digital Tuning of an RF MEMS Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

479 479 484 484 488 489 489 489 492 492 492 492 493 495 495 495 496 503 504 505 506 512 513

Advanced Packaging of RF MEMS Devices . . . . . 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Zero-Level Packaging . . . . . . . . . . . . . . . . . . . . 13.2.1 Chip Capping . . . . . . . . . . . . . . . . . . . 13.2.2 Thin-Film Capping . . . . . . . . . . . . . . . 13.3 One-Level Packaging . . . . . . . . . . . . . . . . . . . . 13.4 Reliability of Packaged RF MEMS Devices . . . 13.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

515 515 515 516 523 525 526 528 528

Index

531

.......................................

Foreword

T

he invention of the bipolar junction transistor and the junction field-effect transistor by Bardeen, Brattain, and Shockley in 1956 foreshadowed the development of generations of smart phones and computers yet to come. The invention of the silicon integrated circuit (IC) by Jack Kilby of Texas Instruments in 1958 and 6 months later by Robert Noyce of Fairchild Semiconductor excited the development of generations of integrations. The proposal of doubling the number of transistors on an IC every 24 months by Gordon Moore in 1965 (also called Moore’s law) has been the most powerful driver for the development of the microelectronic industry in the past 44 years. This law emphasizes lithography scaling and integration (in two dimensions) of all functions on a single chip, through system-on-chip (SoC). Apart from SoC, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, three-dimensional IC integration, which can be called “more than Moore.” Based on siliconplatform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment is known as more than Moore. Microelectromechanical systems (MEMS) is a part of it. Yole Development forecasted the MEMS market to be $14 billion by 2012. The packaging cost of MEMS products in general is about 70 percent. Thus MEMS packaging could be a $10 billion market by 2012. Unlike electronics IC packaging, MEMS packaging is custombuilt and difficult due to the moving structural elements. For some MEMS devices, such as resonators, infrared bolometers, and gyroscopes, vacuum packaging is required. For most researchers and engineers, advanced MEMS packaging is the least understood of all. Thus, there is an urgent need to generate a comprehensive book on the current state of knowledge in the design, materials, process, manufacturing, and reliability of advanced MEMS packaging technology. Institute of Microelectronics (IME), Singapore, one of the research institutes of the Agency for Science, Technology and Research (A∗STAR), has been publishing MEMS papers extensively in a wide spectrum

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Foreword of journals, conference proceedings, symposia, and workshops. However, there is no single comprehensive compilation of information devoted to state-of-the-art advanced MEMS packaging. This book is written for everyone who can quickly learn about the basics and problem-solving methods, understand the trade-offs, and make system-level decisions. John Lau, Chengkuo Lee, C. S. Premachandran, and Yu Aibin of IME have taken the time and made the effort to complete this book on this timely topic of advanced MEMS packaging. This book will help focus the attention of practicing engineers and research scientists, as well as faculty and students, on the complex MEMS packaging challenges that must be overcome. I wish that this book will serve future generations of engineers, scientists, and students who will continue to advance the science and engineering of MEMS packaging. With their predecessors’ knowledge and their creativity, there is no doubt this wish will come true. Professor Dim-Lee Kwong Executive Director Institute of Microelectronics Singapore

Preface

T

he last decade witnessed an explosive growth in research and development efforts devoted to advanced microelectromechanical systems (MEMS) packaging as a direct result of higher requirements for package footprint, density, and performance and cost advantages over conventional MEMS packages. For the next decade, MEMS devices and packaging will penetrate into IT, telecommunications, automotive, life sciences, medical, and implantable applications. However, like many other new technologies, advanced MEMS packaging still has many critical issues that need to be addressed. In the development of advanced MEMS packaging, the following must be noted and understood: The infrastructure of MEMS devices and MEMS packaging is not well established; MEMS packaging expertise is not commonly available; MEMS packaging is unique and custom-built; MEMS general packaging platform technology is not available; hermetic sealing of the MEMS device is necessary; vacuum packaging is even required for some MEMS devices; vertical electrical feed-through with through-silicon vias (TSVs) is still too costly; bare ASIC die/wafers are not commonly available for three-dimensional (3D) integration; bare thin die/wafer handling is not easy; pick and place is more difficult; low-temperature bonding is not mature enough for high-volume production; rework is more difficult; micro solder bumping, assembly, and reliability are more critical; inspection is more difficult; MEMS assembly testability is not well established; dies shrink and expand; known-good-die; thermal management; wafer dicing; and device/chip cracking during bonding. In the past few years, some of these critical issues have been studied by experts in the field. Their results have been disclosed in diverse journals and in the proceedings of many conferences, symposia, and workshops whose primary emphases are electrical designs, materials science, manufacturing engineering, or electronic packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of advanced MEMS packaging technologies for, e.g., inertial, optical, RF, BioMEMS, and medical MEMS devices. This book aims to remedy this deficiency

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Preface by presenting in one complete and concise volume a summary of the progress in this fascinating field that has occurred within the past few years. This book is written for everyone so that they can quickly learn the basics, grasp problem-solving methods, understand the tradeoffs, and make system-level decisions with advanced MEMS packaging technologies. This book is organized into five parts. Chapter 1, the first part, briefly discusses MEMS devices, commercial applications, and markets. MEMS packaging is also briefly mentioned, and some of the MEMS packaging patents from the United States, Japan, and the world since 2001 are provided. Chapter 2, the second part, briefly discusses the state of the art and future trends of advanced integrated-circuit (IC) electronics packaging. It is followed by advanced MEMS packaging, where 10 different designs of 3D MEMS packaging and their assembly processes are presented. There are two chapters in the third part, where some important enabling technologies for advanced MEMS packaging are presented. In Chapter 3, TSVs, stress sensors, wafer thinning and thin-wafer handling, low-temperature C2C, C2W, and W2W bonding, wafer dicing, and the reliability of RoHS-compliant MEMS packaging are discussed. Chapter 4 focuses on wafer-level packaging, where micromachining, wafer-level encapsulation, wafer-level chip capping, and a couple of case studies on wafer bonding based on low-temperature solder for MEMS packaging are presented. The fourth part has six chapters, and its focus is on the applications of advanced packaging on some MEMS devices. Chapter 5 presents an overview of microfabrication technology and major actuation mechanisms in enabling optical MEMS, followed by two well-studied optical MEMS devices in communications: optical switches and variable optical attenuators (VOAs). All aspects of MEMS design, manufacturability, packaging, and reliability are discussed. Chapter 6 presents the packaging and thermal reliability of the solder sealing ring of an RoHS-compliant 3D bubble-actuated photonic crossconnect switch. Emphasis is placed on determination of the thermal fatigue life of the lead-free solder sealing ring under shipping, storing, and handling conditions. Chapter 7 outlines the design, process, packaging, and testing of a bolometer vacuum package. The challenge of vacuum packaging and maintaining the temperature within ±0.1°C, packaging material and getter selections, and testing are presented. Chapter 8 presents the design, materials, process, and testing of bio-MEMS packaging. Emphasis is placed on the process developments of the microfluidics package and its application to extracting dengue virus from the samples. Chapter 9 presents the design, materials, process, and testing of MEMS packaging of a biosensor (micromirror) in an optical probe, which can take images from body tissues. Chapter 10 presents a wafer-level package with

Preface TSV interconnects and a wafer-level vacuum package with lateral electrical feed-through interconnects for accelerometer devices. For TSV interconnects, the die shear and hermeticity tests are used to characterize the package, and their results are discussed. For waferlevel vacuum packages, the C-V curves subjected to reliability tests and the Q-factor measurement of the vacuum inside the package are presented. The fifth part of this book covers radio frequency (RF) MEMS and packaging. Chapter 11 presents the design, fabrication, and characterization of RF MEMS switches. Emphasis is placed on mechanical and electrical design for performance, the micromachining and bulk micromachining processes, and maintaining an insertion loss of the MEMS switch that is lower than 0.5 dB up to 40 GHz and an isolation higher than 15 dB at 10 GHz. Chapter 12 presents different RF MEMS circuits, including tunable capacitors and tunable band-pass filters, which consist of different MEMS switches and can be tuned analogically or digitally. Usually the digital tuning approach has a larger tuning range and has more flexibility for constructing different tuning circuits. Chapter 13 presents the zero-level and first-level packaging of RF MEMS switches, which must be packaged in a nitrogen or dryair atmosphere (for high reliability) owing to hermeticity, temperature, and outgassing constraints. In zero-level packaging, capping of RF MEMS devices can be categorized as chip capping and thin-film capping. In first-level packaging, plastic packaging is the most common solution applicable for frequencies below several gigahertz, and ceramic packages exhibit the potential for good performance into the millimeter-wave region. For whom is this book intended? Undoubtedly, it will be of interest to three groups of specialists: (1) those who are active or intend to become active in research and development of MEMS devices and packaging, (2) those who have encountered practical MEMS packaging problems and wish to understand and learn more methods for solving such problems, and (3) those who have to choose a reliable, creative, high-performance, robust, and cost-effective packaging technique for their MEMS devices. This book also can be used as a text for undergraduate and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics, optoelectronics, and photonics industries. We hope that this book will serve as a valuable reference source for all those faced with the challenging problems created by the everincreasing interest in MEMS devices and packaging. We also hope that it will aid in stimulating further research and development on optical, electrical, thermal, and mechanical designs, materials, processes, manufacturing, testing, and reliability and more sound applications of advanced packaging technologies in MEMS products. The organizations that learn how to design advanced MEMS packaging in their interconnect systems have the potential to make

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Preface major advances in the electronics industry and to gain great benefits in cost, performance, quality, size, and weight. It is our hope that the information presented in this book may assist in removing road blocks, avoiding unnecessary false starts, and accelerating design, materials, and process development of MEMS packaging. We are strongly against the notion that packaging is the bottleneck of advanced MEMS applications. Rather, we would like to consider this as a golden opportunity to make a major contribution to the MEMS industry by developing innovative, high-performance, cost-effective, and reliable packaging for MEMS products. It is an exciting time for advanced (especially 3D) MEMS packaging! John H. Lau Chengkuo Lee C. S. Premachandran Yu Aibin

Acknowledgments

D

evelopment and preparation of Advanced MEMS Packaging was facilitated by the efforts of a number of dedicated people. We would like to thank them all, with special mention to Michael Mulcahy of McGraw-Hill and Somya Rustagi of Glyph International for their unswerving support and advocacy. Our special thanks go to Taisuke Soda and Steve Chapman of McGraw-Hill, who made our dream of this book come true by effectively sponsoring the project, patiently listening to our excuses for delay, and solving many problems that arose during the book’s preparation. It has been a great pleasure and fruitful experience to work with all of them in transferring our messy manuscripts into a very attractive printed book. The material in this book clearly has been derived from many sources, including individuals, companies, and organizations, and we have attempted to acknowledge by citations, in the appropriate parts of the book, the assistance that we have been given. It would be quite impossible for us to express our thanks to everyone concerned for their cooperation in producing this book, but we would like to extend due gratitude. Also, we want to thank several professional societies and publishers for permitting us to reproduce some of their illustrations and information in this book, including the American Society of Mechanical Engineers (ASME) Conference Proceedings (e.g., International Intersociety Electronic Packaging Conference) and Transactions (e.g., Journal of Electronic Packaging), the Institute of Electrical and Electronic Engineers (IEEE) Conference Proceedings (e.g., Electronic Components & Technology Conference) and Transactions (e.g., Advanced Packaging, Components and Packaging Technologies, and Manufacturing Technology), the International Microelectronics and Packaging Society (IMAPS) Conference Proceedings (e.g., International Symposium on Microelectronics) and Transactions (e.g., International Journal of Microcircuits & Electronic Packaging), the IBM Journal of Research and Development, Electronic Packaging & Production, Advanced Packaging, Circuits Assembly, Surface Mount Technology, Connection Technology, Solid State Technology, Circuit World, Microelectronics International, and Soldering and Surface Mount Technology.

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Acknowledgments John Lau would like to thank his former employers, the Institute of Microelectronics (IME), Agilent, and HP, for providing him excellent working environments that have nurtured him as a human being, fulfilled his need for job satisfaction, and enhanced his professional reputation. He also would like to thank Professor Dim-Lee Kwong for his trust, respect, and support of his work at IME, Agency for Science, Technology and Research (A∗STAR), Singapore. Furthermore, he would like to thank Dr. Lim Thiam Beng for helping to bring him into IME and all the members of the Microsystems, Modules, and Components Laboratory for their stimulating discussions, teamwork, and friendship. With respect to this book, Dr. Lau would like to single out the significant contributions of Zhang Xiaowu, Tang Gongyue, Cheryl Selvanayagam, Aditya Kumar, Yan Li Ling, Choi Won Kyoung, Kelvin Chen, Ahmad Kharyanto Bin Ratmin, Navas Khan, Chai Tai Chong, Yu Da Quan, N. Ranganathan, Ebin Liao, Li Hong Yu, Qing Xin Zhang, Seung Yoon, Feng Hanhua, Xie Ling, Ong Yue Ying, Wai Yin Hnin, Eva Wai, Damaruganath Pinjala, Vaidyanathan Kripesh, and Joanne Tan. Finally, he would like to thank his eminent colleagues (the enumeration of whom would not be practical here) at HKUST, IME, HP, and Agilent and throughout the electronics industry for their useful help, strong support, and stimulating discussions. Working and socializing with them has been a privilege and an adventure. He learned a lot about life and advanced packaging and interconnection technologies from them. Chengkuo Lee would like to thank his colleagues at Asia Pacific Microsystems, Inc., in Hsinchu, Taiwan, for their excellent work in MEMS packaging technology development. In particular, Mr. Ming Hung Tasi, Mr. Chia-Yu Wu, Mr. Chihchung Chen, Dr. Yen-Jyh Lai, Mr. Yu-Shen Lin, Mr. Shih-Yun Hung, Mr. Wen-Chih Chen, Dr. ShihChin Gong, and Professor Ruey-Shing Huang are specially acknowledged. Dr. Lee also appreciates his colleagues at the Institute of Microelectronics, A∗STAR, Singapore, for their research work in MEMS wafer-level packaging technology. To name a few, Dr. Daquan Yu, Dr. Li Ling Yan, Dr. Won Kyoung Choi, Dr. Johnny H. He, Dr. Qing Xin Zhang, Dr. Seung-Uk Yoon, and Dr. Hanhua Feng are appreciated most. Dr. Lee extends thanks to Mr. Riko I Made and Professor Chee Lip Gan from the School of Materials Science and Engineering, Nanyang Technological University, for their work in InAg solder bonding. He is further indebted to Professor J. Andrew Yeh at National Tsing Hua University, Hsinchu, Taiwan; Professor T. Suga, Professor H. Toshiyoshi, and Professor H. Fujita at the University of Tokyo, Tokyo, Japan; Dr. R. Maeda, Dr. T. Itoh, and Dr. T. Kobayashi of AIST, Tsukuba, Japan; Professor R. Sawada at Kyushu University, Fukuoka, Japan; Professor R. R. A. Syms at Imperial College, London, United Kingdom; and Professor Lih Y. Lin at the University of Washington, Seattle, Washington, for information on their research results and their continuous support. Dr. Lee also

Acknowledgments acknowledges Professor C.-C. Chen at the National Central University, Jhong-Li, Taiwan, and Professor John T. L. Thong, Professor W. K. Choi, Professor G. Pastorin, and Dr. Fu-Li Hsiao at the National University of Singapore for their continuous support and encouragement. C. S. Premachandran would like to acknowledge and thank his colleagues Ling Xie and Michelle Chew for their contribution on bioMEMS packaging; Dr. Pavel Neuzil, Chong Ser Choong, Navas Khan, Damaruganath Pinjala, Chai Tai Chong, and Dr. Zhang Xiao Wu for their contribution on optical MEMS—bolometer packaging; Dr. Janak Singh, Xu Yingshun, Kelvin Chen, Ahmad Khairyanto, Pamidighantam Ramana, Chuah Tong Kuan, and Jaya Krishnan Chandrappan for their contribution on biosensor packaging; and Dr. Mahadevan K. Iyer, Rangnathan Nagarajan, Choong Ser Chong, Mihai D. Rotaru, Dr. Chen Yu, and Dr. Vaidyanathan Kripesh for their contribution on accelerometer packaging. Finally, he would like to thank Dr. Lim Thiam Beng, who has inspired him in the MEMS packaging research area. Yu Aibin would like to thank all the authors cited in the reference lists for sharing their important and useful knowledge. He also would like to thank Professor AiQun Liu from Nanyang Technological University, Singapore, and Dr. Zhang Qingxin from the Institute of Microelectronics, Singapore, for invaluable support. Lastly, John Lau wants to thank his daughter Judy and his wife Teresa for their love, consideration, and patience by allowing him to work peacefully on this book. Their simple belief that he is making a small contribution to the electronics industry was a strong motivation for him. Knowing that Judy has earned her Ph.D. degree in physics from Princeton University and is working for Stanford University and that Teresa and he are in good health, he wants to thank God for his generous blessings. Chengkuo Lee shares the same feelings about his family. For a certain period of time, he slept only 4 hours a day on average while working on this book. Without the spiritual support of his family, he could never have struggled through those exhausting nights! C. S. Premachandran would like to thank his wife, Asha Venugopal, and their loving children, Karthik and Swetha, for their continuous support, love, and understanding while he worked on this book. Yu Aibin wishes to express his gratitude to his parents for all their support through the years; to his wife, Zhu Suli, for her understanding and loving support; and to his lovely daughter, Yu Wanxin, for her joyful time.

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CHAPTER

1

Introduction to MEMS 1.1

Introduction MEMS stand for microelectromechanical systems, which are the integration of mechanical elements such as sensors and actuators and electronics on a common silicon substrate through the use of microfabrication technology.1–41 The same basic technology and process steps such as the etching, patterning, doping, and connecting employed for making conventional electronic integrated circuits (ICs) such as complementary metal-oxide-semiconductors (CMOS) can be used to fabricate (micromachining) micromechanical elements by selectively etching away parts of a silicon wafer or adding new structural layers to form MEMS devices. However, there is a fundamental difference between MEMS and ICs devices—namely, MEMS devices must remain physically movable. MEMS devices use electronics to move their mechanical elements (parts)! MEMS are made up of elements between 1 and 100 μm (0.001 and 0.1 mm) in size, and MEMS devices generally range in size from 20 to 1000 μm.42 Nanoelectromechanical systems (NEMS) are similar to MEMS but much smaller, and they hold the promise of improving the ability to measure infinitesimal displacements and forces on the molecular scale but will not be discussed in this book. Micro-opto-electromechanical systems (MOEMS) are a special class of MEMS that use electronics to move mechanical parts that can sense and control light and manipulate optical signals. Their fabrication technology and process are similar to those of MEMS except that in addition to silicon materials, they also use, for example, gallium arsenide.

1

2 1.2

Chapter One

Commercial Applications of MEMS MEMS provide a combination of mechanical functions (e.g., sensing, moving, and heating) and electrical functions (e.g., switching and deciding). Some commercial applications42 of MEMS today are as follows: • Inkjet printers, which use piezoelectric or thermal bubble ejection to deposit ink on paper • Accelerometers in modern cars for a large number of purposes, including airbag deployment in collisions • Accelerometers in consumer electronic devices such as game controllers (Nintendo Wii), personal media players/cell phones (Apple iPhone), and a number of digital cameras (various Canon Digital IXUS models), as well as in PCs to park the hard-disk head when free fall is detected to prevent damage and data loss • MEMS gyroscopes used in modern cars and other applications to detect yaw (e.g., to deploy a roll-over bar or trigger dynamic stability control) • Silicon pressure sensors such as car tire-pressure sensors and disposable blood pressure sensors • Displays in projectors (e.g., the DMD chip) based on DLP technology, which has on its surface several hundred thousand micromirors • Optical switching technology such as that used for switching and aligning data communications • Bio-MEMS applications in medical and health related technologies from Lab-On-a-Chip to MicroTotalAnalysis (e.g., biosensors and chemosensors) • Interferometric modulator displays (IMOD) in consumer electronics (primarily displays for mobile devices), which are used to create interferometric modulation (i.e., reflective display technology as found in Mirasol displays)

1.3

MEMS Markets The MEMS market forecast by Yole Development calls for $10 billion by 2010 and $14 billion by 2012. [For 2008, Jean Christophe Eloy, CEO of Yole, expects the market to be $7.8 billion. This represents a combined annual growth rate (CAGR) of 14 percent for the 2007–2012 period. The 2007–2010 growth, however, will be quite modest (11 percent), but strong growth is expected after 2010.] The packaging cost of a MEMS product

Introduction to MEMS in general is between 60 and 80 percent. Thus MEMS packaging could be a $7 billion market by 2010 and $10 billion by 2012. The MEMS devices that make up the market forecast are, for example, inkjet (IJ) heads, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS devices, microbolometers, microdisplays, microfluidics, radiofrequency (RF) MEMS, microtips, microfuel cells, and emerging MEMS. These MEMS devices can be applied to the automotive, aeronautics, consumer, defense, industrial, medical, life science, and telecommunication industries. Their units and market values have been provided by Yole Development and are shown in Figs. 1-1 and 1-2, which also include the forecasts up to 2012. It can be seen that the value of MEMS production is expected to double in 2012 (from 2007) and that the total units of MEMS production are expected to quadruple in 2012 (from 2007). According to Jean Christophe Eloy, whose company tracks 150 MEMS applications, RF MEMS is expected to have the highest growth (50 percent) (Figs. 1-3 and 1-4), followed by microfluidic chips for drug delivery (42 percent), silicon microphones (32 percent), microfluidic chips for diagnostics (23 percent), microtips and microprobes (22 percent), and microbolometers (20 percent). Eloy also said that the most promising MEMS devices include accelerometers for humanmachine interfaces, with a CAGR exceeding 120 percent, followed by RF-MEMS devices for automatic test equipment (81 percent).

16,000.0 Defense

14,000.0

Aeronautics

Million, $ US

12,000.0

Industrial

10,000.0

Telecom

8,000.0

Life science

6,000.0

Medical 4,000.0 Automotive 2,000.0

Consumer

0.0 2006 Consumer Automotive Medical Lifescience Telecom Industrial Aeronautics Defense

2007

2008

2009

2010

2011

2012

2006

2007

2008

2009

2010

2011

2012

854.4 375.6 49.6 154.5 257.8 23.7 0.3 0.8

997.9 422.7 58.1 173.4 386.2 25.2 0.3 1.1

1,231.0 480.5 70.8 199.2 539.9 27.9 0.4 1.4

1,531.9 510.7 85.5 228.8 799.2 36.3 0.5 1.8

1,999.3 541.1 112.0 274.7 1,274.4 49.5 0.5 2.1

2,689.8 571.4 132.1 367.7 2,005.9 64.2 0.6 2.4

3,504.4 615.3 139.5 494.4 3,214.7 154.9 0.6 3.2

FIGURE 1-1 MEMS value market forecast for 2006–2012 ($ US millions).

3

Chapter One

Million, units

9,000.0 8,000.0

Defense

7,000.0

Aeronautics

6,000.0

Industrial

5,000.0

Telecom

4,000.0

Life science

3,000.0

Medical

2,000.0

Automotive

1,000.0 Consumer 0.0 2006 Consumer Automotive Medical Life science Telecom Industrial Aeronautics Defense

2007

2008

2009

2010

2011

2012

2006

2007

2008

2009

2010

2011

2012

2,825.2 1,277.7 336.0 432.6 380.4 853.9 30.0 258.1

2,919.4 1,362.2 381.3 494.6 556.3 912.0 37.8 343.2

3,322.3 1,421.8 422.8 573.4 650.2 991.4 45.4 415.3

3,639.7 1,464.7 457.7 664.3 791.4 1,107.2 52.6 489.3

4,129.2 1,464.0 495.2 788.6 1,002.5 1,244.9 59.8 558.9

4,608.6 1,485.9 535.7 1,254.6 1,325.2 1,439.8 66.0 628.9

5,415.3 1,572.4 560.1 1,645.6 1,827.7 1,945.3 78.5 824.8

FIGURE 1-2 MEMS volume market forecast for 2006–2012 (millions of units).

1,600.0 1,400.0

Million, $ US

4

1,200.0 1,000.0 800.0

RF-MEMS for consumer RF-MEMS for defense RF-MEMS for aeronautics RF-MEMS for industrial RF-MEMS for telecom

600.0 400.0 200.0 0.0 2006 2007 2008 2009 2010 2011 2012

RF-MEMS for telecom RF-MEMS for industrial RF-MEMS for aeronautics RF-MEMS for defense RF-MEMS for consumer

2006

2007

2008

2009

2010

2011

2012

179.0

321.1

385.5

467.9

632.4

888.2

1,284.9

1.0

4.5

9.4

17.6

36.1

56.9

95.8

0.0

0.0

0.0

0.0

0.1

0.1

0.2

0.2

0.8

2.1

4.3

9.0

14.1

22.9

0.0

0.5

2.0

5.0

10.0

20.0

25.0

FIGURE 1-3 RF-MEMS value market forecast for 2006–2012 ($US millions).

Introduction to MEMS 2,500.0

Million, units

2,000.0 1,500.0

RF-MEMS for consumer RF-MEMS for defense RF-MEMS for aeronautics RF-MEMS for industrial RF-MEMS for telecom

1,000.0 500.0 0.0 2006 2007 2008 2009 2010 2011 2012

RF-MEMS for telecom RF-MEMS for industrial RF-MEMS for aeronautics RF-MEMS for defense RF-MEMS for consumer

2006

2007

2008

2009

2010

2011

2012

3.0

5.0

8.3

96.4

371.0

894.7

1,826.2

0.0

0.2

0.4

0.9

2.6

5.3

11.7

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.1

0.1

0.0

5.0

20.0

50.0

100.0

200.0

250.0

FIGURE 1-4 RF-MEMS volume market forecast for 2006–2012 (millions of units).

1.4 Top 30 MEMS Suppliers The top 30 MEMS suppliers ranked by Yole Development 43 are Hewlett-Packard (HP), Texas Instruments (TI), Robert Bosch, Lexmark, Seiko Epson, STMicroelectronics, Freescale Semiconductor, Canon, Analog Devices, Systron Donner, Denso, Avago Technologies, GE Sensing, Honeywell, Infineon Technology, Delphi, Olivettii-Jet, Boehringer Ingelheim Microparts, VTI Technologies, Panasonic, Formfactor, Knowles Electronics, Murata, Continental Automotive, Measurement Specialties, Inc., Flir Systems, Ulis, Omron, Silicon Sensing Systems, and Colibrys. These 30 companies’ global sales totaled approximately $6 billion in 2007, representing approximately 80 percent of the global MEMS market. HP is the largest supplier, mainly supplying inkjet printheads, followed by TI, which mainly provides the digital light processor. For more information about these companies and many others, please see ref. 43.

1.5

Introduction to MEMS Packaging The MEMS device is not an isolated island. It must communicate with other integrated circuit (IC) chips in a circuit through an input/ output (I/O) system of interconnects. Furthermore, the MEMS device needs to be powered up, and its embedded circuitry and elements are

5

6

Chapter One delicate, requiring the package to both carry and protect the device. Consequently, the major functions of MEMS packaging are (1) to provide a path for the electrical current that powers the circuit and moves the moving elements, (2) to distribute the signals onto and off the MEMS device, (3) to remove the heat generated by the circuit, and (4) to support and protect the MEMS device from hostile environments. Unlike electronics IC packaging,44–56 MEMS packaging is not trivial, is expensive (60 to 80 percent of the product total cost), and is custom-built. Electronics IC packaging is a well-developed technology (e.g., wire bonding, tape automated bonding, and the flip chip). However, MEMS packaging is a specially designed packaging process that is difficult owing to moving structural elements, and it is the most expensive process in micromachining. Unlike electronics IC packaging,44–56 MEMS packaging needs a cap. In order for the moving elements of a MEMS device to move effectively (e.g., with minimum damping and stiction) in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices (e.g., resonators, infrared bolometers, and gyroscopes), vacuum packaging is even required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a waferlevel packaging. The design, materials, process, testing, and reliability of MEMS wafer-level packaging will be presented, discussed, and examined throughout this book.

1.6

MEMS Packaging Patents since 2001 In the past few years, many patents have been granted for MEMS packaging. In this section, some of the patents (since 2001) from the United States, Japan, and the world have been selected and listed for convenient practice.

1.6.1

U.S. MEMS Packaging Patents

Some of the U.S. MEMS packaging patents selected from the U.S. Patent and Trademark Office (USPTO) since 2001 are as follows: Patent No. 7,508,063

7,491,567

7,479,516

Owner(s)/Title/Date Duboc, Robert M. (Menlo Park, CA), Tarn, Terry (San Diego, CA), “Low cost hermetically sealed package,” March 24, 2009. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), “MEMS device packaging methods,” February 17, 2009. Chen, Jian (Richardson, TX), Rajagopal, Ramasubramaniam (Richardson, TX), “Nanocomposites and methods thereto,” January 20, 2009.

Introduction to MEMS 7,465,600

7,463,404

7,456,497

7,452,800

7,449,784

7,449,358

7,449,356

7,443,563

7,436,054

7,425,749

Michael, Don (Monmoth, OR), Rossman, Mari J. (Corvallis, OR), Bower, Bradley (Junction City, OR), Haluzak, Charles Craig (Corvallis, OR), Stemer, John R. (Albany, OR), Qi, Quan (Corvallis, OR), Kane, John (Corvallis, OR), “Package for a micro-electro-mechanical device,” December 16, 2008. Chen, Dongmin (Saratoga, CA), Xiong, Fulin (San Jose, CA), “Method of using a preferentially deposited lubricant to prevent anti-stiction in micromechanical systems,” December 9, 2008. Higashi, Mitsutoshi (Nagano, JP), “Electronic devices and its production methods,” November 25, 2008. Sosnowchik, Brian D. (Walnut Creek, CA), Lin, Liwei (Castro Valley, CA), Pisano, Albert P. (Danville, CA), “Bonding a non-metal body to a metal surface using inductive heating,” November 18, 2008. Sherrer, David W. (Radford, VA), Rasnake, Larry J. (Blacksburg, VA), Fisher, John J. (Blacksburg, VA), “Device package and methods for the fabrication and testing thereof,” November 11, 2008. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” November 11, 2008. Weigold, Jason W. (Somerville, MA), “Process of forming a microphone using support member,” November 11, 2008. Palmateer, Lauren (San Francisco, CA), Gally, Brian J. (Los Gatos, CA), Cummings, William J. (Millbrae, CA), Kothari, Manish (Cupertino, CA), Chui, Clarence (San Jose, CA), “Packaging for an interferometric modulator,” October 28, 2008. Zhe, Wang (Singapore, SG), “MEMS microphone with a stacked PCB package and method of producing the same,” October 14, 2008. Hartzell, John Walter (Camas, WA), Zhan, Changqing (Vancouver, WA), Wolfson, Michael Barrett (Somerville, MA), “MEMS pixel sensor,” September 16, 2008.

7

8

Chapter One 7,424,198

7,422,962

7,416,938

7,415,870

7,414,310

7,408,250

7,405,860

7,405,466

7,405,100

7,402,878

Palmateer, Lauren (San Francisco, CA), Cummings, William J. (San Francisco, CA), Gally, Brian (San Rafael, CA), Miles, Mark (San Francisco, CA), Sampsell, Jeffrey B. (San Jose, CA), Chui, Clarence (San Mateo, CA), Kothari, Manish (Cupertino, CA), “Method and device for packaging a substrate,” September 9, 2008. Chen, Chien-Hua (Corvallis, OR), Chen, Zhizhang (Corvallis, OR), Geissler, Steven R (Albany, OR), “Method of singulating electronic devices,” September 9, 2008. Seh, Huankiat (Phoenix, AZ), Min, Yongki (Phoenix, AZ), “Inkjet patterning for thin-film capacitor fabrication, thin-film capacitors fabricated thereby, and systems containing same,” August 26, 2008. Mancosu, Federico (Milan, IT), Brusarosco, Massimo (Cesano Boscone, IT), Fioravanti, Anna Paola (Monza, IT), Romeo, Fabio (Monza, IT), “Movable unit and system for sensing at least one characteristic parameter of a tyre,” August 26, 2008. Do, Byung Tai (Singapore, SG), Yang, Sung Uk (Singapore, SG), “Waferscale package system,” August 19, 2008. Doan, Jonathan (Mountain View, CA), Tarn, Terry (San Diego, CA), “Micromirror array device with compliant adhesive, August 5, 2008. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), “Spatial light modulators with light blocking/absorbing areas,” July 29, 2008. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Wu, Yongling (Singapore, SG), Ng, Fern Lan (Singapore, SG), “Method of fabricating microelectromechanical system structures,” July 29, 2008. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), “Packaging of a semiconductor device with a non-opaque cover,” July 29, 2008. Tarn, Terry (San Diego, CA), “Packaging method for microstructure and semiconductor devices,” July 22, 2008.


7,393,712

7,381,629

7,381,583

7,378,734

7,373,026

7,368,808

7,368,311

7,361,581

7,358,106

Sridhar, Uppili (Dallas, TX), Zou, Quanbo (Plano, TX), “Wafer level packaging process,” July 1, 2008. Smith, Mark A. (Corvallis, OR), Boucher, William R (Corvallis, OR), Haluzak, Charles C (Corvallis, OR), “Fluidic MEMS device,” July 1, 2008. Sankarapillai, Chirayarikathuveedu Premachandran (Singapore, SG), Nagarajan, Ranganathan (Singapore, SG), Soundarapandian, Mohanraj (Singapore, SG), “Method of forming through-wafer interconnects for vertical wafer level packaging,” June 3, 2008. Ebel, John L. (Beavercreek, OH), Cortez, Rebecca (Xenia, OH), Strawser, Richard E. (Greenville, OH), Leedy, Kevin D. (Centerville, OH), “MEMS RF switch integrated process,” June 3, 2008. Yabuki, Richard (Garden Grove, CA), Tea, Nim (Orange, CA), “Stacked contact bump,” May 27, 2008. Chui, Clarence (San Mateo, CA), “MEMS device fabricated on a pre-patterned substrate,” May 13, 2008. Heck, John (Palo Alto, CA), Hayden, III, Joseph S. (Sunnyvale, CA), Greathouse, Steve W. (Chandler, AZ), Wong, Daniel M. (Fremont, CA), “MEMS packaging using a non-silicon substrate for encapsulation and interconnection,” May 6, 2008. Tilmans, Hendrikus (Maastricht, NL), Beyne, Eric (Leuven, BE), Jansen, Henri (Leuven, BE), De Raedt, Walter (Edegem, BE), “Method and system for fabrication of integrated tunable/ switchable passive microwave and millimeter wave modules,” May 6, 2008. Adkisson, James W. (Jericho, VT), Gambino, Jeffrey P. (Westford, VT), Jaffe, Mark D. (Shelburne, VT), Rassel, Richard J. (Colchester, VT), Sprogis, Edmund J. (Underhill, VT), “High surface area aluminum bond pad for through-wafer connections to an electronic package,” April 22, 2008. Potter, Curtis Nathan (Austin, TX), “Hermetic MEMS package and method of manufacture,” April 15, 2008.

9

10


7,324,716

7,314,777

7,309,902

7,307,775

7,302,829

7,297,573

7,288,464

7,286,278

Felton, Lawrence E. (Hopkinton, MA), Harney, Kieran P. (Andover, MA), Roberts, Carl M. (Topsfield, MA), “Wafer level capped sensor,” April 15, 2008. Epitaux, Marc (Sunnyvale, CA), “Silicon packaging for opto-electronic modules,” January 29, 2008. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Chip packaging systems and methods,” January 1, 2008. Reboa, Paul F. (Corvallis, OR), “Microelectronic device with anti-stiction coating,” December 18, 2007. Patel, Satayadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve (Saratoga, CA), Duboc, Robert M. (Menlo Park, CA), Grobelny, Thomas J. (Snohomish, WA), Chen, Hung Nan (Kaohsiung, TW), Dehlinger, Dietrich (Sebastopol, CA), Richards, Peter W. (Palo Alto, CA), Shi, Hongqin (San Jose, CA), Sun, Anthony (San Jose, CA), “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” December 11, 2007. Zribi, Anis (Rexford, NY), “Contactless humidity/chemical vapor sensor device and associated method of fabrication,” December 4, 2007. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Methods and apparatus for particle reduction in MEMS devices,” November 20, 2007. Haluzak, Charles C. (Corvallis, OR), Pollard, Jeffrey R. (Corvallis, OR), “MEMS packaging structure and methods,” October 30, 2007. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” October 23, 2007.


7,276,789

7,276,398

7,275,424

7,262,622 7,259,449

7,243,533

7,238,999

7,238,546

7,233,048

7,218,742

7,217,588

7,203,394

Manalis, Scott (Cambridge, MA), Burg, Thomas (Cambridge, MA), “Suspended microchannel detectors,” October 16, 2007. Cohn, Michael B. (Berkeley, CA), Kung, Joseph T. (Santa Clara, CA), “Microelectromechanical systems using thermocompression bonding,” October 2, 2007. Michael, Don (Monmoth, OR), Rossman, Mari J. (Corvallis, OR), “System and method for hermetically sealing a package,” October 2, 2007. Felton, Lawrence E. (Hopkinton, MA), Harncy, Kieran P. (Andover, MA), Roberts, Carl M. (Topsfield, MA), “Wafer level capped sensor,” October 2, 2007. Zhao, Yang (Andover, MA), “Wafer-level package for integrated circuits,” August 28, 2007. Floyd, Philip D. (Redwood City, CA), “Method and system for sealing a substrate,” August 21, 2007. Mancosu, Federico (Milan, IT), Romeo, Fabio (Monza, IT), Brusarosco, Massimo (Cesano Boscone, IT), Fioravanti, Anna Paolo (Monza, IT), “Movable unit and system for sensing at least one characteristic parameter of a tyre,” July 17, 2007. LaFond, Peter H. (Redmond, WA), Yu, Lianzhong (Redmond, WA), “High performance MEMS packaging architecture,” July 3, 2007. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” July 3, 2007. Rybnicek, Kimon (Santa Barbara, CA), “MEMS device trench plating process and apparatus for through hole vias,” June 19, 2007. Kay, Kelly Q. (Chicago, IL), Gilbert, Mark W. (Park Ridge, IL), “Condenser microphone assembly,” May 15, 2007. Hartzell, John W. (Camas, WA), Walton, Harry Garth (Beckley, GB), Brownlow, Michael James (Drayton, GB), “Integrated MEMS packaging,” May 15, 2007. Wiegele, Thomas (Apple Valley, MN), Apanius, Christopher (Moreland Hills, OH), Goldman, Kenneth G. (Olmsted Township, OH), Guo,

11

12

Chapter One

7,202,553

7,202,552

7,198,982

7,183,176

7,176,106

7,166,488

7,164,199

7,160,637

7,153,759

Shuwen (Lakeville, MN), St. Clair, Loren E. (Apple Valley, MN), O’Meara, Timothy R. (Burnsville, MN), Pohl, James J. (Apple Valley, MN), “Micro mirror arrays and microstructures with solderable connection sites,” April 10, 2007. Snyder, Tanya Jegeris (Edina, MN), Yi, Robert H. (Palo Alto, CA), Wilson, Robert Edward (Palo Alto, CA), “Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging,” April 10, 2007. Zhe, Wang (Singapore, SG), Yubo, Miao (Singapore, SG), “MEMS package using flexible substrates, and method thereof,” April 10, 2007. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” April 3, 2007. Sankarapillai, Chirayarikathuveedu Premachandran (Singapore, SG), Nagarajan, Ranganathan (Singapore, SG), Soundarapandian, Mohanraj (Singapore, SG), “Method of forming through-wafer interconnects for vertical wafer level packaging,” April 3, 2007. Snyder, Tanya Jegeris (Edina, MN), Yi, Robert H. (Palo Alto, CA), Wilson, Robert Edward (Palo Alto, CA), “Wafer bonding using reactive foils for massively parallel micro-electromechanical systems packaging,” February 13, 2007. MacDonald, Noel C. (Santa Barbara, CA), Aimi, Marco F. (Goleta, CA), “Metal MEMS devices and methods of making same,” January 23, 2007. Tarn, Terry (San Diego, CA), “Device packages with low stress assembly process,” January 16, 2007. Chiao, Mu (Beaverton, OR), Lin, Liwei (Castro Valley, CA), Lam, Kien-Bang (Albany, CA), “Implantable, miniaturized microbial fuel cell,” January 9, 2007. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Wu, Yongling (Singapore, SG), Ng, Fern Lan (Singapore, SG), “Method of fabricating microelectromechanical system structures,” December 26, 2006.


7,132,721

7,129,163

7,115,182

7,112,525

7,112,463

7,101,789

7,094,967

7,084,073

7,071,594

Ebel, John L. (Beavercreek, OH), Cortez, Rebecca (Xenia, OH), Strawser, Richard E. (Greenville, OH), Leedy, Kevin D. (Centerville, OH), “MEMS RF switch integrated process,” December 5, 2006. Platt, William P. (Columbia Heights, MN), Ford, Carol M. (Columbia Heights, MN), “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” November 7, 2006. Sherrer, David W. (Radford, VA), Rasnake, Larry J. (Blacksburg, VA), Fisher, John J. (Blacksburg, VA), “Device package and method for the fabrication and testing thereof,” October 31, 2006. Wei, Jun (Singapore, SG), Wong, Stephen Chee Khuen (Singapore, SG), Nai, Sharon Mui Ling (Singapore, SG), “Anodic bonding process for ceramics,” October 3, 2006. Bhansali, Shekhar (Tampa, FL), Aravamudhan, Shyam (Tampa, FL), Luongo, Kevin (St. Petersburg, FL), Kedia, Sunny (Tampa, FL), “Method for the assembly of nanowire interconnects,” September 26, 2006. Horning, Robert (Savage, MN), Ohnstein, Thomas (Roseville, MN), Youngner, Daniel (Maple Grove, MN), “Method for making devices using ink jet printing,” September 26, 2006. Subramanian, Kanakasabapathi (Clifton Park, NY), Fortin, Jeffrey Bernard (Niskayuna, NY), Tian, Wei-Cheng (Clifton Park, NY), “Method of wet etching vias and articles formed thereby,” September 5, 2006. Evans, Cliff (Newtown, CT), Dalton, Mark William (Danbury, CT), “Electrical feedthru,” August 22, 2006. Lee, Moon-chul (Sungnam, KR), Choi, Hyung (Sungnam, KR), Jung, Kyu-dong (Suwon, KR), Jang, Mi (Suwon, KR), Hong, Seog-woo (Busan, KR), Chung, Seok-whan (Suwon, KR), Jun, Chan-bong (Seoul, KR), Kang, Seok-jin (Suwon, KR), “Method of forming a via hole through a glass wafer,” August 1, 2006. Yan, Jun (Cincinnati, OH), Casasanta, III, Vincenzo (Woodinville, WA), Luanava, Selso H. (Woodinville, WA), Urey, Hakan (Istanbul, TR),

13

14

Chapter One

7,030,432

7,029,829

7,011,793

7,008,193

7,004,015

7,002,436

7,002,241

7,002,215

6,995,040

DeWitt, IV, Frank A. (Bloomfield, NY), Tegreene, Clarence T. (Bellevue, WA), Wiklof, Christopher A. (Everett, WA), “MEMS scanner with dual magnetic and capacitive drive,” July 4, 2006. Ma, Qing (San Jose, CA), “Method of fabricating an integrated circuit that seals a MEMS device within a cavity,” April 18, 2006. Stark, Brian H. (Ann Arbor, MI), Najafi, Khalil (Ann Arbor, MI), “Low temperature method for forming a microcavity on a substrate and article having same,” April 18, 2006. Zhou, Peng (Newtown, PA), Young, Lincoln (Ithaca, NY), “Reconfigurable modular microfluidic system and method of fabrication,” March 14, 2006. Najafi, Khalil (Ann Arbor, MI), Kim, Hanseup S. (Ann Arbor, MI), Bernal, Luis P. (Ann Arbor, MI), Astle, Aaron A. (Ann Arbor, MI), Washabaugh, Peter D. (Ann Arbor, MI), “Micropump assembly for a microgas chromatograph and the like,” March 7, 2006. Chang-Chien, Patty P. L. (Hermosa Beach, CA), Wise, Kensall D. (Ann Arbor, MI), “Method and system for locally sealing a vacuum microcavity, methods and systems for monitoring and controlling pressure and method and system for trimming resonant frequency of a microstructure therein,” February 28, 2006. Ma, Qing (San Jose, CA), Cheng, Peng (Campbell, CA), Rao, Valluri (Saratoga, CA), “Vacuum-cavity MEMS resonator,” February 21, 2006. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), “Packaging of semiconductor device with a non-opaque cover,” February 21, 2006. Miller, David (Louisville, CO), “Floating entrance guard for preventing electrical short circuits,” February 21, 2006. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” February 7, 2006.


6,987,304

6,987,258

6,984,866

6,982,491

6,972,955

6,969,635

6,965,721

6,962,834

6,958,846

Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steve S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” February 7, 2006. D’Camp, Jon B. (Savage, MN), Curtis, Harlan L. (Champlin, MN), Dunaway, Lori A. (New Hope, MN), Glenn, Max C. (Chanhassen, MN), “Methods and apparatus for particle reduction in MEMS devices,” January 17, 2006. Mates, John W. (Portland, OR), “Integrated circuit-based compound eye image sensor using a light pipe bundle,” January 17, 2006. Mostafazadeh, Shahram (San Jose, CA), Smith, Joseph O. (Morgan Hill, CA), Penry, Matthew D. (Morgan Hill, CA), “Flip chip optical semiconductor on a PCB,” January 10, 2006. Fan, Chun Ho (Sham Tseng, HK), Labeeb, Sadak Thamby (Tsuen Wan, HK), Chow, Lap Keung (Kowloon, HK), “Sensor semiconductor package and method of manufacturing the same,” January 3, 2006. Pleskach, Michael David (Orlando, FL), Koeneman, Paul Bryant (Palm Bay, FL), Smith, Brian Ronald (Pittsburgh, PA), Newton, Charles Michael (Palm Bay, FL), Gamlen, Carol Ann (Melbourne, FL), “Electro-fluidic device and interconnect and related methods,” December 6, 2005. Patel, Satyadev R. (Sunnyvale, CA), Huibers, Andrew G. (Palo Alto, CA), Chiang, Steven S. (Saratoga, CA), “Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates,” November 29, 2005. Tullis, Barclay J. (Palo Alto, CA), Prince, John H. (Los Altos, CA), “Integrated manufacture of sidepolished fiber optics,” November 15, 2005. Stark, David H. (Evergreen, CO), “Wafer-level hermetic micro-device packages,” November 8, 2005. Huibers, Andrew G. (Mountain View, CA), Richards, Peter W. (Palo Alto, CA), “Spatial light modulators with light absorbing areas,” October 25, 2005.

15

16


6,953,985

6,952,301

6,949,398

6,936,918

6,936,494

6,924,974

6,917,099

6,906,847

6,902,656

Peterson, Kenneth A. (Albuquerque, NM), “Encapsulants for protecting MEMS devices during post-packaging release etch,” October 18, 2005. Lin, Jong-Kai (Chandler, AZ), Lytle, William H. (Chandler, AZ), Fay, Owen (Gilbert, AZ), Markgraf, Steven (Chandler, AZ), Hughes, Henry G. (Scottsdale, AZ), Amrine, Craig (Tempe, AZ), De Silva, Ananda P. (Chandler, AZ), “Wafer level MEMS packaging,” October 11, 2005. Huibers, Andrew G. (Palo Alto, CA), “Spatial light modulators with light blocking and absorbing areas,” October 4, 2005. Lytle, William H. (Chandler, AZ), Fay, Owen (Gilbert, AZ), Markgraf, Steven (Plymouth, MN), Springer, Stephen B. (Mesa, AZ), “Low cost fabrication and assembly of lid for semiconductor devices,” September 27, 2005. Harney, Kieran P. (Andover, MA), Felton, Lawrence E. (Hopkinton, MA), Nunan, Thomas Kieran (Carlisle, MA), Alie, Susan A. (Stoneham, MA), Wachtmann, Bruce (Concord, MA), “MEMS device with conductive path through substrate,” August 30, 2005. Cheung, Kin P. (Hoboken, NJ), “Processes for hermetically packaging wafer level microscopic structures,” August 30, 2005. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package using cold-gas dynamic spray material deposition,” August 2, 2005. Hellekson, Ronald A. (Eugene, OR), Chen, Chien-Hua (Corvallis, OR), Boucher, William R (Corvallis, OR), Smith, Joshua W. (Corvallis, OR), Craig, David M (Albany, OR), Watts, Gary J. (Albany, OR), “Die carrier with fluid chamber,” July 12, 2005. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), “Spatial light modulators with light blocking/absorbing areas,” June 14, 2005. Ouellet, Luc (Granby, CA), Antaki, Robert (St-Luc, CA), Tremblay, Yves (Brigham, CA), “Fabrication of microstructures with vacuumsealed cavity,” June 7, 2005.


6,894,383

6,876,056

6,858,466

6,853,067

6,846,725

6,844,959

6,844,623

6,838,047

6,835,594

Patel, Satyadev R. (Elk Grove, CA), Huibers, Andrew G. (Mountain View, CA), “Method for making a micromechanical device by using a sacrificial substrate,” May 31, 2005. Bar-Sadeh, Eyal (Jerusalem, IL), Talalyevsky, Alexander (Jerusalem, IL), Ginsburg, Eyal (Tel Aviv, IL), “Reduced substrate micro-electromechanical systems (MEMS) device and system for producing the same,” May 17, 2005. Tilmans, Hendrikus (Maastricht, NL), Beyne, Eric (Leuven, BE), Jansen, Henri (Leuven, BE), De Raedt, Walter (Edegem, BE), “Method and system for fabrication of integrated tunable/ switchable passive microwave and millimeter wave modules,” April 5, 2005. Bower, Bradley (Junction City, OR), Qi, Quan (Corvallis, OR), Sand, Kirby (Corvallis, OR), “System and a method for fluid filling wafer level packages,” February 22, 2005. Cohn, Michael B. (Berkeley, CA), Kung, Joseph T. (Santa Clara, CA), “Microelectromechanical systems using thermocompression bonding,” February 8, 2005. Nagarajan, Ranganathan (Singapore, SG), Premachandran, Chirayarikathuveedu Sankarapillai (Singapore, SG), Chen, Yu (Singapore, SG), Kripesh, Vaidyanathan (Singapore, SG), “Wafer-level package for microelectro-mechanical systems,” January 25, 2005. Huibers, Andrew G. (Mountain View, CA), Patel, Satyadev R. (Elk Grove, CA), Duboc, Jr., Robert M. (Menlo Park, CA), “Spatial light modulators with light absorbing areas,” January 18, 2005. Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Temporary coatings for protection of microelectronic devices during packaging,” January 18, 2005. Billiet, Romain Louis (Penang, MY), Nguyen, Hanh Thi (Penang, MY), “MEMS and MEMS components from silicon kerf,” January 4, 2005. Shong, Ci-moo (Sungnam-si, KR), Kang, Seok-jin (Suwon-si, KR), Chung, Seok-whan (Suwon-si, KR), Lee, Moon-chul (Sungnam-si, KR), Jung, Kyu-dong (Suwon-si, KR), Kim, Jong-seok (Gyeonggi-do, KR), Jun, Chan-bong (Seoul, KR),

17

18

Chapter One

6,834,154

6,825,744

6,809,412

6,808,955

6,808,954

6,798,954

6,793,829

6,788,840

6,780,672

6,775,068

6,773,962

Hong, Seog-woo (Busan, KR), Kang, Jung-ho (Suwon-si, KR), “Metal wiring method for an undercut,” December 28, 2004. Carpenter, Barry S. (Oakdale, MN), “Tooling fixture for packaged optical micro-mechanical devices,” December 21, 2004. Harney, Kieran Patrick (Andover, MA), “Active alignment as an integral part of optical package design,” November 30, 2004. Tourino, Cory G. (Georgetown, TX), Rice, Janet L. (Austin, TX), Flynn, Gregory (Austin, TX), “Packaging of MEMS devices using a thermoplastic,” October 26, 2004. Ma, Qing (San Jose, CA), “Method of fabricating an integrated circuit that seals a MEMS device within a cavity,” October 26, 2004. Ma, Qing (San Jose, CA), Cheng, Peng (Campbell, CA), Rao, Valluri (Saratoga, CA), “Vacuum-cavity MEMS resonator,” October 26, 2004. Carpenter, Barry S. (Oakdale, MN), Hagen, Kathy L. (Stillwater, MN), Smith, Robert G. (Vadnais Heights, MN), “Packaged optical micro-mechanical device,” September 28, 2004. Platt, William P. (Columbia Heights, MN), Ford, Carol M. (Columbia Heights, MN), “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” September 21, 2004. Stewart, Robert E. (Woodland Hills, CA), Cherbettchian, Agop H. (Santa Monica, CA), Fersht, Samuel (Studio City, CA), Hall, David B. (La Crescenta, CA), “Bi-stable micro-actuator and optical switch,” September 7, 2004. Steele, Daniel W. (Clay, NY), Chovan, Joseph L. (North Syracuse, NY), “Micro eletro-mechanical component and system architecture,” August 24, 2004. Lomas, Stuart John (Edmonton, CA), McLaughlin, Dean Edward (Baltimore, MD), “Integrated optical channel,” August 10, 2004. Saia, Richard Joseph (Niskayuna, NY), Durocher, Kevin Matthew (Waterford, NY), Kapusta, Christopher James (Duanesburg, NY),

Introduction to MEMS

6,771,859

6,767,764

6,760,500 6,759,590

6,723,379

6,716,767

6,696,645

6,696,343

6,661,069

Nielsen, Matthew Christian (Schenectady, NY), “Microelectromechanical system device packaging method,” August 10, 2004. Carpenter, Barry S. (Oakdale, MN), “Selfaligning optical micro-mechanical device package,” August 3, 2004. Saia, Richard Joseph (Niskayuna, NY), Durocher, Kevin Matthew (Waterford, NY), Kapusta, Christopher James (Duanesburg, NY), Nielsen, Matthew Christian (Schenectady, NY), “Microelectromechanical system device packaging method,” July 27, 2004. Furuyama, Hideto (Kanagawa-ken, JP), “Optical wiring device,” July 6, 2004. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” July 6, 2004. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package using cold-gas dynamic spray material deposition,” April 20, 2004. Shih, Wu-Sheng (Rolla, MO), Lamb, III, James E. (Rolla, MO), Daffron, Mark (Rolla, MO), “Contact planarization materials that generate no volatile byproducts or residue during curing,” April 6, 2004. Margomenos, Alexandros (Ann Arbor, MI), Herrick, Katherine J. (Westford, MA), Becker, James P. (Bozeman, MT), Katehi, Linda P. B. (Northville, MI), “On-wafer packaging for RFMEMS,” February 24, 2004. Chinthakindi, Anil K. (Fishkill, NY), Groves, Robert A. (Highland, NY), Stein, Kenneth J. (Sandy Hook, CT), Subbanna, Seshadri (Brewster, NY), Volant, Richard P. (New Fairfield, CT), “Microelectromechanical varactor with enhanced tuning range,” February 24, 2004. Chinthakindi, Anil K. (Poughkeepsie, NY), Groves, Robert A. (Highland, NY), Stein, Kenneth J. (Sandy Hook, CT), Subbanna, Seshadri (Brewster, NY), Volant, Richard P. (New Fairfield, CT), “Micro-electromechanical varactor with enhanced tuning range,” December 9, 2003.

19

20


6,639,313

6,635,509 6,627,814

6,624,003

6,580,858

6,535,685

6,516,131

6,516,104 6,481,570

6,455,878

6,400,009

6,379,988

Silberman, Donn Michael (Aliso Viejo, CA), “Variable spacing diffraction grating,” November 4, 2003. Martin, John R. (Foxborough, MA), Harney, Kieran H. (Andover, MA), “Hermetic seals for large optical packages and the like,” October 28, 2003. Ouellet, Luc (Granby, CA), “Wafer-level MEMS packaging,” October 21, 2003. Stark, David H. (Evergreen, CO), “Hermetically sealed micro-device package with window,” September 30, 2003. Rice, Janet L. (Round Rock, TX), “Integrated MEMS device and package,” September 23, 2003. Chen, Jingkuang (Rochester, NY), Kubby, Joel A. (Rochester, NY), Sun, Decai (Los Altos, CA), “Micro-opto-electro-mechanical system (MOEMS),” June 17, 2003. Tullis, Barclay J. (Palo Alto, CA), “Arcuate fiber routing using stepped grooves,” March 18, 2003. Tullis, Barclay J. (Palo Alto, CA), “Structures and methods for aligning fibers,” February 4, 2003. Furuyama, Hideto (Kanagawa-ken, JP), “Optical wiring device,” February 4, 2003. Henshall, Gordon D (Harlow, GB), Rolt, Stephen (Herts, GB), “Packaging atmosphere and method of packaging a MEMS device,” November 19, 2002. Bhat, Jerome Chandra (San Francisco, CA), Ludowise, Michael Joseph (San Jose, CA), Steigerwald, Daniel Alexander (Cupertino, CA), “Semiconductor LED flip-chip having low refractive index underfill,” September 24, 2002. Bishop, David John (Summit, NJ), Gates, II, John VanAtta (New Providence, NJ), Kim, Jungsang (Basking Ridge, NJ), “Hermatic firewall for MEMS packaging in flip-chip bonded geometry,” June 4, 2002. Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Pre-release plastic packaging of MEMS and IMEMS devices,” April 30, 2002.


6,297,072

1.6.2

Peterson, Kenneth A. (Albuquerque, NM), Conley, William R. (Tijeras, NM), “Protection of microelectronic devices during packaging,” January 1, 2002. Tilmans, Hendrikus A. C. (Maastricht, NL), Beyne, Eric (Leuven, BE), Van de Peer, Myriam (Brussel, BE), “Method of fabrication of a microstructure having an internal cavity,” October 2, 2001.

Japanese MEMS Packaging Patents

Some of the Japanese MEMS packaging patents selected from the Japan Patent Office (JPO) since 2001 are as follows: Patent No. 2008-298950 2008-244442

2008-229823 2008-221450

2008-211124 2008-209616

2008-198607

2008-193544

2008-185723 2008-185621

Owner(s)/Title/Date Yokoi, Junichi, “Optical scanning apparatus,” 11.12.2008. Seppala, Bryan R., Curtis, Harlan L., DCamp, Jon B., Spielberger, Richard K., “System and method for sealing MEMS device,” 09.10.2008. Aoki, Toshihiko, “Manufacturing method of MEMS device,” 02.10.2008. Fujii, Yoshio, Ogawa, Shinpei, Yokoyama, Yoshinori, Endo, Kazuyo, “MEMS package and manufacturing method therefor,” 25.09.2008. Chino, Mitsuru, “Semiconductor device storing package,” 11.09.2008. Kato, Seiichi, Nanjo, Takeshi, Otaka, Koichi, “Optical deflector and method of manufacturing the same,” 11.09.2008. Arthur, Stephen D., Elasser, Ahmed, Wright, Joshua Isaac, Subramanian, Kanakasabapathi, Keimel, Christopher Fred, Gowda, Arun Virupaksha, “Power overlay structure for MEM device, and method for producing power overlay structure for MEM device,” 28.08.2008. Aoki, Nobuhisa, Takano, Takeshi, Miyashita, Takumi, “Amplifier which takes internal matching according to signal characteristic,” 21.08.2008. Yokoi, Junichi, Sakai, Toshio, “Optical scanner,” 14.08.2008. Fujino, Hitoshi, Sakai, Toshio, “Optical deflector,” 14.08.2008.

21

22

Chapter One 2008-182103 2008-132587

2008-105162 2008-091334

2008-047955

2007-331099

2007-331098

2007-281292 2007-245339

2007-221105 2007-218902 2007-214440 2007-214439 2007-203451 2007-155714 2007-144617 2007-136668

Hatakeyama, Tomoyuki, “Airtight seal package,” 07.08.2008. Eskridge, Mark H., Jafri, Ijaz H., “Method of manufacturing wafer-level vacuum packaged device,” 12.06.2008. Hata, Shohei, Sakamoto, Eiji, Matsushima, Naoki, “Functional element,” 08.05.2008. Manuel, Carmona Flores, Kihara, Tatsuji, Jaume, Esteve Tinto, “MEMS package, and manufacturing method therefore, as well as integrated circuit including MEMS package,” 17.04.2008. Tenmyo, Hiroyuki, Isada, Naoya, Matsumoto, Kunio, Watanabe, Kazushi, Nagashima, Shiro, “Packaging structure having three-dimensional wiring,” 28.02.2008. Pyo, Sung-gyu, Kim, Dong-joon, “Package for MEMS element, and method for manufacturing the same,” 27.12.2007. Kim, Dong-joon, Pyo, Sung-gyu, “Package of MEMS device and method for manufacturing the same,” 27.12.2007. Ohara, Satoshi, “Semiconductor device mounting structure,” 25.10.2007. Robert, Philippe, “Microelectronic composite, especially packaging structure in sealing cavity of MEMS,” 27.09.2007. Eskridge, Mark H., “Sealing of MEMS device using liquid crystal polymer,” 30.08.2007. Eskridge, Mark H., “Discrete stress isolator,” 30.08.2007. Kuramochi, Satoru, Fukuoka, Yoshitaka, “Electronic device,” 23.08.2007. Satoru, Kuramochi and Yoshitaka, Fukuoka, “Composite sensor package,” 23.08.2007. MacGugan, Douglas C., “Integrated MEMS package,” 16.08.2007. MacGugan, Douglas C., “Compact package for moving sensor sensing axis,” 21.06.2007. D’Camp, Jon B., Curtis, Harlan L., “MEMS device packaging method,” 14.06.2007. D’Camp, Jon B., Curtis, Harlan L., “MEMS flipchip packaging,” 07.06.2007.

Introduction to MEMS 2007-132687 2007-124500

2007-108753

2007-088189

2007-082233 2007-060661

2007-042786 2007-017199

2006-321016 2006-286794 2006-270045

2006-247833

2006-202909

Taniguchi, Hajime, “Package for sensor, and detector using the same,” 31.05.2007. Yoshida, Koichi, Yamada, Toru, Kojima, Hideki, Makihata, Katsuhiro, “Acoustic sensor and method for manufacturing acoustic sensor,” 17.05.2007. Park, Heung-woo, Lee, Yeong-gyu, Boku, Shoshu, Lim, Ohk-kun, Park, Dong-hyun, “MEMS package and optical modulator module package,” 26.04.2007. Tenmyo, Hiroyuki, Isada, Naoya, Isobe, Atsushi, Terano, Akihisa, Matsumoto, Kunio, Ite, Mayumi, “MEMS (micro electronic mechanical system) package and its manufacturing method,” 05.04.2007. So, Seitan, “Silicon capacitor microphone and method for packaging same,” 29.03.2007. So, Seitan, “Silicon based condenser microphone and packaging method for the same,” 08.03.2007. Oya, Yoichi, “Micro device and its packaging method,” 15.02.2007. Tokushige, Nobuaki, Naka, Toshio, “Chip scale package and its manufacturing method,” 25.01.2007. Yoshikawa, Yasuhiro, Tajiri, Hiroyuki, “MEMS package,” 30.11.2006. Takahashi, Norio, “Semiconductor chip package and its manufacturing method,” 19.10.2006. Lim, Chang Hyun, Hwang, Woong Lin, Choi, Seog Moon, Park, Ho Joon, Lee, Sung Jun, Choi, Sang Hyun, “Light emitting diode package having electrostatic discharge protection functionality,” 05.10.2006. Kim, Jong-seok, Kim, Duck-hwan, Nam, Kuang-woo, Park, Yun-kwon, Yun, Seok-chul, Choa, Sung-hoon, So, Inso, “MEMS element package and its manufacturing method,” 21.09.2006. Ikeuchi, Naoki, Hashimoto, Hiroyuki, “Semiconductor device having minute structure and method of manufacturing minute structure,” 03.08.2006.

23

24

Chapter One 2006-190804

2006-186376

2006-186362

2006-173599

2006-173598

2006-147995

2006-123160

2006-121052

2006-121043

2006-119603

2006-099107

2006-099096

Kodate, Junichi, Machida, Katsuyuki, Urano, Masami, “Semiconductor device and its manufacturing method,” 20.07.2006. Kim, Jong-seok, Park, Yun-kwon, So, Inso, Kim, Duck-hwan, Nam, Kuang-woo, Yun, Seok-chul, “MEMS element and its manufacturing method,” 13.07.2006. Kim, Jong-seok, Park, Yun-kwon, So, Inso, Nam, Kuang-woo, Yun, Seok-chul, “MEMS element package and its manufacturing method,” 13.07.2006. Fazzio, Ronald S., Dungan, Thomas E., “Integrated wafer package of micro electrical machine and active device circuit,” 29.06.2006. Dungan, Thomas E., Fazzio, Ronald S., “Single integrated wafer package and assembling method of wafer package,” 29.06.2006. Kodate, Junichi, Machida, Katsuyuki, Urano, Masami, Kuwabara, Hiroshi, Terada, Jun, “Variable capacitance element and manufacturing method thereof,” 08.06.2006. Palmateer, Lauren, Gally, Brian J., Cummings, William J., “Method and device for providing MEMS device package having secondary seal,” 18.05.2006. Palmateer, Lauren, Cummings, William J., Gally, Brian J., Chui, Clarence, Kothari, Manish, “Method and system for packaging MEMS device together with incorporated getter,” 11.05.2006. Palmateer, Lauren, Cummings, William J., Gally, Brian J., Sampsell, Jeffrey B., “System and method for display provided with activated desiccant,” 11.05.2006. Gally, Brian J., Palmateer, Lauren, Cummings, William J., “System and method for protecting microelectromechanical system using backplate with non-flat portion,” 11.05.2006. Palmateer, Lauren, “System and method for display device with end-of-life phenomenon,” 13.04.2006. Floyd, Philip D., Arbuckle, Brian W., “Device having patterned spacer for backplate and method of making the same,” 13.04.2006.

Introduction to MEMS 2006-091849

2006-003277

2005-332957 2005-329532

2005-276816

2005-250307 2005-166909 2005-109221

2005-040940

2005-034987 2005-019966

2005-018015

2004-322157

2004-235465 2004-160654

Miles, Mark W., Sampsell, Jeffrey B., Palmateer, Lauren, Arbuckle, Brian W., Floyd, Philip D., “Method and system to package MEMS device,” 06.04.2006. Kanno, Yoshinori, “Semiconductor acceleration sensor system and its manufacturing method,” 05.01.2006. Okamoto, Kazuhisa, “Package manufacturing method,” 02.12.2005. Hong, Suk-kee, Lee, Yeong-gyu, Park, Heungwoo, “MEMS package having side seal member and its manufacturing method,” 02.12.2005. Tsui, Kenneth, Geisberger, Aaron, Skidmore, George, “Micro connector and non-powered microassembly with micro connector,” 06.10.2005. Hara, Koichi, “Optical deflector,” 15.09.2005. Yamamoto, Satoshi, Suemasu, Tatsuo, “Package and its manufacturing method,” 23.06.2005. Kawakubo, Takashi, Yasumoto, Yasuaki, Itaya, Kazuhiko, “Wafer-level package and its manufacturing method,” 21.04.2005. Snyder, Tanya Jegeris, Yi, Robert H., Wilson, Robert Edward, “Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging,” 17.02.2005. Smith, Mark A., Boucher, William R., Haluzak, Charles C., “Fluidic MEMS device,” 10.02.2005. Ikeda, Osamu, Okoda, Toshiyuki, “Semiconductor device and method of manufacturing the same,” 20.01.2005. Lee, Hyun Kee, Jung, Sung Cheon, Hong, Yoon Shik, “Optical switch and manufacturing method thereof,” 20.01.2005. Hino, Atsushi, Matsumura, Takeshi, “Working method for work and tacky adhesive sheet used for the same,” 18.11.2004. Yuasa, Mitsuhiro, “Bonding method, bonding device and sealant,” 19.08.2004. Lee, Eun-sung, Koh, Byeong-cheon, Moon, Chang-youl, Chun, Kuk Jin, “Side-bonding method for flip chip system in semiconductor device, MEMS device package and package method using the same,” 10.06.2004.

25

26

Chapter One 2004-160649

2004-158665

2004-136435

2003-347357 2003-297876

2003-243550

2003-075741

2002-246489

2002-236266

2002-043463

2002-043449

2001-196484

2001-185635

Lee, Moon-chul, Jun, Chan-bong, Choi, Hyung, Jung, Kyu-dong, Jang, Mi, Hong, Seog-woo, Kang, Seok-jin, Chung, Seok-whan, “Forming method of via hole of glass wafer,” 10.06.2004. Usami, Akira, Ohashi, Hidemasa, Nishino, Tamotsu, Owada, Satoru, Maeda, Chisako, Yoshida, Yukihisa, “Substrate for package and its manufacturing method,” 03.06.2004. Song, Ci-moo, Kang, Seok-jin, Chung, Seokwhan, Lee, Moon-chul, Jung, Kyu-dong, Kim, Jong-seok, Jun, Chan-bong, Hong, Seog-woo, Kang, Jung-ho, “Method of metal wiring for undercut,” 13.05.2004. Kawaguchi, Hitoshi, “Manufacturing method of semiconductor package,” 05.12.2003. Kawaguchi, Hitoshi, Takahashi, Toyomasa, “Manufacturing method for semiconductor package,” 17.10.2003. Kim, Woon-bae, Shin, Keisai, Cho, Soko, Kang, Seung-goo, “Hermetic sealing method for oxidation prevention at low temperature,” 29.08.2003. Boie, Robert Albert, Kim, Yunsang, Soh, Hyongsok, “Constitution of MEMS driver circuit,” 12.03.2003. Cho, Chang-ho, Shin, Hyung-jae, Kim, Woonbae, “Wafer level hermetic sealing method,” 30.08.2002. Jin, Sungho, Soh, Hyongsok, “Magnetically packaged optical MEMS device and method for making the same,” 23.08.2002. Kang, Seok-jin, “Surface mounting type chip scale packaging method of electronic and MEMS element,” 08.02.2002. Degani, Yinon, Dudderar, Thomas D., Tai, King L., “Micro mechanical packaging apparatus,” 08.02.2002. Ha, Byeoung Ju, Baek, Seog-soon, Kim, Hyunchul, Song, Hoon, Oh, Yong-soo, “Manufacturing method of MEMS structure enabling wafer level vacuum packaging,” 19.07.2001. Bishop, David John, Gates, John Vanatta, Kim, Jungsang, “Package having cavity for housing MEMS,” 06.07.2001.

Introduction to MEMS 2001-144117

Oakatto, John W., Downa, Andrew Steven, Rin, Tsuen Fwan, “Improved MEMS wafer-level package,” 25.05.2001.

1.6.3 Worldwide MEMS Packaging Patents Some of the MEMS packaging patents selected from European Patent Office (EPO) since 2002 are as follows: Title/Owner(s)/Patent No./Date 1. “Wafer level chip size package for MEMS devices and method for fabricating the same,” Wang, Zhiqi (CN), Yu, Guoqing (CN) (+2), US2009057868 (A1)—2009-03-05. 2. “Method for packaging an optical MEMS device,” Khonsari, Nassim (US), Chui, Clarence (US), EP2029473 (A2)—200903-04. 3. “Patterned contact sheet to protect critical surfaces in manufacturing processes,” Ya, Michael Wang Qing (US), Zhang, Junhong (US), CN101323428 (A)—2008-12-17. 4. “Vertically integrated 3-axis MEMS accelerometer with electronics,” Nasiri, Steven S. (US), Seeger, Joseph (US) (+1), US2008314147 (A1)—2008-12-25. 5. “Mirror and mirror layer for optical modulator and method,” Chui, Clarence (US), Sampsell, Jeffrey B. (US), US2008314866 (A1)—2008-12-25. 6. “System and method of fabricating micro cavities,” Wan, Chang-Feng (US), US2008308920 (A1)—2008-12-18. 7. “Electronic device comprising a MEMS element,” Dekker, Ronald (NL), Polhmann, Hauke (NL) (+1), CN101309854 (A)—2008-11-19. 8. “Apparatus for downhole fluids analysis utilizing micro electro mechanical systems (MEMS) or other sensors,” Terabayashi, Toru (VG), Sugimoto, Tsutomu (VG) (+3), CN101309853 (A)— 2008-11-19. 9. “MEMS device vacuum encapsulation method,” Jin, Yufeng (CN), Zhang, Yangfei (CN) (+2), CN101301993 (A)—2008-11-12. 10. “Packaging body and packaging component for microphone of micro electro-mechanical systems,” Huang, Zhaoda (CN), Jian, Xintang (CN), CN101316462 (A)—2008-12-03. 11. “Packaging body and packaging component for microphone of micro electro-mechanical systems,” Huang, Zhaoda (CN), Jian, Xintang (CN), CN101316461 (A)—2008-12-03. 12. “Packaging of Mems devices,” Johnson, Donald W. (US), Nagale, Milind P. (US), EP1997128 (A2)—2008-12-03.

27

28

Chapter One 13. “Silicon microphone with improved structure,” Wang, Xianbin (CN), Dang, Maoqiang (CN) (+2), CN201138866 (Y)—2008-10-22. 14. “Package and packaging assembly of microelectromechanical sysyem microphone,” Huang, Chao-Ta (TW), Chien, Hsin-Tang (TW), US2008283988 (A1)—2008-11-20. 15. “Package and packaging assembly of microelectromechanical sysyem microphone,” Huang, Chao-Ta (TW), Chien, Hsin-Tang (TW), US2008283942 (A1)—2008-11-20. 16. “Capacitance type micro-accelerometer,” Liu, Minjie (CN), Liu, Yunfeng (CN) (+2), CN101271125 (A)—2008-09-24. 17. “Silicon piezoresistance type pressure transducer encapsulation structure based on substrates,” Wang, Yuelin (CN), Wu, Yanhong (CN) (+2), CN101271029 (A)—2008-09-24. 18. “MEMS device support structure for sensor packaging,” Ahmad, Nazir (US), US2008277747 (A1)—2008-11-13. 19. “MEMS device with integral packaging,” Cohn, Michael B. (US), Xu, Ji-Hai (US), US2008272867 (A1)—2008-11-06. 20. “Packaged MEMS device assembly,” Haluzak, Charles C. (US), Pollard, Jeffrey R. (US) (+5), US2008272446 (A1)—2008-11-06. 21. “MEMS device airtightness packaging method,” Chen, Jing (CN), Wu, Yexian (CN) (+1), CN101234745 (A)—2008-08-06. 22. “Orientation-dependent etching of deposited AIN for structural use and sacrificial layers in MEMS,” Bouche, Guillaume (US), Wall, Ralph N. (US), US2008268575 (A1)—2008-10-30. 23. “Packaging a MEMS device using a frame,” Natarajan, Bangalore R. (US), EP1979268 (A2)—2008-10-15. 24. “Microelectromechanical systems, and methods for encapsualting and fabricating same,” Partridge, Aaron (US), Lutz, Markus (US) (+1), US2008237756 (A1)—2008-10-02. 25. “Functional device,” Hata, Shohei (JP), Sakamoto, Eiji (JP) (+1), US2008233349 (A1)—2008-09-25. 26. “Power overlay structure for MEM device, and method for producing power overlay structure for MEM device,” Arthur, Stephen D., Elasser, Ahmed (+4), JP2008198607 (A)—200808-28. 27. “MEMS fiber optic microphone,” Chin, Ken K. (US), Feng, Guanhua (US) (+1), WO2008100266 (A2)—2008-08-21. 28. “Apparatus for driving micromechanical devices,” Miles, Mark W. (US), US2008191978 (A1)—2008-08-14.

Introduction to MEMS 29. “Method for manufacturing a semiconductor package structure having micro-electro-mechanical systems,” Wang, MengJen (TW), Yang, Hsueh-An (TW), US2008188026 (A1)—200808-07. 30. “Package and method for making the same,” Wang, MengJen (TW), US2008185706 (A1)—2008-08-07. 31. “Methods and systems for wafer level packaging of MEMS structures,” Yang, Xiao (US), Payne, Justin (US) (+3), WO2008085779 (A1)—2008-07-17. 32. “Design of MEMS packaging,” Kvisteroy, Terje (NO), Westby, Eskild (NO), US2008164546 (A1)—2008-07-10. 33. “Packaging structure and method of a MEMS microphone,” Hsiao, Wei-Min (TW), US2008166000 (A1)—2008-07-10. 34. “MEMS packaging with reduced mechanical strain,” Kvisteroy, Terje (NO), Westby, Eskild (NO), EP1944266 (A1)—2008-07-16. 35. “Packaging of Micro Devices,” O’Mahony, Conor (IE), Hill, Martin (IE), US2008145976 (A1)—2008-06-19. 36. “High-aspect-ratio metal-polymer composite structures for nano interconnects,” Aggarwal, Ankur (US), Raj, Pulugurtha Markondeya (US) (+1), US2008136035 (A1)—2008-06-12. 37. “MEMS package and packaging method thereof,” Jung, Sung-Hae (KR), Lee, Myung-Lae (KR) (+4), WO2008069394 (A1)—2008-06-12. 38. “Integrated thermal systems,” Henderson, H. Thurman (US), Shuja, Ahmed (US) (+3), US2008128898 (A1)—2008-06-05. 39. “Microelectromechanical devices and fabrication methods,” Metz, Matthias (US), Pan, Zhiyu (CN) (+3), WO2008067097 (A2)—2008-06-05. 40. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), CN101183675 (A)—2008-05-21. 41. “Polymer object optical fabrication process,” Cregger, Robert Brian (US), WO2008063433 (A2)—2008-05-29. 42. “X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Seeger, Joseph (US), Nasiri, Steven S. (US) (+1), US2008115579 (A1)—2008-05-22. 43. “MEMS package, and manufacturing method therefore, as well as integrated circuit including MEMS package,” Manuel, Carmona Flores, Kihara, Tatsuji (+1), JP2008091334 (A)— 2008-04-17.

29

30

Chapter One 44. “Microelectronic flow sensor packaging method and system,” Ricks, Lamar F. (US), WO2008057911 (A2)—2008-05-15. 45. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), GB2443352 (A)—2008-04-30. 46. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satayadev R. (US), Huibers, Andrew G. (US) (+8), US2008096313 (A1)—2008-04-24. 47. “Package structure and packaging method of MEMS microphone,” Chen, Jung-Tai (TW), Chu, Chun-Hsun (TW), US2008083960 (A1)—2008-04-10. 48. “Laser assisted system and method for bonding of surfaces,” Wang, Changhai (GB), Hand, Duncan (GB) (+1), EP1907160 (A1)—2008-04-09. 49. “Method for preparing spherical glass micro-cavity used for MEMS disc type packaging,” Shang, Jintang (CN), Huang, Qingan (CN) (+2), CN101143702 (A)—2008-03-19. 50. “Chip packaging systems and methods,” D’Camp, Jon B. (US), Curtis, Harlan L. (US) (+2), US2008063505 (A1)—2008-03-13. 51. “Micro electro-mechanical system module package,” Yen, Tzu-Yin (TW), Yeh, Cung-Mao (TW), US2008061409 (A1)— 2008-03-13. 52. “Integrated MEMS packaging,” Lu, Jun (CA), Menard, Stephane (CA), WO2008034233 (A1)—2008-03-27. 53. “Packaging structure having three-dimensional wiring,” Tenmyo, Hiroyuki, Isada, Naoya (+3), JP2008047955 (A)— 2008-02-28. 54. “MEMS fiber optic microphone,” Chin, Ken K. (US), Feng, Guanhua (US) (+1), US2008049230 (A1)—2008-02-28. 55. “MEMS packaging with improved reaction to temperature changes,” Strei, David (US), CN101098825 (A)—2008-01-02. 56. “Method and system for sealing packages for optics,” Yang, Xiao (US), Chen, Dongmin (US), US2008014682 (A1)—200801-17. 57. “MEMS microphone packaging structure,” Pan, Zhengmin (CN), CN200994191 (Y)—2007-12-19. 58. “Multiple internal seal ring micro-electro-mechanical system vacuum packaging method,” Hayworth, Ken J. (US), Yee, Karl Y. (US) (+5), US2007298542 (A1)—2007-12-27. 59. “Method for forming a hermetically sealed cavity,” Witvrouw, Ann (BE), Rico, Raquel H. (ES) (+1), US2007298238 (A1)—200712-27.

Introduction to MEMS 60. “Stacked die package for MEMS resonator system,” Gupta, Pavan (US), Razda, Eric (US), US2007290364 (A1)—2007-12-20. 61. “Hermetically sealed wafer level packaging for optical MEMS devices,” Yang, Xiao (US), GB2439403 (A)—2007-12-27. 62. “Method for manufacturing plastic packaging of MEMS devices and structure thereof,” Chen, Jung Tai (TW), Chang, Wen Yang (TW) (+2), KR20070095756 (A)—2007-10-01. 63. “MEMS device packaging methods,” D’Camp, Jon B., Curtis, Harlan L., SG132639 (A1)—2007-06-28. 64. “MEMS flip-chip packaging,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), SG132638 (A1)—2007-06-28. 65. “Condenser microphone and packaging method for the same,” Song, Chung-Dam, SG131039 (A1)—2007-04-26. 66. “Silicon based condenser microphone and packaging method for the same,” Song, Chung-Dam, SG130158 (A1)—2007-03-20. 67. “Desiccant in a MEMS device,” Palmateer, Lauren (US), WO2007136706 (A1)—2007-11-29. 68. “Semiconductor device having microstructure and method of manufacturing microstructure,” Ikeuchi, Naoki (JP), Hashimoto, Hiroyuki (JP), US2007262306 (A1)—2007-11-15. 69. “High performance MEMS packaging archetecture,” Lafond, Peter H. (US), Yu, Lianzhong (US), EP1853928 (A1)—2007-11-14. 70. “Contact planarization materials that generate no volatile byproducts or residue during curing,” Shih, Wu-Sheng (TW), Lamb, James E. III (US) (+1), TW278488 (B)—2007-04-11. 71. “Packaging structure of MEMS microphone,” Park, Peter (KR), Choo, Yun-Jai (KR) (+1), WO2007123300 (A1)—2007-11-01. 72. “Packaging structure of MEMS microphone,” Choo, Yunjai (KR), Park, Peter (KR), WO2007123293 (A1)—2007-11-01. 73. “Method and system for packaging a MEMS device,” Miles, Mark W. (US), Sampsell, Jeffrey B. (US), US2007247693 (A1)— 2007-10-25. 74. “Packaging a MEMS device using a frame,” Natarajan, Bangalore R. (US), Palmateer, Lauren (US), US2007242345 (A1)— 2007-10-18. 75. “MEMS devices and processes for packaging such devices,” Natarajan, Bangalore R. (US), Ganti, Surya (US), US2007242341 (A1)—2007-10-18. 76. “Microelectronic composite, especially packaging structure in sealing cavity of MEMS,” Robert, Philippe, JP2007245339 (A)—2007-09-27.

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Chapter One 77. “Surface coating for electronic systems,” Cho, Junghyun (US), Oliver, Scott (US) (+2), US7282254 (B1)—2007-10-16. 78. “Self-packaging MEMS device,” Heck, John (US), US2007235501 (A1)—2007-10-11. 79. “Multi-unit planar lightwave circuit wavelength dispersive device,” Colbourne, Paul (CA), CA2584147 (A1)—2007-10-06. 80. “Packaging structure of MEMS microphone,” Park, Sung Ho (KR), Lim, Jun (KR) (+1), KR100737726 (B1)—2007-07-04. 81. “Packaging structure of MEMS microphone and construction method thereof,” Choo, Yun Jai (KR), Park, Peter (KR) (+1), KR100737728 (B1)—2007-07-04. 82. “Method of packaging of MEMS device at the vacuum state using a silicide bonding,” Lee, Ho Young (KR), Cho, Sung Woo (KR), KR20070078239 (A)—2007-07-31. 83. “Method of packaging of MEMS device at the vacuum state using a silicide bonding and vacuum packaged MEMS device using the same,” Lee, Ho Young (KR), Cho, Sung Woo (KR), KR20070078233 (A)—2007-07-31. 84. “Microstructure sealing tool and methods of using the same,” Schaadt, Gregory P. (US), US2007172991 (A1)—2007-07-26. 85. “Systems and methods of controlling micro-electromechanical devices,” Miles, Mark W. (US), US2007146376 (A1)—200706-28. 86. “Method for singulating a released microelectromechanical system wafer,” Loeppert, Peter V. (US), WO2007081346 (A1)— 2007-07-19. 87. “Micro-electro-mechanical systems (MEMS) device and system and method of producing the same,” Bar-Sadeh, Eyal (IL), Talalaevski, Alexander (IL) (+1), TW267490 (B)—2006-12-01. 88. “MEMS module package and packaging method,” Lee, Yeong Gyu (KR), KR20070042244 (A)—2007-04-23. 89. “MEMS device package and packaging method,” Kim, Dae Jun (KR), Lee, Yeong Gyu (KR) (+1), KR20070040472 (A)— 2007-04-17. 90. “MEMS device package and packaging method,” Kim, Dae Jun (KR), Lee, Yeong Gyu (KR) (+1), KR20070040471 (A)— 2007-04-17. 91. “MEMS module and packaging method,” Lee, Yeong Gyu (KR), KR20070040033 (A)—2007-04-16. 92. “Method for adjusting the frequency of a MEMS resonator,” Lutz, Aaron, Partridge, Markus (DE), CN1977448 (A)—200706-06.

Introduction to MEMS 93. “Micro electro-mechanical system packaging and interconnect,” Chen, Chien-Hua (US), Bamber, John (US) (+1), US2007128828 (A1)—2007-06-07. 94. “Wafer level packaging process,” Sridhar, Uppili (US), Zou, Quanbo (US), WO2007055924 (A2)—2007-05-18. 95. “Miniature package for translation of sensor sense axis,” MacGugan, Douglas C. (US), EP1785392 (A2)—2007-05-16. 96. “Method for integrated MEMS packaging,” Hartzell, John W. (US), Walton, Harry G. (GB) (+1), US2007099327 (A1)—200705-03. 97. “Systems and methods of testing micro-electromechanical devices,” Miles, Mark W. (US), US2007097134 (A1)—2007-05-03. 98. “Microphone and manufacturing method thereof,” Jang, Jau-Jr (TW), Tsai, Tzuen-Yi (TW) (+1), TW262735 (B)—2006-09-21. 99. “MEMS (micro electronic mechanical system) package and its manufacturing method,” Tenmyo, Hiroyuki, Isada, Naoya (+4), JP2007088189 (A)—2007-04-05. 100. “Micro electromechanical system chip size airtight packaging vertical interconnecting structure and its manufacturing method,” Wang, Yuchuan Luo (CN), CN1935630 (A)—200703-28. 101. “MEMS package and method of forming the same,” McBean, Ronald V. (US), WO2007027380 (A2)—2007-03-08. 102. “Micro device and its packaging method,” Oya, Yoichi, JP2007042786 (A)—2007-02-15. 103. “Microelectromechanical devices and fabrication methods,” Yama, Gary (US), US2007042521 (A1)—2007-02-22. 104. “Chip scale package and its manufacturing method,” Tokushige, Nobuaki, Naka, Toshio, JP2007017199 (A)—2007-01-25. 105. “MEMS micro high sensitivity magnetic field sensor and manufacturing method,” Liu, Wu Yaming (CN), CN1912646 (A)—2007-02-14. 106. “Silicon based condenser microphone and packaging method for the same,” Song, Chung-Dam (KR), WO2007015593 (A1)— 2007-02-08. 107. “MEMS packaging method for enhanced EMI immunity using flexible substrates,” Wang, Zhe (SG), Miao, Yubo (SG), US2007013052 (A1)—2007-01-18. 108. “Method of making an X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steven S. (US), Flannery, Anthony F., Jr. (US), US2007012653 (A1)—2007-01-18.

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Chapter One 109. “Method and system for packaging MEMS devices with incorporated getter,” Palmateer, Lauren (US), Cummings, William J. (US) (+3), KR20060092914 (A)—2006-08-23. 110. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev R. (US), Huibers, Andrew G. (US) (+1), US2007001247 (A1)—2007-01-04. 111. “Two-freedom air-floated precisely locating platform for IC packaging,” Zhang, Dawei (CN), CN1887686 (A)—2007-01-03. 112. “MEMS package,” Yoshikawa, Yasuhiro, Tajiri, Hiroyuki, JP2006321016 (A)—2006-11-30. 113. “Encapsulation process for microelectromechanical structures,” Dudley, Bruce W., Wood, Robert L., KR20010051498 (A)—200106-25. 114. “Method of packaging MEMS,” Ouellet, Luc (CA), Chowdhury, Mamur (CA), EP1734001 (A2)—2006-12-20. 115. “Display device having a movable structure for modulating light and method thereof,” Miles, Mark W. (US), US2006274074 (A1)—2006-12-07. 116. “Production method of glass penetrating wiring board, glass penetrating wiring board, and probe card and packaging element using glass penetrating wiring board,” Fujimoto, Satoshi (JP), WO2006129848 (A1)—2006-12-07. 117. “X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steve S. (US), Seeger, Joseph (US), TW247896 (B)— 2006-01-21. 118. “Packaging method for rf mems switch to minimize short of switch connection,” Lee, Gyu Bok, KR20040093807 (A)—200411-09. 119. “Bonding method of flip-chip manner for semiconductor apparatus in lateral bonded type, MEMS package using the same, and packaging method,” Jin, Jun Guk, Cheon, Ko Byeong (+2), KR20040042924 (A)—2004-05-22. 120. “Method for forming via hole of glass wafer,” Choi, Hyeong, Hong, Seok U. (+6), KR20040042003 (A)—2004-05-20. 121. “Metal line method even though it has undercut,” Hong, Seok U., Jun, Chan Bong (+7), KR20040034949 (A)—200404-29. 122. “MEMS switch and method for packaging the same,” Lee, Dae Sung (KR), Sung, Woo Kyung (KR) (+3), KR20050113340 (A)—2005-12-02.

Introduction to MEMS 123. “Method of packaging of MEMS device at the vacuum state and vacuum packaged MEMS device using the same,” Lee, Ho Young (KR), Kim, Yong Hyup (KR) (+3), KR20050100039 (A)—2005-10-18. 124. “Electronic parts packaging structure and method of manufacturing the same,” Sunohara, Masahiro (JP), Higashi, Mitsutoshi (JP), US2006246630 (A1)—2006-11-02. 125. “Apparatus for packaging MEMS element and method thereof,” Jang, Hyuk Kyoo (KR), Noh, Seung Jeong (KR) (+3), KR20060061044 (A)—2006-06-07. 126. “Pizoelectric rf MEMS switch using wafer unit packaging and microfabrication technology and fabrication method thereof,” Park, Jae Hyoung (KR), Lee, Hee Chul (KR) (+1), KR20060022561 (A)—2006-03-10. 127. “Method for manufacturing structure of micro electromechanical system capable of wafer-level vacuum packaging,” Baek, Seok Sun (KR), Ha, Byeong Ju (KR) (+3), KR20010045332 (A)—2001-06-05. 128. “Variable display,” Jensen, Thomas (US), Lawler, Casimer E., Jr. (US), US2006227002 (A1)—2006-10-12. 129. “MEMS packaging structure and methods,” Haluzak, Charles C. (US), Pollard, Jeffrey R. (US), US2006228869 (A1)—200610-12. 130. “Reactive nano-layer material for MEMS packaging,” Lu, Daoqiang (US), Heck, John (US), US2006220223 (A1)—200610-05. 131. “Method of fabrication of AI/GE bonding in a wafer packaging environment and a product produced therefrom,” Nasiri, Steven S. (US), Flannery, Anthony Francis, Jr. (US), WO2006101769 (A2)—2006-09-28. 132. “Structure and process for packaging RF MEMS and other devices,” Schaper, Leonard W. (US), Malshe, Ajay P. (US) (+1), US2006211177 (A1)—2006-09-21. 133. “Passive devices and modules for transceiver and manufacturing method thereof,” Song, In Sang (KR), KR20020095728 (A)—2002-12-28. 134. “MEMS device for wafer level packaging and method for fabricating the same,” Jin, Jang Seok (KR), KR20020058223 (A)— 2002-07-12. 135. “MEMS packaging using a non-silicon substrate for encapsulation and interconnection,” Heck, John (US), Hayden, Joseph S., III (US) (+2), US2006194361 (A1)—2006-08-31.

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Chapter One 136. “Optical fiber MEMS pressure sensor packaging structure,” Li, Wang Ming (CN), CN2811965 (Y)—2006-08-30. 137. “Low temperature airtightness packaging method for wafer level micro machinery device and photoelectric device,” Wu, Liu Yufei (CN), CN1821052 (A)—2006-08-23. 138. “Heating device for automatic anode linkage of MEMS hightemperature pressure sensor,” Rong, Xie Hui (CN), CN1815705 (A)—2006-08-09. 139. “Packaging of micro devices,” O’Mahony, Conor (IE), Hill, Martin (IE), IE20060046 (A1)—2006-07-26. 140. “Ultra-small profile, low cost chip scale accelerometers of two and three axes based on wafer level packaging,” Liu, Sheng (CN), Chen, Bin (US) (+3), US2006179940 (A1)—200608-17. 141. “Laser assisted chemical etching method for release of microscale and nanoscale devices,” Abraham, Margaret H. (US), Helvajian, Henry (US) (+1), US2006183330 (A1)—200608-17. 142. “Dimesize attitude measurement system in magnetic infrared ray,” Liu, Ye Xiongying (CN), CN1796932 (A)—2006-07-05. 143. “A packaging method for MEMS devices, and MEMS packages produced using the method,” Wang, Zhe (SG), WO2006085825 (A1)—2006-08-17. 144. “Monolithically integrated switchable circuits with MEMS,” Yang, Jeffrey M. (US), Nishimoto, Matt (US) (+3), WO2006083432 (A1)—2006-08-10. 145. “Method and system for packaging MEMS devices with incorporated getter,” Cummings, Manish, Gall, William J. (US), CN1773358 (A)—2006-05-17. 146. “Method and system for packaging a MEMS device,” Miles, Mark W., Sampsell, Jeffrey (US), CN1755473 (A)—2006-04-05. 147. “Apparatus and method for wafer level packaging,” Chen, Jen-Yi (TW), Chiou, Jing-Hung (TW) (+1), TW236111 (B)— 2005-07-11. 148. “Silicon packaging for opto-electronic modules,” Epitaux, Marc (US), WO2006074048 (A2)—2006-07-13. 149. “Integrated MEMS packaging,” Hartzell, John W. (US), Walton, Harry G. (GB) (+1), US2006148137 (A1)—2006-07-06. 150. “System and method for display device with activated desiccant,” Cummings, William J. (US), MXPA05009407 (A)—200603-29.

Introduction to MEMS 151. “Device having patterned spacers for backplates and method of making the same,” Arbuckle, Brian W. (US), MXPA05009402 (A)—2006-03-29. 152. “Injection-molded package for MEMS inertial sensor,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), WO2006068907 (A1)—2006-06-29. 153. “System and method for protecting microelectromechanical system using back-plate with non-flat portion,” Gally, Brian J., Palmateer, Lauren (+1), JP2006119603 (A)—2006-05-11. 154. “Micro-electromechanical varactor with enhanced tuning range,” Chinthakindi, Anil K. (IN), Groves, Robert A. (US) (+3), TW232500 (B)—2005-05-11. 155. “System and method for display device with end-of-life phenomena,” Palmateer, Lauren (US), US2006077524 (A1)—200604-13. 156. “Package for MEMS devices,” D’Camp, Jon B. (US), Curtis, Harlan L. (US), US2006042382 (A1)—2006-03-02. 157. “Micro-fluidic interconnect,” Okandan, Murat (US), Galambos, Paul C. (US) (+2), US7004198 (B1)—2006-02-28. 158. “Semiconductor acceleration sensor system and its manufacturing method,” Kanno, Yoshinori, JP2006003277 (A)—200601-05. 159. “Embedded integrated circuit packaging structure,” Park, Heung-Woo (KR), Song, Jong-Hyeong (KR), US2005275113 (A1)—2005-12-15. 160. “Lead-free bonding systems,” Aggarwal, Ankur (US), Abothu, Isaac R. (US) (+2), US2005274227 (A1)—2005-12-15. 161. “Micro electrical mechanical system (MEMS) tuning using focused ion beams,” Kubena, Randall L. (US), Joyce, Richard J. (US), US2005269901 (A1)—2005-12-08. 162. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P. (US), US2005189621 (A1)— 2005-09-01. 163. “MEMS device with integral packaging,” Cohn, Michael B. (US), Xu, Ji-Hai (US), US2005168306 (A1)—2005-08-04. 164. “Microelectromechanical systems having trench isolated contacts, and methods for fabricating same,” Partridge, Aaron (US), Lutz, Markus (US) (+1), US2005156260 (A1)—2005-07-21. 165. “Micro connector and non-powered microassembly with micro connector,” Tsui, Kenneth, Geisberger, Aaron (+1), JP2005276816 (A)—2005-10-06.

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Chapter One 166. “Hermetic wafer-level packaging for MEMS devices with low-temperature metallurgy,” Ouellet, Luc (CA), Turcotte, Karine (CA), EP1544164 (A2)—2005-06-22. 167. “Hermetic wafer-level packaging for MEMS devices with low-temperature metallurgy,” Ouellet, Luc (CA), Turcotte, Karine (CA), US2005142685 (A1)—2005-06-30. 168. “Microelectromechanical system and method for determning temperature and moisture profiles within pharmaceutical packaging,” Walker, Dwight S. (US), US2005223827 (A1)— 2005-10-13. 169. “Packaging microelectromechanical structures,” Ma, Qing (US), Rao, Valluri (US) (+3), US2005062120 (A1)—2005-03-24. 170. “Method of making an X-Y axis dual-mass tuning fork gyroscope with vertically integrated electronics and wafer-scale hermetic packaging,” Nasiri, Steven S., Flannery, Anthony Francis, Jr., WO2005043078 (A2)—2005-05-12. 171. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev R. (US), Huibers, Andrew G. (US) (+1), US2005048688 (A1)—2005-03-03. 172. “A biological micro spray array dot sample device and method for making same,” Zhao, Jianlong (CN), Xu, Baojian (CN) (+1), CN1629319 (A)—2005-06-22. 173. “Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices,” Platt, William P. (US), Ford, Carol M. (US), US2004266048 (A1)—2004-12-30. 174. “Micro electro-mechanical variable capacitor,” Chinthakindi, Anil K. (US), US6906905 (B1)—2005-06-14. 175. “Wafer bonding method using reactive foils for massively parallel micro-electromechanical systems packaging,” Snyder, Tanya Jegeris, Yi, Robert H. (+1), JP2005040940 (A)—2005-02-17. 176. “Ultra-miniature accelerometers,” Kenny, Thomas W., Park, Woo-Tae, WO2004092746 (A1)—2004-10-28. 177. “Ultra-miniature accelerometers,” Kenny, Thomas W. (US), Park, Woo-Tae (US), US2004200281 (A1)—2004-10-14. 178. “Magneic switch for use in a system that includes an in-vivo device, and method of use thereof,” Iddan, Gavriel J. (IL), US2004254455 (A1)—2004-12-16. 179. “Magnetic switch for use in a system that includes an in-vivo device, and a method of use thereof,” Iddan, Gavriel J. (IL), WO2004086434 (A2)—2004-10-07.

Introduction to MEMS 180. “Electromechanical system having a controlled atmosphere, and method of fabricating same,” Kronmueller, Silvia (DE), Lutz, Markus (US) (+1), EP1460038 (A2)—2004-09-22. 181. “Optical deflector,” Hara, Koichi, JP2005250307 (A)—200509-15. 182. “Method for fabricating a lid for a wafer level packaged optical MEMS device,” Ehmke, John C. (US), Lopes, Vincent C. (US) (+1), US6856014 (B1)—2005-02-15. 183. “MEMS package,” Brady, Frederick T. (US), US2004099921 (A1)—2004-05-27. 184. “Micro dynamic piezoresistance pressure sensor and manufacturing method thereof,” Wang, Wenxiang (CN), Li, Shuixia (CN) (+1), CN1544901 (A)—2004-11-10. 185. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P, WO2004037711 (A2)— 2004-05-06. 186. “Processes for hermetically packaging wafer level microscopic structures,” Cheung, Kin P. (US), US2004126953 (A1)— 2004-07-01. 187. “Optical switch and method of producing the same,” Lee, Hyun Kee (KR), Jung, Sung Cheon (KR) (+1), US2004264848 (A1)—2004-12-30. 188. “Method of fabricating an integrated circuit and its precursor assembly,” Ouellet, Luc (CA), Poisson, Jules (CA), EP1405821 (A2)—2004-04-07. 189. “Method of air tight packaging micro computer electric system device using capillary tube method,” Wang, Lichun (CN), Luo, Le (CN) (+1), CN1513751 (A)—2004-07-21. 190. “Latching micro magnetic relay packages and methods of packaging,” Stafford, John (US), Tam, Gordon (US) (+1), US2004027218 (A1)—2004-02-12. 191. “MEMS control chip integration,” Kuo, Shun-Meen, Foerstner, Juergen A (+7), WO2004051744 (A2)—2004-06-17. 192. “Whole wafer MEMS release process,” Dewa, Andrew S. (US), US2004002215 (A1)—2004-01-01. 193. “Encapsulants for protecting MEMS devices during postpackaging release etch,” Peterson, Kenneth A. (US), US6956283 (B1)—2005-10-18. 194. “Method of trimming micro-machined electromechanical sensors (MEMS) devices,” Dwyer, Paul W. (US), US2003196489 (A1)—2003-10-23.

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Chapter One 195. “Methods for depositing, releasing and packaging microelectromechanical devices on wafer substrates,” Patel, Satyadev (US), Huibers, Andrew (US) (+8), WO03105198 (A1)— 2003-12-18. 196. “Microelectromechanical system and method for determining temperature and moisture profiles within pharmaceutical packaging,” Walker, Dwight Sherod (US), WO03107397 (A2)—2003-12-24. 197. “Post-package technology for microelectromechinical system,” Liu, Sheng (CN), Zhang, Honghai (CN) (+1), CN1449990 (A)— 2003-10-22. 198. “On-wafer packaging for rf-MEMS,” Margomenos, Alexandros (US), Herrick, Katherine J. (US) (+2), WO03095357 (A2)—200311-20. 199. “Wafer-level MEMS packaging,” Ouellet, Luc (CA), EP1352877 (A2)—2003-10-15. 200. “Bonding method, bonding device and sealant,” Yuasa, Mitsuhiro, JP2004235465 (A)—2004-08-19. 201. “CMOS compatible microswitches,” Huang, Jung-Tang (TW), Li, Sheng-Hung (TW) (+2), TW565530 (B)—2003-12-11. 202. “Structure and process for packaging rf MEMS and other devices,” Schaper, Leonard W. (US), Malshe, Ajay P. (US) (+1), WO03054927 (A2)—2003-07-03. 203. “Package structure and method for making the same,” Lee, Chenkuo (TW), Yi-Mou, Huang (TW), US2004087043 (A1)— 2004-05-06. 204. “MEMS device sealing packaging method and the fabrication method of metal cap thereof,” Pan, Jeng-Tang (TW), Lin, Kuen-Lung (TW), TW560028 (B)—2003-11-01. 205. “MEMS direct chip attach packaging methodologies and apparatuses for harsh environments,” Okojie, Robert S. (US), US6845664 (B1)—2005-01-25. 206. “Latching micro magnetic relay packages and methods of packaging,” Stafford, John (US), Tam, Gordon (US) (+1), WO03026369 (A1)—2003-03-27. 207. “Electromagnetic actuation optical switch and the fabrication method thereof,” Lu, Hui-Chuan (TW), Lee, Hsin-Li (TW) (+2), TW562951 (B)—2003-11-21. 208. “MEMS wafer level package,” Orcutt, John W. (US), Dewa, Andrew Steven (US) (+1), US2002179986 (A1)—2002-12-05. 209. “A low-cost HDMI-D packaging technique for integrating an efficient reconfigurable antenna array with rf MEMS switches

Introduction to MEMS and a high impedance surface,” Sievenpiper, Daniel F. (US), Schmitz, Adele E. (US) (+3), TW583789 (B)—2004-04-11. 210. “Packaging of MEMS devices using a thermoplastic,” Tourino, Cory G. (US), Rice, Janet L. (US) (+1), US6809412 (B1)—200410-26. 211. “Wafer level MEMS packaging,” Lin, Jong-Kai (US), Lytle, William H. (US) (+5), US2003230798 (A1)—2003-12-18. 212. “Microelectromechanical system device package and packaging method,” Saia, Richard Joseph (US), Durocher, Kevin Matthew (US) (+2), US2002173080 (A1)—2002-11-21. 213. “Surface excited device package including a substrate having a vibration-permitted cavity,” Youl, Min Byoung (KR), Lee, Choon Heung (KR) (+1), US2004164384 (A1)—2004-08-26. 214. “Electrostatically actuated micro-electro-mechanical devices and method of manufacture,” Kudrle, Thomas David (US), Mastrangelo, Carlos Horacio (US) (+6), WO02079853 (A1)— 2002-10-10. 215. “Electrostatically actuated micro-electro-mechanical devices and method of manufacture,” Kudrle, Thomas David (US), Mastrangelo, Carlos Horacio (US) (+6), US2002146200 (A1)— 2002-10-10. 216. “Packaging micromechanical devices,” Low, Yee Leng (US), Ramsey, David Andrew (US), US6603182 (B1)—2003-08-05. 217. “Micromachined fiber optic sensors,” Boyd, Joseph T. (US), Abeysinghe, Don C. (US) (+2), US2002159671 (A1)—200210-31. 218. “Micro-electro-mechanical systems packaging,” West, Glenn S. (SG), Alai, Aijay Babulal (SG) (+1), WO03085732 (A1)—200310-16. 219. “Multilayered microelectronic device package with an integral window,” Peterson, Kenneth A. (US), Watson, Robert D. (US), US6538312 (B1)—2003-03-25. 220. “Photonic component package and method of packaging,” Vaganov, Vladlmin (US), US2003138220 (A1)—2003-07-24. 221. “Method for calibrating a MEMS device,” Gates, John V. (US), Holland, William R. (US) (+2), US2003133644 (A1)— 2003-07-17. 222. “Flex circuit interconnect subassembly and electronic device packaging utilizing same,” Simmons, Richard L. (US), TW548233 (B)—2003-08-21. 223. “Microbar and method of its making,” Kemeny, Zoltan A. (US), US6515346 (B1)—2003-02-04.

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Chapter One 224. “Method of packaging a photonic component and package,” Kohlstadt, Michael (US), Vaganov, Vladmir (US) (+1), US2003113074 (A1)—2003-06-19. 225. “Magnetically packaged optical MEMS device and method for making the same,” Jin, Sungho, Soh, Hyongsok, JP2002236266 (A)—2002-08-23. 226. “Packaging atmosphere and method of packaging a MEMS device,” Henshall, Gordon (GB), Rolt, Stephen (GB), WO0227381 (A2)—2002-04-04. 227. “Method of trimming micro-machined electromechanical sensor (MEMS) devices,” Dwyer, Paul, WO0228766 (A2)— 2002-04-11. 228. “Temporary coatings for protection of microelectronic devices during packaging,” Peterson, Kenneth A. (US), Conley, William R. (US), US6844623 (B1)—2005-01-18. 229. “Wafer level hermetic sealing method,” Cho, Chang-Ho, Shin, Hyung-Jae (+1), JP2002246489 (A)—2002-08-30. 230. “Vacuum package fabrication of integrated circuit components,” Gooch, Roland W. (US), Schimert, Thomas R. (US), US2002000646 (A1)—2002-01-03. 231. “Chip scale surface-mountable packaging method for electronic and MEMS devices,” Kang, Seok-Jin (KR), US2002001873 (A1)—2002-01-03. 232. “Protective fullerene (C60) packaging system for microelectromechanical systems applications,” Olivas, John D. (US), US6791108 (B1)—2004-09-14. 233. “Micro mechanical packaging apparatus,” Degani, Yinon, Dudderar, Thomas D. (+1), JP2002043449 (A)—2002-02-08. 234. “Vacuum package fabrication of microelectromechanical system devices with integrated circuit components,” Gooch, Roland W., Schimert, Thomas R., WO0156921 (A2)—200108-09. 235. “Module with bumps for connection and support,” Pace, Benedict G (US), US6614110 (B1)—2003-09-02. 236. “Guided bullet,” Lipeles, Jay (US), Brosch, R Glenn (US), US2002190155 (A1)—2002-12-19. 237. “Package having cavity for housing MEMS,” Bishop, David John, Gates, John Vanatta (+1), JP2001185635 (A)—2001-07-06. 238. “Improved MEMS wafer-level package,” Oakatto, John W., Dowa, Andrew Steven (+1), JP2001144117 (A)—2001-05-25. 239. “Low-temp MEMS vacuum sealing technique for metals,” Jin, Yufeng (CN), Wu, Guoying (CN) (+1), CN1289659 (A)— 2001-04-04.

Introduction to MEMS 240. “Pre-release plastic packaging of MEMS and IMEMS devices,” Peterson, Kenneth A. (US), Conley, William R. (US), US6379988 (B1)—2002-04-30. 241. “Vacuum package fabrication of microelectromechanical system devices with integrated circuit components,” Gooch, Roland W. (US), US6479320 (B1)—2002-11-12. 242. “Hermetic chip scale packaging means and method including self test,” Bartlett, James L. (US), Wooldridge, James R. (US) (+1), US2003073292 (A1)—2003-04-17. 243. “Cover cap for semiconductor wafer devices,” Karpman, Maurice S. (US), Sengupta, Dipak (US), US6534340 (B1)— 2003-03-18. 244. “Microjoinery methods and devices,” Collins, Scott D. (US), US6393685 (B1)—2002-05-28.

References 1. Madou, M. J. Fundamentals of Microfabrication: The Science of Miniaturization. Boca Raton, FL: CRC Press, 2002. 2. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 3. Gad-el-Hak, M. The Mems Handbook. Boca Raton, FL: CRC Press, 2002. 4. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51: 305–308, 2003. 5. Menz, W., Mohr, J., and Paul, O. Microsystem Technology. Hoboken, NJ: WileyVCH, 2001. 6. Goldsmith, C. L., Yao, Z., Eshelman, S., and Denniston, D. “Performance of low-loss rf MEMS capacitive switches.” IEEE Microwave Wireless Compon. Lett. 8:269–271, 1998. 7. Senturia, S. D. Microsystem Design. New York: Springer, 2000. 8. Rebeiz, G. M. RF MEMS: Theory, Design and Technology. Hoboken, NJ: Wiley, 2003. 9. Anagnostou, D. E., Christodoulou, C. G., Tzeremes, G., Liao, T. S., and Yu, P. K. L. “Fractal antennas with rf-MEMS switches for multiple frequency applications.” In Proceedings of the IEEE APS/URSI International Symposium, Vol. 2, San Antonio, TX, June 2002, pp. 22–25. 10. Yano, M., Yamagishi, F., and Tsuda, T. “Optical MEMS for photonic switchingcompact and stable optical crossconnect switches for simple, fast, and flexible wavelength applications in recent photonic networks.” J. Selected Topics Quantum Elect. 11:383–394, 2005. 11. Anagnostou, D. E., Zheng, G., Chryssomallis, M., Lyke, J. C., Ponchak, G. E., Papapolymerou, J., and Christodoulou, C. G. “Design, fabrication and measurements of a self-similar re-configurable antenna with rf-MEMS switches.” IEEE Trans. Antennas Propagat. 54:422–432, 2006. 12. Liu, A. Q., and Zhang, X. M. “A review of MEMS external-cavity tunable lasers.” J. Micromech. Microeng. 17:R1–R13, 2007. 13. Huff, G. H., and Bernhard, J. T. “Integration of packaged rf MEMS switches with radiation pattern reconfigurable square spiral microstrip antennas.” IEEE Trans. Antennas Propagat. 54:464–469, 2006. 14. Kingsley, N., Anagnostou, D. E., Tentzeris, M., and Papapolymerou, J. “Rf MEMS sequentially reconfigurable Sierpinski antenna on a flexible organic substrate with novel dc-biasing technique.” IEEE/ASME J. Microelectromech. Syst. 16:1185–1192, 2007.

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Chapter One 15. Van Caekenberghe, K., and Sarabandi, K. “A 2-bit Ka-band rf MEMS frequency tunable slot antenna.” IEEE Antennas Wireless Propagat. Lett. 7:179–182, 2008. 16. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 17. Young, R. M., Adam, J. D., Vale, C. R., Braggins, T. T., Krishnaswamy, S. V., Milton, C. E., Bever, D. W., Chorosinski, L. G., Li-Shu Chen, Crockett, D. E., Freidhoff, C. B., Talisa, S. H., Capelle, E., Tranchini, R., Fende, J. R., Lorthioir, J. M., and Tories, A. R. “Low-loss bandpass rf filter using MEMS capacitance switches to achieve a one-octave tuning range and independently variable bandwidth.” IEEE MTT-S Int. Microwave Symp. Digest 3:1781–1784, 2003. 18. Tan, G. L., Mihailovich, R. E., Hacker, J. B., DeNatale, J. F., and Rebeiz, G. M. “Low-loss 2- and 4-bit TTD MEMS phase shifters based on SP4T switches.” IEEE Trans. Microwave Theory Tech. 51:297–304, 2003. 19. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51: 305–308, 2003. 20. Ford, J. E., Goossen, K. W., Walker, J. A., Neilson, D. T., Tennant, D. M., Park, S. Y., and Sulhoff, J. W. “Interference-based micromechanical spectral equalizers.” IEEE J. Selected Topics Quantum Elect. 10:579–587, 2004. 21. Nordquist, C. D., Dyck, C. W., Kraus, G. M., Reines, I. C., Goldsmith, L., Cowan, D., Plut, T.A., Austin, F., IV, Finnegan, P. S., Ballance, M. H., and Sullivan, T. “A dc to 10 GHz 6-bit rf MEMS time delay circuit.” IEEE Microwave Wireless Compon. Lett. 16:305–307, 2006. 22. Perruisseau-Carrier, J., Fritschi, R., Crespo-Valero, P., and Skrivervik, A. K. “Modeling of periodic distributed MEMS application to the design of variable true-time-delay lines.” IEEE Trans. Microwave Theory Tech. 54:383–392, 2006. 23. Kim, C.-H., Park, N., and Kim, Y.-K. “MEMS reflective type variable optical attenuator using off-axis misalignment.” Proc. IEEE/LEOS Int. Conf. Opt. MEMS, Lugano, Switzerland, 2002, pp. 55–56. 24. Lakshminarayanan, B., and Weller, T. M. “Design and modeling of 4-bit slowwave MEMS phase shifters.” IEEE Trans. Microwave Theory Tech. 54:120–127, 2006. 25. Lakshminarayanan, B., and Weller, T. M. “Optimization and implementation of impedance-matched true-time-delay phase shifters on quartz substrate.” IEEE Trans. Microwave Theory Tech. 55:335–342, 2007. 26. Van Caekenberghe, K., and Vaha-Heikkila, T. “An analog rf MEMS slotline true-time-delay phase shifter.” IEEE Trans. Microwave Theory Tech. 56:2151–2159, 2008. 27. Maciel, J. J., Slocum, J. F., Smith, J. K., and Turtle, J. “MEMS electronically steerable antennas for fire control radars.” IEEE Aerosp. Electron. Syst. Mag. Nov. 2007, pp. 17–20. 28. Yeow, T.-W., Law, K. L. E., and Goldenberg, A. “MEMS optical switches.” IEEE Commun. Mag. 39:158–163, 2001. 29. Herrick, K. J., Jerinic, G., Molfino, R. P., Lardizabal, S. M., and Pillans, B. “S-Ku band intelligent amplifier microsystem.” Proc. SPIE 6232, May 2006. 30. Neukermans, A., and Ramaswami, R. “MEMS technology for optical networking.” IEEE Commun. Mag. 39:62–69, 2001. 31. Pranonsatit, S., Holmes, A. S., Robertson, I. D., and Lucyszyn, S. “Single-pole eight-throw rf MEMS rotary switch.” IEEE/ASME J. Microelectromech. Syst. 15:1735–1744, 2006. 32. Lin, L. Y., and Goldstein, E. L. “Opportunities and challenges for MEMS in lightwave communications.” IEEE J. Selected Topics Quantum Elect. 8:163–172, 2002. 33. Vaha-Heikkila, T., Van Caekenberghe, K., Varis, J., Tuovinen, J., and Rebeiz, G. M. “Rf MEMS impedance tuners for 6–24 GHz applications.” Wiley Int. J. RF Microwave Computer-Aided Eng. 17: 265–278, 2007. 34. Syms, R. A., and Moore, D. F. “Optical MEMS for telecoms.” Materials Today 5:26–35, 2002.

Introduction to MEMS 35. Schoebel, J., Buck, T., Reimann, M., Ulm, M., Schneider, M., Jourdain, A., Carchon, G., and Tilmans, H., “Design considerations and technology assessment of phased array antenna systems with rf MEMS for automotive radar applications.” IEEE Trans. Microwave Theory Tech. 53:1968–1975, 2005. 36. Wu, M. C., Solgaard, O., and Ford, J. E. “Optical MEMS for lightwave communication.” J. Lightwave Technol. 24:4433–4454, 2006. 37. Mailloux, R. J. Phased Array Antenna Handbook. New York: Artech House, 2005. 38. Hoffmann. M., and Voges, E. “Bulk silicon micromachining for MEMS in optical communication systems.” J. Micromech. Microeng. 12:349–360, 2002. 39. Jung, C., Lee, M., Li, G. P., and Flaviis, F. D. “Reconfigurable scan-beam singlearm spiral antenna integrated with rf MEMS switches.” IEEE Trans. Antennas Propagat. 54:455–463, 2006. 40. Chang-Hasnain, C. J. “Tunable VCSEL.” J. Selected Topics Quantum Elect. 6: 978–987, 2000. 41. Lijie, J. Z., and Uttamchandani, D. “Integrated self-assembling and holding technique applied to a 3-D MEMS variable optical attenuator.” IEEE J. Microelectromech. Syst. 13:83–90, 2004. 42. Wikipedia. “Microelectromechanical systems:” available at http://en.wikipedia .org/wiki/MEMS, last accessed on April 1, 2008. 43. Yole Development. “World MEMS Markets: The 2006–2012 MEMS Market Database,” 2008. 44. Lau, J. H., Wong, C. P., Lee, N. C., and Lee, R. Electronics Manufacturing with Lead-Free, Halogen-Free, and Adhesive Materials. New York: McGraw-Hill, 2003. 45. Lau, J. H., and Lee, R. Microvias for Low Cost, High Density Interconnects. New York: McGraw-Hill, 2001. 46. Lau, J. H. Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies. New York: McGraw-Hill, 2000. 47. Lau, J. H., and Lee, R. Chip Scale Package Design: Materials, Process, Reliability, and Applications. New York: McGraw-Hill, 1999. 48. Lau, J. H., Wong, C. P., Prince, J., and Nakayama, W. Electronic Packaging: Design, Materials, Process, and Reliability. New York: McGraw-Hill, 1998. 49. Lau, J. H., and Pao, Y. Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies. New York: McGraw-Hill, 1997. 50. Lau, J. H. Flip Chip Technologies. New York: McGraw-Hill, 1996. 51. Lau, J. H. Ball Grid Array Technology. New York: McGraw Hill, 1995. 52. Lau, J. H. Chip on Board Technologies for Multichip Modules. New York: Van Nostrand Reinhold, 1994. 53. Lau, J. H. Handbook of Fine Pitch Surface Mount Technology. New York: Van Nostrand Reinhold, 1994. 54. Lau, J. H. Thermal Stress and Strain in Microelectronics Packaging. New York: Van Nostrand Reinhold, 1993. 55. Lau, J. H. Handbook of Tape Automated Bonding. New York: Van Nostrand Reinhold, 1992. 56. Lau, J. H. Solder Joint Reliability: Theory and Applications. New York: Van Nostrand Reinhold, 1991.

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CHAPTER

2

Advanced MEMS Packaging 2.1

Introduction This chapter briefly discusses the state of the art and future trends in advanced integrated circuit (IC) electronics packaging, followed by a discussion of advanced microelectromechanical systems (MEMS) packaging, where 10 different designs of three-dimensional (3D) MEMS packaging will be presented.

2.2 Advanced IC Packaging 3D IC integration with wafer-level packaging (WLP) has been the hottest packaging technology in the past few years and will be the trend in the future. The supply chain of 3D IC integration and WLP includes semiconductor device designers, foundries, packaging and testing houses, electronic design automation (EDA) vendors, processing equipment suppliers, materials suppliers, universities and research institutes, and industry analysts. In this section, the Moore’s law versus more than Moore (MTM) will be discussed briefly first. Next, some of the critical issues of 3D IC integration will be presented. Finally, a couple of enabling technologies (e.g., microbumps and thermal management) for 3D IC integration with WLP will be provided.

2.2.1

Moore’s Law versus More Than Moore (MTM)

In April 1965, Moore published a paper in Electronics with the title, “Cramming More Components onto Integrated Circuits.” Based on a few data points (Figs. 2-1 and 2-2), Moore proposed to put more transistors on an IC by reducing the feature sizes. Further, he suggested that the number of transistors on an IC (for minimum cost) doubles every 24 months. In the past 40+ years, Moore’s observation (law) about silicon integration (i.e., cost, yield, and reliability) has been the most powerful driver for development of the microelectronics industry. This law places emphasis on lithography scaling and integration

47

Chapter Two 16 15 Log2 of the number of components per integrated function

14 13 12 11 10 9 8 7 6 5 4 3 2 1975

1974

1973

1972

1971

1970

1969

1968

1967

1966

1965

1964

1963

1962

1961

1960

1959

1

Year

FIGURE 2-1 The empirical observation made by Moore in 1965 that the number of transistors on an IC for minimum component cost doubles every 24 months. 105 1962 Relative manufacturing cost/component

48

104

1965 103

102

1970

10

1 1

10

102

103

104

105

Number of components per integrated circuit

FIGURE 2-2 Moore’s observation about silicon integration (i.e., cost, yield, and reliability) has fueled the worldwide technology revolution: (1) IC miniaturization down to the nanoscale and (2) SoC-based system integration.


MEMS ASIC

Seal ring

FIGURE 2-3 The accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip, resulting in 3D MEMS packaging.

[in two dimensions (2D)] of all functions on a single chip, perhaps through system-on-chip (SoC) capabilities. Today, 32-nm ICs are in volume production, and production of 28-nm ICs is planned to begin in the second half of 2010. In the meantime, 22-nm technology has been working/performing very well in research institutions and laboratories. On the other hand, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration and WLP, which is called more than Moore (MTM).1–54 Figure 2-3 shows an example of Moore’s law (2D) versus MTM (3D). It can be seen from the left side of the figure that the accelerometer MEMS device is integrated into the ASIC chip by Analog Devices. On the other hand, the same functions can be achieved by stacking the MEMS device on the ASIC chip,52–54 resulting in 3D MEMS packaging (or 3D MEMS SiP or 3D MEMS WLP), which is the focus of this book. It should be pointed out that MTM is much more than just SiP. Based on the silicon-platform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment can be called MTM. One of the reasons why MEMS is called MTM is because the microelectronic ICs are thought of as the “brains” of a system, and MEMS augments this decision-making capability with “eyes” and “arms” to allow microsystems to sense and control the environment.

2.2.2

3D IC Integration with WLP

The Holy Grail of 3D IC integration (heterogeneous integration) is shown in Fig. 2-4, where all the chips [e.g., microdisplay, MEMS, memory, microprocessor, multiple outputs dc-dc converter, digital signal processor, microbattery, and analog-to-digital (A/D) mixed signal]

49

50

Chapter Two

DSP B A

Memory Display B

DSP

OPTO

Display

Processor Memory

MEMS

Long wiring (from A to B) in 2D SoC

OPTO

MEMS TSV

A

Micro bumps

Processor

Short wiring (from A to B) in 3D IC integration with TSV and microbumps

FIGURE 2-4 The Holy Grail of 3D IC integration (heterogeneous integration) with TSV, which provides shorter wiring than 2D SoC.

are stacking in three dimensions. Just as with many other new technologies, 3D IC integration still faces many critical issues. In the development of 3D IC integration, the following must be noted and understood:1–24 • Design guidelines and software are not available. • Test methods and equipment are lacking. • Known good dies (KGDs) are required. • Through-silicon vias (TSVs) with redistribution layers (RDLs) usually are required. • Microbumps usually are required. • Equipment accuracy is necessary for alignments. • Fast chips must be mixed with slow chips. • Large chips must be mixed with small chips. • Wafer thinning and thin-wafer handling during processing are necessary. • Thermal issues: • The heat flux generated by stacked multifunctional chips in miniature packages is extremely high. • 3D circuits increase total power generated per unit surface area. • Chips in the 3D stack may be overheated if proper and adequate cooling is not provided. • The space between the 3D stack may be too small for cooling channels (i.e., no gap for fluid flow).

Advanced MEMS Packaging • Thin chips may create extreme conditions for on-chip hot spots. • 3D IC stacking inspection methodology is needed. • 3D IC stacking expertise is lacking. • 3D IC stacking infrastructure is lacking. • 3D IC stacking standards are lacking. In the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in diverse journals or, more specifically, in the proceedings of many conferences, symposia, and workshops whose primary emphases have been on electrical packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of 3D IC integration with WLP technology. This section briefly mentions only microbumps and thermal management of 3D IC integration. The other important enabling technology (e.g., TSV; wafer thinning and thin-wafer handling; thin-wafer strengthening; wafer dicing; underfilling; lead-free soldering; low-temperature bonding; chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) bonding; and in situ stress measurement for MEMS applications) will be discussed throughout the remaining chapters of this book. Figure 2-5 shows a generic 3D IC packaging roadmap provided by IBM.1 It can be seen from the “Chip-to-chip/chip-to-wafer” line that microbumps are used for connecting the high-performance chips and the TSV silicon carrier (interposer) and the 3D TSV memory-chip stack. Figure 2-6 shows Intel’s proposed roadmap of package-architecture

Wafer to wafer

3D Si integration

Device layer 2 Vertical interconnect Device layer 2

Silicon

Chip to chip/chip to wafer Performance

Silicon carrier Chip 1 Chip 2

TSV for interposer

3D chip stack

Substrate

TSV for 3D chip stacking

Chip to package Caramic and organic packages Evolutionary improvements Printed circuit card 2000

2005

2010 Time

FIGURE 2-5 IBM’s generic 3D IC packaging roadmap.

2015

51

52

Chapter Two 3D Stackeddie MCP Memory CPU

Substrateembeddeddie MCP 2D Planar MCP

BW > 1 TB/s

CPU Memory

BW = 200 GB/s–1 TB/s CPU

Memory

Off-pkg BW = 100–200 GB/s CPU

Memory

BW < 100 GB/s

FIGURE 2-6 Intel’s proposed roadmap of package-architecture transitions to address the memory-bandwidth challenge.

transitions to address the memory-bandwidth challenge.14 It can be seen that 3D stacked-die multiple-chip packaging is needed to meet the performance requirements and that microbumps are used to connect the memory chip to the central processor unit (CPU).

2.2.3

Low-Cost Solder Microbumps for 3D IC SiP

The material used for connecting high-pin-count, small-pad, and finepitch chips can be either high-cost metal bumps (e.g., copper and gold) or low-cost solder bumps (e.g., tin). In this section, only low-cost solder microbumps will be discussed. Figure 2-7 is a schematic of the 3D stacking of a memory chip and an Si carrier chip (could be the CPU) with TSV.21 There are more than 4000 solder microbumps between them, and their distribution is shown in Fig. 2-8. The functional bumps are concentrated in a

Si chip Solder microbumps

TSV

UBM pad 25 Si carrier μm

Ordinary solder bumps

FIGURE 2-7 Schematic of the 3D stacking of a memory chip and an Si carrier (could be a CPU) at 25 μm pitch.


All the others are dummy bumps/UBM pads for stability assembly

Bumps/UBM pads for interconnection

FIGURE 2-8 Distribution of solder microbumps/under-bump-metallurgy (UBM) pads on an Si chip/Si carrier (not in scale).

very narrow strip with very fine pitches (≤25 μm) and small pads (≤15 μm), and the dummy bumps (to provide support during assembly and to absorb the stresses and strains of thermal-expansion mismatch between the Si chip and the copper-filled TSV chip) are around the edges. Figure 2-9 shows a schematic of the cross section of a solder microbump on an Si chip. It can be seen that it consists of the metal pad and a Ti (or Ta) adhesion layer, Cu seed layer, plated Cu layer, plated Sn layer, and passivation layer. Figure 2-10 shows a schematic of the cross section of an electroless Ni and immersion Au (ENIG) under-bump metallurgy (UBM) pad. It can be seen that it consists of the Al pad, Ni layer, Au layer, and two passivation layers.

a. Bump height

b

b. Bump width c. Ti adhesion

g

a

d. Cu seed layer e. Cu f. Sn g. Passivation: SiO2

f e d

c Metal pad Si chip

FIGURE 2-9 Schematic of the cross section of a solder microbump on an Si chip.

53

54

Chapter Two FIGURE 2-10 Schematic of the cross section of the electroless Ni and immersion Au (ENIG) UBM pad.

d

e

c b a f Si carrier

a. Passivation 1 (SiO2) b. Passivation 2 (SiO2) c. Al pad (daisy chain) d. Electroless Ni e. Immersion Au f. Al pad opening

Figure 2-11 shows scanning electron microscope (SEM) images of the electroplated Cu-Sn solder microbumps on an Si chip, and Fig. 2-12 shows the Cu-Sn solder microbumps on an Si chip after reflow at 265°C. Figure 2-13 shows a focused-ion-beam (FIB) image of the Cu-Sn solder microbumps on an Si chip. It can be seen that nice and smooth Cu-Sn solder microbumps on a 25-μm pitch and 15-μm pad have been achieved.

Plated Sn at 25-μm pitch

10 μm

FIGURE 2-11 SEM image of the electroplated Cu-Sn solder microbumps on an Si chip.

Advanced MEMS Packaging Reflowed Sn at 25-μm pitch

10 μm

FIGURE 2-12 SEM image of the Cu-Sn solder microbumps on an Si chip after reflow at 265°C.

Cu6Sn3

Cu3Sn

Sn

Cu

FIGURE 2-13 FIB image of the Cu-Sn solder microbumps on an Si chip.

55

56

Chapter Two Electroless Ni & lmmersion Au at 25-μm pitch

FIGURE 2-14 SEM image of ENIG UBM on an Si carrier.

Just as with ordinary solder bumps, there are two layers of intermetallic compounds (IMCs), the Cu3Sn and Cu6Sn5. Figures 2-14 and 2-15 show, respectively, SEM and FIB images of the ENIG UBM on an Si carrier. It can be seen that the Ni layer is about 4 μm thick and that there is no cracking around the edges of

FIGURE 2-15 FIB image of ENIG UBM on an Si carrier.

4 μm

Au Ni

Passivation


Chip with solder bumps Cu Sn Ni

Chip with UBMs μm

μm

FIGURE 2-16 SEM images of the assembly cross section of an Si chip and Si carrier (15 μm pitch and 8 µm pad).

the passivations. A similar UBM has been made for a 15-μm pitch and 8-μm pad. In this case, the Ni layer is about 2 μm thick.22 Figure 2-16 shows the assembly of an Si chip and Si carrier with 15-μm pitch and 8-μm pad Cu-Sn solder microbumps. It can be seen from the cross section that the micro solder joints between these chips can be assembled properly and that the standoff is about 12 μm, which is preferred for 3D IC stacking and SiP. The effective thermal expansion coefficient of the Cu-filled TSV Si carrier (~10 × 10–6/°C) is larger than that (~2.5 × 10–6/°C) of the Si chip, and therefore, underfill may be necessary to ensure the reliability of the micro solder joint. Figure 2-17 shows an optical photograph of

Si chip

Si chip Underfill

Underfill in the assembly gap Si carrier Si carrier Si chip Si chip Underfill and microbumps in the assembly gap

Underfill

FIGURE 2-17 Optical photograph of a cross section of the underfill between an Si chip and Si carrier.

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Chapter Two a cross section of underfill between these two chips. For results of shearing and thermal cycling tests for these micro solder joint assemblies, please see refs. 21 and 22, which demonstrate that these solder microbumps are adequate for most operating conditions.

2.2.4 Thermal Management of 3D IC SiP with TSV As mentioned earlier, thermal management is one of the critical issues of 3D IC integration. Thus low-cost and effective thermal management design guidelines and solutions are desperately needed for widespread use of 3D IC integration. Based on the theory of heat transfer, this section examines the thermal performance of 3D stacking of up to eight copper-filled TSV chips. The results are plotted in useful design charts for engineering practice convenience, and design guidelines are also provided.20 In order to have a miniature product with low-profit and smallform-factor components, the chip thickness in a 3D stacked component must be very thin (e.g., 50 μm or less). Unfortunately, chip temperature and the hot-spot temperature in a chip increase with reductions in chip thickness, which poses significant thermal management challenges. This section also presents heat-transfer analysis of a (5 × 5 mm) chip with different thicknesses (from 10 to 200 μm) subjected to various heat sources. In addition, the thermal coupling effects of a (5 × 5 × 0.05 mm) chip subjected to heat sources at various locations are presented. Again, useful design charts and design guidelines relating the important parameters are provided. Even with the most effective software and advanced high-speed hardware, it is impossible to model all the TSVs in a 3D IC integration SiP. Therefore, this section develops empirical equations for the equivalent thermal conductivity of a copper-filled TSV chip with various TSV diameters, pitches, and aspect ratios through detailed 3D heat-transfer Computational Fluid Dynamic (CFD) analysis. These equations then are used (for each TSV chip as a lumped block) to perform all the simulations reported herein.

Equivalent Thermal Conductive of TSV Chips Figure 2-18 is a schematic of a 3D IC integration of eight copperfilled TSV chips. The top-layer chip does not (and does not need to) have a TSV. These chips are connected through microbumps, and the bottom TSV chip is also connected to the organic printed circuit board (PCB) by ordinary flip-chip solder bumps. Owing to the large thermal expansion mismatch between the silicon chip and the organic PCB, underfill is needed to cement the bottom chip (and the stack) to the PCB so that the solder joints are reliable. Underfill may not be necessary between all the TSV chips. As mentioned earlier, this section determines the equivalent thermal conductivity of the copper-filled TSV chips through detailed 3D

Advanced MEMS Packaging Copper-filled TSV (many)

TSV chip

TSV

z

y x

Micro bump

Chip q T

Solder bump

Adiabatic

Δz PCB

Underfill

Adiabatic

Δz q = –keq,z dT = k eq,z ΔT ⇒ k eq,z = q Δz dz ΔT ΔT Δx q = –keq,x dT = k eq,x ⇒ k eq,x = q dx Δx ΔT keq,y = keq,x

Isotherm (T1 = 25°C)

T q Adiabatic

Δx

FIGURE 2-18 Schematic of a 3D IC integration of eight copper-filled TSV chips along with the equivalent thermal conductive model and boundary conditions.

CFD analysis. One of the TSV chip is shown schematically in the upper right-hand corner of Fig. 2-18. It can be seen that unlike the thermal conductivity of an ordinary silicon chip [150 W/(m · °C)], which is isotropic, the thermal conductivity of a copper-filled TSV silicon chip is anisotropic; that is, the thermal conductivity in the xy-planar directions (keq,x = keq,y) is not equal to that in z-normal direction (keq,z). [The thermal conductivity of copper is 390 W/(m · °C).] The approaches for extracting keq,x = keq,y and keq,z are shown, respectively, in the center and bottom right-hand side of Fig. 2-18. First, construct the geometry of the copper-filled TSV chip with various diameters, pitches, and aspect ratios. Then input the thermal material properties [the thermal conductivity of silicon is 150 W/(m · °C) and that of copper is 390 W/(m · °C)]. Finally, apply the kinetic and kinematic boundary conditions, and calculate the temperature distributions. The equivalent thermal conductivity can be obtained with the equations shown in the lower left-hand corner of Fig. 2-18. For example, to extract the equivalent thermal conductivity in the z direction, the geometry of the TSV chip is constructed, then a uniform heat flux q is imposed on the top surface of the TSV chip, and the bottom surface is set as an isotherm boundary (i.e., 25°C), whereas the four surrounding boundaries are set as adiabatic boundaries. By using the Flowtherm software, the average temperature on the top surface of the TSV chip can be calculated, and consequently, keq,z can be obtained using the first equation in the figure.

59

Chapter Two 260 Equivalent conductivity, W/(m·K)

250

Pitch = 0.2 mm, Keq,z Pitch = 0.3 mm, Keq,z Pitch = 0.5 mm, Keq,z

240

Pitch = 0.25 mm, Keq,z Pitch = 0.4 mm, Keq,z Pitch = 0.6 mm, Keq,z

230 Keq, z

220 Pitch: 0.3 mm – correlation

210

D1

D1

200 0.3 mm

190

P

180

D2

D2

170 160 150 140 2

4

6

8

10

Aspect ratio, A keq,z = 150 + 188D 2P –2; D = (D1 + D2)/2; A = thickness/D

FIGURE 2-19 The equivalent thermal conductivity (in the vertical direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Figures 2-19 and 2-20, respectively, show the equivalent thermal conductivity for keq,z and keq,x = keq,y of a copper-filled TSV chip with various diameters, pitches, and aspect ratios. It can be seen that (1) the equivalent thermal conductivity in all directions of the TSV chip is 260 250 Equivalent conductivity, W/(m·K)

60

Pitch = 0.2 mm, Keq,x,y Pitch = 0.3 mm, Keq,x,y Pitch = 0.5 mm, Keq,x,y

240

Pitch = 0.25 mm, Keq,x,y Pitch = 0.4 mm, Keq,x,y Pitch = 0.6 mm, Keq,x,y

230 220 210 200

Pitch: 0.30 mm – correlation

190

Keq,x,y

D1 0.3 mm

D1 P

180

D2

170

D2

160 150 140 2

4

6 Aspect ratio, A

8

10

keq,x = keq,y = 150 + 105D 2P –2; D = (D1 + D2)/2; A = thickness/D

FIGURE 2-20 The equivalent thermal conductivity (in the horizontal direction) for a copper-filled TSV chip with various diameters, pitches, and aspect ratios.

Advanced MEMS Packaging larger than that of a pure silicon chip, (2) the equivalent thermal conductivity in all directions is larger for smaller pitches of the TSV chip, and (3) the equivalent thermal conductivity in all directions is larger for larger diameters of the TSV chip. For engineering convenience, the results in Figs. 2-19 and 2-20 have been curve-fitted into the following empirical equations for equivalent thermal conductivity: keq,z = 150 + 188D2P–2 keq,x = keq,y = 150 + 105D2P–2 where P is the pitch, D = (D1 + D2)/2 is the diameter, and D1 and D2 are the diameters of a tapered TSV chip. The accuracy of these equations has been demonstrated by showing the correlation between the empirical equations (for the case of P = 0.3 mm) with the detailed 3D CFD analyses, as shown in Figs. 2-19 and 2-20. Consequently, these empirical equations will be used for TSV chips as a lumped block without any vias for analysis of the 3D SiP. Table 2-1 shows the material properties for the simulations.

Thermal Performance of 3D Stacked TSV Chips with a Uniform Heat Source Figure 2-21 shows the maximum junction temperature of a stackedchip (varying with the number of the chips) package. In these simulations, all the chips have the same size (5 × 5 × 0.05 mm), and there are 225 (15 × 15) copper-filled TSVs with a 0.2-mm pitch on each chip. The power dissipated by each chip is 0.2 W, and it is assumed that the power is uniformly distributed on each chip. The ambient temperature is 25°C. It can be seen from the figure that the maximum junction temperature increases linearly with the number of the chips stacked. In addition, it can be seen that if the maximum allowable junction temperature is 85°C, then the maximum number of chips that can be stacked together is seven under the present conditions. Figure 2-22 shows the maximum junction temperature at each layer of the TSV chip stack. It can be seen that the maximum junction

Chip

TSV

Bumps

Underfill

PCB

Material

Si (TSV)

Cu

SnAg

Polymer

FR4

K [W/(m · °C)]

Empirical equation

390

57

0.5

// 0.8 ⊥ 0.3

Dimension (mm)

5×5

Ø = 0.05

Ø = 0.20 Height = 0.15

5×5× 0.15

76 × 114 × 1.6

Power (W)

0.2 W

NA

NA

NA

NA

TABLE 2-1

Material Properties and Dimensions of 3D IC Integration

61

62

Chapter Two

Max. junction temperature, Tj (°C)

95 85

Tj = 85°C

Uniform 75 heat source over the 65 whole TSV chip 55

TSV chip

45

Chip thickness = 50 μm Chip power = 0.2 W/chip Heat source area = 5 × 5 mm

35 25

0

2

4

6

8

10

Number of stacked TSV chips

Max. Temperature, °C

FIGURE 2-21 Maximum junction temperature of the eight stacked chips.

90

85


0

2

4

6

8

Layer of TSV chip (from the bottom)

FIGURE 2-22 Maximum junction temperature at each layer of the TSV chip stack.

temperature difference between each layer of the stack is negligible. This means that the temperature distribution for the different layer of chips is uniform because we assumed that the power dissipation is uniformly distributed in each chip. Figure 2-23 shows the variation in thermal resistance of the SiP with the number of the TSV chips stacked. The materials, geometry, boundary conditions, and assumptions are the same as those in Fig. 2-21. It can be seen that the thermal resistance of the stacked SiP decreases as the number of chip in the stack increases.


Thermal resistance, Rja (°C/W)

45

Uniform heat source over the whole TSV chip

44 43 42 41

TSV chip

40 39 38


37 46 35

0

2

4 6 Number of stacked TSV chips

8

10

FIGURE 2-23 Variation in thermal resistance of the SiP with the number of TSV stacked chips.

Thermal Performance of 3D Stacked TSV Chips with a Nonuniform Heat Source The results presented in Figures 2-21, 2-22, and 2-23 are based on the assumption that the power is dissipated uniformly over the whole chip. However, in most applications, the power dissipated by each chip is basically nonuniform, and as such, it will induce quite different thermal behaviors of the 3D IC SiP with TSV chips. In addition, it is well known that ordinary silicon chips normally have large parallel conduction of heat (parallel to the chip surface) owing to the large thermal conductivity of the Si material. However, for 3D IC chip stacking, in order to have a low profile, the chip thickness of each layer of the 3D SiP must be ground down to 50 μm and less. Thus the parallel spreading effect is suppressed by the very thin chip, and the hot spot will be very intense. Compounding this with the nonuniform heat source, the hot spot becomes a challenge in 3D IC integration SiP. Figures 2-24, 2-25, and 2-26 show the thermal performance of a 3D integration of two copper-filled TSV chips stacking in an SiP, where a single copper-filled TSV chip is also included. All the chips are 5 × 5 mm, and their thicknesses vary from 10 to 200 μm. Each chip’s center is subjected to a distinct heat source (0.2 W) in a tiny area (0.2 × 02 mm). It can be seen from Figs. 2-24 and 2-25 that (for both one- and two-chip stacks) (1) for a nonuniform heat source, the effect of chip thickness on the thermal performance of 3D IC integrations is very important, (2) this thickness effect is even more significant in the application range (≤50 μm) of 3D IC integrations, and (3) the maximum junction temperature and thermal resistance decrease as chip thickness increases.

63

Chapter Two

Max. Junction temperature Tj (°C)

95 85 75

Two TSV chips

Heat source

65 One TSV chip

55

Chip

45 Chip power = 0.2 W/chip Chip heat source area = 0.2 × 0.2 mm

35 25

0

50

100 TSV chip thickness, μm

150

200

FIGURE 2-24 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips.

250 Thermal resistance, Rja (°C/W)

64

200 Two TSV chips

150

Heat source One TSV chip

100

Chip

50

0

Chip power = 0.2 W/chip Chip heat source area = 0.2 × 0.2 mm 0

50

100 TSV chip thickness, μm

150

200

FIGURE 2-25 Thermal resistance of a 3D integration of two Cu-filled TSV chips.

Figure 2-26 shows the temperature maps on the chip for various chip thicknesses. It can be seen that the heat on the chip surface is well dissipated for typical chip thicknesses of 100 to 200 μm subjected to a generated power of 0.2 W. For the 200-μm-thick chip, the temperature distribution is almost uniform and equal to 35°C. However, the hot-spot temperature on the chip increases to 69°C (0.2-W power) if the chip thickness is reduced to 10 μm, and the hot-spot area is clearly shown.

Advanced MEMS Packaging t = 10 μm

t = 25 μm

t = 100 μm

t = 50 μm

t = 200 μm Temperature (°C) 68.9

49.5

Chip power: 0.2 W/chip Chip heat source area: 0.2 × 0.2 mm

30

FIGURE 2-26 Temperature maps on the chip for various chip thicknesses (hot spots).

In addition to one heat source per chip (5 × 5 mm), Figs. 2-27 and 2-28 show the effect of two heat sources at a distance apart (gap) on the thermal performance of 3D IC integrations of copper-filled TSV chips. There are two distinct heat sources (each with 0.1 W and on 0.2 × 0.2 mm area) on each chip (5 × 5 × 0.05 mm). It can be seen from the

Max. junction temperature, Tj (°C)

60

a

Chip power = 0.2 W/chip b

55

50

Heat source area = 0.2 × 0.2 mm

Two TSV chips

45 One TSV chip

40

35

0

0.2

0.4 0.6 Gap between heat sources, b/a

0.8

FIGURE 2-27 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

1

65

Chapter Two 110 Thermal resistance, Rja (°C/W)

66

a

100

b

Chip power = 0.2 W/chip Heat source area = 0.2 × 0.2 mm

90 80

One TSV chip

70 Two TSV chips

60 50

0

0.2

0.4

0.6

0.8

1

Gap between heat sources, b/a

FIGURE 2-28 Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct heat sources.

figures that (1) the larger the gap (b/a ≤ 0.7) between the two heat sources, the better is the thermal performance (i.e., lower maximum junction temperature and thermal resistance), and (2) when the gap between the two heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker. This is due to suppressible spreading effects near the edges of the chips. In addition to the case of overlapping heat sources discussed in the preceding paragraph, finally, Figs. 2-29 and 2-30 show the orientation effect (staggered heat sources) of two stacked chips, each with two heat sources at a certain distance apart, on the thermal performance of a 3D SiP. It can be seen that (1) similar to case of overlapping heat sources, the larger the gap (b/a ≤ 0.7) between those two pairs of staggered heat sources, the lower are the maximum junction temperature and thermal resistance, (2) when the gap between the two pairs of staggered heat sources is larger than 0.7 (i.e., the heat sources are too close to the edge of the chip), the thermal performance is weaker, and (3) the maximum junction temperature and thermal resistance of the 3D SiP with two TSV chips subjected to two pairs of staggered heat sources are lower than those with two pairs of overlapping heat sources. This is so because the staggered heat sources avoid the superimposition of heat sources and thus lead to better thermal performance. This result is very useful for the design and layout 3D SiP because it permits relocation of the heat sources and/or rotation of the chip.


Max. Junction temperature, Tj (°C)

55

a


a

54 b

53

b

52 51

Overlapped sources

50

2 TSV chips with over lapped heat sources

Staggered sources

49 48

2 TSV chips with staggered heat sources

47 46 45

0

0.2

0.4 0.6 Gap between heat sources, b/a

0.8

1

FIGURE 2-29 Maximum junction temperature of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

75

Thermal resistance, Rja (°C/W)

a b

70

65


a b

Overlapped sources

2 TSV chips with overlapped heat sources

Staggered sources

60 2 TSV chips with staggered heat sources

55

50

0

0.2

0.4

0.6

0.8

1

Gap between heat sources, b/a

FIGURE 2-30 Thermal resistance of a 3D integration of two Cu-filled TSV chips subjected to two distinct staggered heat sources.

2.3 Advanced MEMS Packaging Advanced MEMS packaging usually involves at least three wafers, namely, the MEMS device wafer, the ASIC wafer, and the cavity-cap wafer. This section examines the design and processing of 10 different configurations of 3D MEMS packaging.53 These packages are supposed to yield very low-cost, high-performance packaging with a small footprint.

67

68

Chapter Two Solder bump with TSV substrate

MEMS wafer

Note: Cases 1 to 6 should have the cap without TSV

Solder bump flip-chip without TSV Wire bond

ASIC wafer

5

6

2

3

4 1

With TSV

8

9

7

Without TSV

Note: Cases 7 to 9 should have the ASIC without TSV

Cap wafer TSV in cap

FIGURE 2-31 Nine different designs of 3D MEMS packaging for the MEMS wafer, ASIC wafer, and cavity-cap wafer.

2.3.1

3D MEMS WLP: Designs and Materials

Figure 2-31 shows nine different combinations (designs) of 3D MEMS packaging from the MEMS wafer (with either wire-bonding pads, solder-bumped TSV substrate, or solder-bumped flip-chip without TSV), the ASIC wafer (with or without TSV), and the cavity-cap wafer (with or without TSV).53 Case 1: The MEMS device is die attached and then wire bonded on the ASIC chip or wafer. The cavity-cap chip/wafer is attached to the ASIC chip/wafer with a sealing ring, as shown in Fig. 2-32. Cavity-cap

Wire bondIng

Sealing ring

MEMS device

ASIC chip Signal lines go through beneath sealing ring to wire-bonding pad on the chip periphery

Circuitry

MEMS chip (substrate)

Bonding pad on a substrate or PCB

FIGURE 2-32 All wire-bonding 3D MEMS packaging with lateral electrical feedthrough.

Advanced MEMS Packaging MEMS device and substrate with TSV

Cavity-cap Sealing ring

Wire bonding


Circuitry

Tiny solder bumps


FIGURE 2-33 Solder-bumped MEMS device with TSV substrate on an ASIC chip with lateral electrical feed-through.

The signal lines go through beneath the sealing ring to the wirebonding pad on the ASIC chip periphery. Another set of wirebonding pads connects the MEMS/ASIC 3D stack to either a substrate in a package or on a PCB. Case 2: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC, as shown in Fig. 2-33. The rest is the same as in case 1. Case 3: The solder-bumped flip-chip MEMS device is first attached on the ASIC, as shown in Fig. 2-34. The rest is the same as in case 1. Case 4: The MEMS device is die attached and wire bonded on the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-35. A cavity cap is attached on the ASIC with a sealing ring. The MEMS/ASIC 3D stack is then attached (solder reflowed) to a substrate in a package or on a PCB.

MEMS device and substrate with solder bumps Cavity-cap Sealing ring Wire bonding


Circuitry Solder bumps


FIGURE 2-34 Solder-bumped flip-chip MEMS device on an ASIC chip with lateral electrical feed-through.

69

70

Chapter Two Wire bonding Sealing ring

Cavity-cap

MEMS device

ASIC chip

Ordinary solder bumps MEMS chip (substrate)

Through-silicon via (TSV)

FIGURE 2.35 MEMS device wire bonded on an ASIC chip with vertical electrical feed-through TSV.

MEMS substrate with TSV Cavity-cap Sealing ring

MEMS device

ASIC chip

Ordinary solder bumps Tiny solder bumps


FIGURE 2.36 TSV MEMS device solder bonded on an ASIC chip with vertical electrical feed-through TSV.

Case 5: The micro-solder-bumped MEMS device with a TSV substrate is first attached to the ASIC chip with TSV and ordinary solder bumps, as shown in Fig. 2-36. The rest is the same as in case 4. Case 6: The solder-bumped MEMS device is first attached to the TSV ASIC with ordinary solder bumps, as shown in Fig. 2-37. The rest is the same as in case 5. Case 7: The MEMS device is die attached and then wire bonded on the ASIC. The cavity cap with TSV and ordinary solder bumps is attached to the ASIC with a sealing ring, as shown in Fig. 2-38. Then the whole 3D carrier is attached (solder reflowed) to a substrate in a package or on a PCB. Case 8: The micro-solder-bumped MEMS device with TSV substrate is first attached to the ASIC as shown in Fig. 2-39. The rest is the same as in case 7.

Advanced MEMS Packaging MEMS substrate with solder bumps Cavity-cap Solder bumps

Sealing ring

ASIC chip

Ordinary solder bumps


MEMS device

FIGURE 2-37 Solder-bumped MEMS device flip-chip on an ASIC chip with vertical electrical feed-through TSV. Ordinary solder bumps Cavity-cap Through-silicon via (TSV)

Wire bonding Sealing ring

MEMS device

ASIC chip MEMS chip (substrate)

FIGURE 2-38 MEMS device wire bonded on an ASIC chip (vertical electrical feed-through TSV is in the package cap). Ordinary solder bumps Cavity-cap Sealing ring Through-silicon via (TSV)

MEMS device

ASIC chip MEMS substrate with TSV

Tiny solder bumps

FIGURE 2-39 TSV MEMS device solder bonded on an ASIC chip (vertical electrical feed-through TSV is in the package cap).

Case 9: The solder-bumped MEMS device is first attached to the ASIC as shown in Fig. 2-40. The rest is the same as in case 7. Case 10: The MEMS device is attached to the ordinary solderbumped TSV ASIC with a sealing ring, as shown in Fig. 2-41. Then the whole 3D stack is attached (solder reflowed) to a substrate in a package or on a PCB.

71

72

Chapter Two Ordinary solder bumps Cavity-cap Sealing ring Through-silicon via (TSV) ASIC chip MEMS device

Solder bumps

MEMS substrate with solder bumps

FIGURE 2-40 Solder-bumped MEMS device flip-chip on an ASIC chip (vertical electrical feed-through TSV is in the package cap). MEMS substrate

Sealing ring

ASIC chip

Ordinary solder bumps MEMS device


FIGURE 2-41 MEMS device is bonded (with a sealing ring) on an ASIC chip with vertical electrical feed-through TSV.

2.3.2

3D MEMS WLP: Processes

There are many different processes to assemble these 10 MEMS SiPs. For example, the assembly process shown in Fig. 2-42 can be applied to cases 1 through 3; Fig. 2-43, to cases 4 to 6; and Fig. 2-44, to cases 7 to 9.53 Case 10 will be discussed later. As mentioned earlier, the MEMS wafer can be fabricated either with wire-bonding pads or TSV and solder bumps or a solder-bumped flip-chip, as shown in Figs. 2-42 through 2-44. These are followed by releasing (etching) the MEMS wafer and singulation. For 3D MEMS packaging with lateral electrical feed-through (cases 1, 2, and 3), there is no TSV in both the ASIC and cap wafers (see Fig. 2-42). In these cases, cavities should be formed in the cap wafer by either KOH etching or use of a laser. Then one performs the bonding of the MEMS device (chip) to the ASIC wafer (C2W). This

Advanced MEMS Packaging MEMS wafer

MEMS with wire-bonding pad

MEMS with TSV

MEMS with flip-chip

MEMS devices released

TSV formations and wafer bumping

Wafer bumping

Singulation



ASIC wafer without TSV

Singulation

C2W wire bonding

Singulation

C2W solder bonding

C2W solder bonding

Cap wafer without TSV

ASIC wafer to cap wafer bonding Cavity formation on cap wafer without TSV

Singulation

FIGURE 2-42 Assembly process for 3D MEMS packaging with lateral electrical feedthrough. MEMS wafer

ASIC wafer


MEMS with TSV



Wafer bumping

Singulation



Singulation

Singulation

C2W solder bonding

C2W solder bonding

TSV formation on ASIC wafer C2W wire bonding


ASIC wafer to cap wafer bonding Wafer bumping

Cavity formation on cap wafer

Singulation

FIGURE 2-43 Assembly process for 3D MEMS packaging with vertical electrical feed-through the TSV in an ASIC chip.

73

74

Chapter Two MEMS wafer


MEMS with TSV

MEMS with flip-chip



Wafer bumping

Singulation



ASIC wafer without TSV

Singulation

C2W wire bonding

C2W solder bonding

Singulation

C2W solder bonding


ASIC wafer to cap wafer bonding Cavity formation on cap wafer without TSV

Singulation

FIGURE 2-44 Assembly process for 3D MEMS packaging with vertical electrical feed-through the TSV in the package cap.

will be followed by bonding of the cavity-cap wafer to the ASIC wafer (W2W). Finally, the bonded wafers are singulated into individual units, which are ready to be wire bonded on the substrate of a package or on a PCB, as shown in Fig. 2-45. For both cases, encapsulant is recommended. For 3D MEMS packaging with vertical electrical feed-through in the ASIC chip (cases 4, 5, and 6), the TSV must be fabricated on the ASIC wafer before C2W bonding, as shown in Fig. 2-43. After the W2W (cap-to-ASIC) bonding, wafer bumping should be performed on the bottom side of the ASIC wafer. After singulations, the individual units can be soldered on the substrate of either a package or a PCB, as shown in Fig. 2-46. For the PCB case, underfill is necessary for the reliability of the solder joints. For the solder-bumped flip-chipin-package case, use of underfill depends on the substrate material. If it is made of ceramic, then underfill is optional. However, if it is an organic substrate, then underfill is a must. For 3D MEMS packaging with vertical electrical feed-through in the package cap (cases 7, 8, and 9), the TSV and cavity must be fabricated on the cap wafer before W2W bonding, as shown in Fig. 2-44. After W2W bonding, wafer bumping should be performed on the bottom side of the cap wafer. The rest is the same as in cases 4 through 6, and Fig. 2-47 shows an example of the complete 3D MEMS packaging with vertical electrical feed-through in the package cap.

Advanced MEMS Packaging Cavity-cap Sealing ring

Wire bonding MEMS device


Circuitry MEMS chip (substrate)

MEMS/ASIC module wire-bonding on the substrate of a package which is assembled on PCB


MEMS/ASIC module wire-bonding directly on PCB

Substrate

PCB

FIGURE 2-45 Complete 3D MEMS packaging with lateral electrical feed-through (encapsulants are recommended).

MEMS substrate with TSV Cavity-cap Sealing ring

MEMS device

ASIC chip

Ordinary solder bumps Tiny solder bumps


MEMS/ASIC module attached on the substrate of a package which is assembled on PCB

MEMS/ASIC module flipchip attached on PCB

Substrate Solder balls PCB

FIGURE 2-46 Complete 3D MEMS packaging with vertical electrical feed-through in the TSV of a ASIC chip (underfills are recommended).

75

76

Chapter Two Ordinary solder bumps Cavity-cap

Sealing ring


ASIC chip MEMS device

Solder bumps

MEMS substrate with solder bumps

MEMS/ASIC module attached on the substrate of a package which is assembled on PCB

MEMS/ASIC module flipchip attached on PCB

Substrate Solder balls PCB

FIGURE 2-47 Complete 3D MEMS packaging with vertical electrical feed-through the TSV of the package cap (underfills are recommended).

In the food chain of electronic products, packaging is a downstream process (i.e., the packaging people cannot be or are not in a proactive position and cannot say too much), and the packaging people just package whatever is given them by the semiconductor people (i.e., our job starts from the wafers). Case 10 (see Fig. 2-41) is a very low-cost, high-performance 3D MEMS package.53 However, in order to make it, the MEMS device (chip) must be much larger (to make space for the sealing ring) than that packages in cases 1 through 9 with a cavity cap. Thus, from a semiconductor points of view, this is a very bad idea because many fewer MEMS devices can be produced on the same size MEMS wafer.

References 1. Andry, P. S., Tsang, C. K., Webb, B. C., Sprogis, E. J., Wright, S. L., Bang, B., and Manzer, D. G. “Fabrication and characterization of robust through-silicon vias for silicon-carrier applications.” IBM Journal of Research and Development 52:571–581, 2008. 2. Knickerbocker, J. U., Andry, P.S., Dang, B., Horton, R. R., Patel, C. S., Polastre, R. J., Sakuma, K., Sprogis, E. S., Tsang, C. K., Webb, B. C., and Wright, S. L. “3-D silicon integration.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 538–543. 3. Kumagai, K., Yoneda, Y., Izumino, H., Shimojo, H., Sunohara, M., and Kurihara, T. “A silicon interposer BGA package with Cu-filled TSV and multilayer Cu-plating


4.

5.

6. 7.

8. 9.

10.

11.

12.

13.

14. 15.

16.

17.

interconnection.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 571–576. Sunohara, M., Tokunaga, T., Kurihara, T., and Higashi, M., “Silicon interposer with TSVs (through-silicon vias) and fine multilayer wiring.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 847–852. Lee, H. S., Choi, Y.-S., Song, E., Choi, K., Cho, T., and Kang, S. “Power delivery network design for 3D SIP integrated over silicon interposer platform.” In IEEE Proceedings of Electronic Components and Technology Conference, Reno, NV, May 2007, pp. 1193–1198. Matsuo, M., Hayasaka, N., and Okumura, K. “Silicon interposer technology for high-density package.” In IEEE Proceedings of Electronic Components and Technology Conference, Las Vegas, NV, May 2000, pp. 1455–1459. Selvanayagam, C., Lau, J. H., Zhang, X., Seah, S., Vaidyanathan, K., and Chai, T. “Nonlinear thermal stress/strain analysis of copper filled TSV (through silicon via) and their flip-chip microbumps.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 2008, pp. 1073–1081. Wong, E., Minz, J., and Lim, S. K. “Effective thermal via and decoupling capacitor insertion for 3D system-on-package.” In IEEE Proceedings of Electronic Components and Technology Conference, San Siego, CA, May 2006, pp. 1795–1801. Khan, N., Rao, V., Lim, S., Ho, S., Lee, V., Zhang, X., Yang, R., Liao, E., Ranganathan, N., Chai, T., Kripesh, V., and Lau, J. H. “Development of 3D silicon module with TSV for system in packaging.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 550–555. Ho, S., Yoon, S., Zhou, Q., Pasad, K., Kripesh, V., and Lau, J. H. “High rf performance TSV for silicon carrier for high frequency application.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 1956–1952. Premachandran, C., Rangnathan, N., Mohanraj, S., Chong Ser Choong, and Iyer, M. K. “A vertical wafer level packaging using through hole filled via interconnect by lift off polymer method for MEMS and 3D stacking applications.” In Proceedings of the Fifty-first Electronic Components and Technology Conference, Lake Buena Vista, FL, 2005, pp. 1094–1098. Chen, K. S., Ayon, A. A., Zhang, X., and Spearing, S. M. “Effect of process parameters on the surface morphology and mechanical performance of silicon surfaces after deep reactive ion etching (DRIE).” J. Microelectromech. Syst. 11:264–275, 2002. Zhang, X., Chai, T., Lau, J. H., Selvanayagam, C., Biswas, K., Liu, S., Pinjala, D., Tang, G., Ong, Y., Vempati, S., Wai, E., Li, H., Liao, B., Ranganathan, N., Kripesh, V., Sun, J., Doricko, J., and Vath, C. “Development of through silicon via (TSV) interposer technology for large die (21 × 21 mm) fine-pitch Cu/low-k FCBGA package.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 305–312. Hu, G., Kalyanam, H., Krishnamoorthy, S., and Polka, L. “Package technology to address the memory bandwidth challenge for tera-scale computing.” INTEL Technol. J. 11:197–206, 2007. Knickerbocker, J. U., Andry, P. S., Buchwalter, L. P., Deutsch, A., Horton, R. R., Jenkins, K. A., Kwark,Y. H., McVicker, G., Patel, C. S., Polastre, R. J., Schuster, C., Sharma, A., Sri-Jayantha, S. M., Surovic, C. W., Tsang, C. K., Webb, B. C., Wright, S. L., McKnight, S. R., Sprogis, E. J., and Dang, B. “Development of next-gereration system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection.” IBM J. Res. Dev. 49:725–754, 2005. Tomita, Y., Morifuji, T., Ando, T., Tago, M., Kajiwara, R., Nemoto, Y., Fujii, T., Kitayama, Y., and Takahashi, K. “Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation.” In Proceedings of the Fifty-first Electronic Components and Technology Conference, Orlando, FL, 2001, pp. 353–360. Choi, W. K., Premachandran, C., Ong, C., Ling, X., Liao, E., Khairyanto, A., Chne, K., Thaw, P., and Lau, J. H. “Development of novel intermetallic joints

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Chapter Two using thin film indium based solder by low temperature bonding technology for 3D IC stacking.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 333–338. 18. Takahashi, K., Umemoto, M., Tanaka, N., Tanida, K., Nemoto, Y., Tomita, Y., Tage, M., and Bonkohara, M. “Ultra-high-density interconnection technology of three-dimensional packaging.” Microelectronics Reliability 43:1267–1279, 2003. 19. Lau, J. H., Lim, Y., Lim, T., Tang, G., Khong, C., Zhang, X., Ramana, P., Zhang, J., Tani, C., Chandrappan, J., Chai, J., Li, J., Tangdiongga, G., and Kwong, D. “Design and analysis of 3D stacked optoelectronics on optical printed circuit boards.” In Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 19–24, 2008, Vol. 6899, pp. 07.1–07.20. 20. Lau, J. H., and Tang, G. “Thermal management of 3D IC integration with TSV (through silicon via).” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 635–640. 21. Yu, A., Kumar, A., Ho, S., Wai, H., Lau, J. H., Khong, C., Lim, S., Zhang, X., Yu , D., Su, N., Chew, M., Ching, J., Tan, T., Kripesh, V., Lee, C., Huang, J., Chiang, J., Chen, S., Chiu, C., Chan, C., Chang, C., Huang, C., and Hsiao, C., “Development of fine pitch solder microbumps for 3D chip stacking.” IEEE Proceedings of Electronic Packaging and Technology Conference, Singapore, December 2008, pp. 387–392. 22. Yu, A., Lau, J. H., Ho, S., Kumar, A., Wai, Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D., Kwong, D., “Study of 15-μm-pitch solder microbumps for 3D IC integration.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 6 –10. 23. Yu, A., Lau, J. H., Ho, S., Kumar, A., Yin, H., Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., “Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps.” IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 350–354. 24. Yu, A., Khan, N., Archit, G., Pinjala1, D., Toh, K., Kripesh1, V., Yoon, S., and Lau, J. H. “Development of silicon carriers with embedded thermal solutions for high power 3D package.” IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 24–28. 25. Rebeiz, G. M. RF MEMS: Theory, Design and Technology. New York: Wiley, 2003. 26. Nguyen, C. “MEMS technology for timing and frequency control.” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 27. Mohamed Gad-el-Hak. The Mems Handbook. Boca Raton, FL: CRC Press, 2002. 28. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microw. Theory Tech. 51:305–308, 2003. 29. Anagnostou, D. E., Zheng, G., Chryssomallis, M., Lyke, J., Ponchak, G., Papapolymerou, J., and Christodoulou, C. G. “Design, fabrication and measurements of a self-similar re-configurable antenna with rf-MEMS switches.” IEEE Transactions on Antennas Propagat. 54:422–432, 2006. 30. Liu, A. Q., and Zhang, X. M. “A review of MEMS external-cavity tunable lasers.” J. Micromech. Microeng. 17:R1–R13, 2007. 31. Huff, G. H., and Bernhard, J. T. “Integration of packaged rf MEMS switches with radiation pattern reconfigurable square spiral microstrip antennas.” IEEE Trans. Antennas Propagat. 54:464–469, 2006. 32. Van Caekenberghe, K., and Sarabandi, K. “A 2-bit Ka-band rf MEMS frequency tunable slot antenna.” IEEE Antennas and Wireless Propagat. Lett. 7:179–182, 2008. 33. Nguyen, C. “MEMS technology for timing and frequency control,” IEEE Trans. Ultrason. Ferroelect. Freq. Contr. 54:251–270, 2007. 34. Tan, G. L., Mihailovich, R. E., Hacker, J. B., DeNatale, J. F., and Rebeiz, G. M. “Low-loss 2- and 4-bit TTD MEMS phase shifters based on SP4T switches.” IEEE Trans. Microwave Theory Tech. 51:297–304, 2003. 35. Hacker, J. B., Mihailovich, R. E., Kim, M., and DeNatale, J. F. “A Ka-band 3-bit rf MEMS true-time-delay network.” IEEE Trans. Microwave Theory Tech. 51:305–308, 2003.

Advanced MEMS Packaging 36. Ford, J. E., Goossen, K. W. , Walker, J. A., Neilson, D. T., Tennant, D. M., Park, S. Y., and Sulhoff, J. W. “Interference-based micromechanical spectral equalizers.” IEEE J. Select. Topics Quantum Elect. 10:579–587, 2004. 37. Nordquist, C. D., Dyck, C. W., Kraus, G. M., Reines, I. C., Goldsmith, C. L., Cowan, W. D., Plut, T. A., Austin, F., Finnegan, P. S., Ballance, M. H., and Sullivan, C. T. “A dc to 10 GHz 6-BIT RF MEMS time delay circuit.” IEEE Microwave Wireless Component Lett. 16:305–307, 2006. 38. Perruisseau-Carrier, J., Fritschi, R., Crespo-Valero, P., and Skrivervik, A. K. “Modeling of periodic distributed MEMS application to the design of variable true-time-delay lines.” In IEEE Trans. Microwave Theory Tech. 54:383–392, 2006. 39. Lakshminarayanan, B., and Weller, T. M., “Design and modeling of 4-bit slowwave MEMS phase shifters.” IEEE Trans. Microwave Theory Tech. 54:120–127, 2006. 40. Lakshminarayanan, B., and Weller, T. M. “Optimization and implementation of impedance-matched true-time-delay phase shifters on quartz substrate.” IEEE Trans. Microwave Theory Tech. 55:335–342, 2007. 41. Van Caekenberghe, K., and Vaha-Heikkila, T. “An analog rf MEMS slotline true-time-delay phase shifter.” IEEE Trans. Microwave Theory Tech. 56: 2008. 42. Maciel, J. J., Slocum, J. F., Smith, J. K., and Turtle, J. “MEMS electronically steerable antennas for fire control radars.” IEEE Aerosp. Electron. Syst. Mgnt., November 2007, pp. 17–20. 43. Pranonsatit, S., Holmes, A. S., Robertson, I. D., and Lucyszyn, S. “Single-pole eight-throw rf MEMS rotary switch.” IEEE/ASME J. Microelectromech. Syst. 15:1735–1744, 2006. 44. Lin, L. Y., and Goldstein, E. L. “Opportunities and challenges for MEMS in lightwave communications.” IEEE J. Select. Topics Quantum Electron. 8:163–172, 2002. 45. Vaha-Heikkila, T., Van Caekenberghe, K., Varis, J., Tuovinen, J., and Rebeiz, G. M. “Rf MEMS impedance tuners for 6–24 GHz applications.” Wiley Int. J. RF Microwave Computer-Aided Engineering 17:265–278, 2007. 46. Schoebel, J., Buck, T., Reimann, M., Ulm, M., Schneider, M., Jourdain, A., Carchon, G. J., and Tilmans, H. A. C. “Design considerations and technology assessment of phased array antenna systems with rf MEMS for automotive radar applications.” IEEE Trans. Microwave Theory Tech. 53:1968–1975, 2005. 47. Wu, M. C., Solgaard, O., and Ford, J. E. “Optical MEMS for lightwave communication.” J. Ligtwave Technol. 24:4433–4454, 2006. 48. Mailloux, R. J. Phased Array Antenna Handbook. London: Artech House, 2005. 49. Hoffmann, M., and Voges, E. “Bulk silicon micromachining for MEMS in optical communication systems.” J. Micromech. Microeng. 12:349–360, 2002. 50. Jung, C., Lee, M., Li, G. P., and Flaviis, F. D. “Reconfigurable scan-beam singlearm spiral antenna integrated with rf MEMS switches.” IEEE Trans. Antennas Propagat. 54:455–463, 2006. 51. Premachandran, C. S., Chew, M., Choi, W., Khairyanto, A., Chen, K., Singh, J., Wang, S., Xu, Y., Chen, N., Sheppard, C., Olivo, M., and Lau, J. H. “Influence of optical probe packaging on a 3D MEMS scanning micro mirror for optical coherence tomography (OCT) applications.” In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 829–833. 52. Premachandran, C. S., Lau, J. H., Ling, X., Khairyanto, A., Chen, K., and Myo Ei Pa Pa. “A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SiP applications. In IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, May 27–30, 2008, pp. 314–318. 53. Lau, J. H. “3D MEMS packaging.” In IMAPS Proceedings, San Jose, CA, November 2009. 54. Chen, K., Premachandran, C., Choi, K., Ong, C., Ling, X., Ratmin, A., Pa, M., and Lau, J. H. “C2W low temperature bonding method for MEMS applictions.” In IEEE Proceedings of Electronics Packaging Technology Conference, Singapore, December 2008, pp. 1–7.

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3

Enabling Technologies for Advanced MEMS Packaging 3.1 Introduction As discussed in previous chapters, through-silicon vias (TSVs); wafer thinning; thin-wafer strength measurements; thin-wafer handling; chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) bonding; and microelectromechanical systems (MEMS) wafer dicing are key enabling technologies for advanced MEMS packaging. This chapter presents TSVs, piezoresistive stress sensors, wafer thinning and thin-wafer handling, low temperature bonding, and MEMS wafer dicing. In order to make and ship green MEMS products everywhere in the world, these products must be compliant with the Restriction of the Use of Certain Hazardous Substances (RoHS) directive (e.g., lead free). Thus RoHS requirements, such as the fact that MEMS packaging must be lead-free and their lead-free solder joints must be reliable, will be discussed briefly.

3.2 TSVs for MEMS Packaging For three-dimensional (3D) MEMS packaging, TSVs are the most important enabling technology. TSVs provide advanced vertical interconnects and system-in-package (SiP) solutions such as C2C, C2W, and W2W stacking; wafer-level packaging and redistribution; interposer packaging; and the shortest electrical path (vertical electrical feedthrough) between two sides of a silicon “chip.” Just as with many other new technologies, TSVs still face many critical issues. In the development of TSVs, the following must be noted and understood.1–21

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Chapter Three • TSV cost is higher than that of wire bonding. • The only TSV volume product is CMOS image sensors. • Memory (e.g., Flash, DRAM, and SRAM) have just been talked about. • High-speed logic (e.g., processors and FPGAs) will come even later. • High-volume production tools are lacking and/or expensive. • TSV design guidelines are not commonly available. • TSV design software is lacking. • TSV technology usually requires redistribution layers (RDL). • TSV technology usually requires microbumps. • Test methods and software for TSVs are lacking. • Copper filling helps on thermal problems but increases thermal coefficient of expansion (TCE). • Copper filling takes a long time (low throughputs). • TSV wafer yields are high (>99.8 percent) owing to the large number of vias. • TSV wafer warpage is a problem owing to TCE mismatch. • Thin-wafer handling is necessary during all processes. • TSVs with high aspect ratios are difficult to make. • TSV inspection methodology is lacking. • TSV expertise is lacking. • TSV infrastructure is lacking. • TSV standards are lacking. Over the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in various journals or, more incidentally, in the proceedings of a number of conferences, symposia, and workshops whose primary emphases are electrical packaging and interconnection.1–21 Consequently, there is no single source of information devoted to the state of the art of TSV technology. This chapter discusses only the five key TSV process steps, and they are demonstrated through the vias-first process.

3.2.1 Via Formation The vias in a silicon wafer can be formed either by etching (wet process) or by laser drilling (dry process). Reviewing the literatures, more than 80 percent of vias have been formed by deep reactive-ion etching (DRIE), which is a highly anisotropic etching process. However,

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g 10000 Laser-A Laser-B Laser-C Laser-D DRIE-A DRIE-B DRIE-C DRIE-D

Cost ($/w)

1000

100

10 10

100

1000

10000

# Vias/die

FIGURE 3-1 Sematech’s cost model for fabricating TSVs by laser and by DRIE.

based on Sematech’s cost model of DRIE versus laser (Fig. 3-1), it can be seen that for lower numbers of vias per die, laser drilling may be cheaper. In addition, vias made by laser are adequate for most of applications of MEMS packaging. For example, Fig. 3-2 shows the vias of a cap wafer made by laser.20 Furthermore, the cavity of a cap

TSV

Cross section of cap wafer by laser machining

Cross section of cap wafer by laser machining

Cross section of cap wafer by KOH (potassium hydroxide) wet etch

FIGURE 3-2 MEMS cap wafer with cavity and TSV fabricated by laser and by KOH etch methods.

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Chapter Three wafer can be made by laser machining, even though KOH etch yields a better (straight) wall condition. In this chapter, however, the threestep method developed14,16,18 based on the high-rate DRIE BOSCH technology will be discussed. The silicon vias are formed in an inductive-coupled plasma (ICP)–based deep reactive ion etching system from Surface Technology Systems (STS). Although the STS ICP system is designed mainly for performing deep reactive-ion etching of silicon by a specially designed switched etch and passivation process, also known as the BOSCH process, it also can be used in reactive-ion etch mode, referred as the non-BOSCH process.18 The system consists of ICP electronics, loadlock and carousel wafer-loading unit, and a process chamber. The plasma is generated by a coil assembly that is inductively coupled at 13.56 MHz via the matching unit in a ceramic plasma chamber. This provides high-density plasma capable of achieving high etch rates with little substrate damage. Independent biasing of the platen is made available by a separate 13.56-MHz radiofrequency (RF) biasing circuit on the bottom electrode that comes with automatic power control and impedance matching. Process gas is introduced to the chamber through the upper electrode assembly. Wafers are clamped by electrostatic chuck (ESC) on the lower electrode, which is powered at 13.56 MHz. The platen temperature is kept at 10°C by using recirculating deionizer (DI) water through a chiller system. The high-aspect-ratio tapered silicon vias are formed by three independently controlled process steps: (1) the straight via formation step by the BOSCH etch process, (2) the via tapering step by a controlled isotropic etch process, and (3) the corner-rounding step by a global isotropic etch process. The first etching step is designed mainly to achieve high etch rates with the BOSCH etch process. Typically, a high-etch-rate BOSCH process tends to give a vertical to slightly reentrant profile, as shown in Fig. 3-3 (left). The gases used in the BOSCH process are mainly sulfur hexafluoride (SF6) plus oxygen (O2) in the etch phase and C4F8 in the passivation phase. The recipes are shown in Table 3-1.18 It should be noted that as a consequence of the cyclic etch/passivation process, the sidewalls become scalloped or rough. In this step, the via is etched to approximately 50 to 60 percent of the final depth. This step defines the dimension of the via at the bottom and the depth. A non-BOSCH etch process consisting of a reactive-ion etching (RIE) process is used to produce the required tapered-sidewall profile. This is basically a controlled isotropic etch process that uses SF6 plus O2 plus Ar (argon) etch chemistry (see Table 3-1). The oxygen used helps in sidewall passivation and also controls excessive lateral etch rate. A proper balance between SF6 and O2 provides the desired taper angle to the via structure. As a consequence of this process, a sharp curvature is formed at the top of the via, as shown in Fig. 3-3 (center). At the end of step 1 (BOSCH process) and step 2 (non-BOSCH process),

108.1 µm

62.2 µm

137.82 µm 91.48 µm

96.5 17.05 µm

210µm

57.3 µm

After step 1 (BOSCH)

222µm

55.3 µm

220.45 µm

After step 2 (RIE)

55.11 µm

After step 3 (isotropic)

FIGURE 3-3 Step 1 shows the results achieved after 50-μm-diameter vias are etched to a depth in the range of 200 to 220 μm. Step 2 shows the evolution of a tapered profile after etch by a controlled-isotropic etch process and step 3 shows the final tapered via profile after the top corner is rounder by a global isotropic etch process.

Step 1: Straight (BOSCH) etch process

Etch cycle: APC: 77% (26 mt); 130 sccm SF6; 13 sccm O2; 600-W coil power; 20-W platen power; 6 seconds Passivation cycle: APC: 77% (17 mt); 85 sccm C4F8; 600-W coil; 5 seconds Platen temperature: 10°C Total process time: 60 minutes Etch rate: 3 to 3.5 μm/min on 15% to 20% exposed area

Step 2: Via tapering (RIE) process

APC: 78% (30 mt); 84 sccm SF6; 67 sccm O2; 59 sccm Ar; 600-W coil power; 30-W platen power Platen temperature: 10°C Process time: 60 minutes Etch rate: 3.5 to 4.0 μm/min on 15% to 20% exposed area

Step 3: Via corner rounding (isotropic etch) process

APC: 65% (12 to 13 mtorr); 180 sccm SF6; 18 sccm O2; 600-W coil power; 30-W platen power Platen temperature: 10°C Process time: 10 minutes Etch rate: 1.5 to 2.0 μm/min on blanket silicon wafer

TABLE 3-1

Summary of the Three-Step Via Tapering Process

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Chapter Three the required via depth and taper angle are almost achieved, except for the sharp curvature at the top of the via. After completing the earlier two etch steps, the etch mask is fully stripped and cleaned. The wafer then is subjected to a maskless global isotropic etch process. In this etch step, the etched via patterns are mainly subjected to an isotropic etch plasma that is rich in fluorine radical (see Table 3-1 for the recipes). Since the reaction in this step is mainly chemical in nature and mostly diffusion-limited, the reaction occurs more on the rough edges and sharp corners in the top region of the microstructure, resulting in well-rounded, smooth sidewalls inside the vias, as shown in Fig. 3-3 (right).

3.2.2

Dielectric Isolation Layer (SiO2) Deposition

The thermal oxidation (wet process) is used to deposit the isolation layer. The 1-μm SiO2 is grown in a Micro Fabrication Laboratory (MFL) furnace. Hydrogen and oxygen are mixed in the quartz bulb, where they react to create a flame and steam at 1050°C. The oxidation time of Si is 3-½ hours. Conformal SiO2 is shown in Fig. 3-4. The top, middle, and bottom of the via are covered by uniform SiO2. Uniformity of SiO2 is within ±5 percent. The sidewall roughness decreases from 200 to 250 nm to less than 100 nm because of silicon consumption in wet oxidation.18 The SiO2 also can be deposited by the dry process—plasma-enhanced chemical vapor deposition (PECVD), as shown in Fig. 3-5. It can be seen that the deposited oxide thickness is 1.9 to 2 μm on the top side of the via, 1.3 to 1.4 μm on the top sidewall, 0.7 to 0.8 μm on the middle sidewall, and 0.35 to 0.45 μm on the via bottom. Thus, the SiO2 thickness made by the dry process is not as uniform as that made by the wet process. In this case, the process temperature is less than 250°C.18 Top Top Middle

Middle

Bottom of via Bottom Bottom

FIGURE 3-4 Dielectric isolation layer (SiO2) deposited by wet thermal oxidation (1080°C).

E n a b l i n g Te c h n o l o g i e s f o r A d v a n c e d M E M S P a c k a g i n g Top

Middle

Bottom

FIGURE 3-5 Dielectric isolation layer (SiO2) created by plasma deposition

( 400°C

ηCu6(InSn)5

–10

–15 0

100

200 300 Temperature, °C

400

500

FIGURE 3-45 Cross section of a joint bonded at 1.5 MPa and 180°C for 20 minutes (left) and its DSC curve (right).

are given. Figure 3-45 shows a void-free cross section and the differential scanning calorimetry (DSC) curve indicting that the remelting temperature is higher than 400°C. Figure 3-46 shows the very good helium-leakage test results and shear-strength test results. The lowtemperature interconnects also pass some reliability assessments, such as the pressure cook test (PCT), the high-temperature-storage test (HTS), and the thermal cycling test (TCT).

As Sealed

PCT

HTS

TCT

He leakage (atm · cc/s)

100,000

O2

350

CH3COOH3 (acetone)

>100,000

Aluminum

(Reprinted with permission from Maluf, N., and Williams, K., An introduction to microelectromehcanical systems engineering, 2nd Edition, London: Artech House, 2004, ISBN 1-58053-590-9, Copyright 2004 Artech House)

TABLE 4-1

Wet and Dry Etchants of Thin Metal Films and Dielectric Insulators

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Other than the dry-etching mechanisms introduced earlier (e.g., ion-bombard etching and RIE using capacitively coupled parallelplate electrodes), the last mechanism, and perhaps the most important dry-etching technique used in bulk micromachining, is high-density plasma etching. By using inductively coupled plasma (ICP) or an electroncyclotron resonance (ECR)–based power source, the high-density plasma reactor can independently control plasma parameters such as electron energy, ion energy, and plasma density. The high-density plasma reactor operates at lower process pressures and achieves a high ionization ratio such that the density of the plasma is higher than that of capacitively coupled plasma because the high-density plasma reactor can efficiently transfer energy to electrons so as to achieve a high ionization ratio. Furthermore, the longer mean free path of ions in the lowpressure process in a high-density plasma reactor enables significant improvements in directional etching. Therefore, high-density plasma etching is called deep reactive ion etching (DRIE). Starting in early 1990s, research attempts were focused on advanced DRIE in order to develop bulk micromachined structures with very high aspect ratios. One approach was for the glow discharge to supply the etchants, energetic ions, and inhibitor precursor molecules. Most plasma processes are a critical race between deposition of polymeric material from the plasma and removal of material from the surface. In well-designed plasma chemistries, removal (i.e., the etch process) dominates. By using a cryogenic cooling technique, when a wafer is maintained at liquid-nitrogen temperatures, the reactant gases condense onto the silicon surface, thus passivating the surface. For example, the inhibitor precursor molecules (e.g. CF2, CF3, CCl2, and CCl3), which are called unsaturates, deposit on the substrate surface to form fluoro- or chlorocarbon polymer films (i.e., a protective layer). In such DRIE equipment, the ion-bombardment effect is suppressed, but just enough for removal of the polymer layer on the bottom surfaces of etched trenches so as to perform the reactive ion etching continuously, whereas the polymer layer on the sidewalls of the trenches is retained owing to the directional ion etching effect (i.e., energetic ions move along the direction normal to the substrate). SF6 typically is used because of the high etch rates that can be achieved. The passivation can be enhanced by the addition of oxygen to the plasma, which results in an increased ratio of fluoro- to carbon, meaning more fluorounsaturates for polymer passivation. A potential problem with the cryogenic approach involves maintaining the cryogenic temperature of all the microstructures during the etch process. Some microstructures may become thermally isolated from the substrate when they are released from the substrate and become free-standing. The raised temperature in the local freestanding microstructures may lead to deterioration of polymer passivation. When polymer passivation on these microstructures is not sufficient, the etching mode dominates. As a result, notching and RIE

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Chapter Four

C4F8

Photoresist

Scallop SF6

CF2 species for passivation

F species for etching

(a)

(b)

Photoresist

Silicon 10 μm (c)

1 μm (d)

FIGURE 4-2 Profile of a DRIE trench using the Bosch process: (a) passivation step of using CF2 species; (b) fluoroion-based etching step; (c) SEM microphotograph of cross-sectional view of DRIE trenches; (d ) SEM microphotograph of close-up view of scalloped sidewall. The process cycles between an etch step using SF6 gas and a polymer deposition step using C4F8. The polymer protects the sidewalls from etching by the reactive fluorine radicals.

lag effects are observed in this case such that the uniformity of etching results is not good. Scientists at Bosch have developed a revised process to further improve process control in DRIE.10 Instead of relying on the balance between plasma etching and polymer passivation, the Bosch process uses alternate etching and passivation steps, as shown in Fig. 4-2. The passivation is achieved by deposition of a polymer using CFx+, which is decomposed from C4F8 feedgas. The subsequent step is a reactiveion etching process using such species as F+ and SFx+, whereas the polymer on the bottom of the trench is removed owing to the directional etching effect of ion bombardment. The normal cycle time for each deposition or etch step is a few seconds. The resulting etch rate is 1 to 15 μm/min typically. An aspect ratio of etched trench of 30:1 can be achieved. A comparison of DRIE technology with other bulk micromachining technology is given in Table 4-2. The general issues

HF:HNO3: CH3COOH

KOH

EDP

N(CH3)4OH (TMAH)

SF6

SF6/C4F3 (DRIE)

XeF2

Etch type

Wet

Wet

Wet

Wet

Plasma

Plasma

Vapor

Typical formulation

250-ml HF, 500-ml HNO3, 800-ml CH3COOH

40 to 50 wt%

750-ml ethylenediamine, 120-g pyrochatechol, 100-ml water

20 to 25 wt%

Anisotropic

No

Yes

Yes

Yes

Varies

Yes

No

Temperature

25°C

70–90°C

115°C

90°C

0–100°C

20–80°C

20°C

Etch rate (μm/min)

1–20

0.5–3

0.75

0.5–1.5

0.1–0.5

1–15

0.1–10

[111]/[100] Selectivity

None

100:1

35:1

50:1

None

None

None

Nitride etch (nm/min)

Low

1

0.1

0.1

200

200

12

SiO2 etch (nm/min)

10–30

10

0.2

0.1

10

10

0

p + + etch stop

No

Yes

Yes

Yes

No

No

No

Roomtemp. vapor pressure

167

(Reprinted with permission from Maluf, N., and Williams, K., An Introduction to Microelectromehcanical Systems Engineering, 2nd Edition, London: Artech House, 2004, ISBN 1-58053-590-9, Copyright 2004 Artech House).

TABLE 4-2

Liquid, Plasma, and Gas Phase Etchants of Silicon

168

Chapter Four in both DRIE processes is that the etch rate is a function of the density of the opening area and trench width. Investigation of an etched dummy wafer is necessary for etch-rate calibration when users have a new lithography mask layout. Another dry bulk micromachining approach is vapor-phase etching. A reactive gas mixture that typically contains fluorine can etch silicon with very high selectivity to many masking layers, including Al, SiO2, Si3N4, photoresist (PR), and phosphosilicate glass (PSG). One of the most widely employed reactive gases is XeF2. As suggested by Chang and colleagues,11 the reaction with silicon is given by 2XeF2 + Si → 2Xe + SiF4

(4-6)

The gas xenon diflouride performs the non-plasma-based isotropic etch of the solid silicon surface and forms the volatile SiF4 product. This etch reaction completes with desorption of the volatile SiF4 product and residual xenon from the silicon surface. It is noteworthy that the etched surfaces shows granular structures of a few microns, making the etched surface unsuitable for situations where smooth surfaces are required (e.g., optical reflection surfaces). This reaction is exothermic. Thus the generated heat may adversely influence some microstructures. Pulse-mode operation of XeF2 etching is suggested. An important concern is that XeF2 reacts with water (even moisture in air) to form Xe and HF, whereas the generated HF will unintentionally etch silicon dioxide. A properly designed reaction chamber linked with a vacuum pump is still required for handling XeF2 vaporphase etching. The typical etch rate is a few micrometers per minute, as shown in Table 4-2. It is ideal for the dry release of CMOS MEMS devices (i.e., dielectric layers from a CMOS substrate) and surface micromachined structures in which polysilicon is used as the sacrificial layer.

4.2.3

Conventional Wafer-Bonding Technologies for Packaging

Wafer bonding is used widely in MEMS fabrication and packaging.12 It refers to approaches of firmly joining two wafers (or more) to create a stacked and bonded wafer. There are three main kinds of waferbonding processes: direct bonding, field-assisted bonding, and bonding with an intermediate layer. The choice of which is most suitable depends on the particular application and the materials involved. Silicon-to-silicon direct bonding, also called fusion bonding, is a direct silicon-to-silicon bonding technique without the assistance of significant pressure or any intermediate layers or fields.13 The process requires rather flat and clean surfaces as the bonding interface for the two wafers. The surfaces of silicon wafers are cleaned and rinsed first. Hydroxyl (–OH) groups form on the surfaces of the two wafers with

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g a thin native silicon oxide layer (i.e., hydrophilic surface). Two wafers can be joined together at room temperature, resulting in an immediate weak bond owing to van der Waals forces. Then the bonded wafers are heated to 800 to 1000°C to remove the water molecules and leave behind Si–O–Si bonds at the interface. Owing to perfectly matched thermal-expansion coefficients of the two wafers, silicon direct-bonded wafers have little or no residual stress owing to thermal mismatch. However, silicon direct bonding normally is used as the beginning step in an integrated process because of the rather high annealing temperature and high-quality requirement of the bonding interface in terms of cleanness and flatness. Another direct-bonding technology is restricted to bonding glass to a conductive substrate using electrical bias, that is, field-assisted bonding or anodic bonding.14 A glass wafer with a high concentration of sodium ions (e.g., Pyrex 7740 glass from Corning) is biased as the cathode, and the silicon wafer is the anode. The contacted wafers are heated to 300 to 400°C, and a voltage of about 200 to 1000 V is applied. The applied voltage produces a very high electrostatic attractive force that pulls the silicon and glass into intimate contact. The sodium ions in the glass wafer (i.e., the cathode side) diffuse toward the opposite side from the bonding interface, whereas the oxygen ions of negative charge are left behind and accumulate at the bonding interface. The available oxygen ions and silicon atoms at the interface will form strong Si–O bond, whereas a current of a few milliamperes per square centimeter flows between the two electrodes, signifying the movement of ions and completion of the process. When bonding is completed, this current drops to zero. Similar to the concern we have in silicon direct bonding, the anodic bonding is very susceptible to interference from particulate contaminants. To achieve an anodic bonded interface of good quality, there are several parameters, such as surface preparation, contact load, temperature, time of applied voltage, and magnitude of the applied voltage, that should be monitored during the bonding process. A number of glasses from different vendors can be used in anodic bonding. Basically, conductive glasses with a reasonably high content of sodium and boron have lower melting and softening temperatures. These glasses are more suitable for anodic bonding. When the glass is purer, its electrical conductivity decreases, which reduces the electric field strength and lowers the electrostatic attraction that exists between the two wafers. As a result, glass substrates of lower conductivity typically need a higher bonding temperature and a higher biased voltage to achieve a successful bond. A wide range of intermediate layers has been used for wafer-towafer bonding in microstructure fabrication. These intermediate-layer bonding approaches include eutectic bonding, glass-frit bonding, solder-based thermocompression bonding, and adhesive bonding. Eutectic bonding deploys a thin gold layer as an adhesive layer to

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170

Chapter Four bond silicon wafers.15 The wafers, coated with a thin gold layer, are brought into contact at a temperature higher than Au-Si eutectic point (i.e., 363°C for 2.65% Si in Au). The common practice is bonding at 370°C for 15 minutes under 7 kN of applied force using a commercially available bonding tool. Wafer-level packaging based on a glassfrit-sealed interface between the MEMS wafer and a cap wafer has been a major technology for volume production of MEMS accelerometers in automotive airbag systems to realize hermetic sealing. This method is similar to the long-established approach of glass frits as seals in conventional hermetic ceramic packages.16 The cap wafer is stenciled with a mixture of glass and binder and patterned to form the walls of each device cavity. Another cap wafer is aligned and thermocompression bonded to the device wafer with glass-frit bonding rings. The bonding condition typically requires a temperature higher than 400°C and an applied pressure of 2 bars. However, reliable sealing using glass frits requires a relatively wider wall-sealing pattern. This implies fewer gross dies per bonded wafer. Eutectic Au-Sn solder has long been recognized as an approach offering superior high-temperature performance, high mechanical strength, and fluxless soldering because the melting temperature of its eutectic composition (Au 30 at% Sn) is 280°C.17,18 This approach has been used widely in the optoelectronics and microelectronics industries. It is a reliable solution for packages comprised of sealing of a Kovar case to a ceramic substrate. However, there is concern that a large residual stress will be introduced when two bonded wafers with a relatively large difference in coefficient of thermal expansion (CTE) undergo a process with a large temperature difference. In addition to the above-mentioned wafer-bonding technologies using the intermediate layer for hermetic bonding, the last group is polymer-based adhesive bonding. First, polymer-based adhesive bonding is used as temporary bonding of wafers, where the polymer just has to keep the wafers together during the micromachining process. Second, polymer-based adhesive bonding can be used to form waferbonded structures in nonhermetic and near-hermetic packages. Various kinds of adhesives, including epoxies, poly(methylmethacrylate) (PMMA), polyimides, silicone rubbers, and negative photoresists, are used. Generally, such polymer bonds can be achieved at temperatures lower than 150°C. Thus there is no serious concern about residual stress owing to the thermal-expansion mismatch between different types of wafers in the bonded wafers.19 Two polymer materials with major research interests are SU-8 and benzocyclobutene (BCB). SU-8 is an epoxy-based negative-resist material from Microchem, whereas BCB is from the Dow Chemical. BCB shows minimal outgassing, low moisture uptake, and excellent electrical properties. In one process, as shown in Fig. 4-3, BCB is spincoated onto the capping wafer and photopatterned to provide sealing

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g

Si Si

(a)

BCB intermediate bounding layer

(b) (e)

Spacing created by using dicing saw

(c) Si cap

(d)

PCB

(f)

FIGURE 4-3 Wafer-level packaging approach using polymer as the intermediate layer to form the sealing interface, ref. 21.

rings. After the cap wafer is bonded with the device wafer, multistep dicing is used to expose the bonding-pad area and separate each die from the bonded wafer (see Fig. 4-3b and c). For example, the capped die can be die-bonded and wire-bonded on a PCB. Thereafter, the whole packaging process is accomplished by a molding step (see Fig. 4-3d). The bonded wafer after dicing and a close-up view are shown in Fig. 4-3e and f, respectively. The reflow characteristic of BCB during the curing step allows the planar electrical signal feed-throughs passing through the bonding ring while maintaining a good seal. RF MEMS switches and film bulk acoustic resonator (FBAR) filters have been packaged by using the BCB capping process.20,21 On the other hand, we do not want residual BCB left inside deep cavities for wafers with high-aspect-ratio cavities; thus, we should not use a spin-on step to prepare the BCB coating layer. Besides, we could not use the spin-on process to prepare the BCB coating layer on a wafer with free-standing structures. A new process called contact printing provides better results than the spin-on technique. The contact printing method uses viscous BCB as “ink” and a soft-cured BCB pattern as a stamp to improve the bond strength of full-wafer adhesive bonding with patterned BCB as the intermediate bonding layer. This technology successfully demonstrated that the bond strength of samples has been improved by a factor of 2 over the conventional spin-on BCB bonding technique.22,23

171

172

Chapter Four

4.2.4

Plasma-Assisted Wafer-Bonding Technologies

Another low-temperature direct bonding approach is known as plasma-activated wafer bonding or surface-activation bonding. The plasmaactivation step modifies the surface chemistry in a similar manner to hydrophilic surface treatment. The substrates are pretreated with plasma and cleaned off, and then they are brought into contact with or without external pressure and high temperature to form an irreversible bond.24,25 Plasma may be generated from different feedgases, including oxygen, argon, nitrogen, and hydrogen. Oxygen plasma creates a thin oxide layer on the interface and is used for applications that require electrical isolation at the interface. On the other hand, hydrogen, nitrogen, and argon plasmas are used in applications where a bonded interface is preferred that does not have a residual oxide layer. Obviously, this process has to be carried out in a vacuum environment (i.e., a plasma chamber such as an RIE chamber or an ICP chamber). It is also possible to treat the surfaces chemically using a barrier-discharge method, where plasma is formed in the atmosphere. Plasma-activated bonding now has been applied to various materials, including silicon, compound semiconductors, oxides, and polymers.25 Normally, an annealing step at an elevated temperature of 100 to 400°C is needed depending on the required bond strength and the materials being bonded. When the wafer surface is cleaned using argon-beam sputtering in a high-vacuum environment, silicon wafers can be bonded at room temperature.26,27 The type of plasma used to activate the bonding surface, plasma power, and the annealing step all can have a significant influence on bond strength and void or defect density at the interface. Because wafers need to be aligned and then bonded in the plasma chamber without breaking vacuum, specialized alignment and bonding stages, as well as the substrate heater, need to be included in a single machine.

4.2.5

Electrical Interconnects

The most common electrical interconnects are the planar electrical leads. They are typically prepared on the same side of MEMS wafer. There are two major kinds of planar electrical leads: buried leads and surface leads. Buried leads can be heavily doped Si or metal silicide (e.g., AlSi) that forms a low-resistive path on the silicon substrate. For the surface lead line, the Al-alloy process used in microelelctronics is a common solution for MEMS (see Fig. 4-3). However, the Al may need to be substituted by other materials that can withstand the hightemperature process. Highly doped polysilicon is used commonly as a lead-line material in the surface micromachining technology, and it can sustain in all kinds of high-temperature wafer-bonding processes using the intermediate layer. Generally speaking, highly doped silicon or polysilicon is used widely as lead lines in electrostatic actuated

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g MEMS and capacitive sensors. It should be noted, though, that polysilicon leads typically exhibit higher 1/f noise than metal leads. Thus, in some resistive types of MEMS sensors, polysilicon leads may not be a good choice. Second, anisotropic wet-etched Si V-grooves could be used for through-wafer vertical electrical vias when metal leads are sputtered or electroplated on the V-groove sidewalls. Owing to the angle of the V-grooves, the footprint of through-wafer V-groove vias is relatively larger, as shown in Fig. 4-4a.28 Since the size of the through-wafer V-groove vias is determined simply by the thickness of wafer, by using a thin device layer of a silicon-on-insulator (SOI) wafer, the V-groove vias can be shrunk to a very small area (see Fig. 4-4b and c).18

(a) Electrical interconnects

μ-via

Solder ball (b)

V-groove μ-via SMD pad

Sealing ring

μ-via

(c)

FIGURE 4-4 V-groove type of vertical interconnects with small footprint for wafer-level MEMS packaging.

173

174

Chapter Four On the other hand, through-wafer vertical holes of silicon and glass substrates can be created by using DRIE or photo-assisted electrochemical etching. After forming the insulation layer based on thermal oxidation, chemical vapor deposition (CVD) dielectric-layer coating, or CVD parylene coating, the through-wafer vertical interconnects can be formed by heavily doped polysilicon conformal deposition, metal sputtering, metal plating, or vacuum metal sucking and refilling.29–32 Combining the vertical interconnects with cavities on the cap wafer allows the formation of a large number of interconnects and wafer-level packaging by means of a simple bonding step at the same time. In particular, wafer-level packaging using a solder intermediate layer with reflow is very suitable to this approach because the solderreflow step will enhance the connection between the vertical interconnects of the cap wafer and the planar electrical pads of MEMS wafer both mechanically and electrically. As shown in Fig. 4-5, this concept has been applied to the vacuum sealing of accelerometers (see Fig. 4-5a and b) and the hermetic sealing of RF MEMS switches (see Fig. 4-5c and d).33,34 Without using the high-temperature thermal oxidation process, a novel low-temperature process of creating a thick SU-8 dielectric isolation between Cu vertical interconnects and surrounding Si sidewalls has been reported.35 This approach allows one to create vertical interconnects on a wafer after MEMS devices

Transmission line Piezoelectric actuator

Via hole

Cap wafer

Vacuum Cap substrate

MEMS device Contact electrode

(a) Bottom substrate

Accelerometer device

(c) Via hole Electrode

Copper via

CPW line Bonding material Cap substrate

Cap wafer

Sealing rim

Solder ball Bottom substrate

Substrate (PCB)

(b)

Piezoelectric film

(d)

Contact electrode

Dielectric membrane

FIGURE 4-5 Through-wafer vertical interconnects with solder joints formed at the same wafer-bonding step for solder-based wafer-bonding MEMS packaging.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g or Al planar electrical leads have been prepared on the same wafer. Additionally, the vertical interconnects are quite useful for SiP applications with high input-output (I/O) pin counts.

4.2.6

Solder-Based Intermediate-Layer Bonding

The choice of the intermediate bonding layer is made based on the types of substrates to be bonded, the thermal budget of the process temperature, and whether hermetic sealing is required or not. The well-known intermediate-layer bonding techniques include the use of polymer-based bonding at temperatures ranging from 100 to 150°C, Au/Sn solder–based eutectic bonding at 280°C,17,36 Au/Si eutectic bonding at 365°C,37 and glass-frit bonding at 400°C. Given that most of applications require hermetically sealed packages, polymer-based intermediate-layer bonding produces a gas-permeable interface and therefore does not meet the hermetic sealing requirements. Thus Au/Sn solder bonding and glass-frit bonding are the mainstream approaches in the MEMS industry nowadays. However, many MEMS devices contain different materials or need to bond substrates containing the electronic part of the device (e.g. CMOS wafers). Thus the difference in thermal-expansion coefficients of the dissimilar materials results in mechanical stress that is in proportion to the process temperature. Therefore, low-temperature wafer bonding is the key to avoiding such residual mechanical stress. To fulfill the requirements for hermetic sealing and low process temperatures, indium and indium-based alloy solders have been reported to be very attractive intermediate-layer materials. The batch-type techniques for preparing the solder pattern on wafers for bonding include stenciling, dip coating, electroplating, and evaporation/sputtering. The technical challenges of this process involve uniformity control of the solder pattern, thickness, and composition. Since the In-Sn material system has a eutectic point at 118°C and pure indium melts at 156.6°C, In-Sn (50/50) solder has been investigated as the bonding intermediate layer for packaging of thermal sensors and infrared imaging sensors.38 A helium-leakage rate less than 1 × 10–8 (torr · liter)/s and tensile strength of 200 kg/cm2 for the bonding interface can be obtained with a bonding temperature of 150°C.39 Au-In-Ni intermediatelayer material has been used for packaging thermal sensor arrays as well.40 The authors of this study suggested a thermocompression approach based on the cold-welding characteristics of indium. In a bonding chamber with a forming-gas environment (e.g., N2 90 percent and H2 10 percent), a shear strength of 72 MPa at the bonding interface can be obtained with a bonding temperature of 195°C for 10 minutes with an applied pressure of 8 MPa. This package shows postbonding temperature stability up to 473°C. On the other hand, In compression bonding has been reported for wafer bonding of vacuum-packaged microbolometers for infrared imaging applications.41–43 Extensive

175

176

Chapter Four studies on low-temperature bonding and the characteristics of the bonding interface on the chip-to-chip scale have been reported44–48 using various bonding-interface materials (e.g., In-Sn, In-Ag, In-Cu, and In-Au). Moreover, the industry also requires solder-bonded interfaces to be able to survive at temperature at least as high as 285°C, which is the peak temperature in the surface-mounting-technology (SMT) manufacturing line. This means that the resulting intermetallic compounds (IMCs) of the solder-bonded interfaces in any postbonding steps need to have a melting temperature (i.e., a remelting temperature) that is higher than the postbonding process temperature. Incorporating In and Sn as the solder layer to react at a high melting temperature to form stable IMCs is a new research direction in low-temperature solder-based wafer bonding that aims to create a materials evolution of the resulting IMCs at the bonded interfaces with respect to various postbonding heat-treatment process conditions. We will discuss this recent progress in Sec. 4.6.

4.3 Wafer-Level Encapsulation Wafer-level encapsulation is an approach that consists of using a sacrificial material to cover the MEMS device and a deposited thin film under tensile stress to encapsulate the MEMS device, followed by removal of the sacrificial layer by wet etching or vapor-phase etching through the opening and then encapsulation of the opening by deposition of a thin film. In the case of encapsulating the opening in a thinfilm reaction chamber under vacuum, the sealed cavity of the MEMS device can be preserved at low vacuum. This concept has been applied to achieve wafer-level packaging for capacitive- and piezoresistivesensing pressure sensors49–51 (Fig. 4-6a and b) based on low-pressure chemical vapor deposition (LPCVD) SiN film sealing and for resonators based on polysilicon-film sealing (Fig. 4-6c).52-53 This process is suitable for sealing surface-micromachined MEMS devices owing to its perfect process integration. To enhance the durability and mechanical robustness of the encapsulation, a 20-μm-thick epitaxial Si layer is prepared using dichlorosilane at 1080°C to seal the MEMS structure first, denoted as the cap layer in Fig. 4-6d. Then trenches are etched through the cap layer to allow the HF vapor etching to remove the refilled SiO2 and release the MEMS structure, thereby isolating the electrical conductive paths.54,55 Finally, a layer of LPCVD oxide is deposited on top of the cap layer to create a seal over the trenches. Since the oxide deposition furnace is under vacuum, the parts are also under vacuum when sealed. After the sealing oxide is deposited, metal layer is deposited and patterned to form the electrical leads and pads. Since SiO2 is permeable to the ambient gases, the silicon nitride film or metal layer on top of the oxide seal location can extend the vacuum life of package.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g SiN diaphragm PolySi piezoresistors

Optional CMOS

Electrode contact

Epi layer

Sealed vacuum cavity

(a)

Poly layer

SOI layer

(e)

Handle wafer

Deflection electrode

Vibrating resonator

(b) Si epilayer

Shell of sealed vacuum cavity

SOI layer

(c)

Seal oxide Aluminum pads

Al contacts Sealing of vents Seal oxide Cap layer Refill oxide Device layer Sacrificial oxide

(d)

Handle wafer

(f)

PolySi

(g)

FIGURE 4-6 Wafer-level packaging approaches using high-temperature processes to form the wafer-level encapsulation.

4.3.1

High-Temperature Encapsulation Process

The last process described in previous section has been further developed by the Bosch Group and Stanford University and was commercialized recently by SiTime (www.sitime.com) for packaging of MEMS oscillators.56 As shown in Fig. 4-6e and f, this technology encapsulates silicon resonators in epitaxially sealed chambers buried under the wafer surface. Recently, an ultracompact encapsulated accelerometer with a die size of 387 × 387 × 230 μm has been demonstrated using this epitaxial Si encapsulation technology, as shown in Fig. 4-6g.57 The first step in the fabrication process is patterning the resonator structure from an SOI wafer with a 10- to 20-μm-thick device layer. An oxide layer is deposited and patterned to cover the resonator structure while providing via openings for electrical contacts. Then a thin epitaxial silicon layer is grown and patterned to get via openings through the oxide layer down to the silicon electrode part of the

177

178

Chapter Four device layer. Using the HF vapor-based etching, a portion of the oxide layer is removed to release the movable parts of the resonator structure. Thus the portion of this oxide layer that is the sacrificial layer, whereas the remaining portion is the insulating oxide layer (see Fig. 4-6e and f ). In the last step, a thick epitaxial silicon layer is grown on top to seal the trenches such that the cavity containing the movable parts of the resonator is sealed with the same degree of vacuum as the process-chamber pressure used in the epitaxial silicon deposition process. The epitaxial silicon grown on top of the oxide layer forms a polycrystalline silicon layer, whereas a single-crystal silicon layer is formed in the area where the oxide has been removed. After surface planarization and formation of contact isolation trenches, the wafer with encapsulated MEMS structures can be used as a starting wafer for further CMOS processing to create monolithically integrated circuits. The MEMS-first front-end wafer-level packaging process completely defines, releases, and seals the resonant microstructures in the front-end processing steps. Thus it provides reliable wafer-level vacuum packaging at low cost. One advantage of using a high-temperature sealing process (i.e., epitaxial Si deposition) to enable the Si oscillators to be embedded inside a sealed vacuum cavity is that the absorbed molecules inside the cavity will be removed during the high-temperature sealing step, just as in the hot baking treatment. Thus the newly released product exhibits excellent performance in terms of ultralow long-term drift of device features and good frequency stability against temperature variation.56

4.3.2

Low-Temperature Encapsulation Process

This high-temperature epitaxial Si sealing process limits material selection for MEMS devices. Some metals and low-temperature oxides cannot sustain their material characteristics under such high temperatures. As shown in Fig. 4-7, a three-mask low-temperature electroplating process has been proposed.58 An electroplated 40-μmthick nickel film is prepared on a sacrificial photoresist layer of several microns first (see Fig. 4-7a, 5). After the photoresist has been removed via access holes (see Fig. 4-7a, 8), the access holes can be sealed by sputtering a metal layer or melting Pb/Sn solder (see Fig. 4-7a, 9 and 10). If the final sealing step is handled inside a vacuum chamber, a sealed vacuum of about 1.5 torr can be obtained. Figure 4-7b and c show a schematic drawing of a sealed Pirani vacuum sensor and electroplated nickel thick-film cap, respectively. One drawback of this process is that the photoresist-removal step may take several hours. Recently, a novel encapsulation technique used a thermal decomposition step within the temperature range of 180 to 260°C to vaporize the sacrificial polymer via a permeable polymer overcoat, resulting in an encapsulated cap made of the suspended polymer overcoat,59 as shown

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g NI

Cr/Al Si 1. Pattern Cr/AI feed-throughs

PR

PR

Si

Si

PR Si

2. Pattern 3. Evaporate Cr/Au 4. Define plating sacrificial PR seed layer mold

NI

NI

PR

PR

Si 6. Strip PR and AU

PR Si 5. Plate Ni

NI

NI

NI

Si

Si

Si

Si

7. Strip Cr/Al

8. Strip PR

9. Sputter Cr/Au

10. Plate Au

(a) Dielectric membrane Package lid

Cr/Pt resistor

Rounded tethers Cr/Au contacts

Polysilicon Polysilicon anchor feed-throughs

(b)

AccW Spot magn WD Exp 500 μm 10.0 kV 3.0 70x 9.3 1 EMAL XL-50 FEG SEM

(c)

FIGURE 4-7 Wafer-level packaging approaches using low-temperature processes to form the wafer-level encapsulation, in ref. 58.

in Fig. 4-8b to d and f. The hermetic sealing can be realized by additional sputtered metal on top of the polymer overcoat (see Fig. 4-8e and g). Moreover, a sealed vacuum of around 1 torr or less can be achieved by conducting the metal hermetic sealing step inside a vacuum chamber. There are several advantages to this technology, such as 1. Low-temperature processing. The technology is suitable for packaging of MEMS devices that are sensitive to high temperatures and thermally induced residual stress. 2. Low cost and simple packaging. Both the sacrificial and the overcoat polymers can be made photosensitive. The process does not require cap-to-wafer alignment or a wafer-bonding step. 3. High-yield process. Thermal decomposition of the sacrificial polymer is used instead of etching, which is stictionless, structurally benign, and easily controlled. In summary, recent progress in wafer-level encapsulation technology has proven to be versatile and can be extended to any device that does not need direct physical contact with the ambient

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180

Chapter Four Embedded cavity Insulator

Si beam

(a) Unity

(b) Polymer overcoat (f) (c)

Gold coating Polymer overcoat Vacuum channel

(d) Metal t Ch

tC

1-μm gap (e)

(g)

Beam 50 μm

FIGURE 4-8 Wafer-level packaging approaches using low-temperature encapsulation steps involving polymer and metal coatings, ref. 59.

(e.g., accelerometers, gyroscope sensors, MEMS resonators, RF switches, varactors, and filters). The footprint of MEMS package using this technology is always smaller than that with the bondedcap approach because it does not require extra bonding area in the bonding ring region. Both planar and vertical interconnects can be realized with this technology.

4.4 Wafer-Level Chip Capping and MCM Technologies In addition to wafer-to-wafer bonding–based packaging solutions, a silicon chip with a V-groove cavity can be used as a cap chip to form a sealing cap on top of a MEMS structure on a wafer. This step can be implemented using the common flip-chip bonding technology. Discrete components such as IC chips and capacitors can be assembled on the wafer by the same flip-chip bonding approach. After chip separation, the diced MEMS chip is a carrier chip that hosts the other function chips that require different process technologies to fabricate. An epoxy-based molding step is used to finish the package for such devices. Module-like devices for such applications as RF MEMS, optical MEMS, and wireless sensor nodes can be created with this approach. This approach reflects the concept of a

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g system-in-a-packaging (SiP) solution. A similar approach uses ceramic substrates with cavities to host MEMS chips and other function chips inside the cavities. The standard high-density interconnect (HDI) process consists of embedding bare die into cavities milled into a base substrate and then fabricating a thin-film interconnect structure on top of the components. Each layer in the HDI overlay is constructed by bonding a sheet of dielectric film onto the substrate and forming via holes through a laser ablation process. The Ti/Cu/Ti metallization used for the die interconnects then is created through sputtering and photolithography.60 A device packaged in this manner is called a multiple-chip module (MCM), and it incorporates epoxy-mounted MEMS chips, ICs, surface-mount capacitors, and thick-film resistors. Combining MCM and HDI technology for optical MEMS packaging has been demonstrated.60 Moreover, electrical interconnects can be realized by wire bonds in an MCMpackaged MEMS pressure sensor.61 Another unique technology deploys localized heating to avoid the potential constraints owing to wafer-bonding temperatures because the wafer-bonding temperature must be compatible with all on-chip components, such as microstructures, metallization lines, and integrated circuitry, when the entire wafer is subjected to the same waferbonding temperature in a wafer-to-wafer bonding process. However, for reliable bonding and a hermetically sealed bonding interface, appropriate wafer-bonding technologies such as Au/Sn solder–based eutectic bonding at 280°C, Au/Si eutectic bonding at 365°C, and glassfrit bonding at 400°C normally are used. With this background as motivation, a microresistive heater is integrated into the bonding area either on the substrate or on the capping wafer. After the wafers are brought into contact, the bond is created by locally heating the bonding area via biasing the integrated microheater.62 Based on the reported simulation data,62 a thermal insulating layer (e.g., an SiO2 film) deposited on the thermally conductive substrate (e.g., silicon) can effectively prevent the temperature-sensitive MEMS components from being affected by the high bonding temperatures generated by the microheater during the heating step. With selection of the appropriate material combinations, Au-Si eutectic bonding, Si-glass fusion bonding, and indium solder bonding have been used for demonstrating this localized heating and bonding concept. Either in the wafer-based batch-type process or the chip-based approach, the techniques for preparing the solder pattern on wafers for bonding include stenciling, dip coating, electroplating, and evaporation/sputtering. The technical challenges of this process include uniformity control of the solder pattern, thickness, and composition. B. H. Stark and K. Najafi reported a molding and transferring technology that provides a way to solve these challenges. They reflowed the solder paste in cavities with accurate volume inside a vacuum chamber so as to convert the solder paste to a discrete solder

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Chapter Four ball in each cavity. Then this solder mold was aligned and bonded with the MEMS device wafer in a vacuum. By bonding at 260°C for 2 hours with Bi/Sn solder, a vacuum-packaged cavity that can withstand 1.5 torr can be achieved.63

4. 5 Wafer-Level MEMS Packaging Based on Low-Temperature Solders: Case Study As discussed in Sec. 4.2.6, formation of the bonding interface at low temperature with low-temperature solder (e.g., indium) has attracted a lot of research attention in the creation of hermetically sealed packaging. In order to withstand higher postbonding process temperatures, high-melting-temperature IMCs formed after low-temperaturesolder bonding are preferred. Stable and high-temperature resist bonding interfaces rely on the formation of IMCs of high melting temperature from a low-melting-point (LMP) component such as In or Sn and a high-melting-point (HMP) component such as Au, Ag, or Cu. Looking into the mechanisms of bonding-interface formation using low-temperature solder, two mechanisms are reported. Pure indium is melted at 156.6°C, as seen in the phase diagram in Fig. 4-9a. Reaction between the melted indium (LMP component) and Au, Ag, or Cu (HMP component) is the first mechanism.44–47

0

10

20

Atomic percent indium 30 40 50 60 70

80

90

100

1000 961.93°C 900

Temperature, °C

800 700

670°C

695°C β

L

680°C

600 500 ζ

(Ag)

400 300

187°C

100

α′

205°C 166°C AgIn2

200

γ

0 0 Ag (a)

10

20

30

40

50

60

166.634°C 144°C

70

80

(In)

90

Weight percent indium

FIGURE 4-9 (a) The In-Ag phase diagram. (b) The In-Sn phase diagram.

100 In

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Weight percent tin 0

10

20

30

40

50

60

70

80

90

100

250 95.7 224°C 200

231.9681°C

L

Temperature, °C

156.634°C 14 10 12

150

120°C 44 48.3

100 β

(In)

γ

50 (βSn)

(αSn)

0 0 In

10

20

(b)

30

40

50

60

70

80

90

130°C

100 Sn

Atomic percent tin

FIGURE 4-9 (Continued )

In-Sn eutectic solder bonding without reaction to form the highmelting-point IMCs is the second approach38,39 (Fig. 4-9b). Considering the bonding temperatures and the formation of void-free joints and reliable IMCs, Sn/Au and In/Au systems have been studied extensively.64,65 Section 4.5.1 will report our recent results of investigations into the reliable high-melting-point IMCs in the In/Ag system for wafer-bonding-based MEMS packaging applications. More important, the use of Au would lead to a high cost for wafer bonding. Compared with Single-component solder of Sn or In, the In-Sn alloy is very attractive because of its low eutectic temperature (118°C) and good wettability with various common substrates. Since Cu is used widely in modern IC packaging technology and in 12-in CMOS process technology and is much cheaper than Au, Sec. 4.5.2 will report on the use of In-Sn of eutectic composition for Cu-based metallization.

4.5.1

Case Study: In/Ag System of Noneutectic Composition

In the In-Ag phase diagram (see Fig. 4-9a),66 the eutectic temperature is seen to be 144°C at 96.5 wt% In, whereas the melting temperatures of indium and silver are 156.7 and 961.9°C, respectively. Without using the eutectic composition, the HMP:LMP ratio of the overall

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Chapter Four Cap wafer UBM (Ti/Cu/Ni/Au)~1 μm Ag 4 μm In 2 μm Ag 0.1 μm Ag 0.1 μm In 2 μm Ag 4 μm UBM (Ti/Cu/Ni/Au)~1 μm Substrate wafer

FIGURE 4-10 The intermediate bonding layers on both sides of a bonding pair of wafers, where the schematic drawing shows the thin silver coating of both sides arranged face-to-face.

intermediate bonding layer (IBL) is selected to be high enough that the LMP component is essentially depleted into the HMP layer and reacted into high-melting-temperature IMCs. Figure 4-10 shows the IBL combination on both bonding surfaces of a pair of 8-in wafers. The IBLs include 2-μm In and 4-μm Ag layers, which are evaporated and patterned using the lift-off process on the top of the Si device wafer coated with a 300-Å Ti, 3000-Å Cu, 5000-Å Ni, and 1000-Å Au under-bump metallization (UBM) layer. Owing to the high interdiffusion rate within the layers of the IBL, some IMCs can be formed between the noble metals and indium even at room temperature. We take advantage of this and prepare a thin Ag layer of 1000 Å on top of the In layer to form a thin layer of AgIn2 at the surface. This will prevent oxidation of In layer below when these wafers are prepared and exposed to air after chamber opening. Thus we can avoid flux treatment of the wafer surface before the wafer-bonding step, so we say that it is a fluxless process. The weight percentage of the 2-μm In layer versus the 4-μm Ag layer is 25.4 percent. From the Fig. 4-9a, this 25.4 wt% In composition implies that the homogeneous phase of the bonded interface layer will be the solid solution of α′ phase and Ag. But the actual IMC phases of the bonded interface layer strongly depend on the layer sequence, interdiffusion process, and bonding conditions. In addition to the α′ phase, more IMC phases with In of 22 wt% up to 34 wt% are expected to be seen from our experimental results. Practically, the IMC phases containing In within this weight percentage range are the γ, ζ, and β phases, where these are the stable phases in each specific temperature range from ambient up to 695°C. Again, from Fig. 4-9a, we should notice that the melting point of IMCs increases with silver content, that is, eutectic composition (144°C) < AgIn2 (166°C) < γ (300°C) < ζ (670°C) < β (695°C).

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g Bonding ring of intermediate layer

Comb electrodes Comb electrodes

Torsion bar

Mirror

Mirror plate

Electrical isolation trench

Torsion bar

Comb electrodes

Posts of electrical feed-throughs

(a)

(b)

FIGURE 4-11 (a) Schematic top-view drawing of the micromirror device. (b) SEM photograph of the fabricated micromirror with two sets of vertical comb electrodes and a torsion bar.

In order to explore the feasibility of MEMS packages based on this concept, we developed an integrated process flow for making micromirror wafers and cap wafers. A silicon-on-insulator (SOI) wafer with a device layer of 30 μm, a buried oxide (BOX) layer of 2 μm, and a handle wafer of 690 μm was used for constructing the micromirror. Two steps of the DRIE process are carried out to pattern structures of the comb actuator and mirrors from the front side and to open the backside cavity for releasing the mirrors, respectively. Figure 4-11 shows a schematic drawing and scanning electron microscope (SEM) photograph of the micromirror device, respectively. The center white area represents the reflection mirror. After the backside cavity of the mirror wafer is sealed by bonding with another wafer on the backside, a dry film of photoresist is attached and lithographed on top of the mirror wafer. The In/Ag IBL is prepared by evaporation and lift-off steps. Finally, the whole mirror device is enclosed in an In/Ag IBL ring. The same In/Ag IBL ring is prepared separately on cap wafers containing a glass wafer on a silicon wafer with through-wafer holes. During the bonding process, these wafers are aligned and put into a bonding chamber under 6 mtorr of pressure first. Then the fluxless solder bonding is conducted at 180°C for 40 minutes under 8 kN of applied bonding force. Both the hermetically sealed ring and the electrical interconnects are formed at this bonding step. As shown in Fig. 4-11a, two metal posts on the mirror chip are separated electrically by a silicon trench. These two metal posts are connected electrically via a metal line on the cap-wafer side. The metal posts cross underneath the solder sealing ring with dielectriclayer passivation. Thus the hermetic sealing can be kept inside the sealed cavity. Figure 4-12a shows a top view of the bonded 8-in wafers. Figure 4-12b shows the wafer-bonding-packaged micromirror chip after dicing, whereas Fig. 4-12c shows an x-ray image of the bonded

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Chapter Four

(a)

(c)

(b)

(d)

FIGURE 4-12 (a) The bonded 8-in-diameter stack wafers. (b) Top-view photograph of separated micromirror chip with the reflective mirror at the center. (c) X-ray image of one chip area of cap wafer with bonding ring shown in dark square ring pattern. (d ) Photograph of diced micromirror chip after assembly on a DIP carrier.

wafer is taken from the cap-wafer side. The bright square in the center of micromirror chip in Fig. 4-12b is the reflective micromirror. Then the wafer-bonding-packaged micromirror chip is assembled on a dual in-line package (DIP) carrier for further device function testing, as shown in Fig. 4-12d.

Effect of Postbonding Annealing First, we conducted the postbonding annealing at 130°C for 24 hours for the wafer-bonding-packaged mirror chips after dicing in an N2filled furnace. Properly diced chips were mounted on epoxy resin and subsequently polished. The cross-sectional elemental composition of the bonded interface was characterized by energy dispersive x-ray spectroscopy (EDX). Samples were mounted on epoxy resin and subsequently polished. Figure 4-13 shows the weight percentage of all the components as a function of the depth along the bonded interface. Along the cross section of the bonded interface it is observed

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g 100 90

Weight percentage, %

80 70 Ag In Ti Ni cu

60 50 40 30 20 10 0

0

1

2

3

4

5 6 7 8 9 10 11 12 13 14 15 Interface thickness, μm

FIGURE 4-13 EDX analysis data along a cross section of the bonded interface.

that there is an intermediate layer of a homogeneous composition with a thickness of about 7.5 μm at the center zone. The composition ratio of this intermediate layer is referred to as the Ag9In4 IMC phase mainly, whereas the IMC phase at 7 μm is called the Ag2In phase because both Ag2In and Ag9In4 are the observed phases based on crystal structure analysis by XRD for the samples bonded at 180°C.67 It also should be noticed that there is a thin pure Ag layer of about 1 μm thickness on both sides of the IBL. These two pure Ag layers are referred to the remaining Ag on top of the UBM layers on the two bonding wafers. It also means that the current IBL design leads to IMCs with high remelting temperatures (e.g., γ of 300°C and ζ of 670°C). In other words, the HMP:LMP ratio of the IBL in Fig. 4-10 is an appropriate combination. The bonded interface of Ag9In4 and/or Ag2In IMC phases and pure Ag will guarantee a MEMS package with good high-temperature resistance to postbonding process temperatures (e.g., SMT peak temperature of 285°C).

Effect of Long-Term Room-Temperature Storage It has been reported that Ag2In and AgIn2 are the stable phases at temperatures above and below 100°C in an In-Ag diffusion-couple experiment using thick foils of pure In and Ag.68 When the diffusion couple with a dominant IMC of Ag2In was cooled down and maintained at room temperature for a long time, the Ag atoms diffused from some Ag2In grains into the adjacent pure Ag grains, and In atoms from adjacent pure In grains diffused into the Ag2In grains.

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Chapter Four Some of these Ag2In grains gradually became AgIn2 grains. In a later stage, the grain boundary of these AgIn2 grains expanded continuously by consuming adjacent Ag2In grains (i.e., the grain-growth process). Eventually, AgIn2 became the major IMC phase along the interface of the diffusion couple after room-temperature storage for a long time (e.g., 1 month).68 Because of this, we have kept diced chips in N2-filled containers at room temperature for 80 days (the chips were derived from bonded wafers that were bonded at 180°C for 40 minutes). We investigated the bonded interfaces of these chips via EDX analysis. Figure 4-14a shows a SEM photograph of the bonding-interface cross section denoted along with the phase composition, whereas the Fig. 4-14b shows the measured EDX results, which are plotted versus the position of bonding interface. In addition, the original positions of all layers except the UBM are marked on the left side of Fig. 4-14a. Figure 4-14c and d shows the results from another chip. First, no pure In phase is observed. We also concluded that both Ag2In and AgIn2 coexist in the bonding interface after room-temperature storage of 80 days. Some data points are derived with a weight percentage close to that of Ag9In4, as shown in Fig. 4-14c. For example, the composition at 3.3 μm in Fig. 4-14d is matched with Ag9In4. This observation is in agreement with previous bulk-based diffusion-couple results.68

Effect of Aging When we consider the postdicing chip-assembly process, such a process typically involves baking of the solvent and/or curing at low temperature. In the case of a packaged MEMS devices used in some high-temperature environment, the question becomes, What is the influence of such aging treatment? Thus we have kept diced chips in an N2-filled container at 70°C for 80 hours (where these chips have been stored at room temperature for 80 days and were derived from a bonded wafer that was bonded at 180°C for 40 minutes). The EDX results of a cross section of the bonded interface are shown in Fig. 4-15. We have conducted several line-scan analyses. Two of these line-scan data results are plotted in Fig. 4-15b and c. These data consistently show that the amount of AgIn2 phase is increasing when we compare these samples with long-term room-temperature storage samples and the as-bonded samples. However, the bonding interface does not convert into single IMC AgIn2 phase after this aging at 70°C for 80 hours. Given that the original weight ratio of Ag/In in the present IBL combination is 2.94, we strongly believe that the single IMC phase of AgIn2 will never happen at the bonding interface even after an extremely long period of low-temperature aging. The melting temperature of AgIn2 is 166°C. Thus the existing AgIn2 may be a concern in terms of long-term reliability.

Effect of Additional Postbonding Annealing In the last part of the experiment, we explored the influence of annealing. We have kept diced chips in an N2-filled container at 120°C for 80 hours


Mixture of Ag2In and AgIn2

Ag

Mainly Ag2 In

In Ag In

Mainly AgIn2

Ag

(a) 100 In

Ag

Weight %

80 60 40 20 0

(b)

0

2

4

6

8

12

10

Position along cross section of the bonded interface (μm)

AgIn2 Mixture of AgIn2 and Ag2In Ag9In4 Mixture of AgIn2 and Ag2In

Ag In Ag In

Ag2In/Ag9In4

Ag AgIn2

(c) 100 Ag

In

Weight %

80 60 40 20 0

(d)

0

2

4

6

8

10

12


FIGURE 4-14 Study of the bonded interface after long-term room-temperature storage: (a) SEM photograph of first chip with the identified IMC phases denoted; (b) EDX data derived from the spots shown in part a; (c) SEM photograph of the second chip denoted with the identified IMC phases denoted; (d ) EDX data derived from the spots shown in part c.

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Chapter Four

A

B

Ag AgIn2

AgIn2 In Ag In

Mixture of Ag2In and AgIn2

Ag

Mixture of Ag2In and AgIn2 Ag

(a) 100

Weight %

Ag

A scan

80

In

60 40 20 0

0

2

4

6

8

10

12


(b) 100

B scan Weight %

80 Ag

In

60 40 20 0

(c)

0

2

4

6

8

10

12


FIGURE 4-15 Study of the bonded interface under low-temperature aging: (a) SEM photograph showing the identified IMC phases; (b) EDX data derived from scan-line A in part a; (c) EDX data derived from scan-line B in part a.

(and these chips have been stored at room temperature for 80 days and were derived from a bonded wafer that was bonded at 180°C for 40 minutes). The SEM photograph and line-scan-based EDX results of the cross section of the bonded interface are shown in Fig. 4-16. Interestingly, single-phase IMC of Ag2In has been observed and occupies the major portion of the bonding interface. Compared with the case in Fig. 4-13 (i.e., with existing pure Ag phase on both sides), Fig. 4-16 shows very limited thickness of the remaining phase other than Ag2In.


A

B

Ag In Ag In

Ag2In

Ag

Ag2In

Mixture of Ag, In, Ti, and Ni

Mixture of Ag, In, Ti, and Ni

(a) 100 Ag

A scan

In

Weight %

80 60 40 20 0

0

(b)

2

4

6

8

10

12

Position along cross section of the bonded interface (μm) 100

Weight %

Ag

B scan

80

In

60 40 20 0

(c)

0

2

4

6

8

10

12


FIGURE 4-16 Study of bonded interface under additional annealing effect: (a) SEM photograph with identified IMC phases denoted; (b) EDX data derived from scan-line A shown in part a; (c) EDX data derived from scan-line B in part a.

This result points out that appropriate low-temperature annealing (e.g., at 120°C for 80 hours) can effectively get rid of low-meltingtemperature IMC phases, that is, AgIn2. In particular, the composition at the 2-μm position of the scan in Fig. 4-16a is quite close to Ag9In4. We can imagine that such annealing at 120°C for 80 hours could be well accepted by most packaged MEMS devices. Thus we can apply this annealing step to refine the microstructure of the sealing rings of packaged MEMS devices.

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Chapter Four

Ag wt%

In wt%

100.00

0

100.00

0

70.77

29.23

71.39

28.61

68.07

31.93

69.38

30.62

65.11

34.89

67.6

32.40

69.68

30.32

67.53

32.47

100.00

0

Cu Ti, Ni, and Cu Ag

Ag

In Ag In

Ag2In/Ag9In4

Ag Ag Ni, Ag, and Cu

10 μm

FIGURE 4-17 SEM photograph of the bonded interface after prolonged additional annealing. EDX results are shown on left side, and the suggested IMC phases are shown on right side.

On the other hand, some microcracks are observed at the bonding interface for the samples that underwent an even longer annealing step (i.e., 120 hours at 120°C). Figure 4-17 shows that the dominant phases are Ag2In and Ag9In4, whereas microcracks appear at the bonded interface. Both Ag2In and Ag9In4 are the high-melting-temperature phases and are desired to be the final IMCs at the interface. Moreover, to explore the reason behind such microcracks, we first calculate the density of AgIn2 as 8.43 g/cm3 and the density of Ag2In as 9.78 g/cm3. Then we determined the corresponding volume change of AgIn2 in unit mass to Ag2In in unit mass as an increment of 13.8 percent. The IBL ring structure is confined between two substrates and cannot absorb 13.8 percent volume expansion easily. Thus the residual stress eventually leads to the observed microcracks. A meander trace on the IBL ring and a narrow ring may be potential ways to release the residual stress so as to avoid microcrack generation. High-melting-temperature IMCs of Ag9In4 and Ag2In at the interface are derived after additional annealing at 120°C for 80 hours for samples after long-term room-temperature storage. The melting temperature of IMCs of Ag9In4 and Ag2In is higher than 400°C. This implies that appropriate annealing can get rid of low-melting-temperature IMC phases (e.g., AgIn2). However, prolonged annealing in this situation leads to the generation of microcracks because the IBL ring faces a significant volume change from phase transformation (i.e., from AgIn2 into Ag2In).


4.5.2

Case Study: Eutectic InSn Solder for Cu-Based Metallization

In order to obtain a high yield of good bonded dies via wafer bonding, issues of wafer warpage and topography differences along the bonding rings across a wafer can be overcome by a solder-reflow step when sufficient solder is placed in the bonding rings. However, the LMP solder has to be fully consumed by reacting with HMP metals during the bonding and annealing steps to form reliable and hightemperature-resistant IMC phases at the bonding rings for hermetic sealing applications. This suggests that solder layers of reasonable thickness are an important case-sensitive parameter. We have studied the interface microstructure of Sn/In/Au/Cu metallization after solder deposition in detail. Since the diffusion rates between low-temperature solders and HMP metal substrates such as Cu and Au are very high, a portion of the as-deposited solders on the HMP metal would be consumed before the wafer-bonding step. As shown in Fig. 4-18, it is obvious that extensive interdiffusion between

InSn

AuIn2

Cu6(Sn,In)5

Cu

1 μm

1 μm

FIGURE 4-18 TEM analysis of thin Au0.03/(InSn)3/Au0.03/Cu2 metallization after deposition (thickness in microns). In order to accelerate the interdiffusion between Sn and In and to obtain an In-Sn alloy before bonding, 10 thin alternative In/Sn solder layers with each layer 0.3 µm thick were deposited by E-beam evaporation. The Au layers were deposited to protect the Cu and solder from getting oxidized.

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Chapter Four solder materials (i.e., Sn and In) and Au/Cu layers occurs. On the Cu substrate, Cu6(Sn, In)5 ternary phase was formed owing to interdiffusion. Additionally, Au diffused toward the solder side to from the AuIn phase, which was found inside the Cu6(Sn, In)5 phase. The residual low-temperature SnIn phase is located at the top of the interface, as shown by the dashed line in the figure. Based on preliminary 8-in wafer-bonding results using these SnIn/Au/Cu layers, complete depletion of the low-temperature solders in the as-deposited films would lead to a low yield of good bonded dies.69,70 Owing to the lack of reflow function provided by low-temperature solders, large voids and cracks were found inside the joint, and the hermeticity was quite poor. We screened the bonded dies after dicing by using cross-sectional scanning acoustic microscopy (C-SAM). A die was labeled as a “good die” if there were no detectable voids and/or cracks under C-SAM. The bonding yield was further defined as the percentage of “good dies” to the “bad dies” of a bonded wafer. As listed in Table 4-3, the bonding yield was 44 and 67 percent with a pressure of 3 and 5.5 MPa at 180°C for 20 minutes. Limited improvement was observed when the bonding pressure was increased.70 Therefore, prevention of interdiffusion between LMP and HMP components during the fabrication process and room-temperature storage is the key to obtaining high-yield wafer-to-wafer bonding. As described in Fig. 4-19, a thin buffer layer is introduced in between the Cu substrate and the solder layers such that interdiffusion is inhibited, whereas this thin buffer layer preferentially dissolves into the melted solder quickly at the beginning of soldering reaction (see Fig. 4-19b and c). Then the diffusion between the liquid solder and the Cu starts, and finally, all solder was converted into IMCs (see Fig. 4-19d). Since the buffer layer saves the low-temperature materials for a successful solder-reflow step during bonding, the production yield of wafer bonding is improved significantly. Ni is well known as a barrier layer for Sn-based solder and Cu substrate, and at the same time, it can easily diffuse into Cu-based IMCs.71 Thus a thin Ni buffer layer was chosen and investigated to control diffusion mechanism between In-Sn solder and Cu. For In/Sn/Cu systems after eutectic bonding, we hope that all low-temperature phase can be converted to high-temperature IMCs. According to the ternary-phase diagram of Cu-In-Sn, the calculated thickness ratio of Cu to In-Sn needs to be larger than 0.5 to form Cu6(Sn, In)5 compounds. To protect In-Sn from oxidization, a thin Au layer is deposited on top of the solder layers. Since In will form Au-In IMCs with Au, there will be two kinds of IMCs in the final seal joint: Cu6(Sn, In)5 and Au-In. To get a robust joint, the Au layer should be as thin as possible to reduce the volume of the Au-In IMC. To validate this new combination of materials for wafer bonding, we conducted a wafer-bonding experiment. First, 300-Å-thick SiO2 and 1500-Å-thick SiN were formed on a silicon wafer by thermal oxidation

Cap Wafer (Thickness in Micron) Wafer Pair 1 2

HMP Component Cu2/Au0.03 Cu2/Au0.03

Solder (Sn/In)3∗ (Sn/In)3∗

Bottom Wafer (Thickness in Micron) HMP Component Cu2/Au0.03 Cu2/Au0.03

Bonding Parameter Pressure (MPa)

Temperature (∞C)

Time (min)

Yield (%)

†

3.0

180

20

44

†

5.5

180

20

67

Solder (Sn/In)4

(Sn/In)4

∗Ten layers in turn, each layer was 0.3 μm. † Ten layers in turn, each layer 0.4 μm.

TABLE 4-3 Bonding Experiments of In-Sn Low-Temperature Solders versus Cu Bonding Rings

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Chapter Four • Buffer layer Copper Copper

Copper

Liquid solder

Liquid solder

Copper

Copper

Solder • Au Solder Copper (a)

(b)

(c)

IMCs

(d)

FIGURE 4-19 Schematic drawing of the role of a buffer layer during bonding: (a) before bonding; (b) liquid solder formed at the beginning of wafer bonding; (c) buffer layer dissolved into solder; (d ) high-temperature IMC joint finally formed during bonding.

and the LPCVD process. They acted as a photolithography mask for cavity etching. A cavity with a 6 × 6 mm2 area and 250-μm depth was formed using a KOH wet-etching process inside each bonding ring on both the cap wafer and the bottom wafer. By using photolithography to pattern dry film as a lift-off mask, Ti/Cu/Ni/Au metallization was sputtered on Si/SiO2/SiN substrate as the HMP component for diffusion bonding. The thickness of Ti/Cu/Ni/Au metallization was designed as 0.05, 2, 0.05, and 0.03 μm, respectively. The multilayered bonding-ring structure is shown in Fig. 4-20. The thin Ti layer acting as the adhesive layer is not shown in the figure, and the Ni is the buffer layer. We used the well-known Ti/Cu/Ni/Au under-bump metallization (UBM) process to prepare the HMP component while we increased the thickness of Cu layer up to 2 μm. Thus we called these HMP rings UBM rings. Then the solder layers and Au protection layer were deposited in turn in an E-beam evaporation chamber. After another dry-film-strip step, 300-μm-wide square bonding rings 11 mm long were finally fabricated on a wafer with

Au In Sn Ni Cu

FIGURE 4-20 Schematic depiction of the InSn solder versus Ti/Cu/Ni/Au UBM metallization.

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g cavities. After deposition and dry-film stripping, O2 plasma descum was conducted before the bonding process to remove the oxide layer and organic contaminants to produce a clean surface. In the waferbonding step, two wafers with cavities enclosed by bonding rings were aligned and brought into the vacuum chamber of a commercial wafer bonder. When the wafers were heated up to 180°C (i.e., bonding temperature), a bonding pressure of 5.5 MPa was applied to press the bonding-pair wafers into tight contact for 20 minutes. After the bonding step, the wafer was diced into chips of 13 × 13 mm2 in which each chip has a vacuum cavity sealed inside the bonded structure (Fig. 4-21). Scanning acoustic microscopy (SAM) was deployed for nondestructive study of the bonding interface. There were no detectable voids in any single seal ring. This meant that a 100 percent yield after bonding was achieved by this bonding method. A typical C-SAM graphs of dies is shown in Fig. 4-22.

FIGURE 4-21 Photo of a successfully bonded wafer with 100 percent yield.

FIGURE 4-22 SAM graph of bonded devices using Ti/Cu/Ni/Au UBM. The bonding temperature was 180°C.

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Chapter Four Each bonding ring was a uniform gray color, indicating the bonded joints have intimate contact. The hermeticity of the ring seals for pattered dies was evaluated by helium leak-rate testing (MIL-STD-883). A shear test was done with a shear tester (BT4000 Dage) using a speed of 50 μm/s. Reliability tests of the bonded devices was studied in detail. A pressure-cooker test was conducted at 121°C and 2 atm for 300 hours. High-humidity storage was done at 85°C and 85 percent relative humidity (RH) for 1000 hours. A high-temperature storage test at 125°C and a temperature cycling test (–45 to 125°C) for up to 1000 hours also were performed. For each item, 21 chips were tested. After the tests, these chips were examined by SAM and helium leak-rate and shear tests again.

Reliability Study The microstructure of the bonded interface is shown in Fig. 4-23 in the case of 180°C bonding. In the center region of the bonded interface, thick residual Cu and a thin IMC layer were found, as shown in the figure. Two kinds of IMCs were detected by EDX. One composition (atomic percent) is Cu:Ni:In:Sn = 56.17:4.63:12.37:26.84, which also corresponds to the η phase, that is, (Cu, Ni)6(Sn, In)5. Another is AuIn2 phases with white-particle morphology. According to the present materials design, the thickness of the seal joint should be around 10 μm. However, the actual thickness value achieved was about 7 μm. Under the present bonding temperature, solder materials melt fast and have good flowability. When bonding pressure was applied, a portion of the liquid alloy squeezed out. As shown in Fig. 4-23b, the length of the squeezed solder was about 80 μm. In order to know the kinetics of the bonding process involving the Ni buffer layer, TEM/EDX analysis was performed on the seal joint. The results are shown in Fig. 4-24 and Table 4-4. It was found that the

Au(In, Sn)2 Cu

Cu

Squeezed solder (Cu, Ni)6(Sn, In)5

(a)

(b)

FIGURE 4-23 Interfacial microstructure of the joint bonding at 180°C: (a) center region of the joint; (b) bonded joint of two wafers.


0.5 μm

FIGURE 4-24 TEM/EDX analysis of the seal-ring joint after bonding. In order to find the trace of the Ni buffer layer, the analyzing position is near the residual Cu.

Element (at%) Position

Cu

1

88.1

2

47.4

3

32.6

8

4

36.5

11.7

5

5.7

6

11.6

7

42.6

TABLE 4-4

Ni 4.8

6

Sn

In

7.1

4.8

35.4

17.2

43.2

16.2

Au

45

6.8

6

55.1

33.3

13.2

47.6

27.7

41.8

9.6

Compositions of Selected Positions of TEM/EDX

Analysis

phase adjacent to the Cu substrate was Cu6(Sn, In)5, and next was (Cu,Ni)6(Sn, In)5. Island shape Au(In, Sn)2 phases embedded in the (Cu, Ni)6(Sn, In)5 phase also were identified. These results confirmed that the Ni buffer layer had been dissolved into a Cu6(Sn, In)5 IMC and formed a (Cu, Ni)6(Sn, In)5 phase in some regions. The content of Ni in this quaternary phase can reach 11.7 at%. The bonding process involving the buffer layer can be explained as follows: First, owing to the slow reaction between solder and Ni at room temperature, a major portion of the solder remains on top of the Ni

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Chapter Four buffer layer. When wafers are heated up to the bonding temperature, the solder melted and started to react with the thin Ni buffer layer. The Ni dissolved into the solder as Ni3Sn4 or NiInSn ternary phase72,73 according to studies of the interfacial reactions between liquid InSn solder and Ni. Since the Ni buffer layer is very thin, after a short time, InSn solder started to react with Cu to form Cu6(Sn, In)5 compounds. Since Ni has great solubility in the Cu6(Sn, In)5 compounds, a chemical potential gradient was generated, which led to dissolution of the Ni-containing compounds. Finally, all Ni atoms went into Cu6(Sn, In)5 solution to form the (Cu, Ni)6(Sn, In)5 phase. The testing results showed that the leak rates of all the samples bonded at 180°C were less than 5 × 10–8 (atm · cc)/s, which indicated that the dies obtained acceptable hermeticity based on the criteria of MIL-STD-883. The average shear strength of the joints was 32.13 MPa, which meant that robust bonding strength was achieved for these patterned dies. These results indicate that the Ni buffer layer plays an important role in achieving high-yield wafer-level hermetic bonding. The results of the reliability tests show that ratios of dies with a leak rate of less than 5 × 10–8 (atm · cc)/s after the pressure-cooker test, high-humidity storage, high-temperature storage, and temperature cycling were 71.4, 90.5, 76.2, and 81 percent, respectively. Meanwhile, the tested chips still maintain good mechanical properties. The shear test after pressure cooker test, high humidity storage, high temperature storage and temperature cycling were 27.08, 15.37, 12.32, 16.71 MPa, respectively. As shown in Fig. 4-25, the interfacial microstructures were analyzed after the reliability tests as well. The results show that embedded AuIn compounds congregated and that the size of the accumulation became larger at the interface. With further EDX analysis, the compositions of the bonding interface do not show any detectable change. Such results are reasonable because the temperatures for the reliability tests was not high enough to introduce phase changes at the IMC joints. However, based on the shear-test results, we believe that the adhesion between different IMCs decreased after reliability testing. Bonded chips with poor hermeticity were analyzed to know the failure mechanism of the bonding interface after reliability testing. As shown in Fig. 4-26, visible cracks throughout the bonding interface were found in these samples with poor leak-rate test results. It is clear that the crack expanded along the interface between AuInSn compounds and CuSnIn compounds. Stress generated at the interface between different IMCs when bonded chips were tested under thermal cycling and the pressure-cooker test. This is the reason why after these two tests, the leak-rate test revealed a relative poor hermeticity results compared with other tests. This implies that the adhesion between the two IMC phases is the key to determining the reliability of the bonded chips. Two ways are proposed to improve reliability further. The first is to reduce the amount of AuInSn compound


(a)

(b)

(c)

(d)

FIGURE 4-25 Interfacial microstructure of the seal joints of good dies after reliability tests: (a) high-temperature storage; (b) temperature cycling; (c) high-humidity storage; (d ) pressure-cooker test.

(a)

(b)

FIGURE 4-26 Cracks along the interface after reliability tests: (a) temperature cycling; (b) pressure-cooker test.

by depositing a much thinner Au protection layer for fluxless bonding. The second approach is to increase the amount of low-temperature solder. As a result, the potential to form a continuous Au-rich IMC phase at the interface is reduced significantly. In this way, the reliability of the bonded interface can be improved.

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Chapter Four Low-cost and high-yield wafer-to-wafer bonding using In/Sn solder and a Cu/Ni/Au metallization system was investigated, and the process produced successful bonding at 180°C. Various tests were conducted to evaluate the reliability of the bonded devices. Cracks formed at the interface of the bonded chips after reliability testing are the main cause of deterioration of the bonded interface.

4.6

Summary and Future Outlook After a decade of research and commercialization, wafer-level packaging has proven to be a leading solution for MEMS packaging. In addition to the package size, cost, and performance advantages, wafer-level MEMS packaging provides a way for enabling a SiP-type of ultracompact and thin hybrid package that integrates MEMS, optoelectronics, signal-processing circuits, and even energy sources. In addition to the wafer-bonding type of MEMS packaging based on a BCB intermediate layer, a low-cost, near-hermetic package using a liquid-crystal polymer (LCP) substrate, cap, and sealing ring has been deployed widely for packaging CMOS image sensors nowadays. LCP is a thermoplastic polymer with barrier properties that are an order of magnitude greater than those of epoxy plastic materials. The permeability of LCP to water vapor and oxygen is close to that of glass. Without using wafers containing etched cavities, a thick LCP ring can be used as the necessary spacing layer between two bonded wafers that provides enough room for the motion of MEMS moving parts. A sealed LCP cavity can pass helium leak-rate testing (i.e., MILSTD-883E). However, this sort of testing may not be appropriate for polymer-type packages because it measures only fine and gross leaks without considering permeability and outgassing. Although LCPand BCB-based MEMS packages cannot be considered to be hermetic packages, they could be a cost-effective MEMS packaging solutions for consumer electronics applications. Some of MEMS devices require a controlled atmosphere in the cavity or even a vacuum-packaged cavity. Low-temperature-solderbased wafer bonding can be an effective and low-cost approach to enabling vacuum-packaged MEMS devices. The eutectic InSn solder versus Cu/Ni/Au UBM is characterized as a promising bonding-ring material combination. Wafer-level packaging of vacuum cavities brings the cost advantage of permitting simultaneous sealing of an entire wafer of cavities in a vacuum. This eliminates the manufacturing inefficiencies and costs involved in individual “pump down and pinch off” for archaic conventional metal or ceramic vacuum packages. Wafer-level packaging based on direct bonding, metal-intermediatelayer bonding, and metal-sealed encapsulation may provide the lowcost MEMS vacuum packaging solutions of the future. However, if we want to maintain the high vacuum over long lifetimes, the materials

A d v a n c e d M E M S Wa f e r- L e v e l P a c k a g i n g and seals used must be leak-free, impermeable, and not sources of significant outgassing. The high surface-to-volume ratio of these microcavities makes the maintenance of packaged vacuum even more difficult in wafer-level MEMS packaging. These surfaces are reservoirs of adsorbed gases such as oxygen, carbon dioxide, and reactive gases. A plated metal surface is considered a major source of dissolved hydrogen, which is a potential device killer in some cases. Integrating getter film into the packaged cavities may be a good solution to overcome these concerns for enabling wafer-level MEMS vacuum packaging.33,74 On the other hand, the conventional standard of hermeticity based on MIL-STD-883E is invalid for cavity volumes of less than 1000 nl3. Currently, people measure wafer-level vacuumpackaged MEMS device characteristics and calibrate the measured data with data derived for devices tested in a well-controlled vacuum chamber with a known degree of vacuum. A MEMS resonator can allow us to discriminate the degree of vacuum from 0.1 torr to several tens of torrs.75 A Pirani sensor or a resistive type of thermal sensor with a suspended membrane structure on a V-groove may allow us to measure the degree of vacuum from ambient down to 0.1 torr,76 whereas a degree of vacuum of 4 mtorr can be detected using a bolometer or a resistive type of thermal sensor on the surfacemicromachined membrane with tight gap between the suspended membrane and substrate.77 It is also reported that Pirani sensors using proper readout circuits to counter the self-heating effect can allow us to measure the degree of vacuum down to 10–7 torr.78 However, more research effort is needed to establish the external wafer-level nondestructive characterization approaches for MEMS wafer-level vacuum packaging. Thus we may increase the testing speed and reduce cost.

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Optical MEMS Packaging: Communications 5.1 Introduction Optical microelectromechanical systems (MEMS) combine miniature optical components with elastic suspended springs and microactuators to perform unique and sophisticated functions such as beam steering, attenuation, and filtering in optical communications applications. This chapter discusses the development trends and state-ofthe-art technologies of optical switches and variable optical attenuators (VOAs) over the past few years. The tradeoffs among design, manufacturability, and reliability are explored and discussed in several cases. The technology evolution of optical MEMS in communications applications is scanned and explained in terms of optical configurations, actuator features, and packaging-technology progress. Although an electrostatic actuation mechanism is the mainstream approach in optical MEMS devices, other mechanisms show promising features in various application-specific situations. Both proof-ofconcept devices and commercialized products are introduced and discussed in this chapter. Quite a few reliability results prove that MEMS technology is a suitable solution in optical communications. Based on the indispensable features provided by optical MEMS devices, such as handling optical signals with protocol transparency, and data-rate and wavelength independence, optical MEMS technology finds a unique position in the telecommunications industry. Since the late 1990s, an optimistic telecommunications market forecast has stimulated enormous investment on optical MEMS technology because such technology has been recognized as indispensable in connecting other existing technologies to form an all-optical

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Chapter Five communications network. Telecommunication applications have become the new “killer applications” of optical MEMS.1 Many crucial MEMS-based components for telecommunications applications have been demonstrated and commercialized, such as optical switches, VOAs, tunable filters, tunable lasers, and reconfigurable optical add/drop multiplexers (ROADM). Comprehensive review articles can be found in refs. 2 through 6, whereas topical reviews on optical switches,7–9 VOAs,10 and tunable lasers11,12 also have been published. The requirements for optical communications components vary with the optical networks in which they are deployed. Optical network topologies typically are categorized as three major networks: long haul, metropolitan area, and access. Long-haul networks are the conventional long-distance point-to-point transport networks that can send signals across 1000 km before the need for regeneration. Metropolitan-area networks (MANs) refer to metropolitan-area corering networks that typically are hundreds of kilometers in length and do not use amplification. Access networks are the metropolitan-area access-ring networks, with stretches of a few to tens of kilometers (including the so-called last mile). Since the distance such a network covers is short, amplification is not necessary. Since the widespread deployment of wavelength-division-multiplexing (WDM)–based long-haul optical networks in late 1990s, WDM transmission systems have been evolving from point-to-point transmission to a nextgeneration reconfigurable add/drop mesh structure. In terms of signal-to-noise ratio, power equalization is extremely important in such a system. In addition, power equalization should be performed automatically to reduce operational expenditures. On the other hand, such a technology trend drives MANs to start evolving so as to have a transparent architecture. Regarding multiple service content in MANs, the ability to handle multiple protocols at varying speeds becomes critical to operational efficiency. Thus components with features that handle optical signals with protocol transparency and data-rate and wavelength independence are crucial to the practical implementation of this architecture. To enable an advanced optical network, optical MEMS technology provides free-space propagation of bounded beams among components such as mirrors, gratings, and lenses. These optical MEMS devices offer physical features such as transparency (bit-rate- and protocol-independent), tunability, scalability, low electrical operation power consumption, and small form factor. This chapter reviews the major micromechanisms for actuation. Representative optical MEMS devices are introduced thereafter. Consideration of optical MEMS packaging from the point of view of the optical communications and/or fiber telecommunications industry will occur at the end of this chapter.

Optical MEMS Packaging: Communications

5.2 Actuation Mechanisms and Integrated Micromachining Processes Recent developments in the rapidly emerging discipline of MEMS show special promise in sensors, actuators, and microoptical systems. In fact, optics is an ideal application domain for MEMS technology. Photons have no mass and are much easier to actuate than other micro-scale objects. In conjunction with properly designed mirrors, lenses, and gratings, various microoptical systems driven by microactuators can provide unique functions in light manipulation, such as reflection, beam steering, filtering, focusing, collimating, and diffracting. Although the force and displacement generated by the mciroactuators are normally quite small [e.g., displacement is on the order of a wavelength (a few microns)], these features make microoptical systems a promising application area for MEMS technology. The structures we discuss in the optical MEMS area range in dimension from a few microns to millimeters and are mostly fabricated on silicon substrates by micromachining techniques that came from standard semiconductor processing techniques. In other words, lithographic batch fabrication of MEMS devices, made possible and driven by the infrastructure of the integrated circuits (ICs) industry, is a relatively inexpensive fabrication method. As a result, MEMS devices offer the same potential benefits as advanced ICs in terms of low-cost, high-volume, and automated production. Another benefit that MEMS technology contributes to microoptical systems is assembly and packaging. The forms of light propagation in microoptical systems are categorized as free space and guided wave. Both schemes need to consider the light coupling loss and alignment accuracy between two elements in a microoptical system. In the case of optical MEMS-based approaches, the light path among various elements built on a silicon substrate can be defined precisely by the lithographic batch-fabrication technology. Alignment accuracy is guaranteed by the photolithographic resolution. Accuracy from the submicron level to 2 μm is normally achievable for lithographic processes using a stepper mask, whereas contact-mask lithographic processes provide an accuracy of 2 to 5 μm. On-chip active alignment with the aid of microactuators for position adjustment can give optical alignment accuracy as precise as 0.1 μm or less. In this way, an entire optical system can be integrated and realized monolithically on a single chip. Therefore, single-chip microoptical systems can be built by integrating multiple free-space microoptics that are cascaded along the optical axes on the same substrate.13 On the other hand, packaging of optical MEMS devices needs to comply with industrial reliability standards. Unlike the common solid-state lasers and discrete microoptics, the reliability issue of micromechanical movable elements involved in an optical MEMS system typically is imposed on the whole system as a

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Chapter Five reliability challenge. Reliability-proven designs have been reported in such applications as optical switches and VOAs. In principle, silicon is a qualified and appropriate material for realization of microoptics and microactuators in the optical MEMS area. With proper design, the reliability of optical MEMS is a manageable engineering task. First of all, the excellent mechanical properties of single-crystal silicon allow fabrication of fatigue-free devices. Since single-crystal silicon has no dislocations, it has virtually no fatigue and is a perfectly elastic material—a property that is extremely desirable for precision mechanics applications. Second, the silicon surface, when treated properly, can provide an optical surface of extremely high quality (i.e., flat and scatter-free), and an additional Au thin-film coating layer on top of silicon mirror surface enables perfect reflection on this silicon mirror. Third, the electrical properties of silicon allow for the integration of sensors and photodetectors with extraordinarily high precision, which is often required in optical networks for feedback-control purposes. In next few paragraphs we introduce the concepts of major actuation micromechaisms first. With the background knowledge of micromachining technology that we learned in Chapter 4, complicated and integrated micromachining processes used in optical MEMS applications will be discussed.

5.2.1 Electrostatic Actuation Let’s consider a parallel-plate capacitor with a fixed gap distance g between two plates with overlap area A. The energy stored in this capacitor subject to an applied direct-current (dc) bias V is given as W=

ε ε AV 2 1 CV 2 = 0 r 2 2g

(5-1)

and the attractive force generated between the two plates is

F=

dW ε 0ε r AV 2 = dg 2 g2

(5-2)

where the ε0 is the vacuum permittivity and εr is the relative permittivity or dielectric constant. The actual permittivity ε in a homogeneous material then is calculated by multiplying the relative permittivity εr by vacuum permittivity ε0. In the micromechanisms for electrostatic actuation, a movable electrode connected to suspended mechanical springs and a fixed electrode anchored onto substrate is the typical configuration. When a voltage is applied to the electrodes to form a capacitor, the electrostatic attractive force drives the movable electrode to the stationary electrode, and the capacitance between the two electrodes is increased accordingly. The spring suspending the movable electrode is deformed. Thus the displacement Δx of the movable electrode is determined by the force balance between the spring’s restoring force and the electrostatic force.

Optical MEMS Packaging: Communications There are two major types of electrodes in electrostatic actuators: parallel plate and interdigitated comb. To achieve long displacement, a laterally driven electrostatic comb actuator made of polycrystalline silicon was proposed by Tang and colleagues in 1989.14 The movablecomb electrode was suspended with folded-beam springs (each 100 μm long) and anchored to the substrate. Displacement of the movable comb of 5 to 20 μm was reported with a typical drive voltage ranging from 10 to 30 V. The geometry in such a surface-micromachined polycrystalline silicon substrate leads to the fact that the electrostatic attractive force between two comb electrodes is mainly due to the fringing fields rather than the parallel-plate fields because the thickness of the fingers is small compared with their lengths and widths. The maximum static displacement of a comb actuator is commonly smaller than the theoretical value, which is limited by the sidepulling effect of the comb fingers in the conventional design of comb actuators.15–17 Tiny deviations in comb finger thickness and gap width will lead to an unbalanced force between both sides of finger electrodes, and such a deviation is easily caused by the microfabrication process.18 The unbalanced force between both sides of a finger electrode is the major contributing factor to the side-instability effect. How to design and manufacture a comb-drive actuator that is more robust to process-induced deviation is key to successful industrial applications. As shown in Fig. 5-1a, looking into electrostatic actuators from a three-dimensional (3D) point of view, we normally design a micromechanism with a spring constant kx in the direction of movement (i.e., along the x axis) that is very small, and the spring constants ky and kz along the y and z axes (i.e., in a direction perpendicular to the moving axis) are much higher than kx. In doing so, the maximum static displacement Δx of the movable electrode in the direction of the x axis is derived from F = kxΔx, where the F is the spring restoring

Electrode Electrode finger of finger of fixed movable comb comb Central axis

g

loverlap + – V (a)

y ky

Thin folded spring x

kx Comb actuator

Reflective shutter

(b)

FIGURE 5-1 (a) Conceptual drawing of a small portion of a comb actuator with a pair of comb fingers, and the whole comb actuator contains a number of cascaded comb pairs. (b) Scanning electron microscope (SEM) photograph of an electrostatic comb actuator–driven 2 × 2 optical switch.

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Chapter Five force at this equilibrium position and equals the electrostatic attractive force. Thus the static actuated displacement Δx is given by

Δx =

Nε te 2 V kx g

(5-3)

where N = number of comb-electrode fingers te = comb-electrode thickness ε = actual permittivity of air g = gap between the comb fingers V = actuation voltage Figure 5-1b shows a 2 × 2 optical switch made from a silicon device layer on a silicon-on-insulator (SOI) substrate. By leveraging the high aspect ratio and fine gap of the comb fingers, a large output force from the comb actuator is achievable. On the other hand, Akiyama and colleagues20 reported a creative electrostatic actuator called a scratch-drive actuator (SDA). The SDA consists of a suspended polysilicon plate with a vertical bushing, as shown in Fig. 5-2a. This free-standing plate is linked with the major

Suspended poly-Si plate

Vertical bushing

Supporting beams

(a)

(b)

(c)

(d)

FIGURE 5-2 (a) SEM photograph of an SDA element. (b) SEM photograph of a rotary structure driven by an SDA array. (c) SEM photograph of an assembled polysilicon mirror driven by an SDA array. (d) SEM photograph of an assembled polysilicon shutter driven by an SDA array for a 2 × 2 optical cross-bar switch application.

Optical MEMS Packaging: Communications objects of a micromechanism via supporting beams that are connected at the junction edge of the main plate and the vertical bushing. When a voltage is applied between the free-standing polysilicon plate and the buried electrode layer on the substrate, the plate buckles down, causing the bushing to “scratch” along the insulator, thus resulting in a small forward movement. This means that a step of scratch enables the bushing to move from original contact point P1 to the new contact point P2 between the bushing and the substrate. The free-standing polysilicon plate returns to its original shape after the actuation voltage is removed. The deformed plate will bounce back to the original shape while the bushing maintains contact with the substrate at P2. When a pulse-wave-based actuation voltage is applied, the “scratch” step is repeated to form stepwise linear motion.19,20 An array of SDA devices has been used to drive various microstructures and optical MEMS devices (see Fig. 5-2). The fundamental design tradeoff in optical MEMS devices using electrostatic actuators is the choice between a suitable process technology and the actuation mechanism. Parallel-plate and comb actuators are the available designs for use in bulk micromachined optical MEMS devices, whereas polysilicon-based comb actuators and SDAs are often used in surface-micromachined structures. Such surface micromachining technology will be discussed in Sec. 5.2.5. Briefly, parallel-plate actuation can provide very high forces (~100 μN) with small displacements (~5 μm), but the force is highly nonlinear with instability within the displacement range. Interdigitated comb actuation provides a moderate level of force (~10 μN) with large displacements (~30 μm).

5.2.2 Thermal Actuation Thermal actuation uses the thermal expansion of materials to achieve mechanical actuation. The thermal expansion of a solid material is characterized by the coefficient of thermal expansion (CTE) αT. The CTE of a material generally is a function of temperature. With a small temperature change ΔT, the introduced mechanical strain is defined as the product αT ΔT. The CTE for a material has units of strain per change in temperature (1/°C). One of the basic micromechanisms for thermal actuation is a thermal bimorph, which consists of a cantilever with two or more layers.21 Relying on the difference in linear expansion coefficients between two materials, one layer expands as a result of ΔT by a different amount than the other, creating thermal stress at the interface between these two layers and leading to bending of the cantilever. The ΔT can be created by heating up the cantilever when a biasing current flows through an embedded resistor in the cantilever (i.e., Joule heating effect). Out-of-plane displacement is generated at the bent cantilever because of the volume-expansion difference in the two layers owing to ΔT. The thermal-bimorph actuator is used widely

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Chapter Five in both bulk and surface-micromachined devices in the optical MEMS field. Nevertheless, some applications demand in-plane displacement. By using a single material, a U-shaped thermal actuator consists of two arms of uneven widths suspended above the substrate with two anchor points at the ends of the two arms, as shown in Fig. 5-3.22,23 A U-shaped thermal actuator is made of metallic beams or conductive silicon beams. When an electric current is applied from one anchor to the other, the arm with the larger electrical resistance and resulting power generation achieves a higher temperature and a larger volume expansion (i.e., the so-called hot arm). The other arm is relatively cold and is referred to as the cold arm. The arm with the larger electrical resistance is the longer arm or the arm with the smaller cross-sectional area. These two arms are connected at one end opposite the anchors. The U-shaped thermal actuator will deflect laterally toward the cold arm owing to the asymmetric thermal expansion when the U-shaped thermal actuator is under a dc bias. Deflections of up to 16 μm and a force of 4.4 μN have been obtained for polysilicon

Anchor Hot arm

Dimple

Cold arm Direction of displacement (a)

Flexure

(c)

(b)

FIGURE 5-3 (a) Schematic drawing of a U-shaped thermal actuator. (b) SEM photograph of a suspended polysilicon U-shaped thermal actuator. (c) Closeup view of a U-shaped thermal actuator.

Optical MEMS Packaging: Communications thermal actuators at 10-mW driving power. The area (~20 × 200 μm2) is also very compact compared with comb-drive actuators.22 The polysilicon thermal actuator has been demonstrated to drive stepper motors and linear motors, as well as to assemble the 3D microstructures for optical switches and VOAs.24,25 Field and colleagues26 reported U-shaped thermal actuators with 25 to 50 μm thick electroplated nickel beam for moving optical fibers with static displacements as large as 150 μm for a 1 × 2 optical switch in 1997. The bent-beam thermal actuator consists of an arched beam extending between a pair of anchors, as shown in Fig. 5-4. This arched beam is a symmetric structure consisting of a long, thin beam canted at a small angle θ from the center line. Thus the arched beam is also called a V-shaped beam or V-beam. This V-beam structure was proposed as a strain sensor in the beginning27,28 but was proven to be a good thermal actuator later on.29,30 This arched beam will expand so as to further arch if electric current flows through the arched beams (see Fig. 5-4b). It is a mechanical amplifier of the small deflection produced by thermal expansion. V-beam thermal actuators may be cascaded by running in parallel as well as by using additional bent-beam structures for mechanical amplification.31,32 V-beam thermal actuators also can include a center post that connects the plurality of arched beams and serves to push against the work piece.33,34 V-beam actuators are promising in applications that require large stroke and high force outputs.

Arched direction θ

Suspended Canted beam Anchors

(a)

V Displacement direction

(b)

FIGURE 5-4 (a) Schematic drawings of V-shaped beam actuator of high-aspectratio structure. (b) V-shaped beam deformed in the arched direction owing to a dc bias.

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Chapter Five V-beam actuators are known to provide one-directional static displacement generated from a net volume expansion owing to the thermal-expansion difference distributed over the whole actuator structure. This net volume expansion always points in one direction. In applications such as bistable optical switches, planar micropositioners, and relays, the two-way motion and bidirectional static displacement are desired actuation mechanisms. By linking a set of two separately located V-beam actuators with opposite actuation directions in an H-shape,35 H-beam thermal actuators are reported to have bidirectional static displacement as high as 50 μm, as shown in Fig. 5-5. The design of thermal actuators is a multiphysics problem36 requiring thermal, structural, and electrical analyses. The heat transfer involved in a thermal analysis includes conduction and convection. Radiation heat transfer in a thermal actuator can be ignored because it is generally not significant. The upper practical limit for temperature in the polysilicon and single-crystal-silicon-based thermal actuator is approximately 600 and 800°C, above which material property changes, such as localized plastic yielding and material grain growth, become an issue. The alternating-current (ac) operation of thermal actuators generally is limited to a frequency response of less than 1000 Hz because of the time constants associated with heat transfer. For example, thermally driven scanning mirrors demonstrate scanning frequency in the range of 100 to 600 Hz.37 However, a

Anchor

Tilted angle

Width

Anchor

Tilted angle Actuator beam length (a)

(b)

(c)

(d)

Actuator beam length

FIGURE 5-5 Two types of single-crystal-silicon H-beam actuators are designed and fabricated by the micromachining process. (a) and (c) are a schematic drawing and SEM photograph of an H-beam actuator with outward arched shape, whereas (b) and (d) are a schematic drawing and SEM photograph of an H-beam actuator with inwardly arched shape, respectively.

Optical MEMS Packaging: Communications CMOS-MEMS-based scanning mirror operating at 2.6 kHz has been developed successfully because the thermal time response of the thermal actuator is less than 0.4 ms.38 This shows that a thermal actuator that operates at a few kilohertz is possible to achieve.

5.2.3 Magnetic Actuation A Lorentz force is generated when a current-carrying element is placed within a magnetic field. The Lorentz force FL is given by FL = iL × B

(5-4)

where the FL, i, and B refer to length of conductor, electric current, and a magnetic field, respectively. In addition, FL, i, and B are at right angles according to the right-hand rule implied by the cross-product. Lorentz force occurs in a direction perpendicular to the current and magnetic field. The magnitude of the force is proportional to the current i, length of the conductor L, and the magnetic field B. Although Lorentz-force actuation may be applied to MEMS devices in a number of ways, the prevailing mechanism is to have the metal coils integrated on a movable mirror and actuated by an ac current at resonance when this mirror is placed near a permanent magnet.39 A permanent magnet easily generates a magnetic induction of 0.5 to 1 T, whereas the magnetic induction of a simple planar electromagnetic coil with about 10 windings is in the millitesla range. Another approach is to integrate a permanent magnet (hard ferromagnet) or a soft ferromagnet (Permalloy) layer on a movable mirror, and the Lorentz force is generated by the interaction between the magnetic layer and the surrounding ac magnetic field owing to an external solenoid. Judy and colleagues40 demonstrated a device with an electroplated 7-μm-thick Permalloy layer on the free end of a polysilicon cantilever. Deflections at the cantilever end exceeding 90 degrees were achieved by applying an external magnetic field. The availability of permanent magnetic materials that are compatible with MEMS processing is limited and results in necessary process-development efforts. Thus it is common for the magnetic field to be generated externally, whereas the discrete and movable magnetic actuators often consist of metal coils.

5.2.4 Piezoelectric Actuation An applied dc voltage across the electrodes of a piezoelectric material will result in a net strain that is proportional to the magnitude of the voltage (strictly electric field), whereas a free-standing piezoelectric structure (e.g., a cantilever) will be excited at its mechanical resonant frequency under ac voltage of the same frequency. The piezoelectricity is attributed to charge asymmetry within the primitive unit cell, resulting in the formation of a net electric dipole. Adding up these individual dipoles over the entire crystal gives a net polarization and

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Chapter Five an effective electric field within the material. The popular piezoelectric materials include quartz, lithium niobate, lithium tantalite, AlN, ZnO, and lead zirconate titanate (PZT), whereas the most well-known polymer-based piezoelectric material is polyvinylidene fluoride (PVDF), which is a thermoplastic material. The poled PVDF exhibits piezoelectricity several times greater than quartz. Thin-film-based MEMS actuators using ZnO thin films for feedback control of a ZnOcoated cantilever have been applied to atomic force microscope applications.41,42 ZnO thin film can be prepared by sputtering relatively easily. Among the aforementioned piezoelectric materials, PZT is the most promising because it produces the highest piezoelectric response. PZT is a lead-zirconate-titanate ferroelectric ceramic. In the phase diagram of PZT, Pb(ZrxTi1–x)O3, there is a morphotropic phase boundary (MPB) that separates a rhomboidally distorted ferroelectric region at low Zr concentrations and a tetragonal region at high Ti concentrations. Pb(ZrxTi1–x)O3 exhibits outstanding piezoelectric characteristics at the MPB, where the x refers to 0.52 or 0.53. PZT of composition around this MPB shows the highest piezoelectric effect. The piezoelectric effect is described in terms of piezoelectric charge coefficients dij, which relate the static voltage or electric field in the i direction to displacement or applied force in the j direction. When we consider a PZT thin-film actuator prepared on top of an Si cantilever, we define axes 1 and 3 as longitudinal and normal directions regarding the cantilever. The piezoelectric charge coefficients are given as d33 for both voltage and force along the vertical axis (axis 3) and d31 for voltage along the vertical axis but force in the longitudinal direction (axis 1). The units of the piezoelectric charge coefficients are coulombs per newton (C/N) or meters per volt (m/V), depending on whether the electrical parameter of interest is voltage or charge. The induced strain along the vertical axis is actually very small when a voltage is applied along the vertical axis. The introduced stress, though, will bend the free end of the cantilever significantly. This displacement Δ at cantilever end is in proportion to the length of cantilever. Obviously, a piezoelectric thin-film-coated silicon cantilever is an efficient piezoelectric actuator for displacement amplification. The displacement Δ is given by43,44

Δ=

3 AB d L2V K 31

(

Si PZT PZT Si A = s11 s11 s11 tSi + s11 tPZT

B=

(5-5)

)

(5-6)

tSi (tSi + tPZT ) PZT Si s11 tSi + s11 tPZT

( )

(5-7)

2

Si Si PZT PZT K = s11 (hPZT )4 + 4s11 s11 tSi (tPZT )3 + 6s1Si1s11 (tSi )2 (tPZT )2

(

)

2

PZT Si PZT + 4s11 s11 (tSi )3 (tPZT ) + s11 (hSi )4

(5-8)

Optical MEMS Packaging: Communications Si and where L is the length of the cantilever, V is the applied voltage, s11 PZT −12 −1 s11 are the compliances of the silicon cantilever (5.9 × 10 GPa ) and PZT actuator (1.43 × 10−11 GPa−1), and tSi and tPZT are their respective thicknesses. The piezoelectric charge coefficients of d31 for various piezoelectric thin films of PZT, ZnO, and AlN are reported as –110, 5, and 2 to 3 pC/N, respectively. Several methods have been described for thin-film PZT deposition, for example, sputtering and sol-gel processes. High-temperature annealing (e.g., 600°C) is necessary to achieve a 100-percent perovskite phase of PZT film such that the PZT film exhibits its highest piezoelectric performance.45 The first research attempt to make piezoelectricdriven MEMS mirrors used PZT bimorph plates glued on a stainless steel frame in 1995.46 The first PZT thin-film-driven MEMS mirror was reported in 1996.47,48 One of the main challenges in making PZT thinfilm-driven MEMS mirrors is the residual-stress issue. Removing the PZT film from the silicon mirror area is necessary to keep the mirror flat. Recently, Yasuda and colleagues reported a large elliptical Si mirror (1 × 2 mm) driven by PZT actuators. This two-dimensional (2D) scanning mirror showed large optical scanning angles [e.g., 23 degrees (4.3 kHz for x scan) by 52 degrees (90.3 Hz for y scan] under 10 to 20 V ac with a 5-V dc offset.49 An overview of piezoelectric thin-film actuators has been provided by Maeda and colleagues.50

5.2.5

Integrated Micromachining Processes

We examined a number of thin-film and bulk-micromachining technologies in previous chapters. In contrast to bulk micromachining, surface micromachining refers the microfabrication technology for making MEMS devices entirely from released thin films that are deposited and patterned on top of substrates. Alternating layers of structural and sacrificial materials are deposited and patterned on the substrate first. Then the sacrificial materials are selectively removed by an etchant that attacks only the sacrificial materials. By leveraging the high selectivity of hydrofluoric acid–based sacrificial etching for silicon oxide with respect to polysilicon, a polysilicon-based surface micromachining process was reported by Howe and colleagues in 1983.51,52 With one gold electrode layer, two structural polysilicon layers, and two SiO2 sacrificial layers, complicated polysilicon-based micromechanical gears, springs, latches, micromotors, and sliders have been demonstrated. Polysilicon-based surface micromachining became the prevailing technology for making various optical MEMS devices in late 1990s because of the excellent mechanical properties of the polysilicon material and the availability of process service provided by foundries.5,13,53–56 Electrostatic actuators and thermal actuators are created by polysilicon-based surface micromachining, and additional optical components, such as mirrors, gratings, and lenses, may be integrated selectively in the same devices.53–56 In particular, the technique

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Chapter Five of surface micromachining is interesting in that it is a planar process that is capable of producing large-area, high-quality layered structures along the plane of the substrate, which then can be rotated out of the surface to form large optical surfaces angled to the surface of the substrate. Surface micromachined Au/poly-Si mirrors up to approximately 300 × 300 μm2 in size still can maintain reasonable flatness.57 However, a mirror of 1 mm2 or larger with high optical quality never can be created with polysilicon-based surface micromachining technology because of the deterioration of mirror flatness attributed to residual stress. In surface micromachining, movable structures generally are released by wet etching the sacrificial layer, followed by rinsing in water. After the rinse step, the capillary force generated by the water bridge formed in between the small sacrificial-layer gap leads to the stiction of suspended structures to the underlying substrate during the drying step. Many antistiction approaches have been developed. By dipping surface-micromachined devices in a hydrophobic liquid such as hexane or toluene in the last rinse step, formation of water bridge in the gap can be effectively avoided.58 The second approach relies on a sublimation process. Either by freezing or by heating the liquid to a supercritical state, one can avoid formation of the water bridge during the rinse and drying processes. t-Butyl alcohol is solid at room temperature (the freezing point is 25.6°C), so it is possible to perform freeze-drying without special cooling equipment and low vacuum pressures.59 In the supercritical drying method, the final rinse is done in a pressure vessel in liquid CO2, which is then raised to a supercritical state. The interface between the liquid and gas phases is indistinguishable, and there are no surface-tension forces in the supercritical state.60 Thereafter, the CO2 gas is vented without a surfacetension issue. The fourth method deploys HF vapor to conduct the vapor-phase sacrificial-layer etching. Since sacrificial-layer oxide is etched in vapor, there is no concern for surface-tension forces.61,62 Optical MEMS manufacturing processes require design tradeoffs among optical considerations, actuator performance, process yield, and reliability. Combining unique process steps from various process technologies, such as wet bulk micromachining, deep reactive-ion etching (DRIE), surface micromachining, chemical/mechanical polishing (CMP), and wafer bonding, can provide a wide range of process alternatives. For example, surface-micromachined polysilicon microstructures evidenced low stiffness owing to structures made from the thin-film polysilicon layer. Thus surface-micromachined mirrors with low stiffness could not tolerate the residual stresses. As a result, the size of a surface-micromachined polysilicon mirror typically is limited to 300 × 300 μm2. A creative molded surface-micromachining and bulk etch release (MOSBE) II process has been proposed by Wu and Fang63 to overcome this problem, as shown in Fig. 5-6. First, trenches with various depths are created down to silicon substrate by DRIE


(a)

(e)

(b)

(f)

(c)

(g) Stiff structure (e.g., mirror plate) Flexible structure Multidepth structure (e.g., torsional bar) (e.g., vertical combs)

(d)

(h)

PR

FIGURE 5-6

Oxide

Poly 1

Nitride

Poly 2

The process flow of a MOSBE II process.63

(Fig. 5-6a and b). The processes illustrated in Fig. 5-6c through g are the deposition, patterning, and stacking of thin films, in which these process steps are similar to surface-micromachining process steps. In Fig. 5-6f and g, low-stress nitride was deposited and patterned as the etching mask for bulk silicon etching, whereas the poly-Si film was fully protected by the thermal oxide and the SiN films. After the tetramethyl ammonium hydroxide (TMAH) bulk silicon etching and the HF oxide etching, the high-aspect-ratio polysilicon structures are released from the substrate (Fig. 5-6h). The DRIE-derived trenches are molds for high-aspect-ratio microstructures. The trench-refilled polysilicon film can form reinforced ribs so as to significantly enhance the stiffness of the mirrors, as shown in Fig. 5-7a and b. A mirror with 500-μm reinforced ribs shows a radius of curvature of 150 mm. By using this kind of mirror-fabrication technology, one can design a

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Chapter Five Reinforced ribs

(a)

(b) Supporting frame

Vertical comb actuator

Marks of the reinforced ribs

Mirror plate

Torsional sparing

(c)

FIGURE 5-7 SEM photographs of various mirrors made by the MOSBE II process: (a, b) Top and backside views of a torsional mirror with rib-reinforced structures; (c) optical scanning mirror with vertical comb actuators on two sides.63

scanning mirror of large size, large scanning angle, and high mechanical resonance frequency because the mass of mirror is reduced and the stiffness is increased. Another promising process technology is integration of polysilicon surface micromachining on top of an SOI substrate. By combining surface and bulk micromachining, a movable polymer lens can be released and assembled inside the space etched from the device layer of an SOI substrate.64 In short summary, various optical MEMS devices are derived by surface micromachining and SOI-based bulk micromachining. Through integration of different process technologies, more degrees of freedom in optimization of MEMS devices can be achieved.

5.3 Optical Switches Optical networks based on wavelength-division-multiplexing (WDM) systems have played a key role in increasing the capacity and flexibility of these networks. When the network architecture is evolving

Optical MEMS Packaging: Communications from point-to-point WDM transmission systems into ring-type networks, optical add/drop-multiplexing (OADM) systems and optical cross-connect (OXC) systems are required to enable more flexibility. Thus networks will evolve into a mesh-type architecture in the future. Based on free-space optics, various OADM and OXC devices have been demonstrated using MEMS technology. On the other hand, MEMS-based optical switches route the entire optical signal of various wavelengths from one fiber to another and scale in size from fundamental 1 × 2 and 2 × 2 switches to N × N switches, where N can be as large as 1000, because optical MEMS devices provide such key features as protocol and data-rate transparency, and wavelength independence. The basic 1 × 2 optical switch is often used for protection against equipment failure. For example, metropolitan-scale fiber rings often use fiber redundancy employing a bidirectional lineswitched ring topology. The 1 × 2 switch can route the signals from the main fiber to the backup fiber when a loss of signal occurs. A fundamental 2 × 2 switching element can be used as a stand-alone switch or within a multistage interconnection network for constructing larger switch fabrics. The 2 × 2 switch can be used for implementing OADM architecture on a per-channel basis. A 1 × N switch routes optical signals from one fiber to one of an array of N fibers. The 1 × N switch can be used for efficient equipment sharing, such as optical monitoring at an amplification site. Finally, large N × N switches, often referred to as optical cross-connects (OXCs), are used to establish a desired connectivity pattern across many fibers. An OXC performs as an automated patch panel whose connectivity can be changed without the need for a technician’s visit to the site of the patch panel. In addition, OXCs can be used to route individual WDM channels at a network node using opaque or transparent operating modes.

5.3.1

Small-Scale Optical Switches

An optical add/drop switch, the so-called 2 × 2 crossbar optical switch, is a critical element of OADM devices. It is desired for such a switch to be able to add or drop optical signals to or from current traffic directly without using an optical-electrical-optical (OEO) conversion. The common device configuration of a crossbar switch is that there is a tiny mirror sliding in and out of the intersection point of the light path. Thus light beams either cross unimpeded to the fiber opposite them or get diverted into the next fiber channel. This kind of movable mirror is used for gate switches (1 × 1 on/off switches) as well. Early gate switches and crossbar switches have been realized by using polysilicon-based surface-micromachining and bulkmicromachining technology. The first crossbar switch was created by surface micromachining and assembling of a polysilicon mirror.65 An electrostatic-actuated surface-micromachined polysilicon mirror

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Chapter Five Output fiber

Level arm

Pop-up poly-Si shutter

Pivot

Input fiber

Capacitor plate Spring Light beam

Moving direction

z

+ V

y

x

–

FIGURE 5-8 Schematic drawing of a surface-micromachined polysilicon pop-up shutter connected with a displacement amplification-level arm. The displacement generated by the parallel-plate actuator is amplified via the level arm to the pop-up shutter. This electrostatically actuated pop-up shutter can perform the functions of both a gate switch and a VOA.

has been created with a vertical sidewall electrode,66 a stress-bent parallel-plate electrode,67 and a displacement amplification-level arm.68 Figure 5-8 shows the pop-up mirror moving vertically in between two fibers for a gate-switch application.68 Based on bulk-micromachining technology, a crossbar switch has been created by using electromagnetic69,70 and electrostatic71–73 actuation schemes as well. Combining the comb-drive actuator with DRIEcreated trenches for holding optical fibers, a crossbar switch derived from an SOI substrate is shown in Fig. 5-9. Such an optical switch consists of a high-aspect-ratio micromirror with a vertical sidewall and an electrostatic comb-drive actuator for controlling the position of the micromirror (i.e., the shutter).71–73 The common comb-drive actuator includes a stationary-comb finger electrode and a movablecomb finger electrode connected to the micromirror via a suspended spring. This suspended spring is anchored onto the substrate at one end. Electrostatic force for moving the micromirror can be generated by applying voltage to the comb-drive actuator. The restoration force generated by the deformed spring will pull the actuated micromirror to its initial position. The optical fibers are assembled and aligned properly with respect to the micromirror inside the trenches. Thus the creation of DRIE-derived crossbar switches is much easier than that for the counterpart made by surface-micromachining technology. On the other hand, a similar comb actuator driven crossbar switch can be created from a normal silicon substrate based process combining the DRIE step with an oxide-refill step.74 To reduce the driving voltage, a two-step of DRIE process is reported to create a crossbar switch with two steps of height from an SOI substrate; this crossbar switch

Optical MEMS Packaging: Communications Si anchor

Suspended Si spring + V –

Stationary comb finger electrode Movable comb finger electrode

Input fiber In-plane moving Si shutter Output fiber

+ V –

Moving direction

Light beam

+ V –

FIGURE 5-9 Schematic drawing of a surface-micromachined silicon shutter connected with a lateral movable electrostatic comb actuator. This electrostatically actuated lateral movable shutter can perform the functions of both a gate switch and a VOA.

has thin folded springs and high comb-electrode fingers. Therefore, the stiffness of the spring along the moving axis (i.e., kx) is reduced significantly, whereas the stiffness of the spring along the other two axes is kept almost the same because the output electrostatic force versus the applied dc bias is the same as for conventional SOI-based crossbar switches. The switching voltage, however, is reduced significantly.75 Based on a revised structural concept,70 an electrostatic optical crossbar switch has been reported using a KOH-etched mirror on an electrostatically driven torsional plate.76 Regarding the application of an optical switch, the micromirror can be moved from the initial off-state (i.e., light-transmission state) to the actuated on-state (i.e., light-reflection state, or switching) by applying voltage to the comb-drive actuator. In general, the micromirror only needs to be capable of staying at two relative positions. A continuously applied electric bias on a MEMS actuator is necessary to hold the micromirror of the optical switch staying at the on-state because we need the force generated by the MEMS actuator to balance the restoring force from the spring. Therefore, the crossbar switch requires a latching function to allow devices to reliably maintain a known position without power consumption when the power is removed or lost. Bistable micromechanisms provide two relative positions that are both mechanically stable. A buckled-beam archshaped leaf-spring geometry driven by a bidirectional electrostatic comb actuator was the first demonstrated application of an optical switch with a latch function.77–79 The other kind of latch mechanism

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Chapter Five for optical switches uses a gripper to clamp the switch in one position80,81 and a deformed spring to pull the switch body back to the original rest position when the switch structure is released from the gripper. However, such contact-clamping latches may have repeatability and reliability issues because the unbalanced clamping force from both sides, residual electrostatic force, and variations in friction force at the interface between the gripper and the switch structure may lead to different light-reflection angles and different switching speeds. Using the buckled-beam spring (i.e., a buckle spring) to enable the latching function (i.e., bistable switching) is an appropriate alternative to avoid the above-mentioned potential problems. In order to move the buckle-spring-type bistable structure from one stable position to the other, a larger force output of the actuator is preferred. A thermal (denoted as electrothermal) actuator has been demonstrated as an alternative to provide a higher force output under lower applied voltage than an electrostatic comb actuator, although the thermal actuator consumes more power than the electrostatic actuator.34 A symmetric double-beam thermal actuator generating an in-plane bidirectional stroke has been used to perform the bistable function for a relay in association with the latch function provided by buckle springs.82 Obviously, conventional crossbar switches using electrostatic comb-drive actuators and buckle beams formed on SOI substrates have encountered the following problems: (1) The large displacement provided by the comb drive for gaining better optical performance in conjunction with optics will lead to the design limit of comb-drive actuators and a requirement of very high driving voltage for such comb-drive actuators, and (2) the necessary force output provided by the comb drive for moving the arch-shaped leaf spring from one stable state to the other will require the MEMS actuator to generate the needed force. According to the functional requirements for practical application of optical switches mentioned earlier, desirable device features of optical switches include large displacement regarding the mirror, large force output from the actuator, and a latch mechanism for the device itself. On the other hand, V-shaped thermal actuators are promising in applications that need large strokes and high force outputs, but these designs are not compatible with bidirectional movement, which is necessary for latch applications. Lee and Wu82 have reported a bistable crossbar optical switch consisting of two sets of movable V-beam actuators, a set of bucklebeam springs connected to a suspended movable shutter beam with a reflective mirror shutter, and a suspended movable translation link at the ends of the suspended movable shutter beam. Both ends of this set of buckle-beam springs are anchored to the substrate, whereas the center of the buckle beam is connected to the suspended movable shutter beam (Fig. 5-10a and b). The force generated by one of the two


V-beam actuator

V-beam actuator

Fiber

Fiber

Pushing arm

Buckle spring

Buckle spring

Movement translation link

Movement translation link (CH2)

Reflective shutter (CH3)

Reflective shutter

Pulling arm

(CH1) (CH4) (a)

(b)

Movement translation link

(c)

Buckle spring

Buckle spring

V-beam

V-beam

(d)

FIGURE 5-10 Schematic drawing of a bistable optical crossbar switch driven by two sets of V-beam thermal actuators: (a) transmission state; (b) switching state; (c) optical microscope photograph of thermal actuator and movement translation link in the transmission state; (d) optical microscope photograph of the thermal actuator and movement translation link in the switching state.

sets of V-beam thermal actuator on various values of the applied electrical load is against the restoration force from the buckle-beam springs. The buckle beam is deflected to a range where the force from the bent buckle-beam spring is balanced by the force generated by the V-beam actuator when it is under electrical load. The V-beam actuator can push or pull the suspended movable translation link to move the shutter beam when the buckle-beam spring is deflected in the opposite direction, with deflection equivalent to 133 percent of the initial buckle deflection owing to the generated electrothermal force against the existing buckle-beam spring force. Thereafter, the mirror and shutter beam will move from the initial position to another bistable position (Fig. 5-10c and d). On the other hand, the mirror and shutter beam will be moved by the suspended movable translation link back to the initial position of the bistable state when another one of the two sets of V-beam actuators is actuated to pull or push the suspended

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Chapter Five movable translation link. The measured 2- to 6-ms switching time is good enough for commercial applications. Thus an on/off switching operation with a latch function is realized such that this device can stay at bistable positions without demanding electric power. However, a V-beam-driven crossbar switch has a large footprint because it requires two separately controlled actuators to perform the bidirectional strokes. As discussed earlier, the bidirectional static displacement generated by an H-beam thermal actuator, as shown in Fig. 5-5, in an H-beam-driven crossbar switch is smaller than that of the V-beam crossbar switch. An H-beam-driven crossbar switch containing an H-beam actuator, movement link structure, reflective micromirror, and arched buckle spring has been reported.83 As shown in Fig. 5-11, when the electric load is applied to one beam of the H-beam actuator, the arched direction of the biased beam is the same as the direction of forward movement of the reflective shutter. Once the unbiased beam is deformed owing to the pulling force of the biased beam, the whole actuator structure will generate a net displacement in the direction of the biased beam. This side-beam structure will push the shutter and switch-body beam forward, moving it from the initial stable position (see Fig. 5-11a) to the other stable position. Thus the device will change its status from the transmission state (see Fig. 5-11a) to the reflection state (i.e., switching state; see Fig. 5-11b). The device can be changed from the second stable position (see Fig. 5-11b or c) back to its initial stable position (see Fig. 5-11a or d) by applying an electric load on the opposite side of the H-beam to pull the switch body back via movement of the link structure. A close-up view of the H-beam actuator, movement-link structure, and arched buckle spring is shown in Fig. 5-11e. The measured optical switching characteristics include a forward and backward switching time of 5 and 1 ms under a 25-V dc pulse (see Fig. 5-11f ), back-reflection loss of –52 dB, cross-talk of –60 dB, insertion loss of 0.8 dB, polarization-dependent loss of 0.03 dB, and wavelength-dependent loss of 0.11 dB. This H-beam actuator avoids the influence of rotational torque during its bidirectional dynamic and static movement because of its symmetric structural design. The next level of complexity is built using a 2D array of these mirrors to form a matrix switch, with rows of inputs and columns of outputs (or vice versa), as shown in Fig. 5-12a. Optical switches with 8 × 8 and 16 × 16 ports were demonstrated.84–86 Mirror control for these 2D switches is binary and thus straightforward, but the tradeoff for this simplicity is optical loss. The substantially different lengths of the optical paths through various switch configurations limit the scaling. Limits to the scaling also include the diameter of the mirrors and their maximum tilt angle. The mirrors are designed to be about 50 percent bigger than the optical beams to avoid excessive loss, and tilt is limited by both the method used to build the switch and the technique

Optical MEMS Packaging: Communications Applied voltage at one side of H-beam H-beam actuator Movement link structure

Direction of displacement

Fiber 1

Fiber 1 Fiber 4

Transmission state

Fiber 3

Fiber 2

Buckle springs Fiber 4 Switching state

Fiber 2 Fiber 3

(a)

(b) Applied voltage at one side of H-beam

Direction of displacement Fiber 1

Fiber 1

Fiber 4

Fiber 4 Fiber 2 Fiber 3

Transmission state

(c)

Fiber 2

(d) Switching characteristics of H-beam driven optical switch 4 Optical signal 30 Electrical signal 1 ms 5 ms

Switch body

25 Driving voltage, V

Movement link structure

Buckle springs

Fiber 3

3

20

Electrical bias signal Optical signal

15

2

10 1 5

H-beam actuator

0 –10

(e)

(f)

0

10

20

30 40 Time, ms

50

60

70

0 80

FIGURE 5-11 Schematic drawings of an H-beam-driven optical switch in the transmission state (a, d) and in the switching state (b, c). The reflective mirror connected with switch body stays either in the transmission or the switching position, and this behavior is controlled by the buckle springs and driven by the bidirectional movable H-beam thermal actuator. (e) A SEM photographic close-up of the switch body, buckle springs, and movement-link structure of an optical switch. (f ) Switching speeds between the two bistable positions of optical switches under different driving conditions.

O-E converter output voltage, V

Switching state

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Chapter Five

Light beam Free-rotating switch mirror Fiber-collimator array Fiber-collimator array (a) Fiber array

Lens array

Optical signal MEMS array Optical path

Mirror

MEMS array

Fiber array (b)

Lens array (c)

Torsional spring

FIGURE 5-12 (a) Conceptual drawing of a 2D optical switch. (b) Conceptual drawing of a 3D optical switch. (c) Conceptual drawing of beam steering using a dual-axis gimbaled mirror.93

used to actuate the mirror. While the path length grows linearly with N, the number of ports, the optical loss also grows rapidly owing to the Gaussian nature of light. Therefore, 2D architectures are found to be impractical beyond 32 input and 32 output ports. Two major micromirror actuation mechanisms have been reported. The first is based on rotation of the micromirror.84,85,87–89 The mirror is initially parallel to the substrate (OFF position). When actuated, it is rotated to the vertical position (ON). In these cases, control of the mirror is digital; that is, the mirror is swung between fixed stops, and tight control of its motion between the stops is not needed. However, precision manufacturing and packaging are required to ensure that the stops are positioned properly. The second mechanism moves the vertical micromirror in and out of the optical path without changing the mirror angle.67,69,79,90,91 The 2D switches have been created by both bulk-micromachining69,79 and surface-micromachining67,90,91

Optical MEMS Packaging: Communications technologies. Owing to process-integration considerations, these approaches use either electrostatic actuation or magnetic actuation. The aforementioned approach leads to a very cost-effective medium-scale matrix switch because all the packaging is planar. The optical paths between the individual mirrors can be through free space or via waveguides. A combination of MEMS and waveguides has been reported by De Dobbelaere and colleagues.92 This approach has advantages in terms of compact size, scalability, and integration of a few 2D switches into a 3D stacked switch.

5.3.2

Large-Scale Optical Switches

In contrast to the case of 2D optical switches (i.e., all the light beams reside on the surface plane of the MEMS substrate and this feature leads to unacceptably high loss for large port counts), 3D optical switches deploy an array of two-axis mirrors to steer the optical beams in 3D free space, as shown in Fig. 5-12b. These switches require extremely fine analog control to align their optical beams because the beams must be directed accurately along two angles and then stop at precise intermediate positions, not just fixed end points. Thus the two-axis mirror array is the key enabling device for the 3D switch. Key parameters of a two-axis mirror array include size, tilt angle, flatness, fill factor, and resonance frequency of the mirror. More important, the stability and repeatability of the actuated mirror under certain electric loads are critical to the complexity of control schemes. Early devices relied mainly on surface-micromachined two-axis mirrors.94,95 The residual stress limits the size of the mirror to approximately 1 mm, and the different thermal-expansion coefficients between the mirror and the metal coating also cause the mirror curvature to change with temperature. Bulk-micromachined single-crystal silicon micromirrors are used often in high-port-count 3D optical switches that demand larger mirror size.96–101 In the early 2000s, research effort focused on high-port-count 3D optical switches for OXC applications. For example, Kim and colleagues102 reported an OXC of 1100 × 1100 ports based on a surface-micromachined two-axis mirror array because of the explosion of Internet data transport demands in the telecommunications industry boom. They even reported that 3D optical switches with sizes as high as 4096 × 4096 are technically feasible, although their costly 3D packaging makes them too expensive to be implemented practically. Later on, the research effort shifted to applications in metropolitan-area networks (i.e., metro-access and metro-core networks). Such markets demand 3D optical switches with medium port counts (~100 × 100) and features of low cost, low power consumption, and small footprint.100,103 As shown in Fig. 5-12b, the design and optimization of two-axis mirrors require examination of three elements: the mirror, the torsional springs (i.e., the mechanical support), and the actuator—all of

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Chapter Five which determine the overall system parameters of 3D optical switches. Examples of these parameters include • Maximum port count. This depends on the mirror tilt angle. • Switch settling time. This depends on the mirror response time. • Insertion loss. This depends on mirror size, reflectivity, and maximum tilt angle. • Power dissipation. This depends on the power required for mirror actuation and control. For example, each mirror may require a diameter on the order of 1 mm and a mirror radius of curvature (ROC) that is greater than a few tens of centimeters in a 1000-port 3D optical switch. The reflectivity of each mirror should be above 97 percent. The tilt angle needs to be in the range of a few degrees to ±10 degrees depending on the optical-path design of the 3D optical switch. Moreover, there are different tradeoffs among the desired properties of two-axis mirrors. For example, the torsional springs of the mirrors must have sufficient stiffness to meet such requirements as mirror response time and vibration immunity. However, the upper bound of spring stiffness is also restricted by the desired maximum tilt angle and the maximum force or torque output of the actuators. Magnetic and electrostatic actuation are two viable solutions for two-axis mirror actuation in an analogue manner (i.e., positioning the mirror at a particular angle). Magnetic actuation offers the benefit of a large bidirectional (attractive and repulsive) linear force output but requires a relatively complicated fabrication process for making the metal coils or magnetic films and proper package design for electromagnetic shielding.104 Electrostatic actuation is used most commonly in 3D optical switches because of the relative ease of fabrication and its low power consumption and compact footprint in packaged devices. Early electrostatic devices based on parallel-plate actuators demanded high actuation voltages. In order to achieve a large tilt angle, one can use a stiff spring, and then the tradeoffs include high actuation voltages (e.g., 50 to 200 V) and nonlinear torque output. The second issue is that the scan angle is limited owing to pull-in instability and cannot reach the theoretical value.105 Although the pull-in effect can be mitigated by nonlinear controllers, this increases the complexity of the electronics.106 In 2001, Sawada and colleagues107 reported another unique design of electrostatic two-axis tilt mirrors, as shown in Fig. 5-13a through c. First, two wafers are processed independently by silicon bulk micromachining. Through the use of AuSn solder–based wafer bonding, a bonded structure of a mirror with a terraced electrode underneath forms a novel canted parallel electrode (see Fig. 5-13b and d). The 10-μm-thick mirror is supported by folded

Optical MEMS Packaging: Communications Base layer Torsion spring Mirror substrate

Silicon oxide Tilt mirror Pivot

Electrode substrate

(a)

(b)

Trench

Terraced electrode AuSn solder

Pivot

50 μm (c)

10 μm

100 μm (d)

(e)

FIGURE 5-13 (a) Optical microscope photograph of a two-axis tilt mirror with a wafer-bonded electrostatic actuator with a terraced electrode. (b) Schematic crosssectional view. (c) SEM photograph of a two-axis tilt mirror. (d) Photograph of the terraced electrode with a pivot. (e) Optical microscope photograph of high-aspectratio folded torsion spring.107–109

torsion springs on two orthogonal axes and is tilted two-dimensionally by electrostatic force (see Fig. 5-13c and e). The torsion spring has an aspect ratio of greater than 6, which gives it a strong bending stiffness relative to torsion and strong support for the mirror so as to achieve reliable switching operation. The mirror has a diameter of 600 μm and is integrated with the gimbal structures that provide freedom of tilt about two axes. The tilt angle of the mirror can be changed by controlling the applied voltage between the two substrates. In last step, a 10 × 10 two-axis mirror array with 1.3-mm spacing is assembled onto a conventional plastic grid array (PGA)-ceramic package.96,107–109 The packaged 3D optical switching module with 100 × 100 ports is approximately 80 × 60 × 35 mm3. This design can achieve large deflection angles without a severe pull-in effect. Another improved electrostatic actuation mechanism for mirrors is a vertical-comb actuator. The first micromirror with a vertical-comb actuator was reported in 2000.110 By leveraging vertical-comb actuators, tilt-mirror devices can have a much larger electrostatic-forceinduced torque such that one can reduce the operating voltage as well as increase the resonance frequency. Moreover, optical switches with 80 × 80 ports using vertical-comb-driven two-axis mirrors with the V-shaped torsion springs have been reported to show a stable rotation of 5 degrees at 50 V. This approach remedies the pull-in effect

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Chapter Five Au/Cr

SiO2

(a)

(d) Photoresist

(b)

(e) V-shaped torsion bar

Electrical connection bar (c)

(f)

FIGURE 5-14 Process flow for making a two-axis mirror driven by a vertical-comb actuator with step-height difference.111,112

and increases the stable tilt angles.100,111 Figure 5-14 shows the bulkmicromachining process for this vertical-comb-driven two-axis mirror. First, a SOI wafer with 100-μm-thick top and bottom Si layers sandwiched a 1-μm-thick buried oxide layer was oxidized to grow 0.5 μm of thermal oxide. A mirror, anchors, and movable comb fingers were patterned on both sides by a novel through-wafer DRIE process. Using the patterned resist and oxide film as an etching mask, the first DRIE was applied to obtain a 5-μm-deep trench (see Fig. 5-14c). The photoresist then was removed only from the top surface (see Fig. 5-14d). Next, both the top and bottom surfaces were etched with DRIE using the patterned oxide as an etching mask until the buried oxide was exposed (see Fig. 5-14e). Finally, the exposed oxide was removed by HF wet etching (see Fig. 5-14f ). This process flow produced a 5-μm-thick torsion bar. The movable and stationary comb fingers were patterned with DRIE on the top and bottom Si layers, respectively. Figure 5-15 includes a photograph of the resulting mirror array and SEM photographs of both sides of the mirror


11.4 mm

(a)

Front side (b)

14.1 mm

Back side (c)

Mirror

V-shaped torsion bar

Comb-tooth actuator

FIGURE 5-15 (a) Microfabricated two-axis mirror array of 79 channels. (b) Top-view SEM photograph of a two-axis mirror. (c) Backside-view SEM photograph of a twoaxis mirror.111,112

with a vertical comb. The height of the vertical-comb finger is 100 μm. Moreover, optical switches with 80 × 80 ports using a vertical-combdriven two-axis mirror with V-shaped torsion springs have been reported to show stable rotation of 5 degrees at 50 V. This approach remedies the pull-in effect and increases the stable tilt angle. The average insertion loss is 2.6 dB, and the overall insertion loss is 4 dB. This 80 × 80 switch has a packaged size of 77 × 87 × 53 mm3.100,111 The total power consumption is only 8.5 W, attributed to the electrostatic actuation. In 2006, a 3D optical switch with 256 × 256 ports based on a 512-mirror array demonstrated a ±5-degree rotation of the two-axis stationary operation under a drive voltage of 160 V and a resonance frequency of 2 kHz.112 Mirror-based variations with parallel-plate and vertical-comb actuators have been reviewed.113 Among these approaches, angular vertical-comb actuators can be integrated easily with mirror structure by using single-side lithography process on common wafers.113 Thus the angular comb actuator, ref 114, provides a potentially improved solution for a new two-axis mirror for 3D optical switch applications.

5.4 Variable Optical Attenuators Among optical communication applications, VOAs and their arrays are crucial components for enabling advanced optical networks. Nowadays, single-port VOAs are used widely in such applications as attenuation control on individual line cards and total signal-level

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Chapter Five control of the optical input to erbium-doped fiber amplifiers (EDFAs). This section provides an extensive survey of MEMS VOA technology evolution in last decade. First, MEMS VOA devices offer such physical features as transparency (bit-rate- and protocol-independent), tunability, scalability, low power consumption, and small form factor. At nodes of MANs, the optical signals in traffic must be added into or dropped easily and cost-effectively from a particular optical fiber pipeline and switched from one channel to the other, whereas the optical signal power of certain channels may need to be attenuated at nodes as well. Currently, a dynamic gain equalizer (DGE)115,116 is provided in conjunction with wavelength-division multi/demultiplexers (MUXs/DEMUXs) to perform the attenuation function and the function of reconfigurable and transparent add/drop at nodes. The multichanneled VOA device can be the channel-power equalizer in WDM cross-connect nodes, as well as in transmission networks. Thus integrated multichannel VOAs with MUXs/DEMUXs will be an alternative to satisfy this market. In view of market requirements, such as small footprints and low power consumption, an array structure containing multiple MEMS attenuators in a single silicon chip is preferable for future dense wavelengthdivision-multiplexed (DWDM) applications, whereas single-port VOA is required in MAN applications.

5.4.1 Early Development Work The early development work on VOAs in late 1990s was contributed mainly by two groups at Lucent Technology and the group of Professor N. F. de Rooij at the University of Neuchâtel in Switzerland. In 1994, Walker and colleagues117 developed a mechanical antireflection switch (MARS) device. A MARS consists of a suspended membrane with an optical window at the center of membrane. By actuating the membrane with displacement of λ/4, light of particular wavelength can be either transmitted or reflected. The original idea was to use a MARS as an optical modulator for switching in fiber-to-the-home (FTTH) applications. In 1998, Ford and colleagues118 further revised the MARS structure and applied it to VOA applications. This MARS is a silicon nitride suspended membrane with λ/4 optical thickness above a silicon substrate with a fixed 3λ/4 spacing. Voltage applied to electrodes on top of the membrane creates an electrostatic force that pulls the membrane closer to the substrate, whereas membrane tension provides a linear restoring force. When the membrane gap is reduced to λ/2, the layer becomes an antireflection coating with close to zero reflectivity. It is basically a quarter-wave dielectric antireflection coating suspended above a silicon substrate. The membrane varies in size from 100 to 500 μm in diameter. The mechanical resonance frequency of such a MARS device is on the order of megahertz. Thus the response time is extremely fast (i.e., 3 μs). The dynamic range of

Optical MEMS Packaging: Communications attenuation is 25 dB. However, the insertion loss is 2 dB, and wavelength-dependent loss is relatively high for attenuations larger than 5 dB. Ford and Walker115 have further applied the concept of a MARS to a MEMS-based DGE filter. To form the DGE filter, the optical window of the attenuator was elongated to create a suspended rectangular membrane. An array of strip-electrode pairs along the length of the optical window was arranged. By applying independently controlled voltages to all the electrode pairs, a controllable reflectivity function was developed along the length of the device. The diffraction grating– based free-space optics system was used to spread the incoming light spatially along the length of the optical window. An input spectrum with more than 15 dB of dynamic range was flattened to less than a 0.25-dB ripple over a 42-nm-wide spectrum. In contrast to the suspended dielectric antireflection membrane used in the MARS, Bishop and colleagues119,120 at Lucent Technology in 1998 developed a MEMS VOA using a surface-micromachined polysilicon microshutter arranged between a transmission fiber and a reception fiber aligned and located on the same axis. In this fiber-tofiber in-line type of VOA, the shutter is connected with a movable capacitor plate via the pivoted rigid level arm, and this shutter can move upward and downward in an out-of-plane direction by adjusting the position of the capacitor plate owing to electrostatic force based on the applied voltage. Thus it can control the relative amount of attenuation by blocking part of the light beam. This surface-micromachined in-line type MEMS VOA can achieve a dynamic range as high as 50 dB and a less than 1-dB insertion loss, whereas the reported shutter displacement can reach 15 μm under a 25-V dc load. More details about the activities of Lucent Technology can be found in a review article by Walker.1 In addition to the surface-micromachined polysilicon-based approach, DRIE technology is another major alternative for making MEMS VOA structures from the device layers of an SOI wafer. The first demonstration was done by Professor N. F. de Rooji’s group at the University of Neuchâtel in Switzerland in 1998.121 This SOI-based VOA device consists of a movable comb-finger electrode connected with a microshutter via a suspended spring and a stationary combfinger electrode. The attenuation range is determined in terms of the in-plane position of the Si microshutter, where this in-plane position is controlled by force balance between the electrostatic force and the spring force. To reduce the return loss of the input light reflected back into the input fiber, the microshutter and the fiber-end faces are at an 82-degree angle with respect to the longitudinal direction of the fiber channels. This in-line type of VOA achieved an insertional loss and back-reflection loss of less than 1.5 and –37 dB, respectively, whereas it provided 57 dB of attenuation with respect to 32-V bias. Apparently, among these early demonstrations, the movable-microshutter-based

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Chapter Five approaches exhibit promising device features (e.g., larger dynamic range). DRIE-derived SOI MEMS VOAs have silicon trenches to accommodate optical fibers with the alignment accuracy regarding the microshutter determined by the photolithography process. This feature makes the tedious assembly and alignment easier.

5.4.2 Surface-Micromachined VOAs Polycrystalline silicon–based surface micromachining was developed initially for accelerometers in early 1990s. Surface-micromachined electrostatic parallel-plate actuators, electrostatic comb actuators, electrostatic scratch-drive actuators (SDAs), U-shaped thermal actuators, and microstructures such as hinges and latches were demonstrated in early 1990s as well. These actuators and micromechanical elements enabled realization of a monolithically integrated free-space microoptical bench.55,56 In essence, the photon mass is not a physical concern; thus the surface-micromachined actuator does not need to manipulate the small microoptics or micromirrors. The MARS devices of Lucent Technology relied on electrostatic parallel-plate actuation,117,118 whereas the first in-line type of MEMS VOA from Lucent Technology was deployed based on a revised micromechanism using electrostatic parallel-plate actuators.119,120 Demonstration of the first in-line type of MEMS VOA from Lucent Technology really showed the advantages provided by surface-micromachining technology (see Fig. 5-8). These merits include (1) forming 3D complicated structures based on patterned-planar-layer structure and (2) precise control of optical alignment owing to the accuracy granted by the lithographydetermined planar-layer structure. In 2002, another surface-micromachined MEMS in-line type of VOA using a pop-up microshutter based on electrostatic parallelplate actuation was reported by Liu and colleagues at Nanyang Technological University (NTU), Singapore.122–124 The pop-up microshutter uses the same design as that used by Lucent Technology, whereas this microshutter is fixed on a drawbridge plate and can be moved down to the substrate via an applied dc bias. It demonstrates 45 dB of attenuation under 8 V bias and 1.5 dB of insertional loss. Compared with the devices in refs. 119 and 120, the driving voltage has been reduced a lot by using this unique drawbridge structure. In 2003, a group at Asia Pacific Microsystems (APM), Inc., developed a new movement-translation micromechanism (MTM) to convert and amplify small in-plane displacements into large out-of-plane vertical displacements or large out-of-plane rotational angles. As shown in Figs. 5-16 and 5-17, the in-plane displacement is provided by an electrically controlled electrothermal actuator (ETA) array. Based on this MTM, we applied only 3-V dc to generate 3.1 μm of in-plane displacement, then a rotational angle of 26.4 degrees, and an equivalent out-of-plane vertical displacement of 92.7 μm for pop-up

Light transmission direction Lense fiber

Surface-micromachined poly-Si pop-up mirror Movement-translation mechanism

Electrothermal actuator (ETA) array

Lense fiber

Staple and hinge pin

Light transmission direction

FIGURE 5-16 Schematic drawings of a surface-micromachined MEMS VOA consisting of a pop-up micromirror and the input and output fibers. After a wet-etching release process, the lense fibers are aligned to achieve minimum insertion loss first. The attenuated light is reflected in the out-of-plane direction when a dc voltage is applied to the ETA array.

Staple and fixed hinge pin

Reflective micromirror

Movement-translation micromechanism

Movement shuttle arm

Movement-translation link

FIGURE 5-17 SEM photograph of the MEMS VOA shows that in-plane displacement from the ETA array under dc voltage load is converted into out-of-plane rotation. The upperright inset shows a close-up view of the pop-up micromirror, staple, and fixed-hinge pin, whereas the bottom-left inset shows a close-up view of the lifted-up MTM structure.

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Chapter Five micromirror.125,126 Using this MTM, the in-line type of VOA demonstrated a 37-dB attenuation range under a 3-V dc load, whereas return loss, polarization-dependent loss, and wavelength-dependent loss at an attenuation of 3 dB were measured as 45, 0.05, and 0.28 dB, respectively. This reveals the effort needed to reduce the driving voltage for surface-micromachined VOA devices. It shows the third benefit of surface micromachining to optical MEMS, which is that a small planar displacement can be amplified into a large 3D displacement (i.e., large rotational angle or significant displacement) of the micromirror.

5.4.3 DRIE-Derived Planar VOAs Using Electrostatic Actuators Shutter and Single-Reflection Mirror DRIE-derived VOAs from SOI substrates with fiber-alignment trenches make the testing, alignment, and assembly work easier.121 As shown in Fig. 5-9, a DRIE-derived VOA developed by Professor N. F. de Rooji’s group really opens a window for new research activities. Since MEMS VOAs attenuate light signals in free space, the relative wavelength-dependent loss, polarization-dependent loss, and insertion loss are lower than for other waveguide-based approaches, whereas return loss and response time can be as good as the data achieved by the other approaches (e.g., any waveguided format). However, the back-reflected light coupling into the input fiber was a concern for in-line MEMS VOAs. In order to have a smaller return loss, using fibers with 8-degree facet ends is a common solution for in-line VOAs. Kim and colleagues127 reported a new electrostatic comb– actuated VOA with an off-axis misalignment–based light-attenuation scheme (i.e., single-reflection type) in 2002, whereas a similar design was reported by Lee and colleagues at APM.128 The devices made by Kim and colleagues exhibited 2.5 dB of insertion loss and 50 dB of attenuation with respect to 14-μm displacement of the comb actuator at 5 V. Meanwhile, APM’s relevant results have been published elsewhere.129,130 The data show 35 and 50 dB of attenuation under 10 to 13 V and 13 to 15 V, respectively. Kim and colleagues reported their progress in VOA research, indicating that their VOA achieved 35 dB of attenuation at 10 V and that the maximum polarization-dependent loss was 0.24 dB within the 25-dB attenuation range. Their VOA also had a return loss of –38 dB, and the maximum wavelength-dependent loss was 0.7 dB at 25-dB attenuation.131 Furthermore, Lee and colleagues at APM improved the designs of the electrostatic comb actuator and the single-reflection VOA. Figures 5-18 and 5-19 show the equivalent polarization-dependent loss, wavelength-dependent loss, and similar attenuation versus dc bias characteristics. These data are about the same as the results reported by Kim and colleagues.131

Optical MEMS Packaging: Communications 1

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FIGURE 5-18 Measured attenuation characteristic curves of bright operation, including insertion loss (IL), return loss (denoted as BR, i.e., back-reflection loss), polarizationdependent loss (PDL), and micromirror displacement versus the driving dc voltage.

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However, the return loss is kept smaller than –50 dB within the 50-dB dynamic range, which is much better than the data in ref. 131. Bashir and colleagues132 at MEMSCAP in Cairo, Egypt, also developed similar single-reflection-type VOA devices. Their work achieved 30 dB of attenuation at 32-V dc. Within the 30-dB dynamic range, the derived

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Chapter Five polarization-dependent loss was less than 0.1 dB, which was better than the data from the other groups. In terms of networking equipment configurations, we may need VOAs operating in a normally close scheme (i.e., dark type). With a dark-type VOA, all the incoming light is blocked out (i.e., 100 percent attenuation) in the beginning. All the previous reported data and the discussions in the reference are based on a normally open scheme (i.e., bright type). This means that the initial attenuation is zero (i.e., initial insertion loss only). In order to clearly illustrate the difference in operating mechanisms between bright and dark types of VOAs with respect to in-line and single-reflection types, we will explain the relationship between light paths and attenuation mechanisms first. As illustrated in the upper left of Fig. 5-20a showing an in-line VOA with an 8-degree slanted shutter, the insertion loss is maintained initially at its minimum level, and incoming light signals are fully transmitted (i.e., the upper left of Fig. 5-20b). The shutter is approaching the transmitted light owing to an applied electrical bias; then a portion of the incoming light is blocked by as a function of shutter position, as illustrated in the middle left of Fig. 5-20b. The dark circle represents the light beam, and the dotted circle represents the light-receiving area of the output port. This figure illustrates the partially attenuated state of an in-line VOA. Once the shutter approaches further, then all the light is fully blocked. This is the fully attenuated state, as illustrated in the bottom left of Fig. 5-20b. Second, the dark-type in-line VOA is kept at its rest state, that is, the zero-bias state (the upper right of Fig. 5-20b). In other words, the VOA maintains its maximal insertion loss in the initial state, and then a portion of light is allowed to transmit based on the shift in shutter position under a certain level of electrical bias (the middle right of Fig. 5-20b). When the applied electrical bias is larger enough to move the shutter away from the light-transmission path, all light is fully transmitted and coupled into the output port (the bottom right of Fig. 5-20b). Third, Fig. 5-20c illustrates the input and output fiber ports located in an orthogonally planar position, where the transmitted light falls on a reflective mirror and is reflected toward the output port. This is the so-called reflective-type or singlereflection VOA. The reflected light path is changed in accordance with different mirror positions that are determined by the comb-drive actuator based on various applied voltages. Therefore, the coupled light intensity of reflected light to the output port depends on the path of the reflected light. As shown in Fig. 5-20d, the reflected light is fully coupled into output port and fully attenuated at the beginning for bright- and dark-type operation, respectively. Whereas the partially attenuated state is considered as the operative state for both bright- and dark-type VOAs, the actuated position versus the initial rest position of the mirror are opposite each other, as shown in the middle drawings of Fig. 5-20d. Once the applied voltage is larger enough, the reflective mirror pulls back further, and then the reflected


Output fiber port Anchors of comb drive

z x y

Movable comb drive electrode fingers

Transmitted light beam

Attenuated light beam Fixed comb Moving direction drive electrode fingers In-line MEMS VOA (a)

Mirror Input light beam signals Input fiber port

Bright type

Dark type

• Initial state— Fully transmitted

• Initial state— Fully attenuated

• Operation state— Partially attenuated


• Operation state— Fully attenuated

• Operation state— Fully transmitted

In-line MEMS VOA (b)

FIGURE 5-20 (a) Schematic drawing of an in-line MEMS VOA. (Inset) SEM photograph of a microshutter with a tilted mirror plane. (b) Schematic drawing of light-path configurations in an in-line attenuation scheme operating in bright- and dark-type VOAs. (c) Schematic drawing of a reflection-type MEMS VOA. (Inset) SEM photograph of a reflective micromirror with a 45-degree mirror plane. (d) Schematic drawing of light-path configurations in a reflection-type attenuation scheme operating in brightand dark-type VOAs.

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(c)

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• Initial state— Fully transmitted

• Initial state— Fully attenuated



• Operation state— Fully attenuated

• Operation state— Fully transmitted

Reflection MEMS VOA (d)

FIGURE 5-20 (Continued)

Optical coupled light beam Input light beam signals

Optical MEMS Packaging: Communications 1

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FIGURE 5-21 Measured attenuation characteristic curves for dark operation, including insertion loss (IL), return loss (denoted as BR, i.e., back-reflection loss), polarizationdependent loss (PDL), and micromirror displacement versus the driving dc voltage.

light path is shifted far away from the initially optimized light path. In this way, a bright-type VOA reaches its full attenuation (bottom left in Fig. 5-20d), whereas a dark-type VOA reaches its full transmission state (bottom right in Fig. 5-20d). Figure 5-21 shows the measured attenuation characteristics for a reflective VOA operating in a dark-type manner. A dynamic range of 30 dB was achieved for dark-type operation under a driving voltage of 5.25 to 8.25-V dc. The zero-attenuation state (i.e., full transmission state) was reached by applying 8.25-V dc for dark-type operation. The return loss [i.e., back-reflection loss (BR)] was less than –50 dB over the full span for bright-type and –48 dB for dark-type operation, respectively. In addition, the polarization-dependent loss was derived as less than 0.15 dB within 10 dB of attenuation, less than 0.2 dB for attenuation between 10 and 20 dB, and less than 0.3 dB for attenuation between 20 and 30 dB, respectively. Briefly, VOAs using single reflection demonstrate extremely good polarization-dependent loss and better return loss than shutter-based VOAs. With proper design of the comb actuators, a well-optimized DRIE process, and appropriate selection of lense fibers, the reflective VOA is superior, except that there is concern that the package of a reflective VOA with 45 degrees between input and output optical fiber ports is not a common layout configuration in application markets.

Dual-Reflection Mirrors In addressing the layout-format concern mentioned in the preceding paragraph, Lee and colleagues came up with a new retroreflective type of VOA in 2003. Meanwhile, a similar-concept VOA was reported

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Chapter Five by Lim and colleagues as well. Lim and colleagues133 created a folded mirror with 45 degrees between the two reflective surfaces, and this folded mirror was connected with a set of comb actuators and suspended via a silicon beam. This VOA achieved 30 dB of attenuation at 34-V dc. In contrast to the work of Lim and colleagues, the retroreflective VOAs of Lee and colleagues consisted of two separately controlled reflective micromirrors that were allocated in front of the input and output fibers and then assembled in a planar coaxial layout (Fig. 5-22). This design exhibited an insertion loss of less than 0.9 dB, a return loss of less than –50 dB, and a wavelength-dependent loss of less than 0.35 and 0.57 dB at 20 and 30 dB of attenuation, respectively. A measured dynamic range of 50 dB under 7 V dc and a voltage span of 4.7 to 11 V dc was reported for bright- and dark-type operations, respectively. The relevant results were published in 2004.134,135 Basically, this retroreflective attenuation mechanism resulted in a lower operating voltage because the intensity adjustment depends on the light-path shift, which is doubled after retroreflection for the same actuator driving voltage as used in reflective VOAs. These two micromirrors are potentially capable of being feedback-controlled individually; thus the attenuation curve could behave more linearly with dedicated control design. Besides, users in the optical communications industry are familiar with the planar coaxial layout. Additionally, Kim and colleagues have integrated two 45-degree reflective mirrors to form a dual-reflection-based in-line VOA with a minute parallelshifted light-propagation axis between the input and output ports.136 They also reported a comprehensive comparison between a singlereflection VOA using lens fibers and a dual-reflection in-line VOA using common optical fibers.

Rotary-Comb Actuator Lim and colleagues further explored the possibility of driving a folded mirror with a rotary-comb actuator for VOA application. This VOA consisted of a folded mirror connected with a rotary comb via a suspended beam. The attenuation was reported to be 45 dB at a rotation angle of 2.4 degrees under 21-V dc, and response time was less than 5 ms.137 Yeh and colleagues138 reported on a reflective-type VOA. This new VOA attenuates the optical power using a planar rotational tilted mirror driven by novel rotary-comb actuators. Design considerations that are taken into account include linear spring response, smaller moment of inertia, lower rotational spring constants, and extra optical attenuation induced by displacement in addition to rotation. A centrally symmetric structure that occupies the entire circular area was employed, and meander springs were designed specifically for the desired spring responses. As shown in Fig. 5-23a and b, the micromachined rotary-comb actuator is connected with a tilted mirror, and the entire structure is suspended by four orthogonally cross-linked meander springs anchored at four corners. Four strips of comb-electrode


(a)

(b)

FIGURE 5-22 SEM photographs of retroreflective MEMS VOAs: (a) Two reflective micromirrors and two coaxially arranged fiber trenches to form a retrorefractive VOA; (b) close-up view of micromirrors created via DRIE of an SOI substrate.

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FIGURE 5-23 (a) SEM photograph of a MEMS VOA using a rotary-comb actuator. The VOA has four anchors at the ends of two orthogonally located meander springs. (b) Close-up SEM photograph of the 45-degree tilted rotational mirror driven by a beam linked via a rotary-comb actuator. (c) Measured attenuation curve versus driving voltage.

Optical MEMS Packaging: Communications 60.00

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FIGURE 5-23 (Continued)

pairs are packed in each quarter of the rotary-comb actuator. The meander springs were deployed to reduce the rotational spring constant Kφ and to maintain the sufficiently large ratio of radial spring constant Kr to Kφ. Hence stable rotations at low driving voltages can be achieved, along with high radial robustness in the device plane. The device was reported to have 50 dB of attenuation at a rotation angle of 2.5 degrees under 4.1-V dc, as shown in Fig. 5-23c. The response time from 0 to 40 dB of attenuation and backward switching time were measured as 3 and 0.5 ms, respectively. The measured insertion loss was 0.95 dB, and the polarization-dependent loss was 0.3 dB at 20 dB of attenuation with a wavelength of 1550 nm. The wavelength-dependent loss was measured to be 0.19, 0.25, 0.61, and 0.87 dB for attenuations of 0, 3, 10, and 20 dB, respectively.

Functional Shutter and Elliptical Mirror In 2003, a wedge-shaped silicon optical leaker (i.e., a revised shutter) was proposed as a new refractive-type VOA by Kim of the Korean Aerospace Research Institute, Yun and colleagues of the Gwang-Ju Institute of Science and Technology, Gwangju, Korea, and Lee and colleagues of the Samsung Electro-Mechanics Company, Suwon, Korea.139–141 With proper design of the wedge shape, this type of shutter allows multiple optical internal reflection to occur near the fiber core of the input and output fibers. Thus only a small portion of the incoming light leaks out with a tilted propagation angle. This device achieved a return loss of less than –39 dB and a wide attenuation range of 43 dB for 8-degree optical-fiber facet ends, whereas polarizationdependent loss also was less than 0.08, 0.43, 1.23, and 2.56 dB for attenuations of 0.6, 10, 20, and 30 dB, respectively. Without using a 45-degree reflection mirror, Liu and colleagues at NTU, Singapore, proposed a novel elliptical mirror driven by an axial movable-comb actuator in which the input and output fibers were

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Chapter Five arranged and aligned in an orthogonal layout regarding the elliptical mirror.142 In this unique design, the input and output fibers were allocated at the two focal centers of the reflective elliptical mirror. Since the ellipse can focus the light from one center to the other, the VOA enjoys low insertion loss while using common single-mode fibers. As the mirror is shifted in the axial direction of one fiber, the input beam is rapidly defocused, producing a wide attenuation range without requiring a large mirror displacement. A dynamic range of 44 dB was achieved at 10.7 V dc, whereas the response time was 0.22 ms. The insertion loss was 1 dB, and the polarization-dependent loss was 0.5 and 0.8 dB at 20 and 40 dB of attenuation, respectively. The measured wavelength-dependent loss was 1.3 dB at 20 dB of attenuation within 1520 to 1620 nm. Without using expensive optics (e.g., lensed fibers), this new designs provided very interesting results with promising application potential. In 2007, Liu and colleagues at NTU, Singapore, proposed an innovative design of a retroreflective VOA using a parabolic micromirror pair.143 They deployed a rotary mechanism to rotate this parabolic micromirror pair. The input and output fibers were arranged in parallel, and a rod lens was added in between the parabolic micromirror pair and the fiber pair. This device shows good linearity of attenuation versus rotation angle within the attenuation range of 60 dB, and the polarization-dependent loss and wavelength-dependent loss exhibit moderate values. As discussed earlier under the issue of the linearity of attenuation, we have two major nonlinear factors to be considered. First, the moving distance of the microshutter is proportional to square of the driving voltage of the electrostatic comb actuator. Second, the collimated optical beam shows a Gaussian distribution. Lee and colleagues at the Gwang-Ju Institute of Science and Technology, Gwangju, Korea, demonstrated an in-line shutter-type VOA with a linear attenuation curve by using a comb actuator with a curved comb finger shape.144 On the other hand, Liu and colleagues at NTU, Singapore, demonstrated another way to achieve the attenuation versus driving voltage with good linearity by using two curved shutters connected by a pair of individually controlled comb actuators.145 This device shows very good linearity within 25 dB of attenuation with 8-V dc of driving voltage. Recently, Glushko and colleagues146 reported a two-shutter VOA with advantage in reduced driving voltage and compensation of nonlinearity.

5.4.4 DRIE-Derived Planar VOAs Using Electrothermal (Thermal) Actuators All the devices discussed so far have relied on electrostatic actuation mechanisms. Since there is no current flowing between the electrodes of the electrostatic actuators, there is no power consumption within the actuator part during operation of electrostatic actuators. However,

Optical MEMS Packaging: Communications electrothermal actuators are known for their large displacements and high force output. These characteristics make electrothermal actuators a viable alternative for VOA devices. The size and weight of MEMS elements are relatively small, and only a small amount of energy is required to operate a MEMS-based VOA. In other words, the power consumption of an electrothermally driven MEMS VOA is expected to be low as well. Moreover, the nature of the electrothermal actuator structure means that an electrothermally driven MEMS VOA has a smaller footprint and a lighter weight than one with an electrostatic actuator. Chiou and colleagues147 deployed two pairs of U-shaped electrothermal actuators linked together to push two separate microshutters on opposite sides. Although these four U-shaped actuators have been symmetrically placed at the four corners of device, the robustness of this VOA is still constrained by the mechanical weakness of the flexure beam of the U-shaped actuator itself. The driving voltage was as low as 4.5 V dc with 45 dB of attenuation owing to the benefits of the two-shutter approach. The two-shutter concept was first implemented by Chiou and colleagues for reducing the needed moving distance for each shutter. Thus the device gained the advantage of a reduced driving voltage. As shown in Fig. 5-24, Lee148 has reported an H-shaped silicon beam structure consisting of two V-beam electrothermal actuators on both sides and a pair of reflective mirrors for VOA application, where a pair of mirrors is arranged at the center of a linked beam between two V-beam electrothermal actuators. When a dc bias is applied to the anchors of the V-beam, volume expansion owing to Joule heating will

H-Shaped electrothermal actuator of high-aspect-ratio structure along with the perpendicular directions to moving axis

Anchors onto substrate Moving direction Moving direction (arched direction of V-beam) Antishock stopper

Attenuated Original 0

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FIGURE 5-24 VOA device consisting of retroreflective mirrors driven by a linked electrothermal V-beam actuator pair, where four anchors of the V-beam actuators pair are arranged symmetrically on the four corners of device to form a robust VOA structure: (a) Schematic drawing; (b) SEM photograph of retroreflective mirrors and link beam; (c) close-up SEM photograph of mirror; (d) the retroreflective light path attenuation scheme.

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Chapter Five distort the beams on both sides of the H-beam in the arched direction (i.e., denoted as the moving direction in Fig. 5-24). The position of the retroreflective mirrors depends on the applied voltage. If we applied the same bias to both V-beams, the displacement generated of both sides would be the same. Optical attenuation happens when the retroreflective mirrors move from the initial location, where attenuation is optimized in terms of minimal insertion loss. The maximum dynamic range of attenuation was 50 dB under 9-V dc. The polarization-dependent loss was measured as 0.15 dB at 20 dB of attenuation. Lee149 also demonstrated a planar attenuation micromechanism consisting of a planar tilted mirror driven by a V-beam electrothermal actuator via a link beam, as shown in Fig. 5-25a and b. This electrothermally driven tilted mirror can be displaced statically with a motion trace that includes rotational and translational movement, as shown in Fig. 5-25c and d. The rotational and translational misalignment of the reflected light spot toward the core of the output port fiber will lead to light attenuation. Thus the attenuation is controlled by the position of tilted mirror, which depend on the driving dc voltage. This micromechanism provided a more efficient way to conduct the attenuation with respect to the other kinds of planar VOAs. The device achieved 30 dB of attenuation under a 7.5-V dc bias. The PDL was less than 0.1 dB, within the 30-dB attenuation region.

5.4.5 3D VOAs Combining optics and a tilt mirror or an array of mirrors to be assembled in a 3D configuration is also a key approach in making MEMS VOA devices. Andersen and colleagues150 in 2000 reported a surfacemicromachined tilted mirror using a 3D attenuation scheme, whereas Riza and colleagues151 reported a 3D VOA using the Digital Mirror Devices (DMD) micromirror array of Texas Instruments in 1999. Robinsen152 filed in a U.S. patent in 1998 on this sort of tilted mirror idea; that is, the attenuated light is controlled by changing the tilt angle of the mirror or a portion of a mirror array in a digital manner, as shown in Fig. 5-26a. However, early demonstrations show only moderate performance. In principle, we may prepare a large single-crystal silicon tilt mirror by using state-of-the-art DRIE micromachining technologies.153 When tilt mirrors are deployed for 3D VOAs in conjunction with large microoptics, such as the dual core collimator, the resulting VOA can show excellent return loss, PDL, and WDL under a reasonable driving voltage (i.e., a small rotational angle). Toshiyoshi and colleagues have demonstrated a 3D VOA that uses an electrostatic parallel-plate actuator in which the performance is very good in this sense; that is, only 4.5 V dc can achieve 0.3 degree of rotational angle and 40 dB of attenuation.154–156 Recently, Lee and colleagues157 developed a 3D VOA based on a pair of PZT actuators, as shown in Fig. 5-26b. In the operation of a

Optical MEMS Packaging: Communications Rotational axis Anchor

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FIGURE 5-25 VOA consisting of a planar tilted mirror driven by a V-beam electrothermal actuator: (a) Schematic drawing; (b) CCD image of the tilted mirror, spring, link beam, and electrothermal actuator of the VOA; (c) CCD image of the tilted mirror, spring, and trenches for accommodating fibers; (d) novel planar light attenuation scheme is realized by using this tilted mirror with rotational and translational displacement.

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Chapter Five FIGURE 5-26 (a) Schematic drawing of the optical path in a 3D VOA including a tilted mirror and optics. (b) Schematic drawing of a tilt mirror for a 3D VOA. The mirror rotates against the torsion spring owing to static displacements introduced by the lead-zirconatetitanate (PZT) actuator beams.

Collimating lens

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PZT 3D VOA, various dc biases are applied to one or two of the actuators. Then the reflected light is deviated from the optimized light path in a manner that corresponds to the minimum insertion loss. Therefore, the insertion loss is increased as the increased dc bias because the coupled reflected light intensity toward output fiber is reduced (i.e., the attenuation operation). As shown in Fig. 5-27a, an SOI substrate with a 5-μm-thick Si device layer and a 1-μm-thick buried oxide (BOX) layer was used as the starting material. A thermal oxide layer of 0.37 μm was created from the Si device layer surface. A multilayer electrode of LaNiO3 (0.2 μm)/Pt (0.2 μm)/Ti (0.05 μm) was prepared by radiofrequency (for LaNiO3) and dc (for Pt/Ti) magnetron sputtering, respectively. Then a 3.1-μm-thick PZT thin film was formed by sol-gel deposition, as reported previously. The (100)-oriented PZT thin film prepared on the LaNiO3 buffer layers exhibited columnar structure, as shown in Fig. 5-28. This kind of (100)-oriented textured film exhibits a higher dielectric constant than the randomly oriented film and the (111)oriented film. The deposited films were pyrolyzed at 200 to 470°C for 5 minutes and then crystallized by rapid thermal annealing at 700°C for 2 minutes. Finally, a top electrode of Pt/LaNiO3 was sputtered on


(a)

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SiO2

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FIGURE 5-27 Microfabrication process flow for making PZT actuators and mirror.

top of the PZT layer. The poling condition is 30 V for 10 minutes at room temperature. A Pt bottom electrode is used because it is a stable metal in this temperature range. The measured transverse piezoelectric constant d31 of –110 pm/V of the fabricated 3.1-μm PZT layer is rather good compared with published data, which show d31 ranging from –50 to –110 pm/V. Figure 5-27b shows how the top Pt thin film was etched by Ar ion etching and the top LaNiO3 thin film was subsequently etched by diluted HCl. Then the PZT thin film was etched by a mixture of HF, HNO3, and HCl. Finally, the bottom LaNiO3/Pt/Ti electrode layers were etched again, whereas the thermal oxide layer was etched by CHF3 reactive-ion etching to open the area of the mirror and springs shown in Fig. 5-27c. Thereafter, the mirror, springs, and frame of the actuators were patterned from the silicon device layer of the SOI substrate by DRIE, as shown in Fig. 5-27d. Then a 0.07-μm-thick Pt film

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PZT: 3.1 μm LNO/Pt/Ti/SiO2 Device layer Si: 4.8 μm

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5 μm

FIGURE 5-28 SEM micrograph in cross-sectional view of a PZT actuator thin film on an SOI substrate.

was deposited on the mirror as the reflective surface by a lift-off step, as shown in Fig. 5-27e. The lift-off method is chosen to avoid the difficulty of finding good etching stop materials for Pt in the Ar ion etching process. We used Pt as the mirror coating layer because we planned to conduct the postprocess annealing for the PZT layer initially. Only the Pt is very stable even in the annealing step with temperatures as high as 700°C. Using DRIE, the backside Si portion and BOX were etched from the substrate backside to release the mirror, springs, and actuators, as shown in Fig. 5-27f, whereas we used SF6 and CHF3 as the etching feedgas for Si and SiO2 etching, respectively. Figure 5-29 shows the attenuation curve measured when both actuators were under the same dc bias. Only 1 V dc can achieve 42 dB of dynamic range of attenuation, whereas 50 dB is obtained at 1.2 V dc. The optical deflection angle is measured as 0.18 degree at 1 V dc. Referring to most of the commercial applications, the 40-dB dynamic range is enough. This means that the PZT 3D VOA requires an operating voltage of only 1 V dc.157

5.4.6 VOAs Using Various Mechanisms Another type of 3D VOA relies on a grating structure (i.e., a diffractive type of mechanism).158 By modifying the original design of grating light valve (GLV) diffractive technology, Lightconnect has proposed a


Attenuation (dB)

60 50 40 30 20 10 0 1.2

1 0.8 0.6

Bias of actuator A (V)

0.4 0.2 0

0

0.2

0.4

0.8

0.6

1.2

1

Bias of actuator B (V)

FIGURE 5.29 Measured attenuation curve versus dc driving voltage equally applied to PZT actuators A and B, respectively.

revised design using a circularly symmetric membrane structure.159–161 This novel diffractive MEMS VOA is known as the first Telcordiaqualified MEMS VOA. As the SEM photograph in Fig. 5-30a shows, the microfabrication process of a diffractive MEMS VOA starts with patterning of the reference posts with a height of 2.32 μm. Then a thin (20 to 60 nm) layer of silicon dioxide is grown thermally. A layer of sacrificial polysilicon or amorphous silicon is deposited thereafter. This layer must remain optically smooth. If not, any defects on this

Reflecting membrane Release holes

Anchor to substrate

d=N Silicon substrate Array of fixed posts

(a)

Reflecting surface

λ0 2

Achromatic compensator

(b)

FIGURE 5-30 (a) SEM photograph of a diffractive MEMS VOA. (b) Schematic drawing of the diffractive MEMS VOA. The architecture incorporates achromatic compensation and cylindrical symmetry to ensure low dependence on polarization.159–161

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Chapter Five sacrificial layer will subsequently imprint the movable membrane. Holes are etched through the sacrificial layer to allow for the anchor points to the substrate. Silicon nitride film then is deposited and patterned as the movable membrane. Finally, xenon difluoride (XeF2) is used to etch away the sacrificial layer of silicon and to release the membrane. A subsequent gold coating across the entire surface is required to ensure high reflectivity in the infrared-wavelength range. The closely spaced suspended reflective membrane used for the GLV forms an adjustable-phase grating. When the reflective membrane and reflective post surface are coplanar, incident light is reflected back into the aperture without attenuation (Fig. 5-30b). When the reflective membrane is pulled down using electrostatic actuation by one quarter of a wavelength (λ/4) relative to its adjacent reflective post surface, the incident energy diffracts into higher orders that are directed outside the aperture, and the incident beam is completely attenuated. When the separation gap is less than λ/4, the incident beam is partially attenuated because some energy is shifted into the higher diffracted orders. Another unique feature of this diffractive MEMS VOA is the reduction in PDL provided by the design. Without using the ribbonlike microstructures in the GLV device, Lightconnect’s diffractive MEMS VOA deploys reference circular posts to replace the reference ribbon and a suspended reflective membrane to be the movable ribbon. Moreover, the achromatic compensating ribbons become annular rings around the reference posts. The suspended reflective membrane incorporates an array of air holes that assist in fast and uniform removal of the sacrificial layer during fabrication. The dimensions of the gaps remain the same as in the GLV device. In a typical design, N refers to 3 for the center wavelength of 1550 nm, corresponding to a height difference of 2.32 μm between the movable membrane and the compensating annuli. The periodicity of the repeating diffractive element is typically between 20 and 200 μm. The widths of the reference posts, as well as the gaps between the posts and membrane, are typically a few micrometers. This diffractive MEMS VOA has a dynamic range (attenuation range) of 30 dB, a WDL of 0.25 dB, and a PDL of 0.2 dB. The total insertion loss, which includes losses from fiber coupling, is 0.7 dB. The response time of the device is outstandingly fast (i.e., 40 μs) and is attributed to the small mass and short actuation distance (e.g., λ0/4 ≅ 400 nm). The actuation voltage is less than 8 V. We should also address the efforts in digital VOA development. By using an array of digital mirrors (i.e., maintained at either the rest position or the tilted position) with a fixed deflection angle, we may individually address bias to a column of mirrors or a single mirror of an array.162,163 The extended dynamic range of attenuation is up to 80 dB162 and an attenuation curve with good linearity is feasible. On the other hand, to avoid the requirement of on-hold voltage or power, a vernier-type latching mechanism for an in-line shutter-type

Optical MEMS Packaging: Communications VOA affords as small as 0.5-μm step resolution, as has been reported by Syms and colleagues.164,165 Moving-fiber mechanisms can lead to two aligned fibers being moved to misaligned positions from the optimized coupling position so as to perform the power attenuation. Thermal actuators have been proven to be good candidates for movingfiber optical switches.166–168 Such mechanisms can be used as VOAs as well because of analogue control capability. Approaches using a polymer waveguide or a MEMS polymer membrane structure have been investigated and show the potential advantages of a small footprint and low cost.169–172 Optofluidic technology has been applied to VOAs as well.173 Based on the preliminary results, rather good VOA characteristics, including a 38-dB dynamic range, 0.479 dB of insertion loss, and a PDL less than 0.4 dB have been reported.173 Electromagnetic actuation applied to a VOA has been reported to achieve 50 dB of attenuation under only 4 V.174 In order to achieve better optical characteristics, a pair of single-mode fiber collimators is deployed to integrate with a large shutter, a 500 × 1200 μm vertical micromirror, on top of an electromagnetic coil actuation flap. The micromirror was created by tetramethyl ammonium hydroxide (TMAH) anisotropic wet etching with a sharp edge and a smooth reflecting surface. The insertion loss of the VOA is 0.2 and 0.4 dB for normally-on and normally-off modes, respectively. The dynamic range of 40 dB is achieved at 0.5 V, and the driving power is less than 2 mW. A response time of 5 ms is achieved.175

5.5

Packaging, Testing, and Reliability Issues Optical MEMS devices involve either free-space propagation of bounded beams, wave guidance, or a mixture of the two. Optics design can be achieved by considering the properties of Gaussian beams, which propagate in free space and in cylindrically symmetric graded-index media.9 From these properties, we can determine layouts of a MEMS chip and its package. The typical arrangements are categorized into two approaches: (1) chip-level optical alignment and (2) package-level optical alignment. First of all, in the case of chiplevel optical alignment, a wet-etched V-groove can be used as a fiber holder, as shown in Fig 5-31a. A fiber can be aligned to a laser that is placed on top of the V-groove mirror at the end of the groove for holding the fiber. Thus the light coupling via a V-groove mirror can be optimized between the laser chip and the fiber end. This step eliminates all the degrees of freedom except axial motion. The fiber then may be butt-coupled and the assembly fixed by epoxy. An alternative method of alignment relies on a robust metal fixture to hold the components. As shown in Fig. 5-31b, a number of such fixures are soldered to a substrate and used to provide individual mounts for a set of components to form a free-space optical breadboard. This approach was pioneered by Axsun Technologies.176 When combined with

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Laser chip Optic fiber

Probe tip

Shutter

Optical lense fiber (a)

(c) Tilt mirror Fixture

Rotary comb Optic component (b)

Optical lense fiber Optic fiber (d)

FIGURE 5-31 (a) SEM photograph of a typical optoelectronics hybrid package based on an Si optical bench showing passive optical alignment from laser to single-mode fiber to better than 1 μm of accuracy.5 (b) SEM photograph of a freespace optical breadboard using a micromachined metal fixture to clamp the fiber in a predetermined position aligned with the optoelectronic device.5 (c) Optical microscope photograph of a crossbar switch assembled with four optical fibers in DRIE trenches.75,82 (d) Optical microscope photograph of an electrostatic rotarycomb-driven VOA tilt mirror integrated with two optical fibers in DRIE trenches.138

MEMS device fabrication, the fiber trenches can be easily created on the silicon, especially for SOI substrate. For example, the fibers are aligned and assembled inside the trenches for a crossbar optical switch (Fig. 5-31c) and a tilt-mirror VOA (Fig. 5-31d). In the second approach, discrete components are assembled and aligned on a carrier substrate. The electrical interconnects of the assembled components are finished either by wire bonding or flipchip bonding. Then the substrate integrated with several discrete components is arranged in a metal case. In the last step, this metal case typically is hermetically sealed by a seam welder or a laser welder. For example, Fig. 5-32a shows a schematic drawing of a MEMS-based tunable external cavity laser based on a Littman-Metcalf geometry consisting of a diffraction grating illuminated at near-grazing incidence for angularly dispersing light and a mirror on a rotary-comb structure for retroreflecting finite spectral components. Continuous tunability is achieved by rotating the mirror and selecting the wavelength

Optical MEMS Packaging: Communications Lenses

Laser diode

PM fiber pigtail Grating

Wavelength locker

MEMS actuator (b)

Silicon mirror

Shutter/ VOA Beam splitter Isolator

(a)

FIGURE 5-32 (a) Conceptual drawing of a packaged MEMS-based tunable laser with an intracavity grating spectral filter. (b) Photograph of a vertical mirror driven by a rotary-comb actuator integrated with grating, lens, and laser to form the cavity.177,178

that satisfies retroreflection. The rotary comb rotates the attached mirror about a virtual pivot point that is at the intersection of the grating and mirror planes. The position of this pivot point is critical. Cavity length control is provided by a piezoelectric actuator that translates the diffraction grating in order to achieve a full communication-band tuning range. In this double reflection-diffraction arrangement, the light diffracts from the grating toward the mirror, reflects back to the grating, diffracts a second time from the grating, and then falls on the mirror, on which it is a retroreflection path for the center wavelength. By leveraging this design, the angular rotation-range requirement of mirror is reduced because it is directly related to the filter’s tuning range.177,178 From this case, translation and angular misalignment of the relative positions among these components are crucial to the performance of these optical MEMS devices in assembled packages. In fact, angular misalignment is the main concern in all kinds of MEMS devices for optical communications applications. 3D optical switch packaging will be discussed in Sec. 5.5.3. Generally speaking, the packaging of optical MEMS devices constitutes up to 80 percent of the final cost of the device. To highlight these key concerns in optical MEMS packages, we explore such issues from the points of view of manufacturability, yield, and reliability.

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5.5.1

Manufacturability and Self-Assembly

When we consider the manufacturability of an optical MEMS device, we have to look into all the facts related to yield. The yield loss could refer to front-end wafer process factors such as cross-wafer discrepancy of etch rate, residual stress, and film thickness, as well as backend packaging process factors such as damage and contamination introduced in the dicing process, optical loss owing to misalignment in assembly, failure in hermetic sealing owing to a leak in the housing, and the like. However, given the lack of a qualified tool for investigating 3D microstructures such as vertical mirrors in most of optical MEMS devices, we can only conduct final system-level testing. Although a general visual inspection and an actuator function test can be conducted at the wafer level, quite a few parameters can be measured only after fully complete or semicomplete packaging. Multichanneled optical MEMS devices have become indispensable in wavelength-division-multiplexed (WDM) telecommunication networks, such as optical cross-connects (OXCs), wavelength equalizers, and multichanneled variable optical attenuators (MVOAs). Using silicon DRIE to sculpt actuators and micromirrors from SOI substrates has been the most available micromachining process for realizing optical microsystems. A retroreflective MVOA with eight channels packaged in a metal case, as shown in Fig. 5-33, is the basis of our case study. To investigate its manufacturability, we characterized several MVOA devices in terms of insertion loss, PDL, back-reflection loss, and WDL. This eight-channel MVOA has monolithically integrated

FIGURE 5-33 Photograph of a packaged eight-channel MEMS VOA based on a retroreflective light-path arrangement.

Optical MEMS Packaging: Communications Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.07 0.12 0.16 Polarization-dependent (a) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.12 0.17 0.22 0.25 Polarization-dependent (b) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 0.14 0.18 0.22 0.28 Polarization-dependent (c) loss (PDL; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 48.5 50.8 52.3 54.6 Back-reflection (d) loss (BR; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 47.7 50 52.1 55.5 Back-reflection (e) loss (BR; dB)

Percentage % 100 90 80 70 60 50 40 30 20 10 0 48.2 50.3 52.8 54.2 Back-reflection (f) loss (BR; dB)

57

57

57

FIGURE 5-34 Histogram of mean-value distribution of measured data from each individual channel of a multichanneled VOA using a retrorefractive attenuation scheme showing PDL and back-reflection loss characteristics, where (a) and (d) represent measurement at 10 dB of attenuation; (b) and (e), at 20 dB of attenuation; and (c) and (f), at 30 dB of attenuation.

mirrors and optical fibers in a retroreflective type of light-path arrangement in an SOI substrate. A monolithically integrated VOA with multiple channels requires very good process control in microfabrication. As shown in Fig. 5-34, experimental study of such critical parameters as insertion loss, PDL, return loss, and WDL was done for several MVOA devices.179 In a well-controlled process, these MVOAs commonly provide excellent optical performance. These devices show a dynamic range of 50 dB, insertion loss of less than 0.8 dB, back-reflection loss of better than 50 dB, and PDL of less than 0.3 dB over the full span of attenuation. Each channel of an arrayed VOA device can be controlled individually. The channel number is potentially scaled up to 16 channels from 8 channels in current devices configurations. The correlation among measured data on PDL and back-reflection loss, design of the MEMS mirror, and surface quality of the MEMS mirror is not clear so far. The arrayed MEMS VOA using a retroreflection light attenuation scheme and planar layout configuration demonstrates competing optical characteristics and a cost-effective solution in terms of manufacturability, scalability, and compact footprint.179 On the other hand, fully automatic techniques are being developed for assembly of optical MEMS 3D structures. For example, the surface-micromachined shutter and structures are relatively fragile.

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L-shaped curved beam for lifting up shutter plate

Planar latches Scratch-drive actuator (SDA)

(a)

(b) Pop-up shutter clamped by arm lockers

Pop-up shutter driven by SDA into fiber-end spacing

(c)

(d) Curved-flexure-beam electrostatic actuator

FIGURE 5-35 Schematic drawings of self-assembled VOA with pop-up shutter and stress-induced curved-beam electrostatic actuator: (a) device configuration before structure release; (b) device configuration after released and self-assembly; (c) microshutter driven by SDAs and moved into the space between fiber ends; (d) microshutter moved downward and performed the optical attenuation.

During the optical fiber alignment and assembly process, these microstructures are vulnerable to damage when the optical fiber touches the microstructures unexpectedly. Lee and colleagues180,181 reported a self-assembled VOA in 2003. As shown in Figs. 5-35a and b and 5-36, the self-assembly mechanism first allows the reflective shutter to be lifted up and fixed by two individually controlled stress-induced curved polysilicon beams. Second, this self-assembled reflective shutter is driven by a set of electrostatic SDAs that slide into the space between the input and output fiber ends (Fig. 5-35c and d). Then the attenuation is determined by the vertical position of the self-assembled pop-up polysilicon reflective shutter, which is controlled by an applied dc bias. In terms of the mass production of MEMS VOAs nowadays, we normally place and align the input/output fibers above the MEMS chip with the V-groove trench at the beginning. These elements and/ or optics will be fixed at relative positions by laser welding, soldering, or ultraviolet (UV) curing. Thereafter, the assembled components are accommodated into and fixed inside the product housing. As shown in Fig. 5-37, we proposed a new manufacturing flow based on this self-assembly technology to make surface-micromachined VOA devices. First, we could align and fix two fibers on a silicon carrier chip with V-grooved trenches to get an optimized coupling efficiency (i.e., the lowest insertion loss) (see Fig. 5-37a). In the meantime, the


Curved beam acted as electrostatic actuator

SDA Residual stressinduced curved beam for lift-up

Shutter plate

FIGURE 5-36 The SEM photograph of a MEMS VOA with the shutter being lifted by an L-shape stress-induced curved beam and clamped by the arrowhead locking element. (Inset) Close-up view of the bottom of the shutter plate, which is clamped by the arrowhead locking elements.

shutter plate is released first and lifted; then it is fixed on a curved polysilicon beam electrostatic actuator (see Fig. 5-37b). Thereafter, we could attach this self-assembled MEMS chip onto the fiber’s assembled carrier chip using flip-chip technology (see Fig. 5-37c) because the shutter and peripheral MEMS actuators and structures are designed to be allocated away from the area of fiber-to-fiber spacing. As a result, we could avoid damaging the fragile shutter and microstructures during flip-chip assembly. The fiber carrier chip is depicted as an opaque form in the schematic drawing to show the 3D geometric relationship of the relative elements. The V-groove through-wafer electrical feedthrough also is shown on top of the assembled device chip. In the step illustrated in Fig. 5-37c, we could apply an electrical load via the through-wafer electrical feed-through on a set of SDAs located in the area surrounding the shutter, which is hinged on a curved-beam electrostatic actuator. Since the relative positions of the fibers, actuators, and pop-up shutter are determined by photolithographic accuracy, this SDA set and connected polysilicon frame will move forward so as to drive the curved-beam electrostatic actuator and pop-up shutter concurrently toward the tiny space precisely between the two fiber ends. Furthermore, this VOA demonstrated continuous attenuation capability, a wide attenuation range of 60 dB, and an insertion loss of less than 1 dB under the 8 and 5 V dc for bright and dark operation, respectively. This self-assembly approach for creating a VOA reveals the potential solution of getting rid of tedious optical alignment and assembly efforts while drastically reducing or eliminating damage to the fragile surface-micromachined polysilicon shutter.

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Chapter Five FIGURE 5-37 Schematic drawings of the self-assembly mechanism: (a) the fiber-aligned carrier silicon chip; (b) flipchip bonding of the fiber carrier chip and chip with a self-assembled pop-up shutter; (c) final completed MEMS VOA, in which the pop-up shutter is driven by an SDA and moved into the space between the fiber ends.

(a)

(b)

(c)

On the other hand, Uttamchandani and colleagues182 at the University of Strathclyde has demonstrated a thermally controlled selfassembly mechanism for creating the pop-up microshutter, whereas the assembled microshutter is driven by an array of SDAs. In all, 45 dB of attenuation could be achieved at lateral displacement of the popup microshutter of about 20 μm with driving voltages of 60 to 290 V ac for various moving speeds of the microshutter.


5.5.2 Case Study: VOAs Now that we have a basic understanding of manufacturability in terms of yield in front-end and back-end processes, we can look into the factors that influence final product reliability. Generally speaking, the reliability of MEMS devices strongly depends on the detailed design of those structures, as well as the technologies used to fabricate them. These factors include materials failure, vibration tolerance, temperature dependence, and the stiction issue after long-term operation.

Electrostatic VOAs As illustrated in Fig. 5-26a, a MEMS tilt mirror is placed at the back focal plane of the lens to form a 3D VOA. In Sec. 5.4.5 we discussed a 30-μm-thick tilt mirror with a diameter of 600 μm driven by a parallelplate actuator, as shown in Fig. 5-38a.154–156 This VOA is made by using a double-sided DRIE process and HF vapor-phase etching62 to release the mirrors from the SOI substrate. A TO-Can-like package with a diameter of 5.6 mm and a length of 23 mm is demonstrated for a hermetically packaged 3D VOA. When the mirror is in the unactuated state, light from the input fiber is collimated by the lens onto the mirror, is reflected back, and subsequently is focused by the lens onto the output fiber. The PDL is minimized because the beam is almost normally incident onto the mirror. To perform the attenuation, a dc electrical bias is applied across the mirror plate and underneath the silicon substrate of the handle wafer portion of a SOI substrate, and the tilt mirror will bend toward the bottom electrode (i.e., underneath the silicon substrate). When the mirror is tilted, the focused beam is shifted from the optimized path in terms of the output fiber, and this results in increased coupling losses (i.e., the attenuation). To reduce the operating bias voltage, the most straightforward way is to deploy a soft torsion spring for the tilt mirror. However, if the soft spring is too soft, two issues may be introduced in operation. First, the soft springs need to be strong enough to be immune from ambient vibration shock. In the case of this tilt-mirror 3D VOA, two dimensions of the torsion spring have been investigated, namely, ls, hs, and ws = 200, 30, and 2 μm and 150, 30, and 1.6 μm. VOAs of both designs can survive a shock test up to 500g without mechanical failure. The way to avoid damage introduced by mechanical impact is to incorporate a mechanical stopper to limit the allowable spring deformation to within the elastic deformation region. Second, Fig. 5-38b shows the influence of 25g impact on the measured optical attenuation level at an attenuation of 10 dB (i.e., under a bias of 3 to 4 V). A measured fluctuation of more than 7 dB is shown for a VOA with a 200-μm-long spring. Coupling between the mirror angle and external vibration can be explained by the up-and-down motion of the actuator plate, which alters the mean electrostatic gap and thus the mirror angle. Since mechanical analysis tells that the

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Chapter Five suspension rigidity in the torsional motion is proportional to ws3 × ls, whereas that in the direction of bending (normal to substrate) is proportional to ws × ls3, the torsion spring rigidity in this direction can be almost doubled by shortening the length to 75 percent (from 200 to 150 μm) and thinning the width to 80 percent (2 to 1.6 μm) without stiffening rotational rigidity (or without increasing driving voltage). By using the shorter torsion spring (150 μm in length and 1.6 μm in width), the measured attenuation fluctuation is suppressed almost 50 percent and becomes 3 dB, as shown in Fig. 5-38b. Generally speaking, a stiff torsion spring can increase the dynamic stability of a VOA, but the tradeoff is a larger driving voltage. While the sizes of the mirror and springs are reduced, maintaining the necessary aspect ratio to produce the required stiffness is achieved. This is a good way to increase the mechanical stability of VOA mirrors significantly. On the other hand, the collimated optical beam size is another factor that needs to be considered. Optical fibers integrated with a microlens typically offer a focused-beam size of less than 50 μm,184 whereas optical fibers integrated with a collimated lens or GRIN lens normally provide a focused-beam size of 450 to 900 μm. In the 3D VOA configuration, an optics-provided focused-beam size of 450 to 900 μm normally is adopted. Thus the 600-μm-diameter mirror is designed for this reason.154–156 This also implies that reducing mirror size and mass and keeping the same aspect ratio of the torsion springs is a good approach to achieving the required mechanical stability of VOA mirrors, but the limit on the smallest mirror size is about 500 to 600 μm in 3D VOAs. However, the temperature dependence of attenuation characteristics must be explored. In order to apply open-loop control for VOA operation, good thermal stability of the VOA is necessary. Although we typically expect that the temperature dependence of the actuation characteristics of an electrostatically driven mirror is negligible, Isamoto and colleagues155 reported a measured fluctuation of 0.5 dB at 10 dB of attenuation in the temperature range of –5 to 70°C. As the conceptual curves of tilt angle versus voltage show in Fig. 5-38c, the mirror tilts more in the case of low ambient temperature under the same drive voltage but with a smaller contact angle (i.e., less maximum rotation angle). This deviation in rotation angle under the same voltage is attributed to the difference in thermal deformation of the mirror and the actuator plates at different temperatures. The gap between the mirror plate and the substrate is smaller at lower ambient temperatures. The origin of such variation is attributed mainly to the combination of built-in stress and thermal expansion owing to temperature change in the released device layer of the SOI wafer (i.e., the mirror layer). The built-in stress of the mirror after it is released leads to a 0.5-μm bulking-up deformation over a span of 2.6 mm, including the two sides of the torsion springs and center mirror.


Optical attenuation, dB

2.4 mm

0

Suspension length ls = 200 μm

–2

Width ws = 2.0 μm

–4

Suspension length ls = 150 μm > 7 dB

Fluctuation

–6

Width ws = 1.6 μm

–8

~ 3 dB Fluctuation

–10

(a)

0

2

(b) Low temperature

High temperature

Reference attenuation with bias voltage

Impulse 25g in x-direction

–12 –2

4 6 Time, ms

8

10

12

20.4 Without backside metallization

20.3

20.1 20.0

Contact angle Low temperature

Pull-in voltage

Mirror angle θ

20.2 Room temperature

High temperature

19.9 19.8 19.7 19.6

Drive voltage, V

(c)

With backside metallization 0

5

10

15

20 25 Time, s

30

35

40

(d)

FIGURE 5-38 (a) Optical microscope photograph of a 3D VOA showing the mirror, springs, and parallel-plate electrode. (b) Temporal fluctuation of attenuation at 10 dB under mechanical impact of 25g. (c) Temperature dependence of conceptual curves of tilt angle versus voltage. (d) Fluctuation of attenuation at 20 dB owing to electrostatic drift.154–156

To remedy this situation, a tensile Au/Cr metal layer coated on the mirror is suggested.155 On the other hand, the Fig. 5-38d shows the drift of the attenuation value in a short period of time after mirror is biased. Drift of ±0.2 dB at 20 dB of attenuation is observed in the figure. Isamoto and colleagues investigated various methods of die bonding and wire bonding. It was reported that a metallization process of the bottomsubstrate backside of the SOI mirror chip could effectively remove the accumulated charge at the bottom substrate.

VOA Using a Thermal Actuator VOAs were made using DRIE to pattern the H-shaped structures from the device layer of 82 μm of a 6-in SOI wafer. After the DRIE step, the H-shaped structure was released from the substrate after wet etched in HF-buffered solution. After chip separation and visual inspection, selected VOA chips were tested to confirm the function of the thermal actuator by applying bias to the electrode pads of the VOA chip on a probe station. The known-good-die characterization has been achieved by examining mirror displacement under various dc electrical biases

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Moving axis (x axis)

Tilt mirrors for retroreflection Lens fiber

(a)

Lens fiber

(b)

FIGURE 5-39 (a) Packaged VOA using an H-shaped beam actuator. (b) Optical microscope photograph of a pair of tilted mirrors and two coaxially arranged lens fibers.

via CCD camera. The selected good dies with qualified motion characteristics of their mirrors were moved to and fixed on a precision xyz stage. Two lens fibers were placed in the two parallel trenches and faced toward the tilted mirrors in front of them. The attenuation versus voltage curve, insertion loss, and PDL were measured as monitored parameters. The selected good dies were glued on ceramic carrier substrates and then placed in a metal case with metal pins on the backside, as shown in Fig. 5-39a. Then two lens fibers were placed in the DRIE-derived trenches, as shown in Fig. 5-39b. The fiber end faced the tilt mirror. The specifications of this lens fiber are discussed in ref. 184. Then the fibers were fixed in the trenches with UV glue after active alignment and a complete function test. Then this chip was finished with wire bonding, and the cover of the metal case was sealed and the fibers through the inlet tube of metal case were sealed with the tube wall. The finished metal package was 12 × 6.8 × 3.5 mm (length, width, and height). Moreover, the device characteristics in terms of the Telecordia GR1221 regulation are very interesting for practical applications. According to the Telecordia GR1221 regulation, the measured dynamic deviation in attenuation at 20 dB of attenuation should be less than ±0.5 dB under a vibration-testing condition of 20g periodic shocks with a frequency from 20 to 2 kHz along with x, y, and z axes, where four cycles of vibrations are required for each axis. In view of such a strict requirement, an H-shaped electrothermal actuation mechanism has been proposed to address this severe requirement, as shown in Fig. 5-24.148,185 By drastically reducing the mass and enhancing the stiffness of the structure, the mechanical resonance frequency of the H-shaped electrothermal VOA becomes much higher than that of its counterpart (i.e., the electrostatic comb-actuator-based design). As listed in Table 5-1, the measured dynamic attenuation fluctuation is less than ±0.03 and ±0.15 dB at 20 dB of attenuation over the full

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Advanced MEMS packaging

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Materials for Electronic Packaging

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The MEMS Handbook MEMS Applications

An Introduction to MEMs Engineering

Mechanical Analysis of Electronic Packaging Systems

The Electronic Packaging Handbook (Electronics Handbook Series)

Introduction to Electronic Engineering

MEMS MOEM Packaging (Mcgraw-Hill Nanoscience and Technology)

Force Sensors for Microelectronic Packaging Applications (Microtechnology and MEMS)

CMOS-MEMS: Advanced Micro and Nanosystems

CMOS-MEMS: Advanced Micro and Nanosystems

MEMS Reliability (MEMS Reference Shelf)

The MEMS Handbook MEMS Design

Filter Theory in Electronic Engineering

Electronic Engineering and Computing Technology

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BioNanoFluidic MEMS (MEMS Reference Shelf)

Advanced Earthquake Engineering Analysis

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Advanced thermodynamics for engineering

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